2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * SAMSUNG - GPIOlib support
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/of_address.h>
34 #include <mach/regs-gpio.h>
36 #if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX)
37 #include <mach/gpio-samsung.h>
41 #include <plat/gpio-core.h>
42 #include <plat/gpio-cfg.h>
43 #include <plat/gpio-cfg-helpers.h>
46 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
47 unsigned int off, samsung_gpio_pull_t pull)
49 void __iomem *reg = chip->base + 0x08;
53 pup = __raw_readl(reg);
56 __raw_writel(pup, reg);
61 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
64 void __iomem *reg = chip->base + 0x08;
66 u32 pup = __raw_readl(reg);
71 return (__force samsung_gpio_pull_t)pup;
74 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
75 unsigned int off, samsung_gpio_pull_t pull)
78 case S3C_GPIO_PULL_NONE:
81 case S3C_GPIO_PULL_UP:
84 case S3C_GPIO_PULL_DOWN:
88 return samsung_gpio_setpull_updown(chip, off, pull);
91 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
94 samsung_gpio_pull_t pull;
96 pull = samsung_gpio_getpull_updown(chip, off);
100 pull = S3C_GPIO_PULL_UP;
104 pull = S3C_GPIO_PULL_NONE;
107 pull = S3C_GPIO_PULL_DOWN;
114 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
115 unsigned int off, samsung_gpio_pull_t pull,
116 samsung_gpio_pull_t updown)
118 void __iomem *reg = chip->base + 0x08;
119 u32 pup = __raw_readl(reg);
123 else if (pull == S3C_GPIO_PULL_NONE)
128 __raw_writel(pup, reg);
132 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
134 samsung_gpio_pull_t updown)
136 void __iomem *reg = chip->base + 0x08;
137 u32 pup = __raw_readl(reg);
140 return pup ? S3C_GPIO_PULL_NONE : updown;
143 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
146 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
149 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
150 unsigned int off, samsung_gpio_pull_t pull)
152 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
155 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
158 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
161 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
162 unsigned int off, samsung_gpio_pull_t pull)
164 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
168 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
169 * @chip: The gpio chip that is being configured.
170 * @off: The offset for the GPIO being configured.
171 * @cfg: The configuration value to set.
173 * This helper deal with the GPIO cases where the control register
174 * has two bits of configuration per gpio, which have the following
178 * 1x = special function
181 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
182 unsigned int off, unsigned int cfg)
184 void __iomem *reg = chip->base;
185 unsigned int shift = off * 2;
188 if (samsung_gpio_is_cfg_special(cfg)) {
196 con = __raw_readl(reg);
197 con &= ~(0x3 << shift);
199 __raw_writel(con, reg);
205 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
206 * @chip: The gpio chip that is being configured.
207 * @off: The offset for the GPIO being configured.
209 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
210 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
211 * S3C_GPIO_SPECIAL() macro.
214 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
219 con = __raw_readl(chip->base);
223 /* this conversion works for IN and OUT as well as special mode */
224 return S3C_GPIO_SPECIAL(con);
228 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
229 * @chip: The gpio chip that is being configured.
230 * @off: The offset for the GPIO being configured.
231 * @cfg: The configuration value to set.
233 * This helper deal with the GPIO cases where the control register has 4 bits
234 * of control per GPIO, generally in the form of:
237 * others = Special functions (dependent on bank)
239 * Note, since the code to deal with the case where there are two control
240 * registers instead of one, we do not have a separate set of functions for
244 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
245 unsigned int off, unsigned int cfg)
247 void __iomem *reg = chip->base;
248 unsigned int shift = (off & 7) * 4;
251 if (off < 8 && chip->chip.ngpio > 8)
254 if (samsung_gpio_is_cfg_special(cfg)) {
259 con = __raw_readl(reg);
260 con &= ~(0xf << shift);
262 __raw_writel(con, reg);
268 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
269 * @chip: The gpio chip that is being configured.
270 * @off: The offset for the GPIO being configured.
272 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
273 * register setting into a value the software can use, such as could be passed
274 * to samsung_gpio_setcfg_4bit().
276 * @sa samsung_gpio_getcfg_2bit
279 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
282 void __iomem *reg = chip->base;
283 unsigned int shift = (off & 7) * 4;
286 if (off < 8 && chip->chip.ngpio > 8)
289 con = __raw_readl(reg);
293 /* this conversion works for IN and OUT as well as special mode */
294 return S3C_GPIO_SPECIAL(con);
297 #ifdef CONFIG_PLAT_S3C24XX
299 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
300 * @chip: The gpio chip that is being configured.
301 * @off: The offset for the GPIO being configured.
302 * @cfg: The configuration value to set.
304 * This helper deal with the GPIO cases where the control register
305 * has one bit of configuration for the gpio, where setting the bit
306 * means the pin is in special function mode and unset means output.
309 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
310 unsigned int off, unsigned int cfg)
312 void __iomem *reg = chip->base;
313 unsigned int shift = off;
316 if (samsung_gpio_is_cfg_special(cfg)) {
319 /* Map output to 0, and SFN2 to 1 */
327 con = __raw_readl(reg);
328 con &= ~(0x1 << shift);
330 __raw_writel(con, reg);
336 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
337 * @chip: The gpio chip that is being configured.
338 * @off: The offset for the GPIO being configured.
340 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
341 * GPIO configuration value.
343 * @sa samsung_gpio_getcfg_2bit
344 * @sa samsung_gpio_getcfg_4bit
347 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
352 con = __raw_readl(chip->base);
357 return S3C_GPIO_SFN(con);
361 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
364 for (; nr_chips > 0; nr_chips--, chipcfg++) {
365 if (!chipcfg->set_config)
366 chipcfg->set_config = samsung_gpio_setcfg_4bit;
367 if (!chipcfg->get_config)
368 chipcfg->get_config = samsung_gpio_getcfg_4bit;
369 if (!chipcfg->set_pull)
370 chipcfg->set_pull = samsung_gpio_setpull_updown;
371 if (!chipcfg->get_pull)
372 chipcfg->get_pull = samsung_gpio_getpull_updown;
376 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
377 .set_config = samsung_gpio_setcfg_2bit,
378 .get_config = samsung_gpio_getcfg_2bit,
381 #ifdef CONFIG_PLAT_S3C24XX
382 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
383 .set_config = s3c24xx_gpio_setcfg_abank,
384 .get_config = s3c24xx_gpio_getcfg_abank,
388 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
403 .set_config = samsung_gpio_setcfg_2bit,
404 .get_config = samsung_gpio_getcfg_2bit,
408 .set_config = samsung_gpio_setcfg_2bit,
409 .get_config = samsung_gpio_getcfg_2bit,
413 .set_config = samsung_gpio_setcfg_2bit,
414 .get_config = samsung_gpio_getcfg_2bit,
417 .set_config = samsung_gpio_setcfg_2bit,
418 .get_config = samsung_gpio_getcfg_2bit,
423 * Default routines for controlling GPIO, based on the original S3C24XX
424 * GPIO functions which deal with the case where each gpio bank of the
425 * chip is as following:
427 * base + 0x00: Control register, 2 bits per gpio
428 * gpio n: 2 bits starting at (2*n)
429 * 00 = input, 01 = output, others mean special-function
430 * base + 0x04: Data register, 1 bit per gpio
434 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
436 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
437 void __iomem *base = ourchip->base;
441 samsung_gpio_lock(ourchip, flags);
443 con = __raw_readl(base + 0x00);
444 con &= ~(3 << (offset * 2));
446 __raw_writel(con, base + 0x00);
448 samsung_gpio_unlock(ourchip, flags);
452 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
453 unsigned offset, int value)
455 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
456 void __iomem *base = ourchip->base;
461 samsung_gpio_lock(ourchip, flags);
463 dat = __raw_readl(base + 0x04);
464 dat &= ~(1 << offset);
467 __raw_writel(dat, base + 0x04);
469 con = __raw_readl(base + 0x00);
470 con &= ~(3 << (offset * 2));
471 con |= 1 << (offset * 2);
473 __raw_writel(con, base + 0x00);
474 __raw_writel(dat, base + 0x04);
476 samsung_gpio_unlock(ourchip, flags);
481 * The samsung_gpiolib_4bit routines are to control the gpio banks where
482 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
485 * base + 0x00: Control register, 4 bits per gpio
486 * gpio n: 4 bits starting at (4*n)
487 * 0000 = input, 0001 = output, others mean special-function
488 * base + 0x04: Data register, 1 bit per gpio
491 * Note, since the data register is one bit per gpio and is at base + 0x4
492 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
493 * state of the output.
496 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
499 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
500 void __iomem *base = ourchip->base;
503 con = __raw_readl(base + GPIOCON_OFF);
504 if (ourchip->bitmap_gpio_int & BIT(offset))
505 con |= 0xf << con_4bit_shift(offset);
507 con &= ~(0xf << con_4bit_shift(offset));
508 __raw_writel(con, base + GPIOCON_OFF);
510 pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
515 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
516 unsigned int offset, int value)
518 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
519 void __iomem *base = ourchip->base;
523 con = __raw_readl(base + GPIOCON_OFF);
524 con &= ~(0xf << con_4bit_shift(offset));
525 con |= 0x1 << con_4bit_shift(offset);
527 dat = __raw_readl(base + GPIODAT_OFF);
532 dat &= ~(1 << offset);
534 __raw_writel(dat, base + GPIODAT_OFF);
535 __raw_writel(con, base + GPIOCON_OFF);
536 __raw_writel(dat, base + GPIODAT_OFF);
538 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
544 * The next set of routines are for the case where the GPIO configuration
545 * registers are 4 bits per GPIO but there is more than one register (the
546 * bank has more than 8 GPIOs.
548 * This case is the similar to the 4 bit case, but the registers are as
551 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
552 * gpio n: 4 bits starting at (4*n)
553 * 0000 = input, 0001 = output, others mean special-function
554 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
555 * gpio n: 4 bits starting at (4*n)
556 * 0000 = input, 0001 = output, others mean special-function
557 * base + 0x08: Data register, 1 bit per gpio
560 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
561 * routines we store the 'base + 0x4' address so that these routines see
562 * the data register at ourchip->base + 0x04.
565 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
568 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
569 void __iomem *base = ourchip->base;
570 void __iomem *regcon = base;
578 con = __raw_readl(regcon);
579 con &= ~(0xf << con_4bit_shift(offset));
580 __raw_writel(con, regcon);
582 pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
587 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
588 unsigned int offset, int value)
590 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
591 void __iomem *base = ourchip->base;
592 void __iomem *regcon = base;
595 unsigned con_offset = offset;
602 con = __raw_readl(regcon);
603 con &= ~(0xf << con_4bit_shift(con_offset));
604 con |= 0x1 << con_4bit_shift(con_offset);
606 dat = __raw_readl(base + GPIODAT_OFF);
611 dat &= ~(1 << offset);
613 __raw_writel(dat, base + GPIODAT_OFF);
614 __raw_writel(con, regcon);
615 __raw_writel(dat, base + GPIODAT_OFF);
617 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
622 #ifdef CONFIG_PLAT_S3C24XX
623 /* The next set of routines are for the case of s3c24xx bank a */
625 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
630 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
631 unsigned offset, int value)
633 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
634 void __iomem *base = ourchip->base;
639 local_irq_save(flags);
641 con = __raw_readl(base + 0x00);
642 dat = __raw_readl(base + 0x04);
644 dat &= ~(1 << offset);
648 __raw_writel(dat, base + 0x04);
650 con &= ~(1 << offset);
652 __raw_writel(con, base + 0x00);
653 __raw_writel(dat, base + 0x04);
655 local_irq_restore(flags);
660 static void samsung_gpiolib_set(struct gpio_chip *chip,
661 unsigned offset, int value)
663 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
664 void __iomem *base = ourchip->base;
668 samsung_gpio_lock(ourchip, flags);
670 dat = __raw_readl(base + 0x04);
671 dat &= ~(1 << offset);
674 __raw_writel(dat, base + 0x04);
676 samsung_gpio_unlock(ourchip, flags);
679 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
681 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
684 val = __raw_readl(ourchip->base + 0x04);
692 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
693 * for use with the configuration calls, and other parts of the s3c gpiolib
696 * Not all s3c support code will need this, as some configurations of cpu
697 * may only support one or two different configuration options and have an
698 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
699 * the machine support file should provide its own samsung_gpiolib_getchip()
700 * and any other necessary functions.
703 #ifdef CONFIG_S3C_GPIO_TRACK
704 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
706 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
711 gpn = chip->chip.base;
712 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
713 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
714 s3c_gpios[gpn] = chip;
717 #endif /* CONFIG_S3C_GPIO_TRACK */
720 * samsung_gpiolib_add() - add the Samsung gpio_chip.
721 * @chip: The chip to register
723 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
724 * information and makes the necessary alterations for the platform and
725 * notes the information for use with the configuration systems and any
726 * other parts of the system.
729 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
731 struct gpio_chip *gc = &chip->chip;
738 spin_lock_init(&chip->lock);
740 if (!gc->direction_input)
741 gc->direction_input = samsung_gpiolib_2bit_input;
742 if (!gc->direction_output)
743 gc->direction_output = samsung_gpiolib_2bit_output;
745 gc->set = samsung_gpiolib_set;
747 gc->get = samsung_gpiolib_get;
750 if (chip->pm != NULL) {
751 if (!chip->pm->save || !chip->pm->resume)
752 pr_err("gpio: %s has missing PM functions\n",
755 pr_err("gpio: %s has no PM function\n", gc->label);
758 /* gpiochip_add() prints own failure message on error. */
759 ret = gpiochip_add(gc);
761 s3c_gpiolib_track(chip);
764 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
765 int nr_chips, void __iomem *base)
768 struct gpio_chip *gc = &chip->chip;
770 for (i = 0 ; i < nr_chips; i++, chip++) {
771 /* skip banks not present on SoC */
772 if (chip->chip.base >= S3C_GPIO_END)
776 chip->config = &s3c24xx_gpiocfg_default;
778 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
779 if ((base != NULL) && (chip->base == NULL))
780 chip->base = base + ((i) * 0x10);
782 if (!gc->direction_input)
783 gc->direction_input = samsung_gpiolib_2bit_input;
784 if (!gc->direction_output)
785 gc->direction_output = samsung_gpiolib_2bit_output;
787 samsung_gpiolib_add(chip);
791 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
792 int nr_chips, void __iomem *base,
797 for (i = 0 ; i < nr_chips; i++, chip++) {
798 chip->chip.direction_input = samsung_gpiolib_2bit_input;
799 chip->chip.direction_output = samsung_gpiolib_2bit_output;
802 chip->config = &samsung_gpio_cfgs[7];
804 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
805 if ((base != NULL) && (chip->base == NULL))
806 chip->base = base + ((i) * offset);
808 samsung_gpiolib_add(chip);
813 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
814 * @chip: The gpio chip that is being configured.
815 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
817 * This helper deal with the GPIO cases where the control register has 4 bits
818 * of control per GPIO, generally in the form of:
821 * others = Special functions (dependent on bank)
823 * Note, since the code to deal with the case where there are two control
824 * registers instead of one, we do not have a separate set of function
825 * (samsung_gpiolib_add_4bit2_chips)for each case.
828 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
829 int nr_chips, void __iomem *base)
833 for (i = 0 ; i < nr_chips; i++, chip++) {
834 chip->chip.direction_input = samsung_gpiolib_4bit_input;
835 chip->chip.direction_output = samsung_gpiolib_4bit_output;
838 chip->config = &samsung_gpio_cfgs[2];
840 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
841 if ((base != NULL) && (chip->base == NULL))
842 chip->base = base + ((i) * 0x20);
844 chip->bitmap_gpio_int = 0;
846 samsung_gpiolib_add(chip);
850 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
853 for (; nr_chips > 0; nr_chips--, chip++) {
854 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
855 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
858 chip->config = &samsung_gpio_cfgs[2];
860 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
862 samsung_gpiolib_add(chip);
866 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
868 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
870 return samsung_chip->irq_base + offset;
873 #ifdef CONFIG_PLAT_S3C24XX
874 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
877 if (soc_is_s3c2412())
878 return IRQ_EINT0_2412 + offset;
880 return IRQ_EINT0 + offset;
884 return IRQ_EINT4 + offset - 4;
890 #ifdef CONFIG_ARCH_S3C64XX
891 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
893 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
896 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
898 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
902 struct samsung_gpio_chip s3c24xx_gpios[] = {
903 #ifdef CONFIG_PLAT_S3C24XX
905 .config = &s3c24xx_gpiocfg_banka,
907 .base = S3C2410_GPA(0),
908 .owner = THIS_MODULE,
911 .direction_input = s3c24xx_gpiolib_banka_input,
912 .direction_output = s3c24xx_gpiolib_banka_output,
916 .base = S3C2410_GPB(0),
917 .owner = THIS_MODULE,
923 .base = S3C2410_GPC(0),
924 .owner = THIS_MODULE,
930 .base = S3C2410_GPD(0),
931 .owner = THIS_MODULE,
937 .base = S3C2410_GPE(0),
939 .owner = THIS_MODULE,
944 .base = S3C2410_GPF(0),
945 .owner = THIS_MODULE,
948 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
951 .irq_base = IRQ_EINT8,
953 .base = S3C2410_GPG(0),
954 .owner = THIS_MODULE,
957 .to_irq = samsung_gpiolib_to_irq,
961 .base = S3C2410_GPH(0),
962 .owner = THIS_MODULE,
967 /* GPIOS for the S3C2443 and later devices. */
969 .base = S3C2440_GPJCON,
971 .base = S3C2410_GPJ(0),
972 .owner = THIS_MODULE,
977 .base = S3C2443_GPKCON,
979 .base = S3C2410_GPK(0),
980 .owner = THIS_MODULE,
985 .base = S3C2443_GPLCON,
987 .base = S3C2410_GPL(0),
988 .owner = THIS_MODULE,
993 .base = S3C2443_GPMCON,
995 .base = S3C2410_GPM(0),
996 .owner = THIS_MODULE,
1005 * GPIO bank summary:
1007 * Bank GPIOs Style SlpCon ExtInt Group
1013 * F 16 2Bit Yes 4 [1]
1015 * H 10 4Bit[2] Yes 6
1016 * I 16 2Bit Yes None
1017 * J 12 2Bit Yes None
1018 * K 16 4Bit[2] No None
1019 * L 15 4Bit[2] No None
1020 * M 6 4Bit No IRQ_EINT
1021 * N 16 2Bit No IRQ_EINT
1026 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1027 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1030 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1031 #ifdef CONFIG_ARCH_S3C64XX
1034 .base = S3C64XX_GPA(0),
1035 .ngpio = S3C64XX_GPIO_A_NR,
1040 .base = S3C64XX_GPB(0),
1041 .ngpio = S3C64XX_GPIO_B_NR,
1046 .base = S3C64XX_GPC(0),
1047 .ngpio = S3C64XX_GPIO_C_NR,
1052 .base = S3C64XX_GPD(0),
1053 .ngpio = S3C64XX_GPIO_D_NR,
1057 .config = &samsung_gpio_cfgs[0],
1059 .base = S3C64XX_GPE(0),
1060 .ngpio = S3C64XX_GPIO_E_NR,
1064 .base = S3C64XX_GPG_BASE,
1066 .base = S3C64XX_GPG(0),
1067 .ngpio = S3C64XX_GPIO_G_NR,
1071 .base = S3C64XX_GPM_BASE,
1072 .config = &samsung_gpio_cfgs[1],
1074 .base = S3C64XX_GPM(0),
1075 .ngpio = S3C64XX_GPIO_M_NR,
1077 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1083 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1084 #ifdef CONFIG_ARCH_S3C64XX
1086 .base = S3C64XX_GPH_BASE + 0x4,
1088 .base = S3C64XX_GPH(0),
1089 .ngpio = S3C64XX_GPIO_H_NR,
1093 .base = S3C64XX_GPK_BASE + 0x4,
1094 .config = &samsung_gpio_cfgs[0],
1096 .base = S3C64XX_GPK(0),
1097 .ngpio = S3C64XX_GPIO_K_NR,
1101 .base = S3C64XX_GPL_BASE + 0x4,
1102 .config = &samsung_gpio_cfgs[1],
1104 .base = S3C64XX_GPL(0),
1105 .ngpio = S3C64XX_GPIO_L_NR,
1107 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1113 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1114 #ifdef CONFIG_ARCH_S3C64XX
1116 .base = S3C64XX_GPF_BASE,
1117 .config = &samsung_gpio_cfgs[6],
1119 .base = S3C64XX_GPF(0),
1120 .ngpio = S3C64XX_GPIO_F_NR,
1124 .config = &samsung_gpio_cfgs[7],
1126 .base = S3C64XX_GPI(0),
1127 .ngpio = S3C64XX_GPIO_I_NR,
1131 .config = &samsung_gpio_cfgs[7],
1133 .base = S3C64XX_GPJ(0),
1134 .ngpio = S3C64XX_GPIO_J_NR,
1138 .config = &samsung_gpio_cfgs[6],
1140 .base = S3C64XX_GPO(0),
1141 .ngpio = S3C64XX_GPIO_O_NR,
1145 .config = &samsung_gpio_cfgs[6],
1147 .base = S3C64XX_GPP(0),
1148 .ngpio = S3C64XX_GPIO_P_NR,
1152 .config = &samsung_gpio_cfgs[6],
1154 .base = S3C64XX_GPQ(0),
1155 .ngpio = S3C64XX_GPIO_Q_NR,
1159 .base = S3C64XX_GPN_BASE,
1160 .irq_base = IRQ_EINT(0),
1161 .config = &samsung_gpio_cfgs[5],
1163 .base = S3C64XX_GPN(0),
1164 .ngpio = S3C64XX_GPIO_N_NR,
1166 .to_irq = samsung_gpiolib_to_irq,
1173 * S5PC100 GPIO bank summary:
1175 * Bank GPIOs Style INT Type
1176 * A0 8 4Bit GPIO_INT0
1177 * A1 5 4Bit GPIO_INT1
1178 * B 8 4Bit GPIO_INT2
1179 * C 5 4Bit GPIO_INT3
1180 * D 7 4Bit GPIO_INT4
1181 * E0 8 4Bit GPIO_INT5
1182 * E1 6 4Bit GPIO_INT6
1183 * F0 8 4Bit GPIO_INT7
1184 * F1 8 4Bit GPIO_INT8
1185 * F2 8 4Bit GPIO_INT9
1186 * F3 4 4Bit GPIO_INT10
1187 * G0 8 4Bit GPIO_INT11
1188 * G1 3 4Bit GPIO_INT12
1189 * G2 7 4Bit GPIO_INT13
1190 * G3 7 4Bit GPIO_INT14
1191 * H0 8 4Bit WKUP_INT
1192 * H1 8 4Bit WKUP_INT
1193 * H2 8 4Bit WKUP_INT
1194 * H3 8 4Bit WKUP_INT
1195 * I 8 4Bit GPIO_INT15
1196 * J0 8 4Bit GPIO_INT16
1197 * J1 5 4Bit GPIO_INT17
1198 * J2 8 4Bit GPIO_INT18
1199 * J3 8 4Bit GPIO_INT19
1200 * J4 4 4Bit GPIO_INT20
1211 static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1212 #ifdef CONFIG_CPU_S5PC100
1215 .base = S5PC100_GPA0(0),
1216 .ngpio = S5PC100_GPIO_A0_NR,
1221 .base = S5PC100_GPA1(0),
1222 .ngpio = S5PC100_GPIO_A1_NR,
1227 .base = S5PC100_GPB(0),
1228 .ngpio = S5PC100_GPIO_B_NR,
1233 .base = S5PC100_GPC(0),
1234 .ngpio = S5PC100_GPIO_C_NR,
1239 .base = S5PC100_GPD(0),
1240 .ngpio = S5PC100_GPIO_D_NR,
1245 .base = S5PC100_GPE0(0),
1246 .ngpio = S5PC100_GPIO_E0_NR,
1251 .base = S5PC100_GPE1(0),
1252 .ngpio = S5PC100_GPIO_E1_NR,
1257 .base = S5PC100_GPF0(0),
1258 .ngpio = S5PC100_GPIO_F0_NR,
1263 .base = S5PC100_GPF1(0),
1264 .ngpio = S5PC100_GPIO_F1_NR,
1269 .base = S5PC100_GPF2(0),
1270 .ngpio = S5PC100_GPIO_F2_NR,
1275 .base = S5PC100_GPF3(0),
1276 .ngpio = S5PC100_GPIO_F3_NR,
1281 .base = S5PC100_GPG0(0),
1282 .ngpio = S5PC100_GPIO_G0_NR,
1287 .base = S5PC100_GPG1(0),
1288 .ngpio = S5PC100_GPIO_G1_NR,
1293 .base = S5PC100_GPG2(0),
1294 .ngpio = S5PC100_GPIO_G2_NR,
1299 .base = S5PC100_GPG3(0),
1300 .ngpio = S5PC100_GPIO_G3_NR,
1305 .base = S5PC100_GPI(0),
1306 .ngpio = S5PC100_GPIO_I_NR,
1311 .base = S5PC100_GPJ0(0),
1312 .ngpio = S5PC100_GPIO_J0_NR,
1317 .base = S5PC100_GPJ1(0),
1318 .ngpio = S5PC100_GPIO_J1_NR,
1323 .base = S5PC100_GPJ2(0),
1324 .ngpio = S5PC100_GPIO_J2_NR,
1329 .base = S5PC100_GPJ3(0),
1330 .ngpio = S5PC100_GPIO_J3_NR,
1335 .base = S5PC100_GPJ4(0),
1336 .ngpio = S5PC100_GPIO_J4_NR,
1341 .base = S5PC100_GPK0(0),
1342 .ngpio = S5PC100_GPIO_K0_NR,
1347 .base = S5PC100_GPK1(0),
1348 .ngpio = S5PC100_GPIO_K1_NR,
1353 .base = S5PC100_GPK2(0),
1354 .ngpio = S5PC100_GPIO_K2_NR,
1359 .base = S5PC100_GPK3(0),
1360 .ngpio = S5PC100_GPIO_K3_NR,
1365 .base = S5PC100_GPL0(0),
1366 .ngpio = S5PC100_GPIO_L0_NR,
1371 .base = S5PC100_GPL1(0),
1372 .ngpio = S5PC100_GPIO_L1_NR,
1377 .base = S5PC100_GPL2(0),
1378 .ngpio = S5PC100_GPIO_L2_NR,
1383 .base = S5PC100_GPL3(0),
1384 .ngpio = S5PC100_GPIO_L3_NR,
1389 .base = S5PC100_GPL4(0),
1390 .ngpio = S5PC100_GPIO_L4_NR,
1394 .base = (S5P_VA_GPIO + 0xC00),
1395 .irq_base = IRQ_EINT(0),
1397 .base = S5PC100_GPH0(0),
1398 .ngpio = S5PC100_GPIO_H0_NR,
1400 .to_irq = samsung_gpiolib_to_irq,
1403 .base = (S5P_VA_GPIO + 0xC20),
1404 .irq_base = IRQ_EINT(8),
1406 .base = S5PC100_GPH1(0),
1407 .ngpio = S5PC100_GPIO_H1_NR,
1409 .to_irq = samsung_gpiolib_to_irq,
1412 .base = (S5P_VA_GPIO + 0xC40),
1413 .irq_base = IRQ_EINT(16),
1415 .base = S5PC100_GPH2(0),
1416 .ngpio = S5PC100_GPIO_H2_NR,
1418 .to_irq = samsung_gpiolib_to_irq,
1421 .base = (S5P_VA_GPIO + 0xC60),
1422 .irq_base = IRQ_EINT(24),
1424 .base = S5PC100_GPH3(0),
1425 .ngpio = S5PC100_GPIO_H3_NR,
1427 .to_irq = samsung_gpiolib_to_irq,
1434 * Followings are the gpio banks in S5PV210/S5PC110
1436 * The 'config' member when left to NULL, is initialized to the default
1437 * structure samsung_gpio_cfgs[3] in the init function below.
1439 * The 'base' member is also initialized in the init function below.
1440 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1441 * uses the above macro and depends on the banks being listed in order here.
1444 static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1445 #ifdef CONFIG_CPU_S5PV210
1448 .base = S5PV210_GPA0(0),
1449 .ngpio = S5PV210_GPIO_A0_NR,
1454 .base = S5PV210_GPA1(0),
1455 .ngpio = S5PV210_GPIO_A1_NR,
1460 .base = S5PV210_GPB(0),
1461 .ngpio = S5PV210_GPIO_B_NR,
1466 .base = S5PV210_GPC0(0),
1467 .ngpio = S5PV210_GPIO_C0_NR,
1472 .base = S5PV210_GPC1(0),
1473 .ngpio = S5PV210_GPIO_C1_NR,
1478 .base = S5PV210_GPD0(0),
1479 .ngpio = S5PV210_GPIO_D0_NR,
1484 .base = S5PV210_GPD1(0),
1485 .ngpio = S5PV210_GPIO_D1_NR,
1490 .base = S5PV210_GPE0(0),
1491 .ngpio = S5PV210_GPIO_E0_NR,
1496 .base = S5PV210_GPE1(0),
1497 .ngpio = S5PV210_GPIO_E1_NR,
1502 .base = S5PV210_GPF0(0),
1503 .ngpio = S5PV210_GPIO_F0_NR,
1508 .base = S5PV210_GPF1(0),
1509 .ngpio = S5PV210_GPIO_F1_NR,
1514 .base = S5PV210_GPF2(0),
1515 .ngpio = S5PV210_GPIO_F2_NR,
1520 .base = S5PV210_GPF3(0),
1521 .ngpio = S5PV210_GPIO_F3_NR,
1526 .base = S5PV210_GPG0(0),
1527 .ngpio = S5PV210_GPIO_G0_NR,
1532 .base = S5PV210_GPG1(0),
1533 .ngpio = S5PV210_GPIO_G1_NR,
1538 .base = S5PV210_GPG2(0),
1539 .ngpio = S5PV210_GPIO_G2_NR,
1544 .base = S5PV210_GPG3(0),
1545 .ngpio = S5PV210_GPIO_G3_NR,
1550 .base = S5PV210_GPI(0),
1551 .ngpio = S5PV210_GPIO_I_NR,
1556 .base = S5PV210_GPJ0(0),
1557 .ngpio = S5PV210_GPIO_J0_NR,
1562 .base = S5PV210_GPJ1(0),
1563 .ngpio = S5PV210_GPIO_J1_NR,
1568 .base = S5PV210_GPJ2(0),
1569 .ngpio = S5PV210_GPIO_J2_NR,
1574 .base = S5PV210_GPJ3(0),
1575 .ngpio = S5PV210_GPIO_J3_NR,
1580 .base = S5PV210_GPJ4(0),
1581 .ngpio = S5PV210_GPIO_J4_NR,
1586 .base = S5PV210_MP01(0),
1587 .ngpio = S5PV210_GPIO_MP01_NR,
1592 .base = S5PV210_MP02(0),
1593 .ngpio = S5PV210_GPIO_MP02_NR,
1598 .base = S5PV210_MP03(0),
1599 .ngpio = S5PV210_GPIO_MP03_NR,
1604 .base = S5PV210_MP04(0),
1605 .ngpio = S5PV210_GPIO_MP04_NR,
1610 .base = S5PV210_MP05(0),
1611 .ngpio = S5PV210_GPIO_MP05_NR,
1615 .base = (S5P_VA_GPIO + 0xC00),
1616 .irq_base = IRQ_EINT(0),
1618 .base = S5PV210_GPH0(0),
1619 .ngpio = S5PV210_GPIO_H0_NR,
1621 .to_irq = samsung_gpiolib_to_irq,
1624 .base = (S5P_VA_GPIO + 0xC20),
1625 .irq_base = IRQ_EINT(8),
1627 .base = S5PV210_GPH1(0),
1628 .ngpio = S5PV210_GPIO_H1_NR,
1630 .to_irq = samsung_gpiolib_to_irq,
1633 .base = (S5P_VA_GPIO + 0xC40),
1634 .irq_base = IRQ_EINT(16),
1636 .base = S5PV210_GPH2(0),
1637 .ngpio = S5PV210_GPIO_H2_NR,
1639 .to_irq = samsung_gpiolib_to_irq,
1642 .base = (S5P_VA_GPIO + 0xC60),
1643 .irq_base = IRQ_EINT(24),
1645 .base = S5PV210_GPH3(0),
1646 .ngpio = S5PV210_GPIO_H3_NR,
1648 .to_irq = samsung_gpiolib_to_irq,
1654 /* TODO: cleanup soc_is_* */
1655 static __init int samsung_gpiolib_init(void)
1657 struct samsung_gpio_chip *chip;
1662 * Currently there are two drivers that can provide GPIO support for
1663 * Samsung SoCs. For device tree enabled platforms, the new
1664 * pinctrl-samsung driver is used, providing both GPIO and pin control
1665 * interfaces. For legacy (non-DT) platforms this driver is used.
1667 if (of_have_populated_dt())
1670 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
1672 if (soc_is_s3c24xx()) {
1673 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
1674 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
1675 } else if (soc_is_s3c64xx()) {
1676 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
1677 ARRAY_SIZE(s3c64xx_gpios_2bit),
1678 S3C64XX_VA_GPIO + 0xE0, 0x20);
1679 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
1680 ARRAY_SIZE(s3c64xx_gpios_4bit),
1682 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
1683 ARRAY_SIZE(s3c64xx_gpios_4bit2));
1684 } else if (soc_is_s5pc100()) {
1686 chip = s5pc100_gpios_4bit;
1687 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
1689 for (i = 0; i < nr_chips; i++, chip++) {
1690 if (!chip->config) {
1691 chip->config = &samsung_gpio_cfgs[3];
1692 chip->group = group++;
1695 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
1696 #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
1697 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
1699 } else if (soc_is_s5pv210()) {
1701 chip = s5pv210_gpios_4bit;
1702 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
1704 for (i = 0; i < nr_chips; i++, chip++) {
1705 if (!chip->config) {
1706 chip->config = &samsung_gpio_cfgs[3];
1707 chip->group = group++;
1710 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
1711 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
1712 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
1715 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
1721 core_initcall(samsung_gpiolib_init);
1723 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
1725 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1726 unsigned long flags;
1733 offset = pin - chip->chip.base;
1735 samsung_gpio_lock(chip, flags);
1736 ret = samsung_gpio_do_setcfg(chip, offset, config);
1737 samsung_gpio_unlock(chip, flags);
1741 EXPORT_SYMBOL(s3c_gpio_cfgpin);
1743 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
1748 for (; nr > 0; nr--, start++) {
1749 ret = s3c_gpio_cfgpin(start, cfg);
1756 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
1758 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
1759 unsigned int cfg, samsung_gpio_pull_t pull)
1763 for (; nr > 0; nr--, start++) {
1764 s3c_gpio_setpull(start, pull);
1765 ret = s3c_gpio_cfgpin(start, cfg);
1772 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
1774 unsigned s3c_gpio_getcfg(unsigned int pin)
1776 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1777 unsigned long flags;
1782 offset = pin - chip->chip.base;
1784 samsung_gpio_lock(chip, flags);
1785 ret = samsung_gpio_do_getcfg(chip, offset);
1786 samsung_gpio_unlock(chip, flags);
1791 EXPORT_SYMBOL(s3c_gpio_getcfg);
1793 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
1795 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1796 unsigned long flags;
1802 offset = pin - chip->chip.base;
1804 samsung_gpio_lock(chip, flags);
1805 ret = samsung_gpio_do_setpull(chip, offset, pull);
1806 samsung_gpio_unlock(chip, flags);
1810 EXPORT_SYMBOL(s3c_gpio_setpull);
1812 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
1814 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1815 unsigned long flags;
1820 offset = pin - chip->chip.base;
1822 samsung_gpio_lock(chip, flags);
1823 pup = samsung_gpio_do_getpull(chip, offset);
1824 samsung_gpio_unlock(chip, flags);
1827 return (__force samsung_gpio_pull_t)pup;
1829 EXPORT_SYMBOL(s3c_gpio_getpull);
1831 #ifdef CONFIG_S5P_GPIO_DRVSTR
1832 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
1834 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1843 off = pin - chip->chip.base;
1845 reg = chip->base + 0x0C;
1847 drvstr = __raw_readl(reg);
1848 drvstr = drvstr >> shift;
1851 return (__force s5p_gpio_drvstr_t)drvstr;
1853 EXPORT_SYMBOL(s5p_gpio_get_drvstr);
1855 int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
1857 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1866 off = pin - chip->chip.base;
1868 reg = chip->base + 0x0C;
1870 tmp = __raw_readl(reg);
1871 tmp &= ~(0x3 << shift);
1872 tmp |= drvstr << shift;
1874 __raw_writel(tmp, reg);
1878 EXPORT_SYMBOL(s5p_gpio_set_drvstr);
1879 #endif /* CONFIG_S5P_GPIO_DRVSTR */
1881 #ifdef CONFIG_PLAT_S3C24XX
1882 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
1884 unsigned long flags;
1885 unsigned long misccr;
1887 local_irq_save(flags);
1888 misccr = __raw_readl(S3C24XX_MISCCR);
1891 __raw_writel(misccr, S3C24XX_MISCCR);
1892 local_irq_restore(flags);
1896 EXPORT_SYMBOL(s3c2410_modify_misccr);