2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * SAMSUNG - GPIOlib support
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/of_address.h>
33 #include <mach/hardware.h>
35 #include <mach/regs-gpio.h>
38 #include <plat/gpio-core.h>
39 #include <plat/gpio-cfg.h>
40 #include <plat/gpio-cfg-helpers.h>
43 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
44 unsigned int off, samsung_gpio_pull_t pull)
46 void __iomem *reg = chip->base + 0x08;
50 pup = __raw_readl(reg);
53 __raw_writel(pup, reg);
58 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
61 void __iomem *reg = chip->base + 0x08;
63 u32 pup = __raw_readl(reg);
68 return (__force samsung_gpio_pull_t)pup;
71 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
72 unsigned int off, samsung_gpio_pull_t pull)
75 case S3C_GPIO_PULL_NONE:
78 case S3C_GPIO_PULL_UP:
81 case S3C_GPIO_PULL_DOWN:
85 return samsung_gpio_setpull_updown(chip, off, pull);
88 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
91 samsung_gpio_pull_t pull;
93 pull = samsung_gpio_getpull_updown(chip, off);
97 pull = S3C_GPIO_PULL_UP;
101 pull = S3C_GPIO_PULL_NONE;
104 pull = S3C_GPIO_PULL_DOWN;
111 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
112 unsigned int off, samsung_gpio_pull_t pull,
113 samsung_gpio_pull_t updown)
115 void __iomem *reg = chip->base + 0x08;
116 u32 pup = __raw_readl(reg);
120 else if (pull == S3C_GPIO_PULL_NONE)
125 __raw_writel(pup, reg);
129 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
131 samsung_gpio_pull_t updown)
133 void __iomem *reg = chip->base + 0x08;
134 u32 pup = __raw_readl(reg);
137 return pup ? S3C_GPIO_PULL_NONE : updown;
140 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
143 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
146 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
147 unsigned int off, samsung_gpio_pull_t pull)
149 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
152 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
155 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
158 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
159 unsigned int off, samsung_gpio_pull_t pull)
161 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
165 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
166 * @chip: The gpio chip that is being configured.
167 * @off: The offset for the GPIO being configured.
168 * @cfg: The configuration value to set.
170 * This helper deal with the GPIO cases where the control register
171 * has two bits of configuration per gpio, which have the following
175 * 1x = special function
178 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
179 unsigned int off, unsigned int cfg)
181 void __iomem *reg = chip->base;
182 unsigned int shift = off * 2;
185 if (samsung_gpio_is_cfg_special(cfg)) {
193 con = __raw_readl(reg);
194 con &= ~(0x3 << shift);
196 __raw_writel(con, reg);
202 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
203 * @chip: The gpio chip that is being configured.
204 * @off: The offset for the GPIO being configured.
206 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
207 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
208 * S3C_GPIO_SPECIAL() macro.
211 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
216 con = __raw_readl(chip->base);
220 /* this conversion works for IN and OUT as well as special mode */
221 return S3C_GPIO_SPECIAL(con);
225 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
226 * @chip: The gpio chip that is being configured.
227 * @off: The offset for the GPIO being configured.
228 * @cfg: The configuration value to set.
230 * This helper deal with the GPIO cases where the control register has 4 bits
231 * of control per GPIO, generally in the form of:
234 * others = Special functions (dependent on bank)
236 * Note, since the code to deal with the case where there are two control
237 * registers instead of one, we do not have a separate set of functions for
241 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
242 unsigned int off, unsigned int cfg)
244 void __iomem *reg = chip->base;
245 unsigned int shift = (off & 7) * 4;
248 if (off < 8 && chip->chip.ngpio > 8)
251 if (samsung_gpio_is_cfg_special(cfg)) {
256 con = __raw_readl(reg);
257 con &= ~(0xf << shift);
259 __raw_writel(con, reg);
265 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
266 * @chip: The gpio chip that is being configured.
267 * @off: The offset for the GPIO being configured.
269 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
270 * register setting into a value the software can use, such as could be passed
271 * to samsung_gpio_setcfg_4bit().
273 * @sa samsung_gpio_getcfg_2bit
276 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
279 void __iomem *reg = chip->base;
280 unsigned int shift = (off & 7) * 4;
283 if (off < 8 && chip->chip.ngpio > 8)
286 con = __raw_readl(reg);
290 /* this conversion works for IN and OUT as well as special mode */
291 return S3C_GPIO_SPECIAL(con);
294 #ifdef CONFIG_PLAT_S3C24XX
296 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
297 * @chip: The gpio chip that is being configured.
298 * @off: The offset for the GPIO being configured.
299 * @cfg: The configuration value to set.
301 * This helper deal with the GPIO cases where the control register
302 * has one bit of configuration for the gpio, where setting the bit
303 * means the pin is in special function mode and unset means output.
306 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
307 unsigned int off, unsigned int cfg)
309 void __iomem *reg = chip->base;
310 unsigned int shift = off;
313 if (samsung_gpio_is_cfg_special(cfg)) {
316 /* Map output to 0, and SFN2 to 1 */
324 con = __raw_readl(reg);
325 con &= ~(0x1 << shift);
327 __raw_writel(con, reg);
333 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
334 * @chip: The gpio chip that is being configured.
335 * @off: The offset for the GPIO being configured.
337 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
338 * GPIO configuration value.
340 * @sa samsung_gpio_getcfg_2bit
341 * @sa samsung_gpio_getcfg_4bit
344 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
349 con = __raw_readl(chip->base);
354 return S3C_GPIO_SFN(con);
358 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
359 static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
360 unsigned int off, unsigned int cfg)
362 void __iomem *reg = chip->base;
373 shift = (off & 7) * 4;
377 shift = ((off + 1) & 7) * 4;
380 shift = ((off + 1) & 7) * 4;
384 if (samsung_gpio_is_cfg_special(cfg)) {
389 con = __raw_readl(reg);
390 con &= ~(0xf << shift);
392 __raw_writel(con, reg);
398 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
401 for (; nr_chips > 0; nr_chips--, chipcfg++) {
402 if (!chipcfg->set_config)
403 chipcfg->set_config = samsung_gpio_setcfg_4bit;
404 if (!chipcfg->get_config)
405 chipcfg->get_config = samsung_gpio_getcfg_4bit;
406 if (!chipcfg->set_pull)
407 chipcfg->set_pull = samsung_gpio_setpull_updown;
408 if (!chipcfg->get_pull)
409 chipcfg->get_pull = samsung_gpio_getpull_updown;
413 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
414 .set_config = samsung_gpio_setcfg_2bit,
415 .get_config = samsung_gpio_getcfg_2bit,
418 #ifdef CONFIG_PLAT_S3C24XX
419 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
420 .set_config = s3c24xx_gpio_setcfg_abank,
421 .get_config = s3c24xx_gpio_getcfg_abank,
425 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
426 static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
428 .set_config = s5p64x0_gpio_setcfg_rbank,
429 .get_config = samsung_gpio_getcfg_4bit,
430 .set_pull = samsung_gpio_setpull_updown,
431 .get_pull = samsung_gpio_getpull_updown,
435 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
450 .set_config = samsung_gpio_setcfg_2bit,
451 .get_config = samsung_gpio_getcfg_2bit,
455 .set_config = samsung_gpio_setcfg_2bit,
456 .get_config = samsung_gpio_getcfg_2bit,
460 .set_config = samsung_gpio_setcfg_2bit,
461 .get_config = samsung_gpio_getcfg_2bit,
464 .set_config = samsung_gpio_setcfg_2bit,
465 .get_config = samsung_gpio_getcfg_2bit,
470 * Default routines for controlling GPIO, based on the original S3C24XX
471 * GPIO functions which deal with the case where each gpio bank of the
472 * chip is as following:
474 * base + 0x00: Control register, 2 bits per gpio
475 * gpio n: 2 bits starting at (2*n)
476 * 00 = input, 01 = output, others mean special-function
477 * base + 0x04: Data register, 1 bit per gpio
481 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
483 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
484 void __iomem *base = ourchip->base;
488 samsung_gpio_lock(ourchip, flags);
490 con = __raw_readl(base + 0x00);
491 con &= ~(3 << (offset * 2));
493 __raw_writel(con, base + 0x00);
495 samsung_gpio_unlock(ourchip, flags);
499 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
500 unsigned offset, int value)
502 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
503 void __iomem *base = ourchip->base;
508 samsung_gpio_lock(ourchip, flags);
510 dat = __raw_readl(base + 0x04);
511 dat &= ~(1 << offset);
514 __raw_writel(dat, base + 0x04);
516 con = __raw_readl(base + 0x00);
517 con &= ~(3 << (offset * 2));
518 con |= 1 << (offset * 2);
520 __raw_writel(con, base + 0x00);
521 __raw_writel(dat, base + 0x04);
523 samsung_gpio_unlock(ourchip, flags);
528 * The samsung_gpiolib_4bit routines are to control the gpio banks where
529 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
532 * base + 0x00: Control register, 4 bits per gpio
533 * gpio n: 4 bits starting at (4*n)
534 * 0000 = input, 0001 = output, others mean special-function
535 * base + 0x04: Data register, 1 bit per gpio
538 * Note, since the data register is one bit per gpio and is at base + 0x4
539 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
540 * state of the output.
543 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
546 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
547 void __iomem *base = ourchip->base;
550 con = __raw_readl(base + GPIOCON_OFF);
551 if (ourchip->bitmap_gpio_int & BIT(offset))
552 con |= 0xf << con_4bit_shift(offset);
554 con &= ~(0xf << con_4bit_shift(offset));
555 __raw_writel(con, base + GPIOCON_OFF);
557 pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
562 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
563 unsigned int offset, int value)
565 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
566 void __iomem *base = ourchip->base;
570 con = __raw_readl(base + GPIOCON_OFF);
571 con &= ~(0xf << con_4bit_shift(offset));
572 con |= 0x1 << con_4bit_shift(offset);
574 dat = __raw_readl(base + GPIODAT_OFF);
579 dat &= ~(1 << offset);
581 __raw_writel(dat, base + GPIODAT_OFF);
582 __raw_writel(con, base + GPIOCON_OFF);
583 __raw_writel(dat, base + GPIODAT_OFF);
585 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
591 * The next set of routines are for the case where the GPIO configuration
592 * registers are 4 bits per GPIO but there is more than one register (the
593 * bank has more than 8 GPIOs.
595 * This case is the similar to the 4 bit case, but the registers are as
598 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
599 * gpio n: 4 bits starting at (4*n)
600 * 0000 = input, 0001 = output, others mean special-function
601 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
602 * gpio n: 4 bits starting at (4*n)
603 * 0000 = input, 0001 = output, others mean special-function
604 * base + 0x08: Data register, 1 bit per gpio
607 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
608 * routines we store the 'base + 0x4' address so that these routines see
609 * the data register at ourchip->base + 0x04.
612 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
615 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
616 void __iomem *base = ourchip->base;
617 void __iomem *regcon = base;
625 con = __raw_readl(regcon);
626 con &= ~(0xf << con_4bit_shift(offset));
627 __raw_writel(con, regcon);
629 pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
634 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
635 unsigned int offset, int value)
637 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
638 void __iomem *base = ourchip->base;
639 void __iomem *regcon = base;
642 unsigned con_offset = offset;
649 con = __raw_readl(regcon);
650 con &= ~(0xf << con_4bit_shift(con_offset));
651 con |= 0x1 << con_4bit_shift(con_offset);
653 dat = __raw_readl(base + GPIODAT_OFF);
658 dat &= ~(1 << offset);
660 __raw_writel(dat, base + GPIODAT_OFF);
661 __raw_writel(con, regcon);
662 __raw_writel(dat, base + GPIODAT_OFF);
664 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
669 #ifdef CONFIG_PLAT_S3C24XX
670 /* The next set of routines are for the case of s3c24xx bank a */
672 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
677 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
678 unsigned offset, int value)
680 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
681 void __iomem *base = ourchip->base;
686 local_irq_save(flags);
688 con = __raw_readl(base + 0x00);
689 dat = __raw_readl(base + 0x04);
691 dat &= ~(1 << offset);
695 __raw_writel(dat, base + 0x04);
697 con &= ~(1 << offset);
699 __raw_writel(con, base + 0x00);
700 __raw_writel(dat, base + 0x04);
702 local_irq_restore(flags);
707 /* The next set of routines are for the case of s5p64x0 bank r */
709 static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
712 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
713 void __iomem *base = ourchip->base;
714 void __iomem *regcon = base;
734 samsung_gpio_lock(ourchip, flags);
736 con = __raw_readl(regcon);
737 con &= ~(0xf << con_4bit_shift(offset));
738 __raw_writel(con, regcon);
740 samsung_gpio_unlock(ourchip, flags);
745 static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
746 unsigned int offset, int value)
748 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
749 void __iomem *base = ourchip->base;
750 void __iomem *regcon = base;
754 unsigned con_offset = offset;
756 switch (con_offset) {
772 samsung_gpio_lock(ourchip, flags);
774 con = __raw_readl(regcon);
775 con &= ~(0xf << con_4bit_shift(con_offset));
776 con |= 0x1 << con_4bit_shift(con_offset);
778 dat = __raw_readl(base + GPIODAT_OFF);
782 dat &= ~(1 << offset);
784 __raw_writel(con, regcon);
785 __raw_writel(dat, base + GPIODAT_OFF);
787 samsung_gpio_unlock(ourchip, flags);
792 static void samsung_gpiolib_set(struct gpio_chip *chip,
793 unsigned offset, int value)
795 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
796 void __iomem *base = ourchip->base;
800 samsung_gpio_lock(ourchip, flags);
802 dat = __raw_readl(base + 0x04);
803 dat &= ~(1 << offset);
806 __raw_writel(dat, base + 0x04);
808 samsung_gpio_unlock(ourchip, flags);
811 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
813 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
816 val = __raw_readl(ourchip->base + 0x04);
824 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
825 * for use with the configuration calls, and other parts of the s3c gpiolib
828 * Not all s3c support code will need this, as some configurations of cpu
829 * may only support one or two different configuration options and have an
830 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
831 * the machine support file should provide its own samsung_gpiolib_getchip()
832 * and any other necessary functions.
835 #ifdef CONFIG_S3C_GPIO_TRACK
836 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
838 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
843 gpn = chip->chip.base;
844 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
845 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
846 s3c_gpios[gpn] = chip;
849 #endif /* CONFIG_S3C_GPIO_TRACK */
852 * samsung_gpiolib_add() - add the Samsung gpio_chip.
853 * @chip: The chip to register
855 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
856 * information and makes the necessary alterations for the platform and
857 * notes the information for use with the configuration systems and any
858 * other parts of the system.
861 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
863 struct gpio_chip *gc = &chip->chip;
870 spin_lock_init(&chip->lock);
872 if (!gc->direction_input)
873 gc->direction_input = samsung_gpiolib_2bit_input;
874 if (!gc->direction_output)
875 gc->direction_output = samsung_gpiolib_2bit_output;
877 gc->set = samsung_gpiolib_set;
879 gc->get = samsung_gpiolib_get;
882 if (chip->pm != NULL) {
883 if (!chip->pm->save || !chip->pm->resume)
884 pr_err("gpio: %s has missing PM functions\n",
887 pr_err("gpio: %s has no PM function\n", gc->label);
890 /* gpiochip_add() prints own failure message on error. */
891 ret = gpiochip_add(gc);
893 s3c_gpiolib_track(chip);
896 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
897 int nr_chips, void __iomem *base)
900 struct gpio_chip *gc = &chip->chip;
902 for (i = 0 ; i < nr_chips; i++, chip++) {
903 /* skip banks not present on SoC */
904 if (chip->chip.base >= S3C_GPIO_END)
908 chip->config = &s3c24xx_gpiocfg_default;
910 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
911 if ((base != NULL) && (chip->base == NULL))
912 chip->base = base + ((i) * 0x10);
914 if (!gc->direction_input)
915 gc->direction_input = samsung_gpiolib_2bit_input;
916 if (!gc->direction_output)
917 gc->direction_output = samsung_gpiolib_2bit_output;
919 samsung_gpiolib_add(chip);
923 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
924 int nr_chips, void __iomem *base,
929 for (i = 0 ; i < nr_chips; i++, chip++) {
930 chip->chip.direction_input = samsung_gpiolib_2bit_input;
931 chip->chip.direction_output = samsung_gpiolib_2bit_output;
934 chip->config = &samsung_gpio_cfgs[7];
936 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
937 if ((base != NULL) && (chip->base == NULL))
938 chip->base = base + ((i) * offset);
940 samsung_gpiolib_add(chip);
945 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
946 * @chip: The gpio chip that is being configured.
947 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
949 * This helper deal with the GPIO cases where the control register has 4 bits
950 * of control per GPIO, generally in the form of:
953 * others = Special functions (dependent on bank)
955 * Note, since the code to deal with the case where there are two control
956 * registers instead of one, we do not have a separate set of function
957 * (samsung_gpiolib_add_4bit2_chips)for each case.
960 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
961 int nr_chips, void __iomem *base)
965 for (i = 0 ; i < nr_chips; i++, chip++) {
966 chip->chip.direction_input = samsung_gpiolib_4bit_input;
967 chip->chip.direction_output = samsung_gpiolib_4bit_output;
970 chip->config = &samsung_gpio_cfgs[2];
972 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
973 if ((base != NULL) && (chip->base == NULL))
974 chip->base = base + ((i) * 0x20);
976 chip->bitmap_gpio_int = 0;
978 samsung_gpiolib_add(chip);
982 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
985 for (; nr_chips > 0; nr_chips--, chip++) {
986 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
987 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
990 chip->config = &samsung_gpio_cfgs[2];
992 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
994 samsung_gpiolib_add(chip);
998 static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1001 for (; nr_chips > 0; nr_chips--, chip++) {
1002 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1003 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1006 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1008 samsung_gpiolib_add(chip);
1012 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1014 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
1016 return samsung_chip->irq_base + offset;
1019 #ifdef CONFIG_PLAT_S3C24XX
1020 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1023 if (soc_is_s3c2412())
1024 return IRQ_EINT0_2412 + offset;
1026 return IRQ_EINT0 + offset;
1030 return IRQ_EINT4 + offset - 4;
1036 #ifdef CONFIG_PLAT_S3C64XX
1037 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
1039 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
1042 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
1044 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
1048 struct samsung_gpio_chip s3c24xx_gpios[] = {
1049 #ifdef CONFIG_PLAT_S3C24XX
1051 .config = &s3c24xx_gpiocfg_banka,
1053 .base = S3C2410_GPA(0),
1054 .owner = THIS_MODULE,
1057 .direction_input = s3c24xx_gpiolib_banka_input,
1058 .direction_output = s3c24xx_gpiolib_banka_output,
1062 .base = S3C2410_GPB(0),
1063 .owner = THIS_MODULE,
1069 .base = S3C2410_GPC(0),
1070 .owner = THIS_MODULE,
1076 .base = S3C2410_GPD(0),
1077 .owner = THIS_MODULE,
1083 .base = S3C2410_GPE(0),
1085 .owner = THIS_MODULE,
1090 .base = S3C2410_GPF(0),
1091 .owner = THIS_MODULE,
1094 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
1097 .irq_base = IRQ_EINT8,
1099 .base = S3C2410_GPG(0),
1100 .owner = THIS_MODULE,
1103 .to_irq = samsung_gpiolib_to_irq,
1107 .base = S3C2410_GPH(0),
1108 .owner = THIS_MODULE,
1113 /* GPIOS for the S3C2443 and later devices. */
1115 .base = S3C2440_GPJCON,
1117 .base = S3C2410_GPJ(0),
1118 .owner = THIS_MODULE,
1123 .base = S3C2443_GPKCON,
1125 .base = S3C2410_GPK(0),
1126 .owner = THIS_MODULE,
1131 .base = S3C2443_GPLCON,
1133 .base = S3C2410_GPL(0),
1134 .owner = THIS_MODULE,
1139 .base = S3C2443_GPMCON,
1141 .base = S3C2410_GPM(0),
1142 .owner = THIS_MODULE,
1151 * GPIO bank summary:
1153 * Bank GPIOs Style SlpCon ExtInt Group
1159 * F 16 2Bit Yes 4 [1]
1161 * H 10 4Bit[2] Yes 6
1162 * I 16 2Bit Yes None
1163 * J 12 2Bit Yes None
1164 * K 16 4Bit[2] No None
1165 * L 15 4Bit[2] No None
1166 * M 6 4Bit No IRQ_EINT
1167 * N 16 2Bit No IRQ_EINT
1172 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1173 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1176 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1177 #ifdef CONFIG_PLAT_S3C64XX
1180 .base = S3C64XX_GPA(0),
1181 .ngpio = S3C64XX_GPIO_A_NR,
1186 .base = S3C64XX_GPB(0),
1187 .ngpio = S3C64XX_GPIO_B_NR,
1192 .base = S3C64XX_GPC(0),
1193 .ngpio = S3C64XX_GPIO_C_NR,
1198 .base = S3C64XX_GPD(0),
1199 .ngpio = S3C64XX_GPIO_D_NR,
1203 .config = &samsung_gpio_cfgs[0],
1205 .base = S3C64XX_GPE(0),
1206 .ngpio = S3C64XX_GPIO_E_NR,
1210 .base = S3C64XX_GPG_BASE,
1212 .base = S3C64XX_GPG(0),
1213 .ngpio = S3C64XX_GPIO_G_NR,
1217 .base = S3C64XX_GPM_BASE,
1218 .config = &samsung_gpio_cfgs[1],
1220 .base = S3C64XX_GPM(0),
1221 .ngpio = S3C64XX_GPIO_M_NR,
1223 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1229 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1230 #ifdef CONFIG_PLAT_S3C64XX
1232 .base = S3C64XX_GPH_BASE + 0x4,
1234 .base = S3C64XX_GPH(0),
1235 .ngpio = S3C64XX_GPIO_H_NR,
1239 .base = S3C64XX_GPK_BASE + 0x4,
1240 .config = &samsung_gpio_cfgs[0],
1242 .base = S3C64XX_GPK(0),
1243 .ngpio = S3C64XX_GPIO_K_NR,
1247 .base = S3C64XX_GPL_BASE + 0x4,
1248 .config = &samsung_gpio_cfgs[1],
1250 .base = S3C64XX_GPL(0),
1251 .ngpio = S3C64XX_GPIO_L_NR,
1253 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1259 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1260 #ifdef CONFIG_PLAT_S3C64XX
1262 .base = S3C64XX_GPF_BASE,
1263 .config = &samsung_gpio_cfgs[6],
1265 .base = S3C64XX_GPF(0),
1266 .ngpio = S3C64XX_GPIO_F_NR,
1270 .config = &samsung_gpio_cfgs[7],
1272 .base = S3C64XX_GPI(0),
1273 .ngpio = S3C64XX_GPIO_I_NR,
1277 .config = &samsung_gpio_cfgs[7],
1279 .base = S3C64XX_GPJ(0),
1280 .ngpio = S3C64XX_GPIO_J_NR,
1284 .config = &samsung_gpio_cfgs[6],
1286 .base = S3C64XX_GPO(0),
1287 .ngpio = S3C64XX_GPIO_O_NR,
1291 .config = &samsung_gpio_cfgs[6],
1293 .base = S3C64XX_GPP(0),
1294 .ngpio = S3C64XX_GPIO_P_NR,
1298 .config = &samsung_gpio_cfgs[6],
1300 .base = S3C64XX_GPQ(0),
1301 .ngpio = S3C64XX_GPIO_Q_NR,
1305 .base = S3C64XX_GPN_BASE,
1306 .irq_base = IRQ_EINT(0),
1307 .config = &samsung_gpio_cfgs[5],
1309 .base = S3C64XX_GPN(0),
1310 .ngpio = S3C64XX_GPIO_N_NR,
1312 .to_irq = samsung_gpiolib_to_irq,
1319 * S5P6440 GPIO bank summary:
1321 * Bank GPIOs Style SlpCon ExtInt Group
1325 * F 2 2Bit Yes 4 [1]
1327 * H 10 4Bit[2] Yes 6
1328 * I 16 2Bit Yes None
1329 * J 12 2Bit Yes None
1330 * N 16 2Bit No IRQ_EINT
1332 * R 15 4Bit[2] Yes 8
1335 static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1336 #ifdef CONFIG_CPU_S5P6440
1339 .base = S5P6440_GPA(0),
1340 .ngpio = S5P6440_GPIO_A_NR,
1345 .base = S5P6440_GPB(0),
1346 .ngpio = S5P6440_GPIO_B_NR,
1351 .base = S5P6440_GPC(0),
1352 .ngpio = S5P6440_GPIO_C_NR,
1356 .base = S5P64X0_GPG_BASE,
1358 .base = S5P6440_GPG(0),
1359 .ngpio = S5P6440_GPIO_G_NR,
1366 static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1367 #ifdef CONFIG_CPU_S5P6440
1369 .base = S5P64X0_GPH_BASE + 0x4,
1371 .base = S5P6440_GPH(0),
1372 .ngpio = S5P6440_GPIO_H_NR,
1379 static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1380 #ifdef CONFIG_CPU_S5P6440
1382 .base = S5P64X0_GPR_BASE + 0x4,
1383 .config = &s5p64x0_gpio_cfg_rbank,
1385 .base = S5P6440_GPR(0),
1386 .ngpio = S5P6440_GPIO_R_NR,
1393 static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1394 #ifdef CONFIG_CPU_S5P6440
1396 .base = S5P64X0_GPF_BASE,
1397 .config = &samsung_gpio_cfgs[6],
1399 .base = S5P6440_GPF(0),
1400 .ngpio = S5P6440_GPIO_F_NR,
1404 .base = S5P64X0_GPI_BASE,
1405 .config = &samsung_gpio_cfgs[4],
1407 .base = S5P6440_GPI(0),
1408 .ngpio = S5P6440_GPIO_I_NR,
1412 .base = S5P64X0_GPJ_BASE,
1413 .config = &samsung_gpio_cfgs[4],
1415 .base = S5P6440_GPJ(0),
1416 .ngpio = S5P6440_GPIO_J_NR,
1420 .base = S5P64X0_GPN_BASE,
1421 .config = &samsung_gpio_cfgs[5],
1423 .base = S5P6440_GPN(0),
1424 .ngpio = S5P6440_GPIO_N_NR,
1428 .base = S5P64X0_GPP_BASE,
1429 .config = &samsung_gpio_cfgs[6],
1431 .base = S5P6440_GPP(0),
1432 .ngpio = S5P6440_GPIO_P_NR,
1440 * S5P6450 GPIO bank summary:
1442 * Bank GPIOs Style SlpCon ExtInt Group
1448 * G 14 4Bit[2] Yes 5
1449 * H 10 4Bit[2] Yes 6
1450 * I 16 2Bit Yes None
1451 * J 12 2Bit Yes None
1453 * N 16 2Bit No IRQ_EINT
1455 * Q 14 2Bit Yes None
1456 * R 15 4Bit[2] Yes None
1459 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1460 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1463 static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1464 #ifdef CONFIG_CPU_S5P6450
1467 .base = S5P6450_GPA(0),
1468 .ngpio = S5P6450_GPIO_A_NR,
1473 .base = S5P6450_GPB(0),
1474 .ngpio = S5P6450_GPIO_B_NR,
1479 .base = S5P6450_GPC(0),
1480 .ngpio = S5P6450_GPIO_C_NR,
1485 .base = S5P6450_GPD(0),
1486 .ngpio = S5P6450_GPIO_D_NR,
1490 .base = S5P6450_GPK_BASE,
1492 .base = S5P6450_GPK(0),
1493 .ngpio = S5P6450_GPIO_K_NR,
1500 static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1501 #ifdef CONFIG_CPU_S5P6450
1503 .base = S5P64X0_GPG_BASE + 0x4,
1505 .base = S5P6450_GPG(0),
1506 .ngpio = S5P6450_GPIO_G_NR,
1510 .base = S5P64X0_GPH_BASE + 0x4,
1512 .base = S5P6450_GPH(0),
1513 .ngpio = S5P6450_GPIO_H_NR,
1520 static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1521 #ifdef CONFIG_CPU_S5P6450
1523 .base = S5P64X0_GPR_BASE + 0x4,
1524 .config = &s5p64x0_gpio_cfg_rbank,
1526 .base = S5P6450_GPR(0),
1527 .ngpio = S5P6450_GPIO_R_NR,
1534 static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1535 #ifdef CONFIG_CPU_S5P6450
1537 .base = S5P64X0_GPF_BASE,
1538 .config = &samsung_gpio_cfgs[6],
1540 .base = S5P6450_GPF(0),
1541 .ngpio = S5P6450_GPIO_F_NR,
1545 .base = S5P64X0_GPI_BASE,
1546 .config = &samsung_gpio_cfgs[4],
1548 .base = S5P6450_GPI(0),
1549 .ngpio = S5P6450_GPIO_I_NR,
1553 .base = S5P64X0_GPJ_BASE,
1554 .config = &samsung_gpio_cfgs[4],
1556 .base = S5P6450_GPJ(0),
1557 .ngpio = S5P6450_GPIO_J_NR,
1561 .base = S5P64X0_GPN_BASE,
1562 .config = &samsung_gpio_cfgs[5],
1564 .base = S5P6450_GPN(0),
1565 .ngpio = S5P6450_GPIO_N_NR,
1569 .base = S5P64X0_GPP_BASE,
1570 .config = &samsung_gpio_cfgs[6],
1572 .base = S5P6450_GPP(0),
1573 .ngpio = S5P6450_GPIO_P_NR,
1577 .base = S5P6450_GPQ_BASE,
1578 .config = &samsung_gpio_cfgs[5],
1580 .base = S5P6450_GPQ(0),
1581 .ngpio = S5P6450_GPIO_Q_NR,
1585 .base = S5P6450_GPS_BASE,
1586 .config = &samsung_gpio_cfgs[6],
1588 .base = S5P6450_GPS(0),
1589 .ngpio = S5P6450_GPIO_S_NR,
1597 * S5PC100 GPIO bank summary:
1599 * Bank GPIOs Style INT Type
1600 * A0 8 4Bit GPIO_INT0
1601 * A1 5 4Bit GPIO_INT1
1602 * B 8 4Bit GPIO_INT2
1603 * C 5 4Bit GPIO_INT3
1604 * D 7 4Bit GPIO_INT4
1605 * E0 8 4Bit GPIO_INT5
1606 * E1 6 4Bit GPIO_INT6
1607 * F0 8 4Bit GPIO_INT7
1608 * F1 8 4Bit GPIO_INT8
1609 * F2 8 4Bit GPIO_INT9
1610 * F3 4 4Bit GPIO_INT10
1611 * G0 8 4Bit GPIO_INT11
1612 * G1 3 4Bit GPIO_INT12
1613 * G2 7 4Bit GPIO_INT13
1614 * G3 7 4Bit GPIO_INT14
1615 * H0 8 4Bit WKUP_INT
1616 * H1 8 4Bit WKUP_INT
1617 * H2 8 4Bit WKUP_INT
1618 * H3 8 4Bit WKUP_INT
1619 * I 8 4Bit GPIO_INT15
1620 * J0 8 4Bit GPIO_INT16
1621 * J1 5 4Bit GPIO_INT17
1622 * J2 8 4Bit GPIO_INT18
1623 * J3 8 4Bit GPIO_INT19
1624 * J4 4 4Bit GPIO_INT20
1635 static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1636 #ifdef CONFIG_CPU_S5PC100
1639 .base = S5PC100_GPA0(0),
1640 .ngpio = S5PC100_GPIO_A0_NR,
1645 .base = S5PC100_GPA1(0),
1646 .ngpio = S5PC100_GPIO_A1_NR,
1651 .base = S5PC100_GPB(0),
1652 .ngpio = S5PC100_GPIO_B_NR,
1657 .base = S5PC100_GPC(0),
1658 .ngpio = S5PC100_GPIO_C_NR,
1663 .base = S5PC100_GPD(0),
1664 .ngpio = S5PC100_GPIO_D_NR,
1669 .base = S5PC100_GPE0(0),
1670 .ngpio = S5PC100_GPIO_E0_NR,
1675 .base = S5PC100_GPE1(0),
1676 .ngpio = S5PC100_GPIO_E1_NR,
1681 .base = S5PC100_GPF0(0),
1682 .ngpio = S5PC100_GPIO_F0_NR,
1687 .base = S5PC100_GPF1(0),
1688 .ngpio = S5PC100_GPIO_F1_NR,
1693 .base = S5PC100_GPF2(0),
1694 .ngpio = S5PC100_GPIO_F2_NR,
1699 .base = S5PC100_GPF3(0),
1700 .ngpio = S5PC100_GPIO_F3_NR,
1705 .base = S5PC100_GPG0(0),
1706 .ngpio = S5PC100_GPIO_G0_NR,
1711 .base = S5PC100_GPG1(0),
1712 .ngpio = S5PC100_GPIO_G1_NR,
1717 .base = S5PC100_GPG2(0),
1718 .ngpio = S5PC100_GPIO_G2_NR,
1723 .base = S5PC100_GPG3(0),
1724 .ngpio = S5PC100_GPIO_G3_NR,
1729 .base = S5PC100_GPI(0),
1730 .ngpio = S5PC100_GPIO_I_NR,
1735 .base = S5PC100_GPJ0(0),
1736 .ngpio = S5PC100_GPIO_J0_NR,
1741 .base = S5PC100_GPJ1(0),
1742 .ngpio = S5PC100_GPIO_J1_NR,
1747 .base = S5PC100_GPJ2(0),
1748 .ngpio = S5PC100_GPIO_J2_NR,
1753 .base = S5PC100_GPJ3(0),
1754 .ngpio = S5PC100_GPIO_J3_NR,
1759 .base = S5PC100_GPJ4(0),
1760 .ngpio = S5PC100_GPIO_J4_NR,
1765 .base = S5PC100_GPK0(0),
1766 .ngpio = S5PC100_GPIO_K0_NR,
1771 .base = S5PC100_GPK1(0),
1772 .ngpio = S5PC100_GPIO_K1_NR,
1777 .base = S5PC100_GPK2(0),
1778 .ngpio = S5PC100_GPIO_K2_NR,
1783 .base = S5PC100_GPK3(0),
1784 .ngpio = S5PC100_GPIO_K3_NR,
1789 .base = S5PC100_GPL0(0),
1790 .ngpio = S5PC100_GPIO_L0_NR,
1795 .base = S5PC100_GPL1(0),
1796 .ngpio = S5PC100_GPIO_L1_NR,
1801 .base = S5PC100_GPL2(0),
1802 .ngpio = S5PC100_GPIO_L2_NR,
1807 .base = S5PC100_GPL3(0),
1808 .ngpio = S5PC100_GPIO_L3_NR,
1813 .base = S5PC100_GPL4(0),
1814 .ngpio = S5PC100_GPIO_L4_NR,
1818 .base = (S5P_VA_GPIO + 0xC00),
1819 .irq_base = IRQ_EINT(0),
1821 .base = S5PC100_GPH0(0),
1822 .ngpio = S5PC100_GPIO_H0_NR,
1824 .to_irq = samsung_gpiolib_to_irq,
1827 .base = (S5P_VA_GPIO + 0xC20),
1828 .irq_base = IRQ_EINT(8),
1830 .base = S5PC100_GPH1(0),
1831 .ngpio = S5PC100_GPIO_H1_NR,
1833 .to_irq = samsung_gpiolib_to_irq,
1836 .base = (S5P_VA_GPIO + 0xC40),
1837 .irq_base = IRQ_EINT(16),
1839 .base = S5PC100_GPH2(0),
1840 .ngpio = S5PC100_GPIO_H2_NR,
1842 .to_irq = samsung_gpiolib_to_irq,
1845 .base = (S5P_VA_GPIO + 0xC60),
1846 .irq_base = IRQ_EINT(24),
1848 .base = S5PC100_GPH3(0),
1849 .ngpio = S5PC100_GPIO_H3_NR,
1851 .to_irq = samsung_gpiolib_to_irq,
1858 * Followings are the gpio banks in S5PV210/S5PC110
1860 * The 'config' member when left to NULL, is initialized to the default
1861 * structure samsung_gpio_cfgs[3] in the init function below.
1863 * The 'base' member is also initialized in the init function below.
1864 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1865 * uses the above macro and depends on the banks being listed in order here.
1868 static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1869 #ifdef CONFIG_CPU_S5PV210
1872 .base = S5PV210_GPA0(0),
1873 .ngpio = S5PV210_GPIO_A0_NR,
1878 .base = S5PV210_GPA1(0),
1879 .ngpio = S5PV210_GPIO_A1_NR,
1884 .base = S5PV210_GPB(0),
1885 .ngpio = S5PV210_GPIO_B_NR,
1890 .base = S5PV210_GPC0(0),
1891 .ngpio = S5PV210_GPIO_C0_NR,
1896 .base = S5PV210_GPC1(0),
1897 .ngpio = S5PV210_GPIO_C1_NR,
1902 .base = S5PV210_GPD0(0),
1903 .ngpio = S5PV210_GPIO_D0_NR,
1908 .base = S5PV210_GPD1(0),
1909 .ngpio = S5PV210_GPIO_D1_NR,
1914 .base = S5PV210_GPE0(0),
1915 .ngpio = S5PV210_GPIO_E0_NR,
1920 .base = S5PV210_GPE1(0),
1921 .ngpio = S5PV210_GPIO_E1_NR,
1926 .base = S5PV210_GPF0(0),
1927 .ngpio = S5PV210_GPIO_F0_NR,
1932 .base = S5PV210_GPF1(0),
1933 .ngpio = S5PV210_GPIO_F1_NR,
1938 .base = S5PV210_GPF2(0),
1939 .ngpio = S5PV210_GPIO_F2_NR,
1944 .base = S5PV210_GPF3(0),
1945 .ngpio = S5PV210_GPIO_F3_NR,
1950 .base = S5PV210_GPG0(0),
1951 .ngpio = S5PV210_GPIO_G0_NR,
1956 .base = S5PV210_GPG1(0),
1957 .ngpio = S5PV210_GPIO_G1_NR,
1962 .base = S5PV210_GPG2(0),
1963 .ngpio = S5PV210_GPIO_G2_NR,
1968 .base = S5PV210_GPG3(0),
1969 .ngpio = S5PV210_GPIO_G3_NR,
1974 .base = S5PV210_GPI(0),
1975 .ngpio = S5PV210_GPIO_I_NR,
1980 .base = S5PV210_GPJ0(0),
1981 .ngpio = S5PV210_GPIO_J0_NR,
1986 .base = S5PV210_GPJ1(0),
1987 .ngpio = S5PV210_GPIO_J1_NR,
1992 .base = S5PV210_GPJ2(0),
1993 .ngpio = S5PV210_GPIO_J2_NR,
1998 .base = S5PV210_GPJ3(0),
1999 .ngpio = S5PV210_GPIO_J3_NR,
2004 .base = S5PV210_GPJ4(0),
2005 .ngpio = S5PV210_GPIO_J4_NR,
2010 .base = S5PV210_MP01(0),
2011 .ngpio = S5PV210_GPIO_MP01_NR,
2016 .base = S5PV210_MP02(0),
2017 .ngpio = S5PV210_GPIO_MP02_NR,
2022 .base = S5PV210_MP03(0),
2023 .ngpio = S5PV210_GPIO_MP03_NR,
2028 .base = S5PV210_MP04(0),
2029 .ngpio = S5PV210_GPIO_MP04_NR,
2034 .base = S5PV210_MP05(0),
2035 .ngpio = S5PV210_GPIO_MP05_NR,
2039 .base = (S5P_VA_GPIO + 0xC00),
2040 .irq_base = IRQ_EINT(0),
2042 .base = S5PV210_GPH0(0),
2043 .ngpio = S5PV210_GPIO_H0_NR,
2045 .to_irq = samsung_gpiolib_to_irq,
2048 .base = (S5P_VA_GPIO + 0xC20),
2049 .irq_base = IRQ_EINT(8),
2051 .base = S5PV210_GPH1(0),
2052 .ngpio = S5PV210_GPIO_H1_NR,
2054 .to_irq = samsung_gpiolib_to_irq,
2057 .base = (S5P_VA_GPIO + 0xC40),
2058 .irq_base = IRQ_EINT(16),
2060 .base = S5PV210_GPH2(0),
2061 .ngpio = S5PV210_GPIO_H2_NR,
2063 .to_irq = samsung_gpiolib_to_irq,
2066 .base = (S5P_VA_GPIO + 0xC60),
2067 .irq_base = IRQ_EINT(24),
2069 .base = S5PV210_GPH3(0),
2070 .ngpio = S5PV210_GPIO_H3_NR,
2072 .to_irq = samsung_gpiolib_to_irq,
2078 /* TODO: cleanup soc_is_* */
2079 static __init int samsung_gpiolib_init(void)
2081 struct samsung_gpio_chip *chip;
2085 #if defined(CONFIG_PINCTRL_EXYNOS) || defined(CONFIG_PINCTRL_EXYNOS5440)
2087 * This gpio driver includes support for device tree support and there
2088 * are platforms using it. In order to maintain compatibility with those
2089 * platforms, and to allow non-dt Exynos4210 platforms to use this
2090 * gpiolib support, a check is added to find out if there is a active
2091 * pin-controller driver support available. If it is available, this
2092 * gpiolib support is ignored and the gpiolib support available in
2093 * pin-controller driver is used. This is a temporary check and will go
2094 * away when all of the Exynos4210 platforms have switched to using
2095 * device tree and the pin-ctrl driver.
2097 struct device_node *pctrl_np;
2098 static const struct of_device_id exynos_pinctrl_ids[] = {
2099 { .compatible = "samsung,s3c2412-pinctrl", },
2100 { .compatible = "samsung,s3c2416-pinctrl", },
2101 { .compatible = "samsung,s3c2440-pinctrl", },
2102 { .compatible = "samsung,s3c2450-pinctrl", },
2103 { .compatible = "samsung,exynos4210-pinctrl", },
2104 { .compatible = "samsung,exynos4x12-pinctrl", },
2105 { .compatible = "samsung,exynos5250-pinctrl", },
2106 { .compatible = "samsung,exynos5440-pinctrl", },
2109 for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
2110 if (pctrl_np && of_device_is_available(pctrl_np))
2114 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
2116 if (soc_is_s3c24xx()) {
2117 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
2118 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
2119 } else if (soc_is_s3c64xx()) {
2120 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
2121 ARRAY_SIZE(s3c64xx_gpios_2bit),
2122 S3C64XX_VA_GPIO + 0xE0, 0x20);
2123 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
2124 ARRAY_SIZE(s3c64xx_gpios_4bit),
2126 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
2127 ARRAY_SIZE(s3c64xx_gpios_4bit2));
2128 } else if (soc_is_s5p6440()) {
2129 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
2130 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
2131 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
2132 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
2133 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
2134 ARRAY_SIZE(s5p6440_gpios_4bit2));
2135 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
2136 ARRAY_SIZE(s5p6440_gpios_rbank));
2137 } else if (soc_is_s5p6450()) {
2138 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
2139 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
2140 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
2141 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
2142 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
2143 ARRAY_SIZE(s5p6450_gpios_4bit2));
2144 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
2145 ARRAY_SIZE(s5p6450_gpios_rbank));
2146 } else if (soc_is_s5pc100()) {
2148 chip = s5pc100_gpios_4bit;
2149 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
2151 for (i = 0; i < nr_chips; i++, chip++) {
2152 if (!chip->config) {
2153 chip->config = &samsung_gpio_cfgs[3];
2154 chip->group = group++;
2157 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
2158 #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
2159 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2161 } else if (soc_is_s5pv210()) {
2163 chip = s5pv210_gpios_4bit;
2164 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
2166 for (i = 0; i < nr_chips; i++, chip++) {
2167 if (!chip->config) {
2168 chip->config = &samsung_gpio_cfgs[3];
2169 chip->group = group++;
2172 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
2173 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
2174 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2177 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
2183 core_initcall(samsung_gpiolib_init);
2185 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
2187 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2188 unsigned long flags;
2195 offset = pin - chip->chip.base;
2197 samsung_gpio_lock(chip, flags);
2198 ret = samsung_gpio_do_setcfg(chip, offset, config);
2199 samsung_gpio_unlock(chip, flags);
2203 EXPORT_SYMBOL(s3c_gpio_cfgpin);
2205 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
2210 for (; nr > 0; nr--, start++) {
2211 ret = s3c_gpio_cfgpin(start, cfg);
2218 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
2220 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
2221 unsigned int cfg, samsung_gpio_pull_t pull)
2225 for (; nr > 0; nr--, start++) {
2226 s3c_gpio_setpull(start, pull);
2227 ret = s3c_gpio_cfgpin(start, cfg);
2234 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
2236 unsigned s3c_gpio_getcfg(unsigned int pin)
2238 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2239 unsigned long flags;
2244 offset = pin - chip->chip.base;
2246 samsung_gpio_lock(chip, flags);
2247 ret = samsung_gpio_do_getcfg(chip, offset);
2248 samsung_gpio_unlock(chip, flags);
2253 EXPORT_SYMBOL(s3c_gpio_getcfg);
2255 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
2257 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2258 unsigned long flags;
2264 offset = pin - chip->chip.base;
2266 samsung_gpio_lock(chip, flags);
2267 ret = samsung_gpio_do_setpull(chip, offset, pull);
2268 samsung_gpio_unlock(chip, flags);
2272 EXPORT_SYMBOL(s3c_gpio_setpull);
2274 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
2276 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2277 unsigned long flags;
2282 offset = pin - chip->chip.base;
2284 samsung_gpio_lock(chip, flags);
2285 pup = samsung_gpio_do_getpull(chip, offset);
2286 samsung_gpio_unlock(chip, flags);
2289 return (__force samsung_gpio_pull_t)pup;
2291 EXPORT_SYMBOL(s3c_gpio_getpull);
2293 #ifdef CONFIG_S5P_GPIO_DRVSTR
2294 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
2296 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2305 off = pin - chip->chip.base;
2307 reg = chip->base + 0x0C;
2309 drvstr = __raw_readl(reg);
2310 drvstr = drvstr >> shift;
2313 return (__force s5p_gpio_drvstr_t)drvstr;
2315 EXPORT_SYMBOL(s5p_gpio_get_drvstr);
2317 int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
2319 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
2328 off = pin - chip->chip.base;
2330 reg = chip->base + 0x0C;
2332 tmp = __raw_readl(reg);
2333 tmp &= ~(0x3 << shift);
2334 tmp |= drvstr << shift;
2336 __raw_writel(tmp, reg);
2340 EXPORT_SYMBOL(s5p_gpio_set_drvstr);
2341 #endif /* CONFIG_S5P_GPIO_DRVSTR */
2343 #ifdef CONFIG_PLAT_S3C24XX
2344 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
2346 unsigned long flags;
2347 unsigned long misccr;
2349 local_irq_save(flags);
2350 misccr = __raw_readl(S3C24XX_MISCCR);
2353 __raw_writel(misccr, S3C24XX_MISCCR);
2354 local_irq_restore(flags);
2358 EXPORT_SYMBOL(s3c2410_modify_misccr);