2 * Copyright (C) 2015 Linaro Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 #include <linux/bitops.h>
9 #include <linux/device.h>
10 #include <linux/errno.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/irqchip/chained_irq.h>
13 #include <linux/module.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
21 #define ZX_GPIO_DIR 0x00
22 #define ZX_GPIO_IVE 0x04
23 #define ZX_GPIO_IV 0x08
24 #define ZX_GPIO_IEP 0x0C
25 #define ZX_GPIO_IEN 0x10
26 #define ZX_GPIO_DI 0x14
27 #define ZX_GPIO_DO1 0x18
28 #define ZX_GPIO_DO0 0x1C
29 #define ZX_GPIO_DO 0x20
31 #define ZX_GPIO_IM 0x28
32 #define ZX_GPIO_IE 0x2C
34 #define ZX_GPIO_MIS 0x30
35 #define ZX_GPIO_IC 0x34
46 static inline struct zx_gpio *to_zx(struct gpio_chip *gc)
48 return container_of(gc, struct zx_gpio, gc);
51 static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
53 struct zx_gpio *chip = to_zx(gc);
57 if (offset >= gc->ngpio)
60 spin_lock_irqsave(&chip->lock, flags);
61 gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
62 gpiodir &= ~BIT(offset);
63 writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
64 spin_unlock_irqrestore(&chip->lock, flags);
69 static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
72 struct zx_gpio *chip = to_zx(gc);
76 if (offset >= gc->ngpio)
79 spin_lock_irqsave(&chip->lock, flags);
80 gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
81 gpiodir |= BIT(offset);
82 writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
85 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
87 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
88 spin_unlock_irqrestore(&chip->lock, flags);
93 static int zx_get_value(struct gpio_chip *gc, unsigned offset)
95 struct zx_gpio *chip = to_zx(gc);
97 return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset));
100 static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value)
102 struct zx_gpio *chip = to_zx(gc);
105 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
107 writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
110 static int zx_irq_type(struct irq_data *d, unsigned trigger)
112 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
113 struct zx_gpio *chip = to_zx(gc);
114 int offset = irqd_to_hwirq(d);
116 u16 gpiois, gpioi_epos, gpioi_eneg, gpioiev;
117 u16 bit = BIT(offset);
119 if (offset < 0 || offset >= ZX_GPIO_NR)
122 spin_lock_irqsave(&chip->lock, flags);
124 gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
125 gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
126 gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP);
127 gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN);
129 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
131 if (trigger & IRQ_TYPE_LEVEL_HIGH)
138 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
142 if (trigger & IRQ_TYPE_EDGE_RISING) {
145 } else if (trigger & IRQ_TYPE_EDGE_FALLING) {
151 writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE);
152 writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
153 writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
154 writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
155 spin_unlock_irqrestore(&chip->lock, flags);
160 static void zx_irq_handler(struct irq_desc *desc)
162 unsigned long pending;
164 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
165 struct zx_gpio *chip = to_zx(gc);
166 struct irq_chip *irqchip = irq_desc_get_chip(desc);
168 chained_irq_enter(irqchip, desc);
170 pending = readw_relaxed(chip->base + ZX_GPIO_MIS);
171 writew_relaxed(pending, chip->base + ZX_GPIO_IC);
173 for_each_set_bit(offset, &pending, ZX_GPIO_NR)
174 generic_handle_irq(irq_find_mapping(gc->irqdomain,
178 chained_irq_exit(irqchip, desc);
181 static void zx_irq_mask(struct irq_data *d)
183 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
184 struct zx_gpio *chip = to_zx(gc);
185 u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
188 spin_lock(&chip->lock);
189 gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask;
190 writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
191 gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
192 writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
193 spin_unlock(&chip->lock);
196 static void zx_irq_unmask(struct irq_data *d)
198 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
199 struct zx_gpio *chip = to_zx(gc);
200 u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
203 spin_lock(&chip->lock);
204 gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
205 writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
206 gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask;
207 writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
208 spin_unlock(&chip->lock);
211 static struct irq_chip zx_irqchip = {
213 .irq_mask = zx_irq_mask,
214 .irq_unmask = zx_irq_unmask,
215 .irq_set_type = zx_irq_type,
218 static int zx_gpio_probe(struct platform_device *pdev)
220 struct device *dev = &pdev->dev;
221 struct zx_gpio *chip;
222 struct resource *res;
225 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
229 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
230 chip->base = devm_ioremap_resource(dev, res);
231 if (IS_ERR(chip->base))
232 return PTR_ERR(chip->base);
234 spin_lock_init(&chip->lock);
235 if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
236 chip->gc.request = gpiochip_generic_request;
237 chip->gc.free = gpiochip_generic_free;
240 id = of_alias_get_id(dev->of_node, "gpio");
241 chip->gc.direction_input = zx_direction_input;
242 chip->gc.direction_output = zx_direction_output;
243 chip->gc.get = zx_get_value;
244 chip->gc.set = zx_set_value;
245 chip->gc.base = ZX_GPIO_NR * id;
246 chip->gc.ngpio = ZX_GPIO_NR;
247 chip->gc.label = dev_name(dev);
249 chip->gc.owner = THIS_MODULE;
251 ret = gpiochip_add(&chip->gc);
258 writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
259 writew_relaxed(0, chip->base + ZX_GPIO_IE);
260 irq = platform_get_irq(pdev, 0);
262 dev_err(dev, "invalid IRQ\n");
263 gpiochip_remove(&chip->gc);
267 ret = gpiochip_irqchip_add(&chip->gc, &zx_irqchip,
268 0, handle_simple_irq,
271 dev_err(dev, "could not add irqchip\n");
272 gpiochip_remove(&chip->gc);
275 gpiochip_set_chained_irqchip(&chip->gc, &zx_irqchip,
276 irq, zx_irq_handler);
278 platform_set_drvdata(pdev, chip);
279 dev_info(dev, "ZX GPIO chip registered\n");
284 static const struct of_device_id zx_gpio_match[] = {
286 .compatible = "zte,zx296702-gpio",
290 MODULE_DEVICE_TABLE(of, zx_gpio_match);
292 static struct platform_driver zx_gpio_driver = {
293 .probe = zx_gpio_probe,
296 .of_match_table = of_match_ptr(zx_gpio_match),
300 module_platform_driver(zx_gpio_driver)
302 MODULE_AUTHOR("Jun Nie <jun.nie@linaro.org>");
303 MODULE_DESCRIPTION("ZTE ZX296702 GPIO driver");
304 MODULE_LICENSE("GPL");