2 * Freescale i.MX28 GPIO control code
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/errno.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/imx-regs.h>
18 #if defined(CONFIG_SOC_MX23)
19 #define PINCTRL_BANKS 3
20 #define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10))
21 #define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10))
22 #define PINCTRL_DOE(n) (0x0700 + ((n) * 0x10))
23 #define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10))
24 #define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10))
25 #define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10))
26 #elif defined(CONFIG_SOC_MX28)
27 #define PINCTRL_BANKS 5
28 #define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10))
29 #define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10))
30 #define PINCTRL_DOE(n) (0x0b00 + ((n) * 0x10))
31 #define PINCTRL_PIN2IRQ(n) (0x1000 + ((n) * 0x10))
32 #define PINCTRL_IRQEN(n) (0x1100 + ((n) * 0x10))
33 #define PINCTRL_IRQSTAT(n) (0x1400 + ((n) * 0x10))
35 #error "Please select CONFIG_SOC_MX23 or CONFIG_SOC_MX28"
38 #define GPIO_INT_FALL_EDGE 0x0
39 #define GPIO_INT_LOW_LEV 0x1
40 #define GPIO_INT_RISE_EDGE 0x2
41 #define GPIO_INT_HIGH_LEV 0x3
42 #define GPIO_INT_LEV_MASK (1 << 0)
43 #define GPIO_INT_POL_MASK (1 << 1)
45 void mxs_gpio_init(void)
49 for (i = 0; i < PINCTRL_BANKS; i++) {
50 writel(0, MXS_PINCTRL_BASE + PINCTRL_PIN2IRQ(i));
51 writel(0, MXS_PINCTRL_BASE + PINCTRL_IRQEN(i));
52 /* Use SCT address here to clear the IRQSTAT bits */
53 writel(0xffffffff, MXS_PINCTRL_BASE + PINCTRL_IRQSTAT(i) + 8);
57 int gpio_get_value(unsigned gpio)
59 uint32_t bank = PAD_BANK(gpio);
60 uint32_t offset = PINCTRL_DIN(bank);
61 struct mxs_register_32 *reg =
62 (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
64 return (readl(®->reg) >> PAD_PIN(gpio)) & 1;
67 int gpio_set_value(unsigned gpio, int value)
69 uint32_t bank = PAD_BANK(gpio);
70 uint32_t offset = PINCTRL_DOUT(bank);
71 struct mxs_register_32 *reg =
72 (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
75 writel(1 << PAD_PIN(gpio), ®->reg_set);
77 writel(1 << PAD_PIN(gpio), ®->reg_clr);
82 int gpio_direction_input(unsigned gpio)
84 uint32_t bank = PAD_BANK(gpio);
85 uint32_t offset = PINCTRL_DOE(bank);
86 struct mxs_register_32 *reg =
87 (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
89 writel(1 << PAD_PIN(gpio), ®->reg_clr);
94 int gpio_direction_output(unsigned gpio, int value)
96 uint32_t bank = PAD_BANK(gpio);
97 uint32_t offset = PINCTRL_DOE(bank);
98 struct mxs_register_32 *reg =
99 (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
101 gpio_set_value(gpio, value);
103 writel(1 << PAD_PIN(gpio), ®->reg_set);
108 int gpio_request(unsigned gpio, const char *label)
110 if (PAD_BANK(gpio) >= PINCTRL_BANKS)
116 int gpio_free(unsigned gpio)