2 * linux/drivers/gpio/pl061.c
4 * Copyright (C) 2008, 2009 Provigent Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
12 * Data sheet: ARM DDI 0190B, September 2000
14 #include <linux/spinlock.h>
15 #include <linux/errno.h>
16 #include <linux/module.h>
17 #include <linux/list.h>
19 #include <linux/ioport.h>
20 #include <linux/irq.h>
21 #include <linux/bitops.h>
22 #include <linux/workqueue.h>
23 #include <linux/gpio.h>
24 #include <linux/device.h>
25 #include <linux/amba/bus.h>
26 #include <linux/amba/pl061.h>
27 #include <linux/slab.h>
38 #define PL061_GPIO_NR 8
41 /* We use a list of pl061_gpio structs for each trigger IRQ in the main
42 * interrupts controller of the system. We need this to support systems
43 * in which more that one PL061s are connected to the same IRQ. The ISR
44 * interates through this list to find the source of the interrupt.
46 struct list_head list;
48 /* Each of the two spinlocks protects a different set of hardware
49 * regiters and data structurs. This decouples the code of the IRQ from
50 * the GPIO code. This also makes the case of a GPIO routine call from
51 * the IRQ code simpler.
53 spinlock_t lock; /* GPIO registers */
54 spinlock_t irq_lock; /* IRQ registers */
61 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
63 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
65 unsigned char gpiodir;
67 if (offset >= gc->ngpio)
70 spin_lock_irqsave(&chip->lock, flags);
71 gpiodir = readb(chip->base + GPIODIR);
72 gpiodir &= ~(1 << offset);
73 writeb(gpiodir, chip->base + GPIODIR);
74 spin_unlock_irqrestore(&chip->lock, flags);
79 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
82 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
84 unsigned char gpiodir;
86 if (offset >= gc->ngpio)
89 spin_lock_irqsave(&chip->lock, flags);
90 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
91 gpiodir = readb(chip->base + GPIODIR);
92 gpiodir |= 1 << offset;
93 writeb(gpiodir, chip->base + GPIODIR);
94 spin_unlock_irqrestore(&chip->lock, flags);
99 static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
101 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
103 return !!readb(chip->base + (1 << (offset + 2)));
106 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
108 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
110 writeb(!!value << offset, chip->base + (1 << (offset + 2)));
113 static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
115 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
117 if (chip->irq_base == (unsigned) -1)
120 return chip->irq_base + offset;
126 static void pl061_irq_disable(unsigned irq)
128 struct pl061_gpio *chip = get_irq_chip_data(irq);
129 int offset = irq - chip->irq_base;
133 spin_lock_irqsave(&chip->irq_lock, flags);
134 gpioie = readb(chip->base + GPIOIE);
135 gpioie &= ~(1 << offset);
136 writeb(gpioie, chip->base + GPIOIE);
137 spin_unlock_irqrestore(&chip->irq_lock, flags);
140 static void pl061_irq_enable(unsigned irq)
142 struct pl061_gpio *chip = get_irq_chip_data(irq);
143 int offset = irq - chip->irq_base;
147 spin_lock_irqsave(&chip->irq_lock, flags);
148 gpioie = readb(chip->base + GPIOIE);
149 gpioie |= 1 << offset;
150 writeb(gpioie, chip->base + GPIOIE);
151 spin_unlock_irqrestore(&chip->irq_lock, flags);
154 static int pl061_irq_type(unsigned irq, unsigned trigger)
156 struct pl061_gpio *chip = get_irq_chip_data(irq);
157 int offset = irq - chip->irq_base;
159 u8 gpiois, gpioibe, gpioiev;
161 if (offset < 0 || offset > PL061_GPIO_NR)
164 spin_lock_irqsave(&chip->irq_lock, flags);
166 gpioiev = readb(chip->base + GPIOIEV);
168 gpiois = readb(chip->base + GPIOIS);
169 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
170 gpiois |= 1 << offset;
171 if (trigger & IRQ_TYPE_LEVEL_HIGH)
172 gpioiev |= 1 << offset;
174 gpioiev &= ~(1 << offset);
176 gpiois &= ~(1 << offset);
177 writeb(gpiois, chip->base + GPIOIS);
179 gpioibe = readb(chip->base + GPIOIBE);
180 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
181 gpioibe |= 1 << offset;
183 gpioibe &= ~(1 << offset);
184 if (trigger & IRQ_TYPE_EDGE_RISING)
185 gpioiev |= 1 << offset;
187 gpioiev &= ~(1 << offset);
189 writeb(gpioibe, chip->base + GPIOIBE);
191 writeb(gpioiev, chip->base + GPIOIEV);
193 spin_unlock_irqrestore(&chip->irq_lock, flags);
198 static struct irq_chip pl061_irqchip = {
200 .enable = pl061_irq_enable,
201 .disable = pl061_irq_disable,
202 .set_type = pl061_irq_type,
205 static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
207 struct list_head *chip_list = get_irq_chip_data(irq);
208 struct list_head *ptr;
209 struct pl061_gpio *chip;
211 desc->chip->ack(irq);
212 list_for_each(ptr, chip_list) {
213 unsigned long pending;
216 chip = list_entry(ptr, struct pl061_gpio, list);
217 pending = readb(chip->base + GPIOMIS);
218 writeb(pending, chip->base + GPIOIC);
223 for_each_set_bit(offset, &pending, PL061_GPIO_NR)
224 generic_handle_irq(pl061_to_irq(&chip->gc, offset));
226 desc->chip->unmask(irq);
229 static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
231 struct pl061_platform_data *pdata;
232 struct pl061_gpio *chip;
233 struct list_head *chip_list;
235 static DECLARE_BITMAP(init_irq, NR_IRQS);
237 pdata = dev->dev.platform_data;
241 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
245 if (!request_mem_region(dev->res.start,
246 resource_size(&dev->res), "pl061")) {
251 chip->base = ioremap(dev->res.start, resource_size(&dev->res));
252 if (chip->base == NULL) {
257 spin_lock_init(&chip->lock);
258 spin_lock_init(&chip->irq_lock);
259 INIT_LIST_HEAD(&chip->list);
261 chip->gc.direction_input = pl061_direction_input;
262 chip->gc.direction_output = pl061_direction_output;
263 chip->gc.get = pl061_get_value;
264 chip->gc.set = pl061_set_value;
265 chip->gc.to_irq = pl061_to_irq;
266 chip->gc.base = pdata->gpio_base;
267 chip->gc.ngpio = PL061_GPIO_NR;
268 chip->gc.label = dev_name(&dev->dev);
269 chip->gc.dev = &dev->dev;
270 chip->gc.owner = THIS_MODULE;
272 chip->irq_base = pdata->irq_base;
274 ret = gpiochip_add(&chip->gc);
282 if (chip->irq_base == (unsigned) -1)
285 writeb(0, chip->base + GPIOIE); /* disable irqs */
291 set_irq_chained_handler(irq, pl061_irq_handler);
292 if (!test_and_set_bit(irq, init_irq)) { /* list initialized? */
293 chip_list = kmalloc(sizeof(*chip_list), GFP_KERNEL);
294 if (chip_list == NULL) {
295 clear_bit(irq, init_irq);
299 INIT_LIST_HEAD(chip_list);
300 set_irq_chip_data(irq, chip_list);
302 chip_list = get_irq_chip_data(irq);
303 list_add(&chip->list, chip_list);
305 for (i = 0; i < PL061_GPIO_NR; i++) {
306 if (pdata->directions & (1 << i))
307 pl061_direction_output(&chip->gc, i,
308 pdata->values & (1 << i));
310 pl061_direction_input(&chip->gc, i);
312 set_irq_chip(i+chip->irq_base, &pl061_irqchip);
313 set_irq_handler(i+chip->irq_base, handle_simple_irq);
314 set_irq_flags(i+chip->irq_base, IRQF_VALID);
315 set_irq_chip_data(i+chip->irq_base, chip);
323 release_mem_region(dev->res.start, resource_size(&dev->res));
330 static struct amba_id pl061_ids[] __initdata = {
338 static struct amba_driver pl061_gpio_driver = {
340 .name = "pl061_gpio",
342 .id_table = pl061_ids,
343 .probe = pl061_probe,
346 static int __init pl061_gpio_init(void)
348 return amba_driver_register(&pl061_gpio_driver);
350 subsys_initcall(pl061_gpio_init);
352 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
353 MODULE_DESCRIPTION("PL061 GPIO driver");
354 MODULE_LICENSE("GPL");