2 * (C) Copyright 2009 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <dm/device-internal.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 #define S5P_GPIO_GET_PIN(x) (x % GPIO_PER_BANK)
21 #define CON_MASK(val) (0xf << ((val) << 2))
22 #define CON_SFR(gpio, cfg) ((cfg) << ((gpio) << 2))
23 #define CON_SFR_UNSHIFT(val, gpio) ((val) >> ((gpio) << 2))
25 #define DAT_MASK(gpio) (0x1 << (gpio))
26 #define DAT_SET(gpio) (0x1 << (gpio))
28 #define PULL_MASK(gpio) (0x3 << ((gpio) << 1))
29 #define PULL_MODE(gpio, pull) ((pull) << ((gpio) << 1))
31 #define DRV_MASK(gpio) (0x3 << ((gpio) << 1))
32 #define DRV_SET(gpio, mode) ((mode) << ((gpio) << 1))
33 #define RATE_MASK(gpio) (0x1 << (gpio + 16))
34 #define RATE_SET(gpio) (0x1 << (gpio + 16))
36 #define GPIO_NAME_SIZE 20
38 /* Platform data for each bank */
39 struct exynos_gpio_platdata {
40 struct s5p_gpio_bank *bank;
41 const char *bank_name; /* Name of port, e.g. 'gpa0" */
44 /* Information about each bank at run-time */
45 struct exynos_bank_info {
46 char label[GPIO_PER_BANK][GPIO_NAME_SIZE];
47 struct s5p_gpio_bank *bank;
50 static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
52 const struct gpio_info *data;
56 data = get_gpio_data();
57 count = get_bank_num();
60 for (i = 0; i < count; i++) {
61 debug("i=%d, upto=%d\n", i, upto);
62 if (gpio < data->max_gpio) {
63 struct s5p_gpio_bank *bank;
64 bank = (struct s5p_gpio_bank *)data->reg_addr;
65 bank += (gpio - upto) / GPIO_PER_BANK;
66 debug("gpio=%d, bank=%p\n", gpio, bank);
70 upto = data->max_gpio;
77 static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
81 value = readl(&bank->con);
82 value &= ~CON_MASK(gpio);
83 value |= CON_SFR(gpio, cfg);
84 writel(value, &bank->con);
87 static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
91 value = readl(&bank->dat);
92 value &= ~DAT_MASK(gpio);
94 value |= DAT_SET(gpio);
95 writel(value, &bank->dat);
98 #ifdef CONFIG_SPL_BUILD
99 /* Common GPIO API - SPL does not support driver model yet */
100 int gpio_set_value(unsigned gpio, int value)
102 s5p_gpio_set_value(s5p_gpio_get_bank(gpio),
103 s5p_gpio_get_pin(gpio), value);
108 static int s5p_gpio_get_cfg_pin(struct s5p_gpio_bank *bank, int gpio)
112 value = readl(&bank->con);
113 value &= CON_MASK(gpio);
114 return CON_SFR_UNSHIFT(value, gpio);
117 static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
121 value = readl(&bank->dat);
122 return !!(value & DAT_MASK(gpio));
124 #endif /* CONFIG_SPL_BUILD */
126 static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
130 value = readl(&bank->pull);
131 value &= ~PULL_MASK(gpio);
134 case S5P_GPIO_PULL_DOWN:
135 case S5P_GPIO_PULL_UP:
136 value |= PULL_MODE(gpio, mode);
142 writel(value, &bank->pull);
145 static void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
149 value = readl(&bank->drv);
150 value &= ~DRV_MASK(gpio);
153 case S5P_GPIO_DRV_1X:
154 case S5P_GPIO_DRV_2X:
155 case S5P_GPIO_DRV_3X:
156 case S5P_GPIO_DRV_4X:
157 value |= DRV_SET(gpio, mode);
163 writel(value, &bank->drv);
166 static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
170 value = readl(&bank->drv);
171 value &= ~RATE_MASK(gpio);
174 case S5P_GPIO_DRV_FAST:
175 case S5P_GPIO_DRV_SLOW:
176 value |= RATE_SET(gpio);
182 writel(value, &bank->drv);
185 int s5p_gpio_get_pin(unsigned gpio)
187 return S5P_GPIO_GET_PIN(gpio);
190 /* Driver model interface */
191 #ifndef CONFIG_SPL_BUILD
192 static int exynos_gpio_get_state(struct udevice *dev, unsigned int offset,
193 char *buf, int bufsize)
195 struct gpio_dev_priv *uc_priv = dev->uclass_priv;
196 struct exynos_bank_info *state = dev_get_priv(dev);
202 label = state->label[offset];
203 cfg = s5p_gpio_get_cfg_pin(state->bank, offset);
204 is_output = cfg == S5P_GPIO_OUTPUT;
205 size = snprintf(buf, bufsize, "%s%d: ",
206 uc_priv->bank_name ? uc_priv->bank_name : "", offset);
209 if (is_output || cfg == S5P_GPIO_INPUT) {
210 snprintf(buf, bufsize, "%s: %d [%c]%s%s",
211 is_output ? "out" : " in",
212 s5p_gpio_get_value(state->bank, offset),
217 snprintf(buf, bufsize, "sfpio");
223 static int check_reserved(struct udevice *dev, unsigned offset,
226 struct exynos_bank_info *state = dev_get_priv(dev);
227 struct gpio_dev_priv *uc_priv = dev->uclass_priv;
229 if (!*state->label[offset]) {
230 printf("exynos_gpio: %s: error: gpio %s%d not reserved\n",
231 func, uc_priv->bank_name, offset);
238 /* set GPIO pin 'gpio' as an input */
239 static int exynos_gpio_direction_input(struct udevice *dev, unsigned offset)
241 struct exynos_bank_info *state = dev_get_priv(dev);
244 ret = check_reserved(dev, offset, __func__);
248 /* Configure GPIO direction as input. */
249 s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_INPUT);
254 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
255 static int exynos_gpio_direction_output(struct udevice *dev, unsigned offset,
258 struct exynos_bank_info *state = dev_get_priv(dev);
261 ret = check_reserved(dev, offset, __func__);
265 /* Configure GPIO output value. */
266 s5p_gpio_set_value(state->bank, offset, value);
268 /* Configure GPIO direction as output. */
269 s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_OUTPUT);
274 /* read GPIO IN value of pin 'gpio' */
275 static int exynos_gpio_get_value(struct udevice *dev, unsigned offset)
277 struct exynos_bank_info *state = dev_get_priv(dev);
280 ret = check_reserved(dev, offset, __func__);
284 return s5p_gpio_get_value(state->bank, offset);
287 /* write GPIO OUT value to pin 'gpio' */
288 static int exynos_gpio_set_value(struct udevice *dev, unsigned offset,
291 struct exynos_bank_info *state = dev_get_priv(dev);
294 ret = check_reserved(dev, offset, __func__);
298 s5p_gpio_set_value(state->bank, offset, value);
303 static int exynos_gpio_request(struct udevice *dev, unsigned offset,
306 struct exynos_bank_info *state = dev_get_priv(dev);
308 if (*state->label[offset])
311 strncpy(state->label[offset], label, GPIO_NAME_SIZE);
312 state->label[offset][GPIO_NAME_SIZE - 1] = '\0';
317 static int exynos_gpio_free(struct udevice *dev, unsigned offset)
319 struct exynos_bank_info *state = dev_get_priv(dev);
322 ret = check_reserved(dev, offset, __func__);
325 state->label[offset][0] = '\0';
329 #endif /* nCONFIG_SPL_BUILD */
332 * There is no common GPIO API for pull, drv, pin, rate (yet). These
333 * functions are kept here to preserve function ordering for review.
335 void gpio_set_pull(int gpio, int mode)
337 s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
338 s5p_gpio_get_pin(gpio), mode);
341 void gpio_set_drv(int gpio, int mode)
343 s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
344 s5p_gpio_get_pin(gpio), mode);
347 void gpio_cfg_pin(int gpio, int cfg)
349 s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
350 s5p_gpio_get_pin(gpio), cfg);
353 void gpio_set_rate(int gpio, int mode)
355 s5p_gpio_set_rate(s5p_gpio_get_bank(gpio),
356 s5p_gpio_get_pin(gpio), mode);
359 #ifndef CONFIG_SPL_BUILD
360 static int exynos_gpio_get_function(struct udevice *dev, unsigned offset)
362 struct exynos_bank_info *state = dev_get_priv(dev);
365 if (!*state->label[offset])
367 cfg = s5p_gpio_get_cfg_pin(state->bank, offset);
368 if (cfg == S5P_GPIO_OUTPUT)
370 else if (cfg == S5P_GPIO_INPUT)
376 static const struct dm_gpio_ops gpio_exynos_ops = {
377 .request = exynos_gpio_request,
378 .free = exynos_gpio_free,
379 .direction_input = exynos_gpio_direction_input,
380 .direction_output = exynos_gpio_direction_output,
381 .get_value = exynos_gpio_get_value,
382 .set_value = exynos_gpio_set_value,
383 .get_function = exynos_gpio_get_function,
384 .get_state = exynos_gpio_get_state,
387 static int gpio_exynos_probe(struct udevice *dev)
389 struct gpio_dev_priv *uc_priv = dev->uclass_priv;
390 struct exynos_bank_info *priv = dev->priv;
391 struct exynos_gpio_platdata *plat = dev->platdata;
393 /* Only child devices have ports */
397 priv->bank = plat->bank;
399 uc_priv->gpio_count = GPIO_PER_BANK;
400 uc_priv->bank_name = plat->bank_name;
406 * We have a top-level GPIO device with no actual GPIOs. It has a child
407 * device for each Exynos GPIO bank.
409 static int gpio_exynos_bind(struct udevice *parent)
411 struct exynos_gpio_platdata *plat = parent->platdata;
412 struct s5p_gpio_bank *bank, *base;
413 const void *blob = gd->fdt_blob;
416 /* If this is a child device, there is nothing to do here */
420 base = (struct s5p_gpio_bank *)fdtdec_get_addr(gd->fdt_blob,
421 parent->of_offset, "reg");
422 for (node = fdt_first_subnode(blob, parent->of_offset), bank = base;
424 node = fdt_next_subnode(blob, node), bank++) {
425 struct exynos_gpio_platdata *plat;
430 if (!fdtdec_get_bool(blob, node, "gpio-controller"))
432 plat = calloc(1, sizeof(*plat));
435 reg = fdtdec_get_addr(blob, node, "reg");
436 if (reg != FDT_ADDR_T_NONE)
437 bank = (struct s5p_gpio_bank *)((ulong)base + reg);
439 plat->bank_name = fdt_get_name(blob, node, NULL);
440 debug("dev at %p: %s\n", bank, plat->bank_name);
442 ret = device_bind(parent, parent->driver,
443 plat->bank_name, plat, -1, &dev);
446 dev->of_offset = parent->of_offset;
452 static const struct udevice_id exynos_gpio_ids[] = {
453 { .compatible = "samsung,s5pc100-pinctrl" },
454 { .compatible = "samsung,s5pc110-pinctrl" },
455 { .compatible = "samsung,exynos4210-pinctrl" },
456 { .compatible = "samsung,exynos4x12-pinctrl" },
457 { .compatible = "samsung,exynos5250-pinctrl" },
458 { .compatible = "samsung,exynos5420-pinctrl" },
462 U_BOOT_DRIVER(gpio_exynos) = {
463 .name = "gpio_exynos",
465 .of_match = exynos_gpio_ids,
466 .bind = gpio_exynos_bind,
467 .probe = gpio_exynos_probe,
468 .priv_auto_alloc_size = sizeof(struct exynos_bank_info),
469 .ops = &gpio_exynos_ops,