2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/list.h>
25 #include <linux/slab.h>
26 #include <linux/pci.h>
28 #include <linux/firmware.h>
29 #include <drm/amdgpu_drm.h>
31 #include "cgs_linux.h"
33 #include "amdgpu_ucode.h"
36 struct amdgpu_cgs_device {
37 struct cgs_device base;
38 struct amdgpu_device *adev;
41 #define CGS_FUNC_ADEV \
42 struct amdgpu_device *adev = \
43 ((struct amdgpu_cgs_device *)cgs_device)->adev
45 static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type,
46 uint64_t *mc_start, uint64_t *mc_size,
51 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
52 case CGS_GPU_MEM_TYPE__VISIBLE_FB:
54 *mc_size = adev->mc.visible_vram_size;
55 *mem_size = adev->mc.visible_vram_size - adev->vram_pin_size;
57 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
58 case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
59 *mc_start = adev->mc.visible_vram_size;
60 *mc_size = adev->mc.real_vram_size - adev->mc.visible_vram_size;
63 case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
64 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
65 *mc_start = adev->mc.gtt_start;
66 *mc_size = adev->mc.gtt_size;
67 *mem_size = adev->mc.gtt_size - adev->gart_pin_size;
76 static int amdgpu_cgs_gmap_kmem(void *cgs_device, void *kmem,
78 uint64_t min_offset, uint64_t max_offset,
79 cgs_handle_t *kmem_handle, uint64_t *mcaddr)
84 struct page *kmem_page = vmalloc_to_page(kmem);
85 int npages = ALIGN(size, PAGE_SIZE) >> PAGE_SHIFT;
87 struct sg_table *sg = drm_prime_pages_to_sg(&kmem_page, npages);
88 ret = amdgpu_bo_create(adev, size, PAGE_SIZE, false,
89 AMDGPU_GEM_DOMAIN_GTT, 0, sg, &bo);
92 ret = amdgpu_bo_reserve(bo, false);
93 if (unlikely(ret != 0))
96 /* pin buffer into GTT */
97 ret = amdgpu_bo_pin_restricted(bo, AMDGPU_GEM_DOMAIN_GTT,
98 min_offset, max_offset, mcaddr);
99 amdgpu_bo_unreserve(bo);
101 *kmem_handle = (cgs_handle_t)bo;
105 static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle)
107 struct amdgpu_bo *obj = (struct amdgpu_bo *)kmem_handle;
110 int r = amdgpu_bo_reserve(obj, false);
111 if (likely(r == 0)) {
112 amdgpu_bo_unpin(obj);
113 amdgpu_bo_unreserve(obj);
115 amdgpu_bo_unref(&obj);
121 static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device,
122 enum cgs_gpu_mem_type type,
123 uint64_t size, uint64_t align,
124 uint64_t min_offset, uint64_t max_offset,
125 cgs_handle_t *handle)
131 struct amdgpu_bo *obj;
132 struct ttm_placement placement;
133 struct ttm_place place;
135 if (min_offset > max_offset) {
140 /* fail if the alignment is not a power of 2 */
141 if (((align != 1) && (align & (align - 1)))
142 || size == 0 || align == 0)
147 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
148 case CGS_GPU_MEM_TYPE__VISIBLE_FB:
149 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
150 domain = AMDGPU_GEM_DOMAIN_VRAM;
151 if (max_offset > adev->mc.real_vram_size)
153 place.fpfn = min_offset >> PAGE_SHIFT;
154 place.lpfn = max_offset >> PAGE_SHIFT;
155 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
158 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
159 case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
160 flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
161 domain = AMDGPU_GEM_DOMAIN_VRAM;
162 if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
164 max(min_offset, adev->mc.visible_vram_size) >> PAGE_SHIFT;
166 min(max_offset, adev->mc.real_vram_size) >> PAGE_SHIFT;
167 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
172 case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
173 domain = AMDGPU_GEM_DOMAIN_GTT;
174 place.fpfn = min_offset >> PAGE_SHIFT;
175 place.lpfn = max_offset >> PAGE_SHIFT;
176 place.flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
178 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
179 flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
180 domain = AMDGPU_GEM_DOMAIN_GTT;
181 place.fpfn = min_offset >> PAGE_SHIFT;
182 place.lpfn = max_offset >> PAGE_SHIFT;
183 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
184 TTM_PL_FLAG_UNCACHED;
193 placement.placement = &place;
194 placement.num_placement = 1;
195 placement.busy_placement = &place;
196 placement.num_busy_placement = 1;
198 ret = amdgpu_bo_create_restricted(adev, size, PAGE_SIZE,
200 NULL, &placement, &obj);
202 DRM_ERROR("(%d) bo create failed\n", ret);
205 *handle = (cgs_handle_t)obj;
210 static int amdgpu_cgs_import_gpu_mem(void *cgs_device, int dmabuf_fd,
211 cgs_handle_t *handle)
216 struct drm_gem_object *obj;
217 struct amdgpu_bo *bo;
218 struct drm_device *dev = adev->ddev;
219 struct drm_file *file_priv = NULL, *priv;
221 mutex_lock(&dev->struct_mutex);
222 list_for_each_entry(priv, &dev->filelist, lhead) {
224 if (priv->pid == get_pid(task_pid(current)))
230 mutex_unlock(&dev->struct_mutex);
231 r = dev->driver->prime_fd_to_handle(dev,
232 file_priv, dmabuf_fd,
234 spin_lock(&file_priv->table_lock);
236 /* Check if we currently have a reference on the object */
237 obj = idr_find(&file_priv->object_idr, dma_handle);
239 spin_unlock(&file_priv->table_lock);
242 spin_unlock(&file_priv->table_lock);
243 bo = gem_to_amdgpu_bo(obj);
244 *handle = (cgs_handle_t)bo;
248 static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle)
250 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
253 int r = amdgpu_bo_reserve(obj, false);
254 if (likely(r == 0)) {
255 amdgpu_bo_kunmap(obj);
256 amdgpu_bo_unpin(obj);
257 amdgpu_bo_unreserve(obj);
259 amdgpu_bo_unref(&obj);
265 static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
269 u64 min_offset, max_offset;
270 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
272 WARN_ON_ONCE(obj->placement.num_placement > 1);
274 min_offset = obj->placements[0].fpfn << PAGE_SHIFT;
275 max_offset = obj->placements[0].lpfn << PAGE_SHIFT;
277 r = amdgpu_bo_reserve(obj, false);
278 if (unlikely(r != 0))
280 r = amdgpu_bo_pin_restricted(obj, AMDGPU_GEM_DOMAIN_GTT,
281 min_offset, max_offset, mcaddr);
282 amdgpu_bo_unreserve(obj);
286 static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
289 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
290 r = amdgpu_bo_reserve(obj, false);
291 if (unlikely(r != 0))
293 r = amdgpu_bo_unpin(obj);
294 amdgpu_bo_unreserve(obj);
298 static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
302 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
303 r = amdgpu_bo_reserve(obj, false);
304 if (unlikely(r != 0))
306 r = amdgpu_bo_kmap(obj, map);
307 amdgpu_bo_unreserve(obj);
311 static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
314 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
315 r = amdgpu_bo_reserve(obj, false);
316 if (unlikely(r != 0))
318 amdgpu_bo_kunmap(obj);
319 amdgpu_bo_unreserve(obj);
323 static uint32_t amdgpu_cgs_read_register(void *cgs_device, unsigned offset)
326 return RREG32(offset);
329 static void amdgpu_cgs_write_register(void *cgs_device, unsigned offset,
333 WREG32(offset, value);
336 static uint32_t amdgpu_cgs_read_ind_register(void *cgs_device,
337 enum cgs_ind_reg space,
342 case CGS_IND_REG__MMIO:
343 return RREG32_IDX(index);
344 case CGS_IND_REG__PCIE:
345 return RREG32_PCIE(index);
346 case CGS_IND_REG__SMC:
347 return RREG32_SMC(index);
348 case CGS_IND_REG__UVD_CTX:
349 return RREG32_UVD_CTX(index);
350 case CGS_IND_REG__DIDT:
351 return RREG32_DIDT(index);
352 case CGS_IND_REG__AUDIO_ENDPT:
353 DRM_ERROR("audio endpt register access not implemented.\n");
356 WARN(1, "Invalid indirect register space");
360 static void amdgpu_cgs_write_ind_register(void *cgs_device,
361 enum cgs_ind_reg space,
362 unsigned index, uint32_t value)
366 case CGS_IND_REG__MMIO:
367 return WREG32_IDX(index, value);
368 case CGS_IND_REG__PCIE:
369 return WREG32_PCIE(index, value);
370 case CGS_IND_REG__SMC:
371 return WREG32_SMC(index, value);
372 case CGS_IND_REG__UVD_CTX:
373 return WREG32_UVD_CTX(index, value);
374 case CGS_IND_REG__DIDT:
375 return WREG32_DIDT(index, value);
376 case CGS_IND_REG__AUDIO_ENDPT:
377 DRM_ERROR("audio endpt register access not implemented.\n");
380 WARN(1, "Invalid indirect register space");
383 static uint8_t amdgpu_cgs_read_pci_config_byte(void *cgs_device, unsigned addr)
387 int ret = pci_read_config_byte(adev->pdev, addr, &val);
388 if (WARN(ret, "pci_read_config_byte error"))
393 static uint16_t amdgpu_cgs_read_pci_config_word(void *cgs_device, unsigned addr)
397 int ret = pci_read_config_word(adev->pdev, addr, &val);
398 if (WARN(ret, "pci_read_config_word error"))
403 static uint32_t amdgpu_cgs_read_pci_config_dword(void *cgs_device,
408 int ret = pci_read_config_dword(adev->pdev, addr, &val);
409 if (WARN(ret, "pci_read_config_dword error"))
414 static void amdgpu_cgs_write_pci_config_byte(void *cgs_device, unsigned addr,
418 int ret = pci_write_config_byte(adev->pdev, addr, value);
419 WARN(ret, "pci_write_config_byte error");
422 static void amdgpu_cgs_write_pci_config_word(void *cgs_device, unsigned addr,
426 int ret = pci_write_config_word(adev->pdev, addr, value);
427 WARN(ret, "pci_write_config_word error");
430 static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr,
434 int ret = pci_write_config_dword(adev->pdev, addr, value);
435 WARN(ret, "pci_write_config_dword error");
438 static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device,
439 unsigned table, uint16_t *size,
440 uint8_t *frev, uint8_t *crev)
445 if (amdgpu_atom_parse_data_header(
446 adev->mode_info.atom_context, table, size,
447 frev, crev, &data_start))
448 return (uint8_t*)adev->mode_info.atom_context->bios +
454 static int amdgpu_cgs_atom_get_cmd_table_revs(void *cgs_device, unsigned table,
455 uint8_t *frev, uint8_t *crev)
459 if (amdgpu_atom_parse_cmd_header(
460 adev->mode_info.atom_context, table,
467 static int amdgpu_cgs_atom_exec_cmd_table(void *cgs_device, unsigned table,
472 return amdgpu_atom_execute_table(
473 adev->mode_info.atom_context, table, args);
476 static int amdgpu_cgs_create_pm_request(void *cgs_device, cgs_handle_t *request)
482 static int amdgpu_cgs_destroy_pm_request(void *cgs_device, cgs_handle_t request)
488 static int amdgpu_cgs_set_pm_request(void *cgs_device, cgs_handle_t request,
495 static int amdgpu_cgs_pm_request_clock(void *cgs_device, cgs_handle_t request,
496 enum cgs_clock clock, unsigned freq)
502 static int amdgpu_cgs_pm_request_engine(void *cgs_device, cgs_handle_t request,
503 enum cgs_engine engine, int powered)
511 static int amdgpu_cgs_pm_query_clock_limits(void *cgs_device,
512 enum cgs_clock clock,
513 struct cgs_clock_limits *limits)
519 static int amdgpu_cgs_set_camera_voltages(void *cgs_device, uint32_t mask,
520 const uint32_t *voltages)
522 DRM_ERROR("not implemented");
526 struct cgs_irq_params {
528 cgs_irq_source_set_func_t set;
529 cgs_irq_handler_func_t handler;
533 static int cgs_set_irq_state(struct amdgpu_device *adev,
534 struct amdgpu_irq_src *src,
536 enum amdgpu_interrupt_state state)
538 struct cgs_irq_params *irq_params =
539 (struct cgs_irq_params *)src->data;
542 if (!irq_params->set)
544 return irq_params->set(irq_params->private_data,
550 static int cgs_process_irq(struct amdgpu_device *adev,
551 struct amdgpu_irq_src *source,
552 struct amdgpu_iv_entry *entry)
554 struct cgs_irq_params *irq_params =
555 (struct cgs_irq_params *)source->data;
558 if (!irq_params->handler)
560 return irq_params->handler(irq_params->private_data,
565 static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
566 .set = cgs_set_irq_state,
567 .process = cgs_process_irq,
570 static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id,
572 cgs_irq_source_set_func_t set,
573 cgs_irq_handler_func_t handler,
578 struct cgs_irq_params *irq_params;
579 struct amdgpu_irq_src *source =
580 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
584 kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
589 source->num_types = num_types;
590 source->funcs = &cgs_irq_funcs;
591 irq_params->src_id = src_id;
592 irq_params->set = set;
593 irq_params->handler = handler;
594 irq_params->private_data = private_data;
595 source->data = (void *)irq_params;
596 ret = amdgpu_irq_add_id(adev, src_id, source);
605 static int amdgpu_cgs_irq_get(void *cgs_device, unsigned src_id, unsigned type)
608 return amdgpu_irq_get(adev, adev->irq.sources[src_id], type);
611 static int amdgpu_cgs_irq_put(void *cgs_device, unsigned src_id, unsigned type)
614 return amdgpu_irq_put(adev, adev->irq.sources[src_id], type);
617 int amdgpu_cgs_set_clockgating_state(void *cgs_device,
618 enum amd_ip_block_type block_type,
619 enum amd_clockgating_state state)
624 for (i = 0; i < adev->num_ip_blocks; i++) {
625 if (!adev->ip_block_status[i].valid)
628 if (adev->ip_blocks[i].type == block_type) {
629 r = adev->ip_blocks[i].funcs->set_clockgating_state(
638 int amdgpu_cgs_set_powergating_state(void *cgs_device,
639 enum amd_ip_block_type block_type,
640 enum amd_powergating_state state)
645 for (i = 0; i < adev->num_ip_blocks; i++) {
646 if (!adev->ip_block_status[i].valid)
649 if (adev->ip_blocks[i].type == block_type) {
650 r = adev->ip_blocks[i].funcs->set_powergating_state(
660 static uint32_t fw_type_convert(void *cgs_device, uint32_t fw_type)
663 enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;
666 case CGS_UCODE_ID_SDMA0:
667 result = AMDGPU_UCODE_ID_SDMA0;
669 case CGS_UCODE_ID_SDMA1:
670 result = AMDGPU_UCODE_ID_SDMA1;
672 case CGS_UCODE_ID_CP_CE:
673 result = AMDGPU_UCODE_ID_CP_CE;
675 case CGS_UCODE_ID_CP_PFP:
676 result = AMDGPU_UCODE_ID_CP_PFP;
678 case CGS_UCODE_ID_CP_ME:
679 result = AMDGPU_UCODE_ID_CP_ME;
681 case CGS_UCODE_ID_CP_MEC:
682 case CGS_UCODE_ID_CP_MEC_JT1:
683 result = AMDGPU_UCODE_ID_CP_MEC1;
685 case CGS_UCODE_ID_CP_MEC_JT2:
686 if (adev->asic_type == CHIP_TONGA)
687 result = AMDGPU_UCODE_ID_CP_MEC2;
688 else if (adev->asic_type == CHIP_CARRIZO)
689 result = AMDGPU_UCODE_ID_CP_MEC1;
691 case CGS_UCODE_ID_RLC_G:
692 result = AMDGPU_UCODE_ID_RLC_G;
695 DRM_ERROR("Firmware type not supported\n");
700 static int amdgpu_cgs_get_firmware_info(void *cgs_device,
701 enum cgs_ucode_id type,
702 struct cgs_firmware_info *info)
706 if (CGS_UCODE_ID_SMU != type) {
709 const struct gfx_firmware_header_v1_0 *header;
710 enum AMDGPU_UCODE_ID id;
711 struct amdgpu_firmware_info *ucode;
713 id = fw_type_convert(cgs_device, type);
714 ucode = &adev->firmware.ucode[id];
715 if (ucode->fw == NULL)
718 gpu_addr = ucode->mc_addr;
719 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
720 data_size = le32_to_cpu(header->header.ucode_size_bytes);
722 if ((type == CGS_UCODE_ID_CP_MEC_JT1) ||
723 (type == CGS_UCODE_ID_CP_MEC_JT2)) {
724 gpu_addr += le32_to_cpu(header->jt_offset) << 2;
725 data_size = le32_to_cpu(header->jt_size) << 2;
727 info->mc_addr = gpu_addr;
728 info->image_size = data_size;
729 info->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
730 info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version);
732 char fw_name[30] = {0};
735 uint32_t ucode_start_address;
737 const struct smc_firmware_header_v1_0 *hdr;
739 switch (adev->asic_type) {
741 strcpy(fw_name, "amdgpu/tonga_smc.bin");
744 DRM_ERROR("SMC firmware not supported\n");
748 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
750 DRM_ERROR("Failed to request firmware\n");
754 err = amdgpu_ucode_validate(adev->pm.fw);
756 DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
757 release_firmware(adev->pm.fw);
762 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
763 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
764 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
765 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
766 src = (const uint8_t *)(adev->pm.fw->data +
767 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
769 info->version = adev->pm.fw_version;
770 info->image_size = ucode_size;
771 info->kptr = (void *)src;
776 static const struct cgs_ops amdgpu_cgs_ops = {
777 amdgpu_cgs_gpu_mem_info,
778 amdgpu_cgs_gmap_kmem,
779 amdgpu_cgs_gunmap_kmem,
780 amdgpu_cgs_alloc_gpu_mem,
781 amdgpu_cgs_free_gpu_mem,
782 amdgpu_cgs_gmap_gpu_mem,
783 amdgpu_cgs_gunmap_gpu_mem,
784 amdgpu_cgs_kmap_gpu_mem,
785 amdgpu_cgs_kunmap_gpu_mem,
786 amdgpu_cgs_read_register,
787 amdgpu_cgs_write_register,
788 amdgpu_cgs_read_ind_register,
789 amdgpu_cgs_write_ind_register,
790 amdgpu_cgs_read_pci_config_byte,
791 amdgpu_cgs_read_pci_config_word,
792 amdgpu_cgs_read_pci_config_dword,
793 amdgpu_cgs_write_pci_config_byte,
794 amdgpu_cgs_write_pci_config_word,
795 amdgpu_cgs_write_pci_config_dword,
796 amdgpu_cgs_atom_get_data_table,
797 amdgpu_cgs_atom_get_cmd_table_revs,
798 amdgpu_cgs_atom_exec_cmd_table,
799 amdgpu_cgs_create_pm_request,
800 amdgpu_cgs_destroy_pm_request,
801 amdgpu_cgs_set_pm_request,
802 amdgpu_cgs_pm_request_clock,
803 amdgpu_cgs_pm_request_engine,
804 amdgpu_cgs_pm_query_clock_limits,
805 amdgpu_cgs_set_camera_voltages,
806 amdgpu_cgs_get_firmware_info,
807 amdgpu_cgs_set_powergating_state,
808 amdgpu_cgs_set_clockgating_state
811 static const struct cgs_os_ops amdgpu_cgs_os_ops = {
812 amdgpu_cgs_import_gpu_mem,
813 amdgpu_cgs_add_irq_source,
818 void *amdgpu_cgs_create_device(struct amdgpu_device *adev)
820 struct amdgpu_cgs_device *cgs_device =
821 kmalloc(sizeof(*cgs_device), GFP_KERNEL);
824 DRM_ERROR("Couldn't allocate CGS device structure\n");
828 cgs_device->base.ops = &amdgpu_cgs_ops;
829 cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
830 cgs_device->adev = adev;
835 void amdgpu_cgs_destroy_device(void *cgs_device)