2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/amdgpu_drm.h>
35 #include <linux/vgaarb.h>
36 #include <linux/vga_switcheroo.h>
37 #include <linux/efi.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_i2c.h"
42 #include "amdgpu_atombios.h"
43 #include "amdgpu_atomfirmware.h"
45 #ifdef CONFIG_DRM_AMDGPU_SI
48 #ifdef CONFIG_DRM_AMDGPU_CIK
53 #include "bif/bif_4_1_d.h"
54 #include <linux/pci.h>
55 #include <linux/firmware.h>
57 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
58 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
60 static const char *amdgpu_asic_name[] = {
83 bool amdgpu_device_is_px(struct drm_device *dev)
85 struct amdgpu_device *adev = dev->dev_private;
87 if (adev->flags & AMD_IS_PX)
93 * MMIO register access helper functions.
95 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
100 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
101 BUG_ON(in_interrupt());
102 return amdgpu_virt_kiq_rreg(adev, reg);
105 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
106 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
110 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
111 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
112 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
113 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
115 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
119 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
122 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
124 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
125 BUG_ON(in_interrupt());
126 return amdgpu_virt_kiq_wreg(adev, reg, v);
129 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
130 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
134 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
135 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
136 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
137 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
141 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
143 if ((reg * 4) < adev->rio_mem_size)
144 return ioread32(adev->rio_mem + (reg * 4));
146 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
147 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
151 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
154 if ((reg * 4) < adev->rio_mem_size)
155 iowrite32(v, adev->rio_mem + (reg * 4));
157 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
158 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
163 * amdgpu_mm_rdoorbell - read a doorbell dword
165 * @adev: amdgpu_device pointer
166 * @index: doorbell index
168 * Returns the value in the doorbell aperture at the
169 * requested doorbell index (CIK).
171 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
173 if (index < adev->doorbell.num_doorbells) {
174 return readl(adev->doorbell.ptr + index);
176 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
182 * amdgpu_mm_wdoorbell - write a doorbell dword
184 * @adev: amdgpu_device pointer
185 * @index: doorbell index
188 * Writes @v to the doorbell aperture at the
189 * requested doorbell index (CIK).
191 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
193 if (index < adev->doorbell.num_doorbells) {
194 writel(v, adev->doorbell.ptr + index);
196 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
201 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
203 * @adev: amdgpu_device pointer
204 * @index: doorbell index
206 * Returns the value in the doorbell aperture at the
207 * requested doorbell index (VEGA10+).
209 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
211 if (index < adev->doorbell.num_doorbells) {
212 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
214 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
220 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
222 * @adev: amdgpu_device pointer
223 * @index: doorbell index
226 * Writes @v to the doorbell aperture at the
227 * requested doorbell index (VEGA10+).
229 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
231 if (index < adev->doorbell.num_doorbells) {
232 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
234 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
239 * amdgpu_invalid_rreg - dummy reg read function
241 * @adev: amdgpu device pointer
242 * @reg: offset of register
244 * Dummy register read function. Used for register blocks
245 * that certain asics don't have (all asics).
246 * Returns the value in the register.
248 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
250 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
256 * amdgpu_invalid_wreg - dummy reg write function
258 * @adev: amdgpu device pointer
259 * @reg: offset of register
260 * @v: value to write to the register
262 * Dummy register read function. Used for register blocks
263 * that certain asics don't have (all asics).
265 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
267 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
273 * amdgpu_block_invalid_rreg - dummy reg read function
275 * @adev: amdgpu device pointer
276 * @block: offset of instance
277 * @reg: offset of register
279 * Dummy register read function. Used for register blocks
280 * that certain asics don't have (all asics).
281 * Returns the value in the register.
283 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
284 uint32_t block, uint32_t reg)
286 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
293 * amdgpu_block_invalid_wreg - dummy reg write function
295 * @adev: amdgpu device pointer
296 * @block: offset of instance
297 * @reg: offset of register
298 * @v: value to write to the register
300 * Dummy register read function. Used for register blocks
301 * that certain asics don't have (all asics).
303 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
305 uint32_t reg, uint32_t v)
307 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
312 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
316 if (adev->vram_scratch.robj == NULL) {
317 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
318 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
319 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
320 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
321 NULL, NULL, &adev->vram_scratch.robj);
327 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
328 if (unlikely(r != 0))
330 r = amdgpu_bo_pin(adev->vram_scratch.robj,
331 AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
333 amdgpu_bo_unreserve(adev->vram_scratch.robj);
336 r = amdgpu_bo_kmap(adev->vram_scratch.robj,
337 (void **)&adev->vram_scratch.ptr);
339 amdgpu_bo_unpin(adev->vram_scratch.robj);
340 amdgpu_bo_unreserve(adev->vram_scratch.robj);
345 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
349 if (adev->vram_scratch.robj == NULL) {
352 r = amdgpu_bo_reserve(adev->vram_scratch.robj, true);
353 if (likely(r == 0)) {
354 amdgpu_bo_kunmap(adev->vram_scratch.robj);
355 amdgpu_bo_unpin(adev->vram_scratch.robj);
356 amdgpu_bo_unreserve(adev->vram_scratch.robj);
358 amdgpu_bo_unref(&adev->vram_scratch.robj);
362 * amdgpu_program_register_sequence - program an array of registers.
364 * @adev: amdgpu_device pointer
365 * @registers: pointer to the register array
366 * @array_size: size of the register array
368 * Programs an array or registers with and and or masks.
369 * This is a helper for setting golden registers.
371 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
372 const u32 *registers,
373 const u32 array_size)
375 u32 tmp, reg, and_mask, or_mask;
381 for (i = 0; i < array_size; i +=3) {
382 reg = registers[i + 0];
383 and_mask = registers[i + 1];
384 or_mask = registers[i + 2];
386 if (and_mask == 0xffffffff) {
397 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
399 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
403 * GPU doorbell aperture helpers function.
406 * amdgpu_doorbell_init - Init doorbell driver information.
408 * @adev: amdgpu_device pointer
410 * Init doorbell driver information (CIK)
411 * Returns 0 on success, error on failure.
413 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
415 /* doorbell bar mapping */
416 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
417 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
419 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
420 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
421 if (adev->doorbell.num_doorbells == 0)
424 adev->doorbell.ptr = ioremap(adev->doorbell.base,
425 adev->doorbell.num_doorbells *
427 if (adev->doorbell.ptr == NULL)
434 * amdgpu_doorbell_fini - Tear down doorbell driver information.
436 * @adev: amdgpu_device pointer
438 * Tear down doorbell driver information (CIK)
440 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
442 iounmap(adev->doorbell.ptr);
443 adev->doorbell.ptr = NULL;
447 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
450 * @adev: amdgpu_device pointer
451 * @aperture_base: output returning doorbell aperture base physical address
452 * @aperture_size: output returning doorbell aperture size in bytes
453 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
455 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
456 * takes doorbells required for its own rings and reports the setup to amdkfd.
457 * amdgpu reserved doorbells are at the start of the doorbell aperture.
459 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
460 phys_addr_t *aperture_base,
461 size_t *aperture_size,
462 size_t *start_offset)
465 * The first num_doorbells are used by amdgpu.
466 * amdkfd takes whatever's left in the aperture.
468 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
469 *aperture_base = adev->doorbell.base;
470 *aperture_size = adev->doorbell.size;
471 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
481 * Writeback is the the method by which the the GPU updates special pages
482 * in memory with the status of certain GPU events (fences, ring pointers,
487 * amdgpu_wb_fini - Disable Writeback and free memory
489 * @adev: amdgpu_device pointer
491 * Disables Writeback and frees the Writeback memory (all asics).
492 * Used at driver shutdown.
494 static void amdgpu_wb_fini(struct amdgpu_device *adev)
496 if (adev->wb.wb_obj) {
497 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
499 (void **)&adev->wb.wb);
500 adev->wb.wb_obj = NULL;
505 * amdgpu_wb_init- Init Writeback driver info and allocate memory
507 * @adev: amdgpu_device pointer
509 * Disables Writeback and frees the Writeback memory (all asics).
510 * Used at driver startup.
511 * Returns 0 on success or an -error on failure.
513 static int amdgpu_wb_init(struct amdgpu_device *adev)
517 if (adev->wb.wb_obj == NULL) {
518 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t),
519 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
520 &adev->wb.wb_obj, &adev->wb.gpu_addr,
521 (void **)&adev->wb.wb);
523 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
527 adev->wb.num_wb = AMDGPU_MAX_WB;
528 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
530 /* clear wb memory */
531 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t));
538 * amdgpu_wb_get - Allocate a wb entry
540 * @adev: amdgpu_device pointer
543 * Allocate a wb slot for use by the driver (all asics).
544 * Returns 0 on success or -EINVAL on failure.
546 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
548 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
549 if (offset < adev->wb.num_wb) {
550 __set_bit(offset, adev->wb.used);
559 * amdgpu_wb_get_64bit - Allocate a wb entry
561 * @adev: amdgpu_device pointer
564 * Allocate a wb slot for use by the driver (all asics).
565 * Returns 0 on success or -EINVAL on failure.
567 int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb)
569 unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used,
570 adev->wb.num_wb, 0, 2, 7, 0);
571 if ((offset + 1) < adev->wb.num_wb) {
572 __set_bit(offset, adev->wb.used);
573 __set_bit(offset + 1, adev->wb.used);
582 * amdgpu_wb_free - Free a wb entry
584 * @adev: amdgpu_device pointer
587 * Free a wb slot allocated for use by the driver (all asics)
589 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
591 if (wb < adev->wb.num_wb)
592 __clear_bit(wb, adev->wb.used);
596 * amdgpu_wb_free_64bit - Free a wb entry
598 * @adev: amdgpu_device pointer
601 * Free a wb slot allocated for use by the driver (all asics)
603 void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb)
605 if ((wb + 1) < adev->wb.num_wb) {
606 __clear_bit(wb, adev->wb.used);
607 __clear_bit(wb + 1, adev->wb.used);
612 * amdgpu_vram_location - try to find VRAM location
613 * @adev: amdgpu device structure holding all necessary informations
614 * @mc: memory controller structure holding memory informations
615 * @base: base address at which to put VRAM
617 * Function will place try to place VRAM at base address provided
618 * as parameter (which is so far either PCI aperture address or
619 * for IGP TOM base address).
621 * If there is not enough space to fit the unvisible VRAM in the 32bits
622 * address space then we limit the VRAM size to the aperture.
624 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
625 * this shouldn't be a problem as we are using the PCI aperture as a reference.
626 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
629 * Note: we use mc_vram_size as on some board we need to program the mc to
630 * cover the whole aperture even if VRAM size is inferior to aperture size
631 * Novell bug 204882 + along with lots of ubuntu ones
633 * Note: when limiting vram it's safe to overwritte real_vram_size because
634 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
635 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
638 * Note: IGP TOM addr should be the same as the aperture addr, we don't
639 * explicitly check for that thought.
641 * FIXME: when reducing VRAM size align new size on power of 2.
643 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
645 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
647 mc->vram_start = base;
648 if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
649 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
650 mc->real_vram_size = mc->aper_size;
651 mc->mc_vram_size = mc->aper_size;
653 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
654 if (limit && limit < mc->real_vram_size)
655 mc->real_vram_size = limit;
656 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
657 mc->mc_vram_size >> 20, mc->vram_start,
658 mc->vram_end, mc->real_vram_size >> 20);
662 * amdgpu_gtt_location - try to find GTT location
663 * @adev: amdgpu device structure holding all necessary informations
664 * @mc: memory controller structure holding memory informations
666 * Function will place try to place GTT before or after VRAM.
668 * If GTT size is bigger than space left then we ajust GTT size.
669 * Thus function will never fails.
671 * FIXME: when reducing GTT size align new size on power of 2.
673 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
675 u64 size_af, size_bf;
677 size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
678 size_bf = mc->vram_start & ~mc->gtt_base_align;
679 if (size_bf > size_af) {
680 if (mc->gtt_size > size_bf) {
681 dev_warn(adev->dev, "limiting GTT\n");
682 mc->gtt_size = size_bf;
686 if (mc->gtt_size > size_af) {
687 dev_warn(adev->dev, "limiting GTT\n");
688 mc->gtt_size = size_af;
690 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
692 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
693 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
694 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
698 * GPU helpers function.
701 * amdgpu_need_post - check if the hw need post or not
703 * @adev: amdgpu_device pointer
705 * Check if the asic has been initialized (all asics) at driver startup
706 * or post is needed if hw reset is performed.
707 * Returns true if need or false if not.
709 bool amdgpu_need_post(struct amdgpu_device *adev)
713 if (adev->has_hw_reset) {
714 adev->has_hw_reset = false;
717 /* then check MEM_SIZE, in case the crtcs are off */
718 reg = amdgpu_asic_get_config_memsize(adev);
720 if ((reg != 0) && (reg != 0xffffffff))
727 static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
729 if (amdgpu_sriov_vf(adev))
732 if (amdgpu_passthrough(adev)) {
733 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
734 * some old smc fw still need driver do vPost otherwise gpu hang, while
735 * those smc fw version above 22.15 doesn't have this flaw, so we force
736 * vpost executed for smc version below 22.15
738 if (adev->asic_type == CHIP_FIJI) {
741 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
742 /* force vPost if error occured */
746 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
747 if (fw_ver < 0x00160e00)
751 return amdgpu_need_post(adev);
755 * amdgpu_dummy_page_init - init dummy page used by the driver
757 * @adev: amdgpu_device pointer
759 * Allocate the dummy page used by the driver (all asics).
760 * This dummy page is used by the driver as a filler for gart entries
761 * when pages are taken out of the GART
762 * Returns 0 on sucess, -ENOMEM on failure.
764 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
766 if (adev->dummy_page.page)
768 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
769 if (adev->dummy_page.page == NULL)
771 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
772 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
773 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
774 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
775 __free_page(adev->dummy_page.page);
776 adev->dummy_page.page = NULL;
783 * amdgpu_dummy_page_fini - free dummy page used by the driver
785 * @adev: amdgpu_device pointer
787 * Frees the dummy page used by the driver (all asics).
789 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
791 if (adev->dummy_page.page == NULL)
793 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
794 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
795 __free_page(adev->dummy_page.page);
796 adev->dummy_page.page = NULL;
800 /* ATOM accessor methods */
802 * ATOM is an interpreted byte code stored in tables in the vbios. The
803 * driver registers callbacks to access registers and the interpreter
804 * in the driver parses the tables and executes then to program specific
805 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
806 * atombios.h, and atom.c
810 * cail_pll_read - read PLL register
812 * @info: atom card_info pointer
813 * @reg: PLL register offset
815 * Provides a PLL register accessor for the atom interpreter (r4xx+).
816 * Returns the value of the PLL register.
818 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
824 * cail_pll_write - write PLL register
826 * @info: atom card_info pointer
827 * @reg: PLL register offset
828 * @val: value to write to the pll register
830 * Provides a PLL register accessor for the atom interpreter (r4xx+).
832 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
838 * cail_mc_read - read MC (Memory Controller) register
840 * @info: atom card_info pointer
841 * @reg: MC register offset
843 * Provides an MC register accessor for the atom interpreter (r4xx+).
844 * Returns the value of the MC register.
846 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
852 * cail_mc_write - write MC (Memory Controller) register
854 * @info: atom card_info pointer
855 * @reg: MC register offset
856 * @val: value to write to the pll register
858 * Provides a MC register accessor for the atom interpreter (r4xx+).
860 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
866 * cail_reg_write - write MMIO register
868 * @info: atom card_info pointer
869 * @reg: MMIO register offset
870 * @val: value to write to the pll register
872 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
874 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
876 struct amdgpu_device *adev = info->dev->dev_private;
882 * cail_reg_read - read MMIO register
884 * @info: atom card_info pointer
885 * @reg: MMIO register offset
887 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
888 * Returns the value of the MMIO register.
890 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
892 struct amdgpu_device *adev = info->dev->dev_private;
900 * cail_ioreg_write - write IO register
902 * @info: atom card_info pointer
903 * @reg: IO register offset
904 * @val: value to write to the pll register
906 * Provides a IO register accessor for the atom interpreter (r4xx+).
908 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
910 struct amdgpu_device *adev = info->dev->dev_private;
916 * cail_ioreg_read - read IO register
918 * @info: atom card_info pointer
919 * @reg: IO register offset
921 * Provides an IO register accessor for the atom interpreter (r4xx+).
922 * Returns the value of the IO register.
924 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
926 struct amdgpu_device *adev = info->dev->dev_private;
934 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
936 * @adev: amdgpu_device pointer
938 * Frees the driver info and register access callbacks for the ATOM
939 * interpreter (r4xx+).
940 * Called at driver shutdown.
942 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
944 if (adev->mode_info.atom_context) {
945 kfree(adev->mode_info.atom_context->scratch);
946 kfree(adev->mode_info.atom_context->iio);
948 kfree(adev->mode_info.atom_context);
949 adev->mode_info.atom_context = NULL;
950 kfree(adev->mode_info.atom_card_info);
951 adev->mode_info.atom_card_info = NULL;
955 * amdgpu_atombios_init - init the driver info and callbacks for atombios
957 * @adev: amdgpu_device pointer
959 * Initializes the driver info and register access callbacks for the
960 * ATOM interpreter (r4xx+).
961 * Returns 0 on sucess, -ENOMEM on failure.
962 * Called at driver startup.
964 static int amdgpu_atombios_init(struct amdgpu_device *adev)
966 struct card_info *atom_card_info =
967 kzalloc(sizeof(struct card_info), GFP_KERNEL);
972 adev->mode_info.atom_card_info = atom_card_info;
973 atom_card_info->dev = adev->ddev;
974 atom_card_info->reg_read = cail_reg_read;
975 atom_card_info->reg_write = cail_reg_write;
976 /* needed for iio ops */
978 atom_card_info->ioreg_read = cail_ioreg_read;
979 atom_card_info->ioreg_write = cail_ioreg_write;
981 DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
982 atom_card_info->ioreg_read = cail_reg_read;
983 atom_card_info->ioreg_write = cail_reg_write;
985 atom_card_info->mc_read = cail_mc_read;
986 atom_card_info->mc_write = cail_mc_write;
987 atom_card_info->pll_read = cail_pll_read;
988 atom_card_info->pll_write = cail_pll_write;
990 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
991 if (!adev->mode_info.atom_context) {
992 amdgpu_atombios_fini(adev);
996 mutex_init(&adev->mode_info.atom_context->mutex);
997 if (adev->is_atom_fw) {
998 amdgpu_atomfirmware_scratch_regs_init(adev);
999 amdgpu_atomfirmware_allocate_fb_scratch(adev);
1001 amdgpu_atombios_scratch_regs_init(adev);
1002 amdgpu_atombios_allocate_fb_scratch(adev);
1007 /* if we get transitioned to only one device, take VGA back */
1009 * amdgpu_vga_set_decode - enable/disable vga decode
1011 * @cookie: amdgpu_device pointer
1012 * @state: enable/disable vga decode
1014 * Enable/disable vga decode (all asics).
1015 * Returns VGA resource flags.
1017 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
1019 struct amdgpu_device *adev = cookie;
1020 amdgpu_asic_set_vga_state(adev, state);
1022 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1023 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1025 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1029 * amdgpu_check_pot_argument - check that argument is a power of two
1031 * @arg: value to check
1033 * Validates that a certain argument is a power of two (all asics).
1034 * Returns true if argument is valid.
1036 static bool amdgpu_check_pot_argument(int arg)
1038 return (arg & (arg - 1)) == 0;
1041 static void amdgpu_check_block_size(struct amdgpu_device *adev)
1043 /* defines number of bits in page table versus page directory,
1044 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1045 * page table and the remaining bits are in the page directory */
1046 if (amdgpu_vm_block_size == -1)
1049 if (amdgpu_vm_block_size < 9) {
1050 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1051 amdgpu_vm_block_size);
1055 if (amdgpu_vm_block_size > 24 ||
1056 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1057 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1058 amdgpu_vm_block_size);
1065 amdgpu_vm_block_size = -1;
1068 static void amdgpu_check_vm_size(struct amdgpu_device *adev)
1070 if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
1071 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
1076 if (amdgpu_vm_size < 1) {
1077 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1083 * Max GPUVM size for Cayman, SI, CI VI are 40 bits.
1085 if (amdgpu_vm_size > 1024) {
1086 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
1094 amdgpu_vm_size = -1;
1098 * amdgpu_check_arguments - validate module params
1100 * @adev: amdgpu_device pointer
1102 * Validates certain module parameters and updates
1103 * the associated values used by the driver (all asics).
1105 static void amdgpu_check_arguments(struct amdgpu_device *adev)
1107 if (amdgpu_sched_jobs < 4) {
1108 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1110 amdgpu_sched_jobs = 4;
1111 } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
1112 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1114 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1117 if (amdgpu_gart_size != -1) {
1118 /* gtt size must be greater or equal to 32M */
1119 if (amdgpu_gart_size < 32) {
1120 dev_warn(adev->dev, "gart size (%d) too small\n",
1122 amdgpu_gart_size = -1;
1126 amdgpu_check_vm_size(adev);
1128 amdgpu_check_block_size(adev);
1130 if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
1131 !amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
1132 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
1133 amdgpu_vram_page_split);
1134 amdgpu_vram_page_split = 1024;
1139 * amdgpu_switcheroo_set_state - set switcheroo state
1141 * @pdev: pci dev pointer
1142 * @state: vga_switcheroo state
1144 * Callback for the switcheroo driver. Suspends or resumes the
1145 * the asics before or after it is powered up using ACPI methods.
1147 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1149 struct drm_device *dev = pci_get_drvdata(pdev);
1151 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1154 if (state == VGA_SWITCHEROO_ON) {
1155 unsigned d3_delay = dev->pdev->d3_delay;
1157 pr_info("amdgpu: switched on\n");
1158 /* don't suspend or resume card normally */
1159 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1161 amdgpu_device_resume(dev, true, true);
1163 dev->pdev->d3_delay = d3_delay;
1165 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1166 drm_kms_helper_poll_enable(dev);
1168 pr_info("amdgpu: switched off\n");
1169 drm_kms_helper_poll_disable(dev);
1170 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1171 amdgpu_device_suspend(dev, true, true);
1172 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1177 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1179 * @pdev: pci dev pointer
1181 * Callback for the switcheroo driver. Check of the switcheroo
1182 * state can be changed.
1183 * Returns true if the state can be changed, false if not.
1185 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1187 struct drm_device *dev = pci_get_drvdata(pdev);
1190 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1191 * locking inversion with the driver load path. And the access here is
1192 * completely racy anyway. So don't bother with locking for now.
1194 return dev->open_count == 0;
1197 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1198 .set_gpu_state = amdgpu_switcheroo_set_state,
1200 .can_switch = amdgpu_switcheroo_can_switch,
1203 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1204 enum amd_ip_block_type block_type,
1205 enum amd_clockgating_state state)
1209 for (i = 0; i < adev->num_ip_blocks; i++) {
1210 if (!adev->ip_blocks[i].status.valid)
1212 if (adev->ip_blocks[i].version->type != block_type)
1214 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1216 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1217 (void *)adev, state);
1219 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1220 adev->ip_blocks[i].version->funcs->name, r);
1225 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1226 enum amd_ip_block_type block_type,
1227 enum amd_powergating_state state)
1231 for (i = 0; i < adev->num_ip_blocks; i++) {
1232 if (!adev->ip_blocks[i].status.valid)
1234 if (adev->ip_blocks[i].version->type != block_type)
1236 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1238 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1239 (void *)adev, state);
1241 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1242 adev->ip_blocks[i].version->funcs->name, r);
1247 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
1251 for (i = 0; i < adev->num_ip_blocks; i++) {
1252 if (!adev->ip_blocks[i].status.valid)
1254 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1255 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1259 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1260 enum amd_ip_block_type block_type)
1264 for (i = 0; i < adev->num_ip_blocks; i++) {
1265 if (!adev->ip_blocks[i].status.valid)
1267 if (adev->ip_blocks[i].version->type == block_type) {
1268 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1278 bool amdgpu_is_idle(struct amdgpu_device *adev,
1279 enum amd_ip_block_type block_type)
1283 for (i = 0; i < adev->num_ip_blocks; i++) {
1284 if (!adev->ip_blocks[i].status.valid)
1286 if (adev->ip_blocks[i].version->type == block_type)
1287 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1293 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
1294 enum amd_ip_block_type type)
1298 for (i = 0; i < adev->num_ip_blocks; i++)
1299 if (adev->ip_blocks[i].version->type == type)
1300 return &adev->ip_blocks[i];
1306 * amdgpu_ip_block_version_cmp
1308 * @adev: amdgpu_device pointer
1309 * @type: enum amd_ip_block_type
1310 * @major: major version
1311 * @minor: minor version
1313 * return 0 if equal or greater
1314 * return 1 if smaller or the ip_block doesn't exist
1316 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1317 enum amd_ip_block_type type,
1318 u32 major, u32 minor)
1320 struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);
1322 if (ip_block && ((ip_block->version->major > major) ||
1323 ((ip_block->version->major == major) &&
1324 (ip_block->version->minor >= minor))))
1331 * amdgpu_ip_block_add
1333 * @adev: amdgpu_device pointer
1334 * @ip_block_version: pointer to the IP to add
1336 * Adds the IP block driver information to the collection of IPs
1339 int amdgpu_ip_block_add(struct amdgpu_device *adev,
1340 const struct amdgpu_ip_block_version *ip_block_version)
1342 if (!ip_block_version)
1345 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1350 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1352 adev->enable_virtual_display = false;
1354 if (amdgpu_virtual_display) {
1355 struct drm_device *ddev = adev->ddev;
1356 const char *pci_address_name = pci_name(ddev->pdev);
1357 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1359 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1360 pciaddstr_tmp = pciaddstr;
1361 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1362 pciaddname = strsep(&pciaddname_tmp, ",");
1363 if (!strcmp("all", pciaddname)
1364 || !strcmp(pci_address_name, pciaddname)) {
1368 adev->enable_virtual_display = true;
1371 res = kstrtol(pciaddname_tmp, 10,
1379 adev->mode_info.num_crtc = num_crtc;
1381 adev->mode_info.num_crtc = 1;
1387 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1388 amdgpu_virtual_display, pci_address_name,
1389 adev->enable_virtual_display, adev->mode_info.num_crtc);
1395 static int amdgpu_early_init(struct amdgpu_device *adev)
1399 amdgpu_device_enable_virtual_display(adev);
1401 switch (adev->asic_type) {
1405 case CHIP_POLARIS11:
1406 case CHIP_POLARIS10:
1407 case CHIP_POLARIS12:
1410 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1411 adev->family = AMDGPU_FAMILY_CZ;
1413 adev->family = AMDGPU_FAMILY_VI;
1415 r = vi_set_ip_blocks(adev);
1419 #ifdef CONFIG_DRM_AMDGPU_SI
1425 adev->family = AMDGPU_FAMILY_SI;
1426 r = si_set_ip_blocks(adev);
1431 #ifdef CONFIG_DRM_AMDGPU_CIK
1437 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1438 adev->family = AMDGPU_FAMILY_CI;
1440 adev->family = AMDGPU_FAMILY_KV;
1442 r = cik_set_ip_blocks(adev);
1448 adev->family = AMDGPU_FAMILY_AI;
1450 r = soc15_set_ip_blocks(adev);
1455 /* FIXME: not supported yet */
1459 if (amdgpu_sriov_vf(adev)) {
1460 r = amdgpu_virt_request_full_gpu(adev, true);
1465 for (i = 0; i < adev->num_ip_blocks; i++) {
1466 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1467 DRM_ERROR("disabled ip block: %d\n", i);
1468 adev->ip_blocks[i].status.valid = false;
1470 if (adev->ip_blocks[i].version->funcs->early_init) {
1471 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1473 adev->ip_blocks[i].status.valid = false;
1475 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1476 adev->ip_blocks[i].version->funcs->name, r);
1479 adev->ip_blocks[i].status.valid = true;
1482 adev->ip_blocks[i].status.valid = true;
1487 adev->cg_flags &= amdgpu_cg_mask;
1488 adev->pg_flags &= amdgpu_pg_mask;
1493 static int amdgpu_init(struct amdgpu_device *adev)
1497 for (i = 0; i < adev->num_ip_blocks; i++) {
1498 if (!adev->ip_blocks[i].status.valid)
1500 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1502 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1503 adev->ip_blocks[i].version->funcs->name, r);
1506 adev->ip_blocks[i].status.sw = true;
1507 /* need to do gmc hw init early so we can allocate gpu mem */
1508 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1509 r = amdgpu_vram_scratch_init(adev);
1511 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1514 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1516 DRM_ERROR("hw_init %d failed %d\n", i, r);
1519 r = amdgpu_wb_init(adev);
1521 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1524 adev->ip_blocks[i].status.hw = true;
1526 /* right after GMC hw init, we create CSA */
1527 if (amdgpu_sriov_vf(adev)) {
1528 r = amdgpu_allocate_static_csa(adev);
1530 DRM_ERROR("allocate CSA failed %d\n", r);
1537 for (i = 0; i < adev->num_ip_blocks; i++) {
1538 if (!adev->ip_blocks[i].status.sw)
1540 /* gmc hw init is done early */
1541 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC)
1543 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1545 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1546 adev->ip_blocks[i].version->funcs->name, r);
1549 adev->ip_blocks[i].status.hw = true;
1555 static int amdgpu_late_init(struct amdgpu_device *adev)
1559 for (i = 0; i < adev->num_ip_blocks; i++) {
1560 if (!adev->ip_blocks[i].status.valid)
1562 if (adev->ip_blocks[i].version->funcs->late_init) {
1563 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1565 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1566 adev->ip_blocks[i].version->funcs->name, r);
1569 adev->ip_blocks[i].status.late_initialized = true;
1571 /* skip CG for VCE/UVD, it's handled specially */
1572 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1573 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1574 /* enable clockgating to save power */
1575 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1578 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1579 adev->ip_blocks[i].version->funcs->name, r);
1588 static int amdgpu_fini(struct amdgpu_device *adev)
1592 /* need to disable SMC first */
1593 for (i = 0; i < adev->num_ip_blocks; i++) {
1594 if (!adev->ip_blocks[i].status.hw)
1596 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1597 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1598 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1599 AMD_CG_STATE_UNGATE);
1601 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1602 adev->ip_blocks[i].version->funcs->name, r);
1605 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1606 /* XXX handle errors */
1608 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1609 adev->ip_blocks[i].version->funcs->name, r);
1611 adev->ip_blocks[i].status.hw = false;
1616 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1617 if (!adev->ip_blocks[i].status.hw)
1619 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1620 amdgpu_wb_fini(adev);
1621 amdgpu_vram_scratch_fini(adev);
1624 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1625 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1626 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1627 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1628 AMD_CG_STATE_UNGATE);
1630 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1631 adev->ip_blocks[i].version->funcs->name, r);
1636 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1637 /* XXX handle errors */
1639 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1640 adev->ip_blocks[i].version->funcs->name, r);
1643 adev->ip_blocks[i].status.hw = false;
1646 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1647 if (!adev->ip_blocks[i].status.sw)
1649 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1650 /* XXX handle errors */
1652 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1653 adev->ip_blocks[i].version->funcs->name, r);
1655 adev->ip_blocks[i].status.sw = false;
1656 adev->ip_blocks[i].status.valid = false;
1659 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1660 if (!adev->ip_blocks[i].status.late_initialized)
1662 if (adev->ip_blocks[i].version->funcs->late_fini)
1663 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1664 adev->ip_blocks[i].status.late_initialized = false;
1667 if (amdgpu_sriov_vf(adev)) {
1668 amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL);
1669 amdgpu_virt_release_full_gpu(adev, false);
1675 int amdgpu_suspend(struct amdgpu_device *adev)
1679 if (amdgpu_sriov_vf(adev))
1680 amdgpu_virt_request_full_gpu(adev, false);
1682 /* ungate SMC block first */
1683 r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1684 AMD_CG_STATE_UNGATE);
1686 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1689 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1690 if (!adev->ip_blocks[i].status.valid)
1692 /* ungate blocks so that suspend can properly shut them down */
1693 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1694 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1695 AMD_CG_STATE_UNGATE);
1697 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1698 adev->ip_blocks[i].version->funcs->name, r);
1701 /* XXX handle errors */
1702 r = adev->ip_blocks[i].version->funcs->suspend(adev);
1703 /* XXX handle errors */
1705 DRM_ERROR("suspend of IP block <%s> failed %d\n",
1706 adev->ip_blocks[i].version->funcs->name, r);
1710 if (amdgpu_sriov_vf(adev))
1711 amdgpu_virt_release_full_gpu(adev, false);
1716 static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
1720 for (i = 0; i < adev->num_ip_blocks; i++) {
1721 if (!adev->ip_blocks[i].status.valid)
1724 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1725 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1726 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)
1727 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1730 DRM_ERROR("resume of IP block <%s> failed %d\n",
1731 adev->ip_blocks[i].version->funcs->name, r);
1739 static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev)
1743 for (i = 0; i < adev->num_ip_blocks; i++) {
1744 if (!adev->ip_blocks[i].status.valid)
1747 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1748 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1749 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
1752 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1754 DRM_ERROR("resume of IP block <%s> failed %d\n",
1755 adev->ip_blocks[i].version->funcs->name, r);
1763 static int amdgpu_resume(struct amdgpu_device *adev)
1767 for (i = 0; i < adev->num_ip_blocks; i++) {
1768 if (!adev->ip_blocks[i].status.valid)
1770 r = adev->ip_blocks[i].version->funcs->resume(adev);
1772 DRM_ERROR("resume of IP block <%s> failed %d\n",
1773 adev->ip_blocks[i].version->funcs->name, r);
1781 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
1783 if (adev->is_atom_fw) {
1784 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
1785 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1787 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
1788 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1793 * amdgpu_device_init - initialize the driver
1795 * @adev: amdgpu_device pointer
1796 * @pdev: drm dev pointer
1797 * @pdev: pci dev pointer
1798 * @flags: driver flags
1800 * Initializes the driver info and hw (all asics).
1801 * Returns 0 for success or an error on failure.
1802 * Called at driver startup.
1804 int amdgpu_device_init(struct amdgpu_device *adev,
1805 struct drm_device *ddev,
1806 struct pci_dev *pdev,
1810 bool runtime = false;
1813 adev->shutdown = false;
1814 adev->dev = &pdev->dev;
1817 adev->flags = flags;
1818 adev->asic_type = flags & AMD_ASIC_MASK;
1819 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1820 adev->mc.gtt_size = 512 * 1024 * 1024;
1821 adev->accel_working = false;
1822 adev->num_rings = 0;
1823 adev->mman.buffer_funcs = NULL;
1824 adev->mman.buffer_funcs_ring = NULL;
1825 adev->vm_manager.vm_pte_funcs = NULL;
1826 adev->vm_manager.vm_pte_num_rings = 0;
1827 adev->gart.gart_funcs = NULL;
1828 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
1830 adev->smc_rreg = &amdgpu_invalid_rreg;
1831 adev->smc_wreg = &amdgpu_invalid_wreg;
1832 adev->pcie_rreg = &amdgpu_invalid_rreg;
1833 adev->pcie_wreg = &amdgpu_invalid_wreg;
1834 adev->pciep_rreg = &amdgpu_invalid_rreg;
1835 adev->pciep_wreg = &amdgpu_invalid_wreg;
1836 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1837 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1838 adev->didt_rreg = &amdgpu_invalid_rreg;
1839 adev->didt_wreg = &amdgpu_invalid_wreg;
1840 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
1841 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
1842 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1843 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1846 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1847 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1848 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1850 /* mutex initialization are all done here so we
1851 * can recall function without having locking issues */
1852 atomic_set(&adev->irq.ih.lock, 0);
1853 mutex_init(&adev->firmware.mutex);
1854 mutex_init(&adev->pm.mutex);
1855 mutex_init(&adev->gfx.gpu_clock_mutex);
1856 mutex_init(&adev->srbm_mutex);
1857 mutex_init(&adev->grbm_idx_mutex);
1858 mutex_init(&adev->mn_lock);
1859 hash_init(adev->mn_hash);
1861 amdgpu_check_arguments(adev);
1863 /* Registers mapping */
1864 /* TODO: block userspace mapping of io register */
1865 spin_lock_init(&adev->mmio_idx_lock);
1866 spin_lock_init(&adev->smc_idx_lock);
1867 spin_lock_init(&adev->pcie_idx_lock);
1868 spin_lock_init(&adev->uvd_ctx_idx_lock);
1869 spin_lock_init(&adev->didt_idx_lock);
1870 spin_lock_init(&adev->gc_cac_idx_lock);
1871 spin_lock_init(&adev->audio_endpt_idx_lock);
1872 spin_lock_init(&adev->mm_stats.lock);
1874 INIT_LIST_HEAD(&adev->shadow_list);
1875 mutex_init(&adev->shadow_list_lock);
1877 INIT_LIST_HEAD(&adev->gtt_list);
1878 spin_lock_init(&adev->gtt_list_lock);
1880 if (adev->asic_type >= CHIP_BONAIRE) {
1881 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1882 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1884 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
1885 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
1888 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1889 if (adev->rmmio == NULL) {
1892 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1893 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1895 if (adev->asic_type >= CHIP_BONAIRE)
1896 /* doorbell bar mapping */
1897 amdgpu_doorbell_init(adev);
1899 /* io port mapping */
1900 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1901 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1902 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1903 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1907 if (adev->rio_mem == NULL)
1908 DRM_INFO("PCI I/O BAR is not found.\n");
1910 /* early init functions */
1911 r = amdgpu_early_init(adev);
1915 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1916 /* this will fail for cards that aren't VGA class devices, just
1918 vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1920 if (amdgpu_runtime_pm == 1)
1922 if (amdgpu_device_is_px(ddev))
1924 if (!pci_is_thunderbolt_attached(adev->pdev))
1925 vga_switcheroo_register_client(adev->pdev,
1926 &amdgpu_switcheroo_ops, runtime);
1928 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1931 if (!amdgpu_get_bios(adev)) {
1936 r = amdgpu_atombios_init(adev);
1938 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1942 /* detect if we are with an SRIOV vbios */
1943 amdgpu_device_detect_sriov_bios(adev);
1945 /* Post card if necessary */
1946 if (amdgpu_vpost_needed(adev)) {
1948 dev_err(adev->dev, "no vBIOS found\n");
1952 DRM_INFO("GPU posting now...\n");
1953 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
1955 dev_err(adev->dev, "gpu post error!\n");
1959 DRM_INFO("GPU post is not needed\n");
1962 if (!adev->is_atom_fw) {
1963 /* Initialize clocks */
1964 r = amdgpu_atombios_get_clock_info(adev);
1966 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1969 /* init i2c buses */
1970 amdgpu_atombios_i2c_init(adev);
1974 r = amdgpu_fence_driver_init(adev);
1976 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1980 /* init the mode config */
1981 drm_mode_config_init(adev->ddev);
1983 r = amdgpu_init(adev);
1985 dev_err(adev->dev, "amdgpu_init failed\n");
1990 adev->accel_working = true;
1992 /* Initialize the buffer migration limit. */
1993 if (amdgpu_moverate >= 0)
1994 max_MBps = amdgpu_moverate;
1996 max_MBps = 8; /* Allow 8 MB/s. */
1997 /* Get a log2 for easy divisions. */
1998 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2000 r = amdgpu_ib_pool_init(adev);
2002 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2006 r = amdgpu_ib_ring_tests(adev);
2008 DRM_ERROR("ib ring test failed (%d).\n", r);
2010 amdgpu_fbdev_init(adev);
2012 r = amdgpu_gem_debugfs_init(adev);
2014 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2016 r = amdgpu_debugfs_regs_init(adev);
2018 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2020 r = amdgpu_debugfs_firmware_init(adev);
2022 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2024 if ((amdgpu_testing & 1)) {
2025 if (adev->accel_working)
2026 amdgpu_test_moves(adev);
2028 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2030 if (amdgpu_benchmarking) {
2031 if (adev->accel_working)
2032 amdgpu_benchmark(adev, amdgpu_benchmarking);
2034 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2037 /* enable clockgating, etc. after ib tests, etc. since some blocks require
2038 * explicit gating rather than handling it automatically.
2040 r = amdgpu_late_init(adev);
2042 dev_err(adev->dev, "amdgpu_late_init failed\n");
2050 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2055 * amdgpu_device_fini - tear down the driver
2057 * @adev: amdgpu_device pointer
2059 * Tear down the driver info (all asics).
2060 * Called at driver shutdown.
2062 void amdgpu_device_fini(struct amdgpu_device *adev)
2066 DRM_INFO("amdgpu: finishing device.\n");
2067 adev->shutdown = true;
2068 if (adev->mode_info.mode_config_initialized)
2069 drm_crtc_force_disable_all(adev->ddev);
2070 /* evict vram memory */
2071 amdgpu_bo_evict_vram(adev);
2072 amdgpu_ib_pool_fini(adev);
2073 amdgpu_fence_driver_fini(adev);
2074 amdgpu_fbdev_fini(adev);
2075 r = amdgpu_fini(adev);
2076 adev->accel_working = false;
2077 /* free i2c buses */
2078 amdgpu_i2c_fini(adev);
2079 amdgpu_atombios_fini(adev);
2082 if (!pci_is_thunderbolt_attached(adev->pdev))
2083 vga_switcheroo_unregister_client(adev->pdev);
2084 if (adev->flags & AMD_IS_PX)
2085 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2086 vga_client_register(adev->pdev, NULL, NULL, NULL);
2088 pci_iounmap(adev->pdev, adev->rio_mem);
2089 adev->rio_mem = NULL;
2090 iounmap(adev->rmmio);
2092 if (adev->asic_type >= CHIP_BONAIRE)
2093 amdgpu_doorbell_fini(adev);
2094 amdgpu_debugfs_regs_cleanup(adev);
2102 * amdgpu_device_suspend - initiate device suspend
2104 * @pdev: drm dev pointer
2105 * @state: suspend state
2107 * Puts the hw in the suspend state (all asics).
2108 * Returns 0 for success or an error on failure.
2109 * Called at driver suspend.
2111 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2113 struct amdgpu_device *adev;
2114 struct drm_crtc *crtc;
2115 struct drm_connector *connector;
2118 if (dev == NULL || dev->dev_private == NULL) {
2122 adev = dev->dev_private;
2124 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2127 drm_kms_helper_poll_disable(dev);
2129 /* turn off display hw */
2130 drm_modeset_lock_all(dev);
2131 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2132 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2134 drm_modeset_unlock_all(dev);
2136 /* unpin the front buffers and cursors */
2137 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2138 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2139 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
2140 struct amdgpu_bo *robj;
2142 if (amdgpu_crtc->cursor_bo) {
2143 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2144 r = amdgpu_bo_reserve(aobj, true);
2146 amdgpu_bo_unpin(aobj);
2147 amdgpu_bo_unreserve(aobj);
2151 if (rfb == NULL || rfb->obj == NULL) {
2154 robj = gem_to_amdgpu_bo(rfb->obj);
2155 /* don't unpin kernel fb objects */
2156 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2157 r = amdgpu_bo_reserve(robj, true);
2159 amdgpu_bo_unpin(robj);
2160 amdgpu_bo_unreserve(robj);
2164 /* evict vram memory */
2165 amdgpu_bo_evict_vram(adev);
2167 amdgpu_fence_driver_suspend(adev);
2169 r = amdgpu_suspend(adev);
2171 /* evict remaining vram memory
2172 * This second call to evict vram is to evict the gart page table
2175 amdgpu_bo_evict_vram(adev);
2177 if (adev->is_atom_fw)
2178 amdgpu_atomfirmware_scratch_regs_save(adev);
2180 amdgpu_atombios_scratch_regs_save(adev);
2181 pci_save_state(dev->pdev);
2183 /* Shut down the device */
2184 pci_disable_device(dev->pdev);
2185 pci_set_power_state(dev->pdev, PCI_D3hot);
2187 r = amdgpu_asic_reset(adev);
2189 DRM_ERROR("amdgpu asic reset failed\n");
2194 amdgpu_fbdev_set_suspend(adev, 1);
2201 * amdgpu_device_resume - initiate device resume
2203 * @pdev: drm dev pointer
2205 * Bring the hw back to operating state (all asics).
2206 * Returns 0 for success or an error on failure.
2207 * Called at driver resume.
2209 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2211 struct drm_connector *connector;
2212 struct amdgpu_device *adev = dev->dev_private;
2213 struct drm_crtc *crtc;
2216 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2223 pci_set_power_state(dev->pdev, PCI_D0);
2224 pci_restore_state(dev->pdev);
2225 r = pci_enable_device(dev->pdev);
2229 if (adev->is_atom_fw)
2230 amdgpu_atomfirmware_scratch_regs_restore(adev);
2232 amdgpu_atombios_scratch_regs_restore(adev);
2235 if (amdgpu_need_post(adev)) {
2236 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2238 DRM_ERROR("amdgpu asic init failed\n");
2241 r = amdgpu_resume(adev);
2243 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2246 amdgpu_fence_driver_resume(adev);
2249 r = amdgpu_ib_ring_tests(adev);
2251 DRM_ERROR("ib ring test failed (%d).\n", r);
2254 r = amdgpu_late_init(adev);
2259 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2260 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2262 if (amdgpu_crtc->cursor_bo) {
2263 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2264 r = amdgpu_bo_reserve(aobj, true);
2266 r = amdgpu_bo_pin(aobj,
2267 AMDGPU_GEM_DOMAIN_VRAM,
2268 &amdgpu_crtc->cursor_addr);
2270 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2271 amdgpu_bo_unreserve(aobj);
2276 /* blat the mode back in */
2278 drm_helper_resume_force_mode(dev);
2279 /* turn on display hw */
2280 drm_modeset_lock_all(dev);
2281 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2282 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2284 drm_modeset_unlock_all(dev);
2287 drm_kms_helper_poll_enable(dev);
2290 * Most of the connector probing functions try to acquire runtime pm
2291 * refs to ensure that the GPU is powered on when connector polling is
2292 * performed. Since we're calling this from a runtime PM callback,
2293 * trying to acquire rpm refs will cause us to deadlock.
2295 * Since we're guaranteed to be holding the rpm lock, it's safe to
2296 * temporarily disable the rpm helpers so this doesn't deadlock us.
2299 dev->dev->power.disable_depth++;
2301 drm_helper_hpd_irq_event(dev);
2303 dev->dev->power.disable_depth--;
2307 amdgpu_fbdev_set_suspend(adev, 0);
2316 static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2319 bool asic_hang = false;
2321 for (i = 0; i < adev->num_ip_blocks; i++) {
2322 if (!adev->ip_blocks[i].status.valid)
2324 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2325 adev->ip_blocks[i].status.hang =
2326 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2327 if (adev->ip_blocks[i].status.hang) {
2328 DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2335 static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2339 for (i = 0; i < adev->num_ip_blocks; i++) {
2340 if (!adev->ip_blocks[i].status.valid)
2342 if (adev->ip_blocks[i].status.hang &&
2343 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2344 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2353 static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2357 for (i = 0; i < adev->num_ip_blocks; i++) {
2358 if (!adev->ip_blocks[i].status.valid)
2360 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2361 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2362 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2363 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) {
2364 if (adev->ip_blocks[i].status.hang) {
2365 DRM_INFO("Some block need full reset!\n");
2373 static int amdgpu_soft_reset(struct amdgpu_device *adev)
2377 for (i = 0; i < adev->num_ip_blocks; i++) {
2378 if (!adev->ip_blocks[i].status.valid)
2380 if (adev->ip_blocks[i].status.hang &&
2381 adev->ip_blocks[i].version->funcs->soft_reset) {
2382 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2391 static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2395 for (i = 0; i < adev->num_ip_blocks; i++) {
2396 if (!adev->ip_blocks[i].status.valid)
2398 if (adev->ip_blocks[i].status.hang &&
2399 adev->ip_blocks[i].version->funcs->post_soft_reset)
2400 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2408 bool amdgpu_need_backup(struct amdgpu_device *adev)
2410 if (adev->flags & AMD_IS_APU)
2413 return amdgpu_lockup_timeout > 0 ? true : false;
2416 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
2417 struct amdgpu_ring *ring,
2418 struct amdgpu_bo *bo,
2419 struct dma_fence **fence)
2427 r = amdgpu_bo_reserve(bo, true);
2430 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2431 /* if bo has been evicted, then no need to recover */
2432 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2433 r = amdgpu_bo_validate(bo->shadow);
2435 DRM_ERROR("bo validate failed!\n");
2439 r = amdgpu_ttm_bind(&bo->shadow->tbo, &bo->shadow->tbo.mem);
2441 DRM_ERROR("%p bind failed\n", bo->shadow);
2445 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2448 DRM_ERROR("recover page table failed!\n");
2453 amdgpu_bo_unreserve(bo);
2458 * amdgpu_sriov_gpu_reset - reset the asic
2460 * @adev: amdgpu device pointer
2461 * @voluntary: if this reset is requested by guest.
2462 * (true means by guest and false means by HYPERVISOR )
2464 * Attempt the reset the GPU if it has hung (all asics).
2466 * Returns 0 for success or an error on failure.
2468 int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, bool voluntary)
2472 struct amdgpu_bo *bo, *tmp;
2473 struct amdgpu_ring *ring;
2474 struct dma_fence *fence = NULL, *next = NULL;
2476 mutex_lock(&adev->virt.lock_reset);
2477 atomic_inc(&adev->gpu_reset_counter);
2478 adev->gfx.in_reset = true;
2481 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2483 /* block scheduler */
2484 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2485 ring = adev->rings[i];
2487 if (!ring || !ring->sched.thread)
2490 kthread_park(ring->sched.thread);
2491 amd_sched_hw_job_reset(&ring->sched);
2494 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2495 amdgpu_fence_driver_force_completion(adev);
2497 /* request to take full control of GPU before re-initialization */
2499 amdgpu_virt_reset_gpu(adev);
2501 amdgpu_virt_request_full_gpu(adev, true);
2504 /* Resume IP prior to SMC */
2505 amdgpu_sriov_reinit_early(adev);
2507 /* we need recover gart prior to run SMC/CP/SDMA resume */
2508 amdgpu_ttm_recover_gart(adev);
2510 /* now we are okay to resume SMC/CP/SDMA */
2511 amdgpu_sriov_reinit_late(adev);
2513 amdgpu_irq_gpu_reset_resume_helper(adev);
2515 if (amdgpu_ib_ring_tests(adev))
2516 dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r);
2518 /* release full control of GPU after ib test */
2519 amdgpu_virt_release_full_gpu(adev, true);
2521 DRM_INFO("recover vram bo from shadow\n");
2523 ring = adev->mman.buffer_funcs_ring;
2524 mutex_lock(&adev->shadow_list_lock);
2525 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2527 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2529 r = dma_fence_wait(fence, false);
2531 WARN(r, "recovery from shadow isn't completed\n");
2536 dma_fence_put(fence);
2539 mutex_unlock(&adev->shadow_list_lock);
2542 r = dma_fence_wait(fence, false);
2544 WARN(r, "recovery from shadow isn't completed\n");
2546 dma_fence_put(fence);
2548 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2549 struct amdgpu_ring *ring = adev->rings[i];
2550 if (!ring || !ring->sched.thread)
2553 amd_sched_job_recovery(&ring->sched);
2554 kthread_unpark(ring->sched.thread);
2557 drm_helper_resume_force_mode(adev->ddev);
2558 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2560 /* bad news, how to tell it to userspace ? */
2561 dev_info(adev->dev, "GPU reset failed\n");
2564 adev->gfx.in_reset = false;
2565 mutex_unlock(&adev->virt.lock_reset);
2570 * amdgpu_gpu_reset - reset the asic
2572 * @adev: amdgpu device pointer
2574 * Attempt the reset the GPU if it has hung (all asics).
2575 * Returns 0 for success or an error on failure.
2577 int amdgpu_gpu_reset(struct amdgpu_device *adev)
2581 bool need_full_reset;
2583 if (amdgpu_sriov_vf(adev))
2584 return amdgpu_sriov_gpu_reset(adev, true);
2586 if (!amdgpu_check_soft_reset(adev)) {
2587 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2591 atomic_inc(&adev->gpu_reset_counter);
2594 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2596 /* block scheduler */
2597 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2598 struct amdgpu_ring *ring = adev->rings[i];
2600 if (!ring || !ring->sched.thread)
2602 kthread_park(ring->sched.thread);
2603 amd_sched_hw_job_reset(&ring->sched);
2605 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2606 amdgpu_fence_driver_force_completion(adev);
2608 need_full_reset = amdgpu_need_full_reset(adev);
2610 if (!need_full_reset) {
2611 amdgpu_pre_soft_reset(adev);
2612 r = amdgpu_soft_reset(adev);
2613 amdgpu_post_soft_reset(adev);
2614 if (r || amdgpu_check_soft_reset(adev)) {
2615 DRM_INFO("soft reset failed, will fallback to full reset!\n");
2616 need_full_reset = true;
2620 if (need_full_reset) {
2621 r = amdgpu_suspend(adev);
2624 /* Disable fb access */
2625 if (adev->mode_info.num_crtc) {
2626 struct amdgpu_mode_mc_save save;
2627 amdgpu_display_stop_mc_access(adev, &save);
2628 amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);
2630 if (adev->is_atom_fw)
2631 amdgpu_atomfirmware_scratch_regs_save(adev);
2633 amdgpu_atombios_scratch_regs_save(adev);
2634 r = amdgpu_asic_reset(adev);
2635 if (adev->is_atom_fw)
2636 amdgpu_atomfirmware_scratch_regs_restore(adev);
2638 amdgpu_atombios_scratch_regs_restore(adev);
2640 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2643 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2644 r = amdgpu_resume(adev);
2648 amdgpu_irq_gpu_reset_resume_helper(adev);
2649 if (need_full_reset && amdgpu_need_backup(adev)) {
2650 r = amdgpu_ttm_recover_gart(adev);
2652 DRM_ERROR("gart recovery failed!!!\n");
2654 r = amdgpu_ib_ring_tests(adev);
2656 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2657 r = amdgpu_suspend(adev);
2658 need_full_reset = true;
2662 * recovery vm page tables, since we cannot depend on VRAM is
2663 * consistent after gpu full reset.
2665 if (need_full_reset && amdgpu_need_backup(adev)) {
2666 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2667 struct amdgpu_bo *bo, *tmp;
2668 struct dma_fence *fence = NULL, *next = NULL;
2670 DRM_INFO("recover vram bo from shadow\n");
2671 mutex_lock(&adev->shadow_list_lock);
2672 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2674 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2676 r = dma_fence_wait(fence, false);
2678 WARN(r, "recovery from shadow isn't completed\n");
2683 dma_fence_put(fence);
2686 mutex_unlock(&adev->shadow_list_lock);
2688 r = dma_fence_wait(fence, false);
2690 WARN(r, "recovery from shadow isn't completed\n");
2692 dma_fence_put(fence);
2694 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2695 struct amdgpu_ring *ring = adev->rings[i];
2697 if (!ring || !ring->sched.thread)
2700 amd_sched_job_recovery(&ring->sched);
2701 kthread_unpark(ring->sched.thread);
2704 dev_err(adev->dev, "asic resume failed (%d).\n", r);
2705 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2706 if (adev->rings[i] && adev->rings[i]->sched.thread) {
2707 kthread_unpark(adev->rings[i]->sched.thread);
2712 drm_helper_resume_force_mode(adev->ddev);
2714 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2716 /* bad news, how to tell it to userspace ? */
2717 dev_info(adev->dev, "GPU reset failed\n");
2723 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
2728 if (amdgpu_pcie_gen_cap)
2729 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2731 if (amdgpu_pcie_lane_cap)
2732 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2734 /* covers APUs as well */
2735 if (pci_is_root_bus(adev->pdev->bus)) {
2736 if (adev->pm.pcie_gen_mask == 0)
2737 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2738 if (adev->pm.pcie_mlw_mask == 0)
2739 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2743 if (adev->pm.pcie_gen_mask == 0) {
2744 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2746 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2747 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2748 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2750 if (mask & DRM_PCIE_SPEED_25)
2751 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2752 if (mask & DRM_PCIE_SPEED_50)
2753 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2754 if (mask & DRM_PCIE_SPEED_80)
2755 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2757 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2760 if (adev->pm.pcie_mlw_mask == 0) {
2761 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
2765 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
2766 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2767 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2768 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2769 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2770 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2771 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2774 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2775 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2776 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2777 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2778 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2779 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2782 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2783 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2784 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2785 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2786 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2789 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2790 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2791 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2792 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2795 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2796 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2797 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2800 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2801 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2804 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2810 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2818 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2819 const struct drm_info_list *files,
2824 for (i = 0; i < adev->debugfs_count; i++) {
2825 if (adev->debugfs[i].files == files) {
2826 /* Already registered */
2831 i = adev->debugfs_count + 1;
2832 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2833 DRM_ERROR("Reached maximum number of debugfs components.\n");
2834 DRM_ERROR("Report so we increase "
2835 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2838 adev->debugfs[adev->debugfs_count].files = files;
2839 adev->debugfs[adev->debugfs_count].num_files = nfiles;
2840 adev->debugfs_count = i;
2841 #if defined(CONFIG_DEBUG_FS)
2842 drm_debugfs_create_files(files, nfiles,
2843 adev->ddev->primary->debugfs_root,
2844 adev->ddev->primary);
2849 #if defined(CONFIG_DEBUG_FS)
2851 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2852 size_t size, loff_t *pos)
2854 struct amdgpu_device *adev = file_inode(f)->i_private;
2857 bool pm_pg_lock, use_bank;
2858 unsigned instance_bank, sh_bank, se_bank;
2860 if (size & 0x3 || *pos & 0x3)
2863 /* are we reading registers for which a PG lock is necessary? */
2864 pm_pg_lock = (*pos >> 23) & 1;
2866 if (*pos & (1ULL << 62)) {
2867 se_bank = (*pos >> 24) & 0x3FF;
2868 sh_bank = (*pos >> 34) & 0x3FF;
2869 instance_bank = (*pos >> 44) & 0x3FF;
2871 if (se_bank == 0x3FF)
2872 se_bank = 0xFFFFFFFF;
2873 if (sh_bank == 0x3FF)
2874 sh_bank = 0xFFFFFFFF;
2875 if (instance_bank == 0x3FF)
2876 instance_bank = 0xFFFFFFFF;
2882 *pos &= (1UL << 22) - 1;
2885 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
2886 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
2888 mutex_lock(&adev->grbm_idx_mutex);
2889 amdgpu_gfx_select_se_sh(adev, se_bank,
2890 sh_bank, instance_bank);
2894 mutex_lock(&adev->pm.mutex);
2899 if (*pos > adev->rmmio_size)
2902 value = RREG32(*pos >> 2);
2903 r = put_user(value, (uint32_t *)buf);
2917 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2918 mutex_unlock(&adev->grbm_idx_mutex);
2922 mutex_unlock(&adev->pm.mutex);
2927 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2928 size_t size, loff_t *pos)
2930 struct amdgpu_device *adev = file_inode(f)->i_private;
2933 bool pm_pg_lock, use_bank;
2934 unsigned instance_bank, sh_bank, se_bank;
2936 if (size & 0x3 || *pos & 0x3)
2939 /* are we reading registers for which a PG lock is necessary? */
2940 pm_pg_lock = (*pos >> 23) & 1;
2942 if (*pos & (1ULL << 62)) {
2943 se_bank = (*pos >> 24) & 0x3FF;
2944 sh_bank = (*pos >> 34) & 0x3FF;
2945 instance_bank = (*pos >> 44) & 0x3FF;
2947 if (se_bank == 0x3FF)
2948 se_bank = 0xFFFFFFFF;
2949 if (sh_bank == 0x3FF)
2950 sh_bank = 0xFFFFFFFF;
2951 if (instance_bank == 0x3FF)
2952 instance_bank = 0xFFFFFFFF;
2958 *pos &= (1UL << 22) - 1;
2961 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
2962 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
2964 mutex_lock(&adev->grbm_idx_mutex);
2965 amdgpu_gfx_select_se_sh(adev, se_bank,
2966 sh_bank, instance_bank);
2970 mutex_lock(&adev->pm.mutex);
2975 if (*pos > adev->rmmio_size)
2978 r = get_user(value, (uint32_t *)buf);
2982 WREG32(*pos >> 2, value);
2991 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2992 mutex_unlock(&adev->grbm_idx_mutex);
2996 mutex_unlock(&adev->pm.mutex);
3001 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
3002 size_t size, loff_t *pos)
3004 struct amdgpu_device *adev = file_inode(f)->i_private;
3008 if (size & 0x3 || *pos & 0x3)
3014 value = RREG32_PCIE(*pos >> 2);
3015 r = put_user(value, (uint32_t *)buf);
3028 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
3029 size_t size, loff_t *pos)
3031 struct amdgpu_device *adev = file_inode(f)->i_private;
3035 if (size & 0x3 || *pos & 0x3)
3041 r = get_user(value, (uint32_t *)buf);
3045 WREG32_PCIE(*pos >> 2, value);
3056 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
3057 size_t size, loff_t *pos)
3059 struct amdgpu_device *adev = file_inode(f)->i_private;
3063 if (size & 0x3 || *pos & 0x3)
3069 value = RREG32_DIDT(*pos >> 2);
3070 r = put_user(value, (uint32_t *)buf);
3083 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
3084 size_t size, loff_t *pos)
3086 struct amdgpu_device *adev = file_inode(f)->i_private;
3090 if (size & 0x3 || *pos & 0x3)
3096 r = get_user(value, (uint32_t *)buf);
3100 WREG32_DIDT(*pos >> 2, value);
3111 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
3112 size_t size, loff_t *pos)
3114 struct amdgpu_device *adev = file_inode(f)->i_private;
3118 if (size & 0x3 || *pos & 0x3)
3124 value = RREG32_SMC(*pos);
3125 r = put_user(value, (uint32_t *)buf);
3138 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
3139 size_t size, loff_t *pos)
3141 struct amdgpu_device *adev = file_inode(f)->i_private;
3145 if (size & 0x3 || *pos & 0x3)
3151 r = get_user(value, (uint32_t *)buf);
3155 WREG32_SMC(*pos, value);
3166 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
3167 size_t size, loff_t *pos)
3169 struct amdgpu_device *adev = file_inode(f)->i_private;
3172 uint32_t *config, no_regs = 0;
3174 if (size & 0x3 || *pos & 0x3)
3177 config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
3181 /* version, increment each time something is added */
3182 config[no_regs++] = 3;
3183 config[no_regs++] = adev->gfx.config.max_shader_engines;
3184 config[no_regs++] = adev->gfx.config.max_tile_pipes;
3185 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
3186 config[no_regs++] = adev->gfx.config.max_sh_per_se;
3187 config[no_regs++] = adev->gfx.config.max_backends_per_se;
3188 config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
3189 config[no_regs++] = adev->gfx.config.max_gprs;
3190 config[no_regs++] = adev->gfx.config.max_gs_threads;
3191 config[no_regs++] = adev->gfx.config.max_hw_contexts;
3192 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
3193 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
3194 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
3195 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
3196 config[no_regs++] = adev->gfx.config.num_tile_pipes;
3197 config[no_regs++] = adev->gfx.config.backend_enable_mask;
3198 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
3199 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
3200 config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
3201 config[no_regs++] = adev->gfx.config.num_gpus;
3202 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
3203 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
3204 config[no_regs++] = adev->gfx.config.gb_addr_config;
3205 config[no_regs++] = adev->gfx.config.num_rbs;
3208 config[no_regs++] = adev->rev_id;
3209 config[no_regs++] = adev->pg_flags;
3210 config[no_regs++] = adev->cg_flags;
3213 config[no_regs++] = adev->family;
3214 config[no_regs++] = adev->external_rev_id;
3217 config[no_regs++] = adev->pdev->device;
3218 config[no_regs++] = adev->pdev->revision;
3219 config[no_regs++] = adev->pdev->subsystem_device;
3220 config[no_regs++] = adev->pdev->subsystem_vendor;
3222 while (size && (*pos < no_regs * 4)) {
3225 value = config[*pos >> 2];
3226 r = put_user(value, (uint32_t *)buf);
3242 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
3243 size_t size, loff_t *pos)
3245 struct amdgpu_device *adev = file_inode(f)->i_private;
3246 int idx, x, outsize, r, valuesize;
3247 uint32_t values[16];
3249 if (size & 3 || *pos & 0x3)
3252 if (amdgpu_dpm == 0)
3255 /* convert offset to sensor number */
3258 valuesize = sizeof(values);
3259 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
3260 r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize);
3261 else if (adev->pm.funcs && adev->pm.funcs->read_sensor)
3262 r = adev->pm.funcs->read_sensor(adev, idx, &values[0],
3267 if (size > valuesize)
3274 r = put_user(values[x++], (int32_t *)buf);
3281 return !r ? outsize : r;
3284 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
3285 size_t size, loff_t *pos)
3287 struct amdgpu_device *adev = f->f_inode->i_private;
3290 uint32_t offset, se, sh, cu, wave, simd, data[32];
3292 if (size & 3 || *pos & 3)
3296 offset = (*pos & 0x7F);
3297 se = ((*pos >> 7) & 0xFF);
3298 sh = ((*pos >> 15) & 0xFF);
3299 cu = ((*pos >> 23) & 0xFF);
3300 wave = ((*pos >> 31) & 0xFF);
3301 simd = ((*pos >> 37) & 0xFF);
3303 /* switch to the specific se/sh/cu */
3304 mutex_lock(&adev->grbm_idx_mutex);
3305 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3308 if (adev->gfx.funcs->read_wave_data)
3309 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
3311 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3312 mutex_unlock(&adev->grbm_idx_mutex);
3317 while (size && (offset < x * 4)) {
3320 value = data[offset >> 2];
3321 r = put_user(value, (uint32_t *)buf);
3334 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
3335 size_t size, loff_t *pos)
3337 struct amdgpu_device *adev = f->f_inode->i_private;
3340 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
3342 if (size & 3 || *pos & 3)
3346 offset = (*pos & 0xFFF); /* in dwords */
3347 se = ((*pos >> 12) & 0xFF);
3348 sh = ((*pos >> 20) & 0xFF);
3349 cu = ((*pos >> 28) & 0xFF);
3350 wave = ((*pos >> 36) & 0xFF);
3351 simd = ((*pos >> 44) & 0xFF);
3352 thread = ((*pos >> 52) & 0xFF);
3353 bank = ((*pos >> 60) & 1);
3355 data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
3359 /* switch to the specific se/sh/cu */
3360 mutex_lock(&adev->grbm_idx_mutex);
3361 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3364 if (adev->gfx.funcs->read_wave_vgprs)
3365 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
3367 if (adev->gfx.funcs->read_wave_sgprs)
3368 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
3371 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3372 mutex_unlock(&adev->grbm_idx_mutex);
3377 value = data[offset++];
3378 r = put_user(value, (uint32_t *)buf);
3394 static const struct file_operations amdgpu_debugfs_regs_fops = {
3395 .owner = THIS_MODULE,
3396 .read = amdgpu_debugfs_regs_read,
3397 .write = amdgpu_debugfs_regs_write,
3398 .llseek = default_llseek
3400 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
3401 .owner = THIS_MODULE,
3402 .read = amdgpu_debugfs_regs_didt_read,
3403 .write = amdgpu_debugfs_regs_didt_write,
3404 .llseek = default_llseek
3406 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
3407 .owner = THIS_MODULE,
3408 .read = amdgpu_debugfs_regs_pcie_read,
3409 .write = amdgpu_debugfs_regs_pcie_write,
3410 .llseek = default_llseek
3412 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
3413 .owner = THIS_MODULE,
3414 .read = amdgpu_debugfs_regs_smc_read,
3415 .write = amdgpu_debugfs_regs_smc_write,
3416 .llseek = default_llseek
3419 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
3420 .owner = THIS_MODULE,
3421 .read = amdgpu_debugfs_gca_config_read,
3422 .llseek = default_llseek
3425 static const struct file_operations amdgpu_debugfs_sensors_fops = {
3426 .owner = THIS_MODULE,
3427 .read = amdgpu_debugfs_sensor_read,
3428 .llseek = default_llseek
3431 static const struct file_operations amdgpu_debugfs_wave_fops = {
3432 .owner = THIS_MODULE,
3433 .read = amdgpu_debugfs_wave_read,
3434 .llseek = default_llseek
3436 static const struct file_operations amdgpu_debugfs_gpr_fops = {
3437 .owner = THIS_MODULE,
3438 .read = amdgpu_debugfs_gpr_read,
3439 .llseek = default_llseek
3442 static const struct file_operations *debugfs_regs[] = {
3443 &amdgpu_debugfs_regs_fops,
3444 &amdgpu_debugfs_regs_didt_fops,
3445 &amdgpu_debugfs_regs_pcie_fops,
3446 &amdgpu_debugfs_regs_smc_fops,
3447 &amdgpu_debugfs_gca_config_fops,
3448 &amdgpu_debugfs_sensors_fops,
3449 &amdgpu_debugfs_wave_fops,
3450 &amdgpu_debugfs_gpr_fops,
3453 static const char *debugfs_regs_names[] = {
3458 "amdgpu_gca_config",
3464 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3466 struct drm_minor *minor = adev->ddev->primary;
3467 struct dentry *ent, *root = minor->debugfs_root;
3470 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3471 ent = debugfs_create_file(debugfs_regs_names[i],
3472 S_IFREG | S_IRUGO, root,
3473 adev, debugfs_regs[i]);
3475 for (j = 0; j < i; j++) {
3476 debugfs_remove(adev->debugfs_regs[i]);
3477 adev->debugfs_regs[i] = NULL;
3479 return PTR_ERR(ent);
3483 i_size_write(ent->d_inode, adev->rmmio_size);
3484 adev->debugfs_regs[i] = ent;
3490 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
3494 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3495 if (adev->debugfs_regs[i]) {
3496 debugfs_remove(adev->debugfs_regs[i]);
3497 adev->debugfs_regs[i] = NULL;
3502 int amdgpu_debugfs_init(struct drm_minor *minor)
3507 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3511 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }