2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/ktime.h>
29 #include <linux/pagemap.h>
31 #include <drm/amdgpu_drm.h>
34 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
36 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
39 if (robj->gem_base.import_attach)
40 drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
41 amdgpu_mn_unregister(robj);
42 amdgpu_bo_unref(&robj);
46 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
47 int alignment, u32 initial_domain,
48 u64 flags, bool kernel,
49 struct drm_gem_object **obj)
51 struct amdgpu_bo *robj;
52 unsigned long max_size;
56 /* At least align on page size */
57 if (alignment < PAGE_SIZE) {
58 alignment = PAGE_SIZE;
61 if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
62 /* Maximum bo size is the unpinned gtt size since we use the gtt to
63 * handle vram to system pool migrations.
65 max_size = adev->mc.gtt_size - adev->gart_pin_size;
66 if (size > max_size) {
67 DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
68 size >> 20, max_size >> 20);
73 r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
74 flags, NULL, NULL, &robj);
76 if (r != -ERESTARTSYS) {
77 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
78 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
81 DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
82 size, initial_domain, alignment, r);
86 *obj = &robj->gem_base;
91 void amdgpu_gem_force_release(struct amdgpu_device *adev)
93 struct drm_device *ddev = adev->ddev;
94 struct drm_file *file;
96 mutex_lock(&ddev->filelist_mutex);
98 list_for_each_entry(file, &ddev->filelist, lhead) {
99 struct drm_gem_object *gobj;
102 WARN_ONCE(1, "Still active user space clients!\n");
103 spin_lock(&file->table_lock);
104 idr_for_each_entry(&file->object_idr, gobj, handle) {
105 WARN_ONCE(1, "And also active allocations!\n");
106 drm_gem_object_unreference_unlocked(gobj);
108 idr_destroy(&file->object_idr);
109 spin_unlock(&file->table_lock);
112 mutex_unlock(&ddev->filelist_mutex);
116 * Call from drm_gem_handle_create which appear in both new and open ioctl
119 int amdgpu_gem_object_open(struct drm_gem_object *obj,
120 struct drm_file *file_priv)
122 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
123 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
124 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
125 struct amdgpu_vm *vm = &fpriv->vm;
126 struct amdgpu_bo_va *bo_va;
128 r = amdgpu_bo_reserve(abo, false);
132 bo_va = amdgpu_vm_bo_find(vm, abo);
134 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
138 amdgpu_bo_unreserve(abo);
142 void amdgpu_gem_object_close(struct drm_gem_object *obj,
143 struct drm_file *file_priv)
145 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
146 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
147 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
148 struct amdgpu_vm *vm = &fpriv->vm;
150 struct amdgpu_bo_list_entry vm_pd;
151 struct list_head list, duplicates;
152 struct ttm_validate_buffer tv;
153 struct ww_acquire_ctx ticket;
154 struct amdgpu_bo_va *bo_va;
157 INIT_LIST_HEAD(&list);
158 INIT_LIST_HEAD(&duplicates);
162 list_add(&tv.head, &list);
164 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
166 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
168 dev_err(adev->dev, "leaking bo va because "
169 "we fail to reserve bo (%d)\n", r);
172 bo_va = amdgpu_vm_bo_find(vm, bo);
174 if (--bo_va->ref_count == 0) {
175 amdgpu_vm_bo_rmv(adev, bo_va);
178 ttm_eu_backoff_reservation(&ticket, &list);
181 static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
184 r = amdgpu_gpu_reset(adev);
194 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
195 struct drm_file *filp)
197 struct amdgpu_device *adev = dev->dev_private;
198 union drm_amdgpu_gem_create *args = data;
199 uint64_t size = args->in.bo_size;
200 struct drm_gem_object *gobj;
205 /* reject invalid gem flags */
206 if (args->in.domain_flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
207 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
208 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
209 AMDGPU_GEM_CREATE_VRAM_CLEARED|
210 AMDGPU_GEM_CREATE_SHADOW |
211 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
215 /* reject invalid gem domains */
216 if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU |
217 AMDGPU_GEM_DOMAIN_GTT |
218 AMDGPU_GEM_DOMAIN_VRAM |
219 AMDGPU_GEM_DOMAIN_GDS |
220 AMDGPU_GEM_DOMAIN_GWS |
221 AMDGPU_GEM_DOMAIN_OA)) {
226 /* create a gem object to contain this object in */
227 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
228 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
230 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
231 size = size << AMDGPU_GDS_SHIFT;
232 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
233 size = size << AMDGPU_GWS_SHIFT;
234 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
235 size = size << AMDGPU_OA_SHIFT;
241 size = roundup(size, PAGE_SIZE);
243 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
244 (u32)(0xffffffff & args->in.domains),
245 args->in.domain_flags,
250 r = drm_gem_handle_create(filp, gobj, &handle);
251 /* drop reference from allocate - handle holds it now */
252 drm_gem_object_unreference_unlocked(gobj);
256 memset(args, 0, sizeof(*args));
257 args->out.handle = handle;
261 r = amdgpu_gem_handle_lockup(adev, r);
265 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
266 struct drm_file *filp)
268 struct amdgpu_device *adev = dev->dev_private;
269 struct drm_amdgpu_gem_userptr *args = data;
270 struct drm_gem_object *gobj;
271 struct amdgpu_bo *bo;
275 if (offset_in_page(args->addr | args->size))
278 /* reject unknown flag values */
279 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
280 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
281 AMDGPU_GEM_USERPTR_REGISTER))
284 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
285 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
287 /* if we want to write to it we must install a MMU notifier */
291 /* create a gem object to contain this object in */
292 r = amdgpu_gem_object_create(adev, args->size, 0,
293 AMDGPU_GEM_DOMAIN_CPU, 0,
298 bo = gem_to_amdgpu_bo(gobj);
299 bo->prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
300 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
301 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
305 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
306 r = amdgpu_mn_register(bo, args->addr);
311 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
312 down_read(¤t->mm->mmap_sem);
314 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
317 goto unlock_mmap_sem;
319 r = amdgpu_bo_reserve(bo, true);
323 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
324 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
325 amdgpu_bo_unreserve(bo);
329 up_read(¤t->mm->mmap_sem);
332 r = drm_gem_handle_create(filp, gobj, &handle);
333 /* drop reference from allocate - handle holds it now */
334 drm_gem_object_unreference_unlocked(gobj);
338 args->handle = handle;
342 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false);
345 up_read(¤t->mm->mmap_sem);
348 drm_gem_object_unreference_unlocked(gobj);
351 r = amdgpu_gem_handle_lockup(adev, r);
356 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
357 struct drm_device *dev,
358 uint32_t handle, uint64_t *offset_p)
360 struct drm_gem_object *gobj;
361 struct amdgpu_bo *robj;
363 gobj = drm_gem_object_lookup(filp, handle);
367 robj = gem_to_amdgpu_bo(gobj);
368 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
369 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
370 drm_gem_object_unreference_unlocked(gobj);
373 *offset_p = amdgpu_bo_mmap_offset(robj);
374 drm_gem_object_unreference_unlocked(gobj);
378 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
379 struct drm_file *filp)
381 union drm_amdgpu_gem_mmap *args = data;
382 uint32_t handle = args->in.handle;
383 memset(args, 0, sizeof(*args));
384 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
388 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
390 * @timeout_ns: timeout in ns
392 * Calculate the timeout in jiffies from an absolute timeout in ns.
394 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
396 unsigned long timeout_jiffies;
399 /* clamp timeout if it's to large */
400 if (((int64_t)timeout_ns) < 0)
401 return MAX_SCHEDULE_TIMEOUT;
403 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
404 if (ktime_to_ns(timeout) < 0)
407 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
408 /* clamp timeout to avoid unsigned-> signed overflow */
409 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
410 return MAX_SCHEDULE_TIMEOUT - 1;
412 return timeout_jiffies;
415 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
416 struct drm_file *filp)
418 struct amdgpu_device *adev = dev->dev_private;
419 union drm_amdgpu_gem_wait_idle *args = data;
420 struct drm_gem_object *gobj;
421 struct amdgpu_bo *robj;
422 uint32_t handle = args->in.handle;
423 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
427 gobj = drm_gem_object_lookup(filp, handle);
431 robj = gem_to_amdgpu_bo(gobj);
432 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
435 /* ret == 0 means not signaled,
436 * ret > 0 means signaled
437 * ret < 0 means interrupted before timeout
440 memset(args, 0, sizeof(*args));
441 args->out.status = (ret == 0);
445 drm_gem_object_unreference_unlocked(gobj);
446 r = amdgpu_gem_handle_lockup(adev, r);
450 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
451 struct drm_file *filp)
453 struct drm_amdgpu_gem_metadata *args = data;
454 struct drm_gem_object *gobj;
455 struct amdgpu_bo *robj;
458 DRM_DEBUG("%d \n", args->handle);
459 gobj = drm_gem_object_lookup(filp, args->handle);
462 robj = gem_to_amdgpu_bo(gobj);
464 r = amdgpu_bo_reserve(robj, false);
465 if (unlikely(r != 0))
468 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
469 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
470 r = amdgpu_bo_get_metadata(robj, args->data.data,
471 sizeof(args->data.data),
472 &args->data.data_size_bytes,
474 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
475 if (args->data.data_size_bytes > sizeof(args->data.data)) {
479 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
481 r = amdgpu_bo_set_metadata(robj, args->data.data,
482 args->data.data_size_bytes,
487 amdgpu_bo_unreserve(robj);
489 drm_gem_object_unreference_unlocked(gobj);
493 static int amdgpu_gem_va_check(void *param, struct amdgpu_bo *bo)
495 /* if anything is swapped out don't swap it in here,
496 just abort and wait for the next CS */
497 if (!amdgpu_bo_gpu_accessible(bo))
500 if (bo->shadow && !amdgpu_bo_gpu_accessible(bo->shadow))
507 * amdgpu_gem_va_update_vm -update the bo_va in its VM
509 * @adev: amdgpu_device pointer
510 * @bo_va: bo_va to update
511 * @list: validation list
512 * @operation: map or unmap
514 * Update the bo_va directly after setting its address. Errors are not
515 * vital here, so they are not reported back to userspace.
517 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
518 struct amdgpu_bo_va *bo_va,
519 struct list_head *list,
522 struct ttm_validate_buffer *entry;
523 int r = -ERESTARTSYS;
525 list_for_each_entry(entry, list, head) {
526 struct amdgpu_bo *bo =
527 container_of(entry->bo, struct amdgpu_bo, tbo);
528 if (amdgpu_gem_va_check(NULL, bo))
532 r = amdgpu_vm_validate_pt_bos(adev, bo_va->vm, amdgpu_gem_va_check,
537 r = amdgpu_vm_update_page_directory(adev, bo_va->vm);
541 r = amdgpu_vm_clear_freed(adev, bo_va->vm);
545 if (operation == AMDGPU_VA_OP_MAP)
546 r = amdgpu_vm_bo_update(adev, bo_va, false);
549 if (r && r != -ERESTARTSYS)
550 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
553 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
554 struct drm_file *filp)
556 struct drm_amdgpu_gem_va *args = data;
557 struct drm_gem_object *gobj;
558 struct amdgpu_device *adev = dev->dev_private;
559 struct amdgpu_fpriv *fpriv = filp->driver_priv;
560 struct amdgpu_bo *abo;
561 struct amdgpu_bo_va *bo_va;
562 struct amdgpu_bo_list_entry vm_pd;
563 struct ttm_validate_buffer tv;
564 struct ww_acquire_ctx ticket;
565 struct list_head list;
566 uint32_t invalid_flags, va_flags = 0;
569 if (!adev->vm_manager.enabled)
572 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
573 dev_err(&dev->pdev->dev,
574 "va_address 0x%lX is in reserved area 0x%X\n",
575 (unsigned long)args->va_address,
576 AMDGPU_VA_RESERVED_SIZE);
580 invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE |
581 AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE);
582 if ((args->flags & invalid_flags)) {
583 dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
584 args->flags, invalid_flags);
588 switch (args->operation) {
589 case AMDGPU_VA_OP_MAP:
590 case AMDGPU_VA_OP_UNMAP:
593 dev_err(&dev->pdev->dev, "unsupported operation %d\n",
598 gobj = drm_gem_object_lookup(filp, args->handle);
601 abo = gem_to_amdgpu_bo(gobj);
602 INIT_LIST_HEAD(&list);
605 list_add(&tv.head, &list);
607 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
609 r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
611 drm_gem_object_unreference_unlocked(gobj);
615 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
617 ttm_eu_backoff_reservation(&ticket, &list);
618 drm_gem_object_unreference_unlocked(gobj);
622 switch (args->operation) {
623 case AMDGPU_VA_OP_MAP:
624 if (args->flags & AMDGPU_VM_PAGE_READABLE)
625 va_flags |= AMDGPU_PTE_READABLE;
626 if (args->flags & AMDGPU_VM_PAGE_WRITEABLE)
627 va_flags |= AMDGPU_PTE_WRITEABLE;
628 if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
629 va_flags |= AMDGPU_PTE_EXECUTABLE;
630 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
631 args->offset_in_bo, args->map_size,
634 case AMDGPU_VA_OP_UNMAP:
635 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
640 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
642 amdgpu_gem_va_update_vm(adev, bo_va, &list, args->operation);
643 ttm_eu_backoff_reservation(&ticket, &list);
645 drm_gem_object_unreference_unlocked(gobj);
649 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
650 struct drm_file *filp)
652 struct drm_amdgpu_gem_op *args = data;
653 struct drm_gem_object *gobj;
654 struct amdgpu_bo *robj;
657 gobj = drm_gem_object_lookup(filp, args->handle);
661 robj = gem_to_amdgpu_bo(gobj);
663 r = amdgpu_bo_reserve(robj, false);
668 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
669 struct drm_amdgpu_gem_create_in info;
670 void __user *out = (void __user *)(long)args->value;
672 info.bo_size = robj->gem_base.size;
673 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
674 info.domains = robj->prefered_domains;
675 info.domain_flags = robj->flags;
676 amdgpu_bo_unreserve(robj);
677 if (copy_to_user(out, &info, sizeof(info)))
681 case AMDGPU_GEM_OP_SET_PLACEMENT:
682 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
684 amdgpu_bo_unreserve(robj);
687 robj->prefered_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
688 AMDGPU_GEM_DOMAIN_GTT |
689 AMDGPU_GEM_DOMAIN_CPU);
690 robj->allowed_domains = robj->prefered_domains;
691 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
692 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
694 amdgpu_bo_unreserve(robj);
697 amdgpu_bo_unreserve(robj);
702 drm_gem_object_unreference_unlocked(gobj);
706 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
707 struct drm_device *dev,
708 struct drm_mode_create_dumb *args)
710 struct amdgpu_device *adev = dev->dev_private;
711 struct drm_gem_object *gobj;
715 args->pitch = amdgpu_align_pitch(adev, args->width,
716 DIV_ROUND_UP(args->bpp, 8), 0);
717 args->size = (u64)args->pitch * args->height;
718 args->size = ALIGN(args->size, PAGE_SIZE);
720 r = amdgpu_gem_object_create(adev, args->size, 0,
721 AMDGPU_GEM_DOMAIN_VRAM,
722 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
728 r = drm_gem_handle_create(file_priv, gobj, &handle);
729 /* drop reference from allocate - handle holds it now */
730 drm_gem_object_unreference_unlocked(gobj);
734 args->handle = handle;
738 #if defined(CONFIG_DEBUG_FS)
739 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
741 struct drm_gem_object *gobj = ptr;
742 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
743 struct seq_file *m = data;
746 const char *placement;
749 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
751 case AMDGPU_GEM_DOMAIN_VRAM:
754 case AMDGPU_GEM_DOMAIN_GTT:
757 case AMDGPU_GEM_DOMAIN_CPU:
762 seq_printf(m, "\t0x%08x: %12ld byte %s @ 0x%010Lx",
763 id, amdgpu_bo_size(bo), placement,
764 amdgpu_bo_gpu_offset(bo));
766 pin_count = ACCESS_ONCE(bo->pin_count);
768 seq_printf(m, " pin count %d", pin_count);
774 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
776 struct drm_info_node *node = (struct drm_info_node *)m->private;
777 struct drm_device *dev = node->minor->dev;
778 struct drm_file *file;
781 r = mutex_lock_interruptible(&dev->filelist_mutex);
785 list_for_each_entry(file, &dev->filelist, lhead) {
786 struct task_struct *task;
789 * Although we have a valid reference on file->pid, that does
790 * not guarantee that the task_struct who called get_pid() is
791 * still alive (e.g. get_pid(current) => fork() => exit()).
792 * Therefore, we need to protect this ->comm access using RCU.
795 task = pid_task(file->pid, PIDTYPE_PID);
796 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
797 task ? task->comm : "<unknown>");
800 spin_lock(&file->table_lock);
801 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
802 spin_unlock(&file->table_lock);
805 mutex_unlock(&dev->filelist_mutex);
809 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
810 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
814 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
816 #if defined(CONFIG_DEBUG_FS)
817 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);