2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/ktime.h>
30 #include <drm/amdgpu_drm.h>
33 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
35 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
38 if (robj->gem_base.import_attach)
39 drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
40 amdgpu_mn_unregister(robj);
41 amdgpu_bo_unref(&robj);
45 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
46 int alignment, u32 initial_domain,
47 u64 flags, bool kernel,
48 struct drm_gem_object **obj)
50 struct amdgpu_bo *robj;
51 unsigned long max_size;
55 /* At least align on page size */
56 if (alignment < PAGE_SIZE) {
57 alignment = PAGE_SIZE;
60 if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
61 /* Maximum bo size is the unpinned gtt size since we use the gtt to
62 * handle vram to system pool migrations.
64 max_size = adev->mc.gtt_size - adev->gart_pin_size;
65 if (size > max_size) {
66 DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
67 size >> 20, max_size >> 20);
72 r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
73 flags, NULL, NULL, &robj);
75 if (r != -ERESTARTSYS) {
76 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
77 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
80 DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
81 size, initial_domain, alignment, r);
85 *obj = &robj->gem_base;
86 robj->pid = task_pid_nr(current);
88 mutex_lock(&adev->gem.mutex);
89 list_add_tail(&robj->list, &adev->gem.objects);
90 mutex_unlock(&adev->gem.mutex);
95 int amdgpu_gem_init(struct amdgpu_device *adev)
97 INIT_LIST_HEAD(&adev->gem.objects);
101 void amdgpu_gem_fini(struct amdgpu_device *adev)
103 amdgpu_bo_force_delete(adev);
107 * Call from drm_gem_handle_create which appear in both new and open ioctl
110 int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv)
112 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj);
113 struct amdgpu_device *adev = rbo->adev;
114 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
115 struct amdgpu_vm *vm = &fpriv->vm;
116 struct amdgpu_bo_va *bo_va;
118 r = amdgpu_bo_reserve(rbo, false);
122 bo_va = amdgpu_vm_bo_find(vm, rbo);
124 bo_va = amdgpu_vm_bo_add(adev, vm, rbo);
128 amdgpu_bo_unreserve(rbo);
132 void amdgpu_gem_object_close(struct drm_gem_object *obj,
133 struct drm_file *file_priv)
135 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj);
136 struct amdgpu_device *adev = rbo->adev;
137 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
138 struct amdgpu_vm *vm = &fpriv->vm;
139 struct amdgpu_bo_va *bo_va;
141 r = amdgpu_bo_reserve(rbo, true);
143 dev_err(adev->dev, "leaking bo va because "
144 "we fail to reserve bo (%d)\n", r);
147 bo_va = amdgpu_vm_bo_find(vm, rbo);
149 if (--bo_va->ref_count == 0) {
150 amdgpu_vm_bo_rmv(adev, bo_va);
153 amdgpu_bo_unreserve(rbo);
156 static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
159 r = amdgpu_gpu_reset(adev);
169 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
170 struct drm_file *filp)
172 struct amdgpu_device *adev = dev->dev_private;
173 union drm_amdgpu_gem_create *args = data;
174 uint64_t size = args->in.bo_size;
175 struct drm_gem_object *gobj;
180 /* create a gem object to contain this object in */
181 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
182 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
184 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
185 size = size << AMDGPU_GDS_SHIFT;
186 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
187 size = size << AMDGPU_GWS_SHIFT;
188 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
189 size = size << AMDGPU_OA_SHIFT;
195 size = roundup(size, PAGE_SIZE);
197 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
198 (u32)(0xffffffff & args->in.domains),
199 args->in.domain_flags,
204 r = drm_gem_handle_create(filp, gobj, &handle);
205 /* drop reference from allocate - handle holds it now */
206 drm_gem_object_unreference_unlocked(gobj);
210 memset(args, 0, sizeof(*args));
211 args->out.handle = handle;
215 r = amdgpu_gem_handle_lockup(adev, r);
219 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
220 struct drm_file *filp)
222 struct amdgpu_device *adev = dev->dev_private;
223 struct drm_amdgpu_gem_userptr *args = data;
224 struct drm_gem_object *gobj;
225 struct amdgpu_bo *bo;
229 if (offset_in_page(args->addr | args->size))
232 /* reject unknown flag values */
233 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
234 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
235 AMDGPU_GEM_USERPTR_REGISTER))
238 if (!(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) ||
239 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
241 /* if we want to write to it we must require anonymous
242 memory and install a MMU notifier */
246 /* create a gem object to contain this object in */
247 r = amdgpu_gem_object_create(adev, args->size, 0,
248 AMDGPU_GEM_DOMAIN_CPU, 0,
253 bo = gem_to_amdgpu_bo(gobj);
254 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
258 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
259 r = amdgpu_mn_register(bo, args->addr);
264 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
265 down_read(¤t->mm->mmap_sem);
266 r = amdgpu_bo_reserve(bo, true);
268 up_read(¤t->mm->mmap_sem);
272 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
273 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
274 amdgpu_bo_unreserve(bo);
275 up_read(¤t->mm->mmap_sem);
280 r = drm_gem_handle_create(filp, gobj, &handle);
281 /* drop reference from allocate - handle holds it now */
282 drm_gem_object_unreference_unlocked(gobj);
286 args->handle = handle;
290 drm_gem_object_unreference_unlocked(gobj);
293 r = amdgpu_gem_handle_lockup(adev, r);
298 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
299 struct drm_device *dev,
300 uint32_t handle, uint64_t *offset_p)
302 struct drm_gem_object *gobj;
303 struct amdgpu_bo *robj;
305 gobj = drm_gem_object_lookup(dev, filp, handle);
309 robj = gem_to_amdgpu_bo(gobj);
310 if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm) ||
311 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
312 drm_gem_object_unreference_unlocked(gobj);
315 *offset_p = amdgpu_bo_mmap_offset(robj);
316 drm_gem_object_unreference_unlocked(gobj);
320 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
321 struct drm_file *filp)
323 union drm_amdgpu_gem_mmap *args = data;
324 uint32_t handle = args->in.handle;
325 memset(args, 0, sizeof(*args));
326 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
330 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
332 * @timeout_ns: timeout in ns
334 * Calculate the timeout in jiffies from an absolute timeout in ns.
336 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
338 unsigned long timeout_jiffies;
341 /* clamp timeout if it's to large */
342 if (((int64_t)timeout_ns) < 0)
343 return MAX_SCHEDULE_TIMEOUT;
345 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
346 if (ktime_to_ns(timeout) < 0)
349 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
350 /* clamp timeout to avoid unsigned-> signed overflow */
351 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
352 return MAX_SCHEDULE_TIMEOUT - 1;
354 return timeout_jiffies;
357 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
358 struct drm_file *filp)
360 struct amdgpu_device *adev = dev->dev_private;
361 union drm_amdgpu_gem_wait_idle *args = data;
362 struct drm_gem_object *gobj;
363 struct amdgpu_bo *robj;
364 uint32_t handle = args->in.handle;
365 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
369 gobj = drm_gem_object_lookup(dev, filp, handle);
373 robj = gem_to_amdgpu_bo(gobj);
375 ret = reservation_object_test_signaled_rcu(robj->tbo.resv, true);
377 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, timeout);
379 /* ret == 0 means not signaled,
380 * ret > 0 means signaled
381 * ret < 0 means interrupted before timeout
384 memset(args, 0, sizeof(*args));
385 args->out.status = (ret == 0);
389 drm_gem_object_unreference_unlocked(gobj);
390 r = amdgpu_gem_handle_lockup(adev, r);
394 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
395 struct drm_file *filp)
397 struct drm_amdgpu_gem_metadata *args = data;
398 struct drm_gem_object *gobj;
399 struct amdgpu_bo *robj;
402 DRM_DEBUG("%d \n", args->handle);
403 gobj = drm_gem_object_lookup(dev, filp, args->handle);
406 robj = gem_to_amdgpu_bo(gobj);
408 r = amdgpu_bo_reserve(robj, false);
409 if (unlikely(r != 0))
412 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
413 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
414 r = amdgpu_bo_get_metadata(robj, args->data.data,
415 sizeof(args->data.data),
416 &args->data.data_size_bytes,
418 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
419 if (args->data.data_size_bytes > sizeof(args->data.data)) {
423 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
425 r = amdgpu_bo_set_metadata(robj, args->data.data,
426 args->data.data_size_bytes,
431 amdgpu_bo_unreserve(robj);
433 drm_gem_object_unreference_unlocked(gobj);
438 * amdgpu_gem_va_update_vm -update the bo_va in its VM
440 * @adev: amdgpu_device pointer
441 * @bo_va: bo_va to update
443 * Update the bo_va directly after setting it's address. Errors are not
444 * vital here, so they are not reported back to userspace.
446 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
447 struct amdgpu_bo_va *bo_va, uint32_t operation)
449 struct ttm_validate_buffer tv, *entry;
450 struct amdgpu_bo_list_entry *vm_bos;
451 struct ww_acquire_ctx ticket;
452 struct list_head list, duplicates;
456 INIT_LIST_HEAD(&list);
457 INIT_LIST_HEAD(&duplicates);
459 tv.bo = &bo_va->bo->tbo;
461 list_add(&tv.head, &list);
463 vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list);
467 /* Provide duplicates to avoid -EALREADY */
468 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
472 list_for_each_entry(entry, &list, head) {
473 domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);
474 /* if anything is swapped out don't swap it in here,
475 just abort and wait for the next CS */
476 if (domain == AMDGPU_GEM_DOMAIN_CPU)
477 goto error_unreserve;
479 r = amdgpu_vm_update_page_directory(adev, bo_va->vm);
481 goto error_unreserve;
483 r = amdgpu_vm_clear_freed(adev, bo_va->vm);
485 goto error_unreserve;
487 if (operation == AMDGPU_VA_OP_MAP)
488 r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem);
491 ttm_eu_backoff_reservation(&ticket, &list);
494 drm_free_large(vm_bos);
496 if (r && r != -ERESTARTSYS)
497 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
502 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
503 struct drm_file *filp)
505 struct drm_amdgpu_gem_va *args = data;
506 struct drm_gem_object *gobj;
507 struct amdgpu_device *adev = dev->dev_private;
508 struct amdgpu_fpriv *fpriv = filp->driver_priv;
509 struct amdgpu_bo *rbo;
510 struct amdgpu_bo_va *bo_va;
511 struct ttm_validate_buffer tv, tv_pd;
512 struct ww_acquire_ctx ticket;
513 struct list_head list, duplicates;
514 uint32_t invalid_flags, va_flags = 0;
517 if (!adev->vm_manager.enabled)
520 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
521 dev_err(&dev->pdev->dev,
522 "va_address 0x%lX is in reserved area 0x%X\n",
523 (unsigned long)args->va_address,
524 AMDGPU_VA_RESERVED_SIZE);
528 invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE |
529 AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE);
530 if ((args->flags & invalid_flags)) {
531 dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
532 args->flags, invalid_flags);
536 switch (args->operation) {
537 case AMDGPU_VA_OP_MAP:
538 case AMDGPU_VA_OP_UNMAP:
541 dev_err(&dev->pdev->dev, "unsupported operation %d\n",
546 gobj = drm_gem_object_lookup(dev, filp, args->handle);
549 rbo = gem_to_amdgpu_bo(gobj);
550 INIT_LIST_HEAD(&list);
551 INIT_LIST_HEAD(&duplicates);
554 list_add(&tv.head, &list);
556 if (args->operation == AMDGPU_VA_OP_MAP) {
557 tv_pd.bo = &fpriv->vm.page_directory->tbo;
559 list_add(&tv_pd.head, &list);
561 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
563 drm_gem_object_unreference_unlocked(gobj);
567 bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo);
569 ttm_eu_backoff_reservation(&ticket, &list);
570 drm_gem_object_unreference_unlocked(gobj);
574 switch (args->operation) {
575 case AMDGPU_VA_OP_MAP:
576 if (args->flags & AMDGPU_VM_PAGE_READABLE)
577 va_flags |= AMDGPU_PTE_READABLE;
578 if (args->flags & AMDGPU_VM_PAGE_WRITEABLE)
579 va_flags |= AMDGPU_PTE_WRITEABLE;
580 if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
581 va_flags |= AMDGPU_PTE_EXECUTABLE;
582 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
583 args->offset_in_bo, args->map_size,
586 case AMDGPU_VA_OP_UNMAP:
587 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
592 ttm_eu_backoff_reservation(&ticket, &list);
593 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE))
594 amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
596 drm_gem_object_unreference_unlocked(gobj);
600 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
601 struct drm_file *filp)
603 struct drm_amdgpu_gem_op *args = data;
604 struct drm_gem_object *gobj;
605 struct amdgpu_bo *robj;
608 gobj = drm_gem_object_lookup(dev, filp, args->handle);
612 robj = gem_to_amdgpu_bo(gobj);
614 r = amdgpu_bo_reserve(robj, false);
619 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
620 struct drm_amdgpu_gem_create_in info;
621 void __user *out = (void __user *)(long)args->value;
623 info.bo_size = robj->gem_base.size;
624 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
625 info.domains = robj->initial_domain;
626 info.domain_flags = robj->flags;
627 amdgpu_bo_unreserve(robj);
628 if (copy_to_user(out, &info, sizeof(info)))
632 case AMDGPU_GEM_OP_SET_PLACEMENT:
633 if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) {
635 amdgpu_bo_unreserve(robj);
638 robj->initial_domain = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
639 AMDGPU_GEM_DOMAIN_GTT |
640 AMDGPU_GEM_DOMAIN_CPU);
641 amdgpu_bo_unreserve(robj);
644 amdgpu_bo_unreserve(robj);
649 drm_gem_object_unreference_unlocked(gobj);
653 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
654 struct drm_device *dev,
655 struct drm_mode_create_dumb *args)
657 struct amdgpu_device *adev = dev->dev_private;
658 struct drm_gem_object *gobj;
662 args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8);
663 args->size = (u64)args->pitch * args->height;
664 args->size = ALIGN(args->size, PAGE_SIZE);
666 r = amdgpu_gem_object_create(adev, args->size, 0,
667 AMDGPU_GEM_DOMAIN_VRAM,
668 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
674 r = drm_gem_handle_create(file_priv, gobj, &handle);
675 /* drop reference from allocate - handle holds it now */
676 drm_gem_object_unreference_unlocked(gobj);
680 args->handle = handle;
684 #if defined(CONFIG_DEBUG_FS)
685 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
687 struct drm_info_node *node = (struct drm_info_node *)m->private;
688 struct drm_device *dev = node->minor->dev;
689 struct amdgpu_device *adev = dev->dev_private;
690 struct amdgpu_bo *rbo;
693 mutex_lock(&adev->gem.mutex);
694 list_for_each_entry(rbo, &adev->gem.objects, list) {
696 const char *placement;
698 domain = amdgpu_mem_type_to_domain(rbo->tbo.mem.mem_type);
700 case AMDGPU_GEM_DOMAIN_VRAM:
703 case AMDGPU_GEM_DOMAIN_GTT:
706 case AMDGPU_GEM_DOMAIN_CPU:
711 seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n",
712 i, amdgpu_bo_size(rbo) >> 10, amdgpu_bo_size(rbo) >> 20,
713 placement, (unsigned long)rbo->pid);
716 mutex_unlock(&adev->gem.mutex);
720 static struct drm_info_list amdgpu_debugfs_gem_list[] = {
721 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
725 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
727 #if defined(CONFIG_DEBUG_FS)
728 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);