drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33
  34 #include <linux/vga_switcheroo.h>
  35 #include <linux/slab.h>
  36 #include <linux/pm_runtime.h>
  37 #include "amdgpu_amdkfd.h"
  38
  39 /**
  40  * amdgpu_driver_unload_kms - Main unload function for KMS.
  41  *
  42  * @dev: drm dev pointer
  43  *
  44  * This is the main unload function for KMS (all asics).
  45  * Returns 0 on success.
  46  */
  47 void amdgpu_driver_unload_kms(struct drm_device *dev)
  48 {
  49         struct amdgpu_device *adev = dev->dev_private;
  50
  51         if (adev == NULL)
  52                 return;
  53
  54         if (adev->rmmio == NULL)
  55                 goto done_free;
  56
  57         if (amdgpu_sriov_vf(adev))
  58                 amdgpu_virt_request_full_gpu(adev, false);
  59
  60         if (amdgpu_device_is_px(dev)) {
  61                 pm_runtime_get_sync(dev->dev);
  62                 pm_runtime_forbid(dev->dev);
  63         }
  64
  65         amdgpu_amdkfd_device_fini(adev);
  66
  67         amdgpu_acpi_fini(adev);
  68
  69         amdgpu_device_fini(adev);
  70
  71 done_free:
  72         kfree(adev);
  73         dev->dev_private = NULL;
  74 }
  75
  76 /**
  77  * amdgpu_driver_load_kms - Main load function for KMS.
  78  *
  79  * @dev: drm dev pointer
  80  * @flags: device flags
  81  *
  82  * This is the main load function for KMS (all asics).
  83  * Returns 0 on success, error on failure.
  84  */
  85 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
  86 {
  87         struct amdgpu_device *adev;
  88         int r, acpi_status;
  89
  90         adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
  91         if (adev == NULL) {
  92                 return -ENOMEM;
  93         }
  94         dev->dev_private = (void *)adev;
  95
  96         if ((amdgpu_runtime_pm != 0) &&
  97             amdgpu_has_atpx() &&
  98             (amdgpu_is_atpx_hybrid() ||
  99              amdgpu_has_atpx_dgpu_power_cntl()) &&
 100             ((flags & AMD_IS_APU) == 0) &&
 101             !pci_is_thunderbolt_attached(dev->pdev))
 102                 flags |= AMD_IS_PX;
 103
 104         /* amdgpu_device_init should report only fatal error
 105          * like memory allocation failure or iomapping failure,
 106          * or memory manager initialization failure, it must
 107          * properly initialize the GPU MC controller and permit
 108          * VRAM allocation
 109          */
 110         r = amdgpu_device_init(adev, dev, dev->pdev, flags);
 111         if (r) {
 112                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 113                 goto out;
 114         }
 115
 116         /* Call ACPI methods: require modeset init
 117          * but failure is not fatal
 118          */
 119         if (!r) {
 120                 acpi_status = amdgpu_acpi_init(adev);
 121                 if (acpi_status)
 122                 dev_dbg(&dev->pdev->dev,
 123                                 "Error during ACPI methods call\n");
 124         }
 125
 126         amdgpu_amdkfd_load_interface(adev);
 127         amdgpu_amdkfd_device_probe(adev);
 128         amdgpu_amdkfd_device_init(adev);
 129
 130         if (amdgpu_device_is_px(dev)) {
 131                 pm_runtime_use_autosuspend(dev->dev);
 132                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 133                 pm_runtime_set_active(dev->dev);
 134                 pm_runtime_allow(dev->dev);
 135                 pm_runtime_mark_last_busy(dev->dev);
 136                 pm_runtime_put_autosuspend(dev->dev);
 137         }
 138
 139         if (amdgpu_sriov_vf(adev))
 140                 amdgpu_virt_release_full_gpu(adev, true);
 141
 142 out:
 143         if (r) {
 144                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 145                 if (adev->rmmio && amdgpu_device_is_px(dev))
 146                         pm_runtime_put_noidle(dev->dev);
 147                 amdgpu_driver_unload_kms(dev);
 148         }
 149
 150         return r;
 151 }
 152
 153 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 154                                 struct drm_amdgpu_query_fw *query_fw,
 155                                 struct amdgpu_device *adev)
 156 {
 157         switch (query_fw->fw_type) {
 158         case AMDGPU_INFO_FW_VCE:
 159                 fw_info->ver = adev->vce.fw_version;
 160                 fw_info->feature = adev->vce.fb_version;
 161                 break;
 162         case AMDGPU_INFO_FW_UVD:
 163                 fw_info->ver = adev->uvd.fw_version;
 164                 fw_info->feature = 0;
 165                 break;
 166         case AMDGPU_INFO_FW_GMC:
 167                 fw_info->ver = adev->mc.fw_version;
 168                 fw_info->feature = 0;
 169                 break;
 170         case AMDGPU_INFO_FW_GFX_ME:
 171                 fw_info->ver = adev->gfx.me_fw_version;
 172                 fw_info->feature = adev->gfx.me_feature_version;
 173                 break;
 174         case AMDGPU_INFO_FW_GFX_PFP:
 175                 fw_info->ver = adev->gfx.pfp_fw_version;
 176                 fw_info->feature = adev->gfx.pfp_feature_version;
 177                 break;
 178         case AMDGPU_INFO_FW_GFX_CE:
 179                 fw_info->ver = adev->gfx.ce_fw_version;
 180                 fw_info->feature = adev->gfx.ce_feature_version;
 181                 break;
 182         case AMDGPU_INFO_FW_GFX_RLC:
 183                 fw_info->ver = adev->gfx.rlc_fw_version;
 184                 fw_info->feature = adev->gfx.rlc_feature_version;
 185                 break;
 186         case AMDGPU_INFO_FW_GFX_MEC:
 187                 if (query_fw->index == 0) {
 188                         fw_info->ver = adev->gfx.mec_fw_version;
 189                         fw_info->feature = adev->gfx.mec_feature_version;
 190                 } else if (query_fw->index == 1) {
 191                         fw_info->ver = adev->gfx.mec2_fw_version;
 192                         fw_info->feature = adev->gfx.mec2_feature_version;
 193                 } else
 194                         return -EINVAL;
 195                 break;
 196         case AMDGPU_INFO_FW_SMC:
 197                 fw_info->ver = adev->pm.fw_version;
 198                 fw_info->feature = 0;
 199                 break;
 200         case AMDGPU_INFO_FW_SDMA:
 201                 if (query_fw->index >= adev->sdma.num_instances)
 202                         return -EINVAL;
 203                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 204                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 205                 break;
 206         case AMDGPU_INFO_FW_SOS:
 207                 fw_info->ver = adev->psp.sos_fw_version;
 208                 fw_info->feature = adev->psp.sos_feature_version;
 209                 break;
 210         case AMDGPU_INFO_FW_ASD:
 211                 fw_info->ver = adev->psp.asd_fw_version;
 212                 fw_info->feature = adev->psp.asd_feature_version;
 213                 break;
 214         default:
 215                 return -EINVAL;
 216         }
 217         return 0;
 218 }
 219
 220 /*
 221  * Userspace get information ioctl
 222  */
 223 /**
 224  * amdgpu_info_ioctl - answer a device specific request.
 225  *
 226  * @adev: amdgpu device pointer
 227  * @data: request object
 228  * @filp: drm filp
 229  *
 230  * This function is used to pass device specific parameters to the userspace
 231  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 232  * etc. (all asics).
 233  * Returns 0 on success, -EINVAL on failure.
 234  */
 235 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 236 {
 237         struct amdgpu_device *adev = dev->dev_private;
 238         struct drm_amdgpu_info *info = data;
 239         struct amdgpu_mode_info *minfo = &adev->mode_info;
 240         void __user *out = (void __user *)(long)info->return_pointer;
 241         uint32_t size = info->return_size;
 242         struct drm_crtc *crtc;
 243         uint32_t ui32 = 0;
 244         uint64_t ui64 = 0;
 245         int i, found;
 246         int ui32_size = sizeof(ui32);
 247
 248         if (!info->return_size || !info->return_pointer)
 249                 return -EINVAL;
 250
 251         switch (info->query) {
 252         case AMDGPU_INFO_ACCEL_WORKING:
 253                 ui32 = adev->accel_working;
 254                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 255         case AMDGPU_INFO_CRTC_FROM_ID:
 256                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 257                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 258                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 259                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 260                                 ui32 = amdgpu_crtc->crtc_id;
 261                                 found = 1;
 262                                 break;
 263                         }
 264                 }
 265                 if (!found) {
 266                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 267                         return -EINVAL;
 268                 }
 269                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 270         case AMDGPU_INFO_HW_IP_INFO: {
 271                 struct drm_amdgpu_info_hw_ip ip = {};
 272                 enum amd_ip_block_type type;
 273                 uint32_t ring_mask = 0;
 274                 uint32_t ib_start_alignment = 0;
 275                 uint32_t ib_size_alignment = 0;
 276
 277                 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 278                         return -EINVAL;
 279
 280                 switch (info->query_hw_ip.type) {
 281                 case AMDGPU_HW_IP_GFX:
 282                         type = AMD_IP_BLOCK_TYPE_GFX;
 283                         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 284                                 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
 285                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 286                         ib_size_alignment = 8;
 287                         break;
 288                 case AMDGPU_HW_IP_COMPUTE:
 289                         type = AMD_IP_BLOCK_TYPE_GFX;
 290                         for (i = 0; i < adev->gfx.num_compute_rings; i++)
 291                                 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
 292                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 293                         ib_size_alignment = 8;
 294                         break;
 295                 case AMDGPU_HW_IP_DMA:
 296                         type = AMD_IP_BLOCK_TYPE_SDMA;
 297                         for (i = 0; i < adev->sdma.num_instances; i++)
 298                                 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
 299                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 300                         ib_size_alignment = 1;
 301                         break;
 302                 case AMDGPU_HW_IP_UVD:
 303                         type = AMD_IP_BLOCK_TYPE_UVD;
 304                         ring_mask = adev->uvd.ring.ready ? 1 : 0;
 305                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 306                         ib_size_alignment = 16;
 307                         break;
 308                 case AMDGPU_HW_IP_VCE:
 309                         type = AMD_IP_BLOCK_TYPE_VCE;
 310                         for (i = 0; i < adev->vce.num_rings; i++)
 311                                 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
 312                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 313                         ib_size_alignment = 1;
 314                         break;
 315                 case AMDGPU_HW_IP_UVD_ENC:
 316                         type = AMD_IP_BLOCK_TYPE_UVD;
 317                         for (i = 0; i < adev->uvd.num_enc_rings; i++)
 318                                 ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i);
 319                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 320                         ib_size_alignment = 1;
 321                         break;
 322                 default:
 323                         return -EINVAL;
 324                 }
 325
 326                 for (i = 0; i < adev->num_ip_blocks; i++) {
 327                         if (adev->ip_blocks[i].version->type == type &&
 328                             adev->ip_blocks[i].status.valid) {
 329                                 ip.hw_ip_version_major = adev->ip_blocks[i].version->major;
 330                                 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 331                                 ip.capabilities_flags = 0;
 332                                 ip.available_rings = ring_mask;
 333                                 ip.ib_start_alignment = ib_start_alignment;
 334                                 ip.ib_size_alignment = ib_size_alignment;
 335                                 break;
 336                         }
 337                 }
 338                 return copy_to_user(out, &ip,
 339                                     min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
 340         }
 341         case AMDGPU_INFO_HW_IP_COUNT: {
 342                 enum amd_ip_block_type type;
 343                 uint32_t count = 0;
 344
 345                 switch (info->query_hw_ip.type) {
 346                 case AMDGPU_HW_IP_GFX:
 347                         type = AMD_IP_BLOCK_TYPE_GFX;
 348                         break;
 349                 case AMDGPU_HW_IP_COMPUTE:
 350                         type = AMD_IP_BLOCK_TYPE_GFX;
 351                         break;
 352                 case AMDGPU_HW_IP_DMA:
 353                         type = AMD_IP_BLOCK_TYPE_SDMA;
 354                         break;
 355                 case AMDGPU_HW_IP_UVD:
 356                         type = AMD_IP_BLOCK_TYPE_UVD;
 357                         break;
 358                 case AMDGPU_HW_IP_VCE:
 359                         type = AMD_IP_BLOCK_TYPE_VCE;
 360                         break;
 361                 case AMDGPU_HW_IP_UVD_ENC:
 362                         type = AMD_IP_BLOCK_TYPE_UVD;
 363                         break;
 364                 default:
 365                         return -EINVAL;
 366                 }
 367
 368                 for (i = 0; i < adev->num_ip_blocks; i++)
 369                         if (adev->ip_blocks[i].version->type == type &&
 370                             adev->ip_blocks[i].status.valid &&
 371                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 372                                 count++;
 373
 374                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 375         }
 376         case AMDGPU_INFO_TIMESTAMP:
 377                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 378                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 379         case AMDGPU_INFO_FW_VERSION: {
 380                 struct drm_amdgpu_info_firmware fw_info;
 381                 int ret;
 382
 383                 /* We only support one instance of each IP block right now. */
 384                 if (info->query_fw.ip_instance != 0)
 385                         return -EINVAL;
 386
 387                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 388                 if (ret)
 389                         return ret;
 390
 391                 return copy_to_user(out, &fw_info,
 392                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 393         }
 394         case AMDGPU_INFO_NUM_BYTES_MOVED:
 395                 ui64 = atomic64_read(&adev->num_bytes_moved);
 396                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 397         case AMDGPU_INFO_NUM_EVICTIONS:
 398                 ui64 = atomic64_read(&adev->num_evictions);
 399                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 400         case AMDGPU_INFO_VRAM_USAGE:
 401                 ui64 = atomic64_read(&adev->vram_usage);
 402                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 403         case AMDGPU_INFO_VIS_VRAM_USAGE:
 404                 ui64 = atomic64_read(&adev->vram_vis_usage);
 405                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 406         case AMDGPU_INFO_GTT_USAGE:
 407                 ui64 = atomic64_read(&adev->gtt_usage);
 408                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 409         case AMDGPU_INFO_GDS_CONFIG: {
 410                 struct drm_amdgpu_info_gds gds_info;
 411
 412                 memset(&gds_info, 0, sizeof(gds_info));
 413                 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
 414                 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
 415                 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
 416                 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
 417                 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
 418                 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
 419                 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
 420                 return copy_to_user(out, &gds_info,
 421                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 422         }
 423         case AMDGPU_INFO_VRAM_GTT: {
 424                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 425
 426                 vram_gtt.vram_size = adev->mc.real_vram_size;
 427                 vram_gtt.vram_size -= adev->vram_pin_size;
 428                 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
 429                 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
 430                 vram_gtt.gtt_size  = adev->mc.gtt_size;
 431                 vram_gtt.gtt_size -= adev->gart_pin_size;
 432                 return copy_to_user(out, &vram_gtt,
 433                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 434         }
 435         case AMDGPU_INFO_MEMORY: {
 436                 struct drm_amdgpu_memory_info mem;
 437
 438                 memset(&mem, 0, sizeof(mem));
 439                 mem.vram.total_heap_size = adev->mc.real_vram_size;
 440                 mem.vram.usable_heap_size =
 441                         adev->mc.real_vram_size - adev->vram_pin_size;
 442                 mem.vram.heap_usage = atomic64_read(&adev->vram_usage);
 443                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 444
 445                 mem.cpu_accessible_vram.total_heap_size =
 446                         adev->mc.visible_vram_size;
 447                 mem.cpu_accessible_vram.usable_heap_size =
 448                         adev->mc.visible_vram_size -
 449                         (adev->vram_pin_size - adev->invisible_pin_size);
 450                 mem.cpu_accessible_vram.heap_usage =
 451                         atomic64_read(&adev->vram_vis_usage);
 452                 mem.cpu_accessible_vram.max_allocation =
 453                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 454
 455                 mem.gtt.total_heap_size = adev->mc.gtt_size;
 456                 mem.gtt.usable_heap_size =
 457                         adev->mc.gtt_size - adev->gart_pin_size;
 458                 mem.gtt.heap_usage = atomic64_read(&adev->gtt_usage);
 459                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 460
 461                 return copy_to_user(out, &mem,
 462                                     min((size_t)size, sizeof(mem)))
 463                                     ? -EFAULT : 0;
 464         }
 465         case AMDGPU_INFO_READ_MMR_REG: {
 466                 unsigned n, alloc_size;
 467                 uint32_t *regs;
 468                 unsigned se_num = (info->read_mmr_reg.instance >>
 469                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 470                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 471                 unsigned sh_num = (info->read_mmr_reg.instance >>
 472                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 473                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 474
 475                 /* set full masks if the userspace set all bits
 476                  * in the bitfields */
 477                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 478                         se_num = 0xffffffff;
 479                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 480                         sh_num = 0xffffffff;
 481
 482                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 483                 if (!regs)
 484                         return -ENOMEM;
 485                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 486
 487                 for (i = 0; i < info->read_mmr_reg.count; i++)
 488                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 489                                                       info->read_mmr_reg.dword_offset + i,
 490                                                       &regs[i])) {
 491                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 492                                               info->read_mmr_reg.dword_offset + i);
 493                                 kfree(regs);
 494                                 return -EFAULT;
 495                         }
 496                 n = copy_to_user(out, regs, min(size, alloc_size));
 497                 kfree(regs);
 498                 return n ? -EFAULT : 0;
 499         }
 500         case AMDGPU_INFO_DEV_INFO: {
 501                 struct drm_amdgpu_info_device dev_info = {};
 502
 503                 dev_info.device_id = dev->pdev->device;
 504                 dev_info.chip_rev = adev->rev_id;
 505                 dev_info.external_rev = adev->external_rev_id;
 506                 dev_info.pci_rev = dev->pdev->revision;
 507                 dev_info.family = adev->family;
 508                 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
 509                 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 510                 /* return all clocks in KHz */
 511                 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 512                 if (adev->pm.dpm_enabled) {
 513                         dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 514                         dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 515                 } else {
 516                         dev_info.max_engine_clock = adev->pm.default_sclk * 10;
 517                         dev_info.max_memory_clock = adev->pm.default_mclk * 10;
 518                 }
 519                 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 520                 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
 521                         adev->gfx.config.max_shader_engines;
 522                 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 523                 dev_info._pad = 0;
 524                 dev_info.ids_flags = 0;
 525                 if (adev->flags & AMD_IS_APU)
 526                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 527                 if (amdgpu_sriov_vf(adev))
 528                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 529                 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 530                 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 531                 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 532                 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) *
 533                                              AMDGPU_GPU_PAGE_SIZE;
 534                 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 535
 536                 dev_info.cu_active_number = adev->gfx.cu_info.number;
 537                 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 538                 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
 539                 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 540                        sizeof(adev->gfx.cu_info.bitmap));
 541                 dev_info.vram_type = adev->mc.vram_type;
 542                 dev_info.vram_bit_width = adev->mc.vram_width;
 543                 dev_info.vce_harvest_config = adev->vce.harvest_config;
 544                 dev_info.gc_double_offchip_lds_buf =
 545                         adev->gfx.config.double_offchip_lds_buf;
 546
 547                 if (amdgpu_ngg) {
 548                         dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[PRIM].gpu_addr;
 549                         dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[POS].gpu_addr;
 550                         dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[CNTL].gpu_addr;
 551                         dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[PARAM].gpu_addr;
 552                 }
 553
 554                 return copy_to_user(out, &dev_info,
 555                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
 556         }
 557         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 558                 unsigned i;
 559                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 560                 struct amd_vce_state *vce_state;
 561
 562                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 563                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 564                         if (vce_state) {
 565                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 566                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 567                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 568                                 vce_clk_table.num_valid_entries++;
 569                         }
 570                 }
 571
 572                 return copy_to_user(out, &vce_clk_table,
 573                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 574         }
 575         case AMDGPU_INFO_VBIOS: {
 576                 uint32_t bios_size = adev->bios_size;
 577
 578                 switch (info->vbios_info.type) {
 579                 case AMDGPU_INFO_VBIOS_SIZE:
 580                         return copy_to_user(out, &bios_size,
 581                                         min((size_t)size, sizeof(bios_size)))
 582                                         ? -EFAULT : 0;
 583                 case AMDGPU_INFO_VBIOS_IMAGE: {
 584                         uint8_t *bios;
 585                         uint32_t bios_offset = info->vbios_info.offset;
 586
 587                         if (bios_offset >= bios_size)
 588                                 return -EINVAL;
 589
 590                         bios = adev->bios + bios_offset;
 591                         return copy_to_user(out, bios,
 592                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 593                                         ? -EFAULT : 0;
 594                 }
 595                 default:
 596                         DRM_DEBUG_KMS("Invalid request %d\n",
 597                                         info->vbios_info.type);
 598                         return -EINVAL;
 599                 }
 600         }
 601         case AMDGPU_INFO_NUM_HANDLES: {
 602                 struct drm_amdgpu_info_num_handles handle;
 603
 604                 switch (info->query_hw_ip.type) {
 605                 case AMDGPU_HW_IP_UVD:
 606                         /* Starting Polaris, we support unlimited UVD handles */
 607                         if (adev->asic_type < CHIP_POLARIS10) {
 608                                 handle.uvd_max_handles = adev->uvd.max_handles;
 609                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 610
 611                                 return copy_to_user(out, &handle,
 612                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 613                         } else {
 614                                 return -ENODATA;
 615                         }
 616
 617                         break;
 618                 default:
 619                         return -EINVAL;
 620                 }
 621         }
 622         case AMDGPU_INFO_SENSOR: {
 623                 struct pp_gpu_power query = {0};
 624                 int query_size = sizeof(query);
 625
 626                 if (amdgpu_dpm == 0)
 627                         return -ENOENT;
 628
 629                 switch (info->sensor_info.type) {
 630                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 631                         /* get sclk in Mhz */
 632                         if (amdgpu_dpm_read_sensor(adev,
 633                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 634                                                    (void *)&ui32, &ui32_size)) {
 635                                 return -EINVAL;
 636                         }
 637                         ui32 /= 100;
 638                         break;
 639                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 640                         /* get mclk in Mhz */
 641                         if (amdgpu_dpm_read_sensor(adev,
 642                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 643                                                    (void *)&ui32, &ui32_size)) {
 644                                 return -EINVAL;
 645                         }
 646                         ui32 /= 100;
 647                         break;
 648                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 649                         /* get temperature in millidegrees C */
 650                         if (amdgpu_dpm_read_sensor(adev,
 651                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 652                                                    (void *)&ui32, &ui32_size)) {
 653                                 return -EINVAL;
 654                         }
 655                         break;
 656                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 657                         /* get GPU load */
 658                         if (amdgpu_dpm_read_sensor(adev,
 659                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 660                                                    (void *)&ui32, &ui32_size)) {
 661                                 return -EINVAL;
 662                         }
 663                         break;
 664                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 665                         /* get average GPU power */
 666                         if (amdgpu_dpm_read_sensor(adev,
 667                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 668                                                    (void *)&query, &query_size)) {
 669                                 return -EINVAL;
 670                         }
 671                         ui32 = query.average_gpu_power >> 8;
 672                         break;
 673                 case AMDGPU_INFO_SENSOR_VDDNB:
 674                         /* get VDDNB in millivolts */
 675                         if (amdgpu_dpm_read_sensor(adev,
 676                                                    AMDGPU_PP_SENSOR_VDDNB,
 677                                                    (void *)&ui32, &ui32_size)) {
 678                                 return -EINVAL;
 679                         }
 680                         break;
 681                 case AMDGPU_INFO_SENSOR_VDDGFX:
 682                         /* get VDDGFX in millivolts */
 683                         if (amdgpu_dpm_read_sensor(adev,
 684                                                    AMDGPU_PP_SENSOR_VDDGFX,
 685                                                    (void *)&ui32, &ui32_size)) {
 686                                 return -EINVAL;
 687                         }
 688                         break;
 689                 default:
 690                         DRM_DEBUG_KMS("Invalid request %d\n",
 691                                       info->sensor_info.type);
 692                         return -EINVAL;
 693                 }
 694                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 695         }
 696         default:
 697                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 698                 return -EINVAL;
 699         }
 700         return 0;
 701 }
 702
 703
 704 /*
 705  * Outdated mess for old drm with Xorg being in charge (void function now).
 706  */
 707 /**
 708  * amdgpu_driver_lastclose_kms - drm callback for last close
 709  *
 710  * @dev: drm dev pointer
 711  *
 712  * Switch vga_switcheroo state after last close (all asics).
 713  */
 714 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 715 {
 716         struct amdgpu_device *adev = dev->dev_private;
 717
 718         amdgpu_fbdev_restore_mode(adev);
 719         vga_switcheroo_process_delayed_switch();
 720 }
 721
 722 /**
 723  * amdgpu_driver_open_kms - drm callback for open
 724  *
 725  * @dev: drm dev pointer
 726  * @file_priv: drm file
 727  *
 728  * On device open, init vm on cayman+ (all asics).
 729  * Returns 0 on success, error on failure.
 730  */
 731 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 732 {
 733         struct amdgpu_device *adev = dev->dev_private;
 734         struct amdgpu_fpriv *fpriv;
 735         int r;
 736
 737         file_priv->driver_priv = NULL;
 738
 739         r = pm_runtime_get_sync(dev->dev);
 740         if (r < 0)
 741                 return r;
 742
 743         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 744         if (unlikely(!fpriv)) {
 745                 r = -ENOMEM;
 746                 goto out_suspend;
 747         }
 748
 749         r = amdgpu_vm_init(adev, &fpriv->vm);
 750         if (r) {
 751                 kfree(fpriv);
 752                 goto out_suspend;
 753         }
 754
 755         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
 756         if (!fpriv->prt_va) {
 757                 r = -ENOMEM;
 758                 amdgpu_vm_fini(adev, &fpriv->vm);
 759                 kfree(fpriv);
 760                 goto out_suspend;
 761         }
 762
 763         if (amdgpu_sriov_vf(adev)) {
 764                 r = amdgpu_map_static_csa(adev, &fpriv->vm);
 765                 if (r)
 766                         goto out_suspend;
 767         }
 768
 769         mutex_init(&fpriv->bo_list_lock);
 770         idr_init(&fpriv->bo_list_handles);
 771
 772         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
 773
 774         file_priv->driver_priv = fpriv;
 775
 776 out_suspend:
 777         pm_runtime_mark_last_busy(dev->dev);
 778         pm_runtime_put_autosuspend(dev->dev);
 779
 780         return r;
 781 }
 782
 783 /**
 784  * amdgpu_driver_postclose_kms - drm callback for post close
 785  *
 786  * @dev: drm dev pointer
 787  * @file_priv: drm file
 788  *
 789  * On device post close, tear down vm on cayman+ (all asics).
 790  */
 791 void amdgpu_driver_postclose_kms(struct drm_device *dev,
 792                                  struct drm_file *file_priv)
 793 {
 794         struct amdgpu_device *adev = dev->dev_private;
 795         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 796         struct amdgpu_bo_list *list;
 797         int handle;
 798
 799         if (!fpriv)
 800                 return;
 801
 802         pm_runtime_get_sync(dev->dev);
 803
 804         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
 805
 806         amdgpu_uvd_free_handles(adev, file_priv);
 807         amdgpu_vce_free_handles(adev, file_priv);
 808
 809         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
 810
 811         if (amdgpu_sriov_vf(adev)) {
 812                 /* TODO: how to handle reserve failure */
 813                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, false));
 814                 amdgpu_vm_bo_rmv(adev, fpriv->vm.csa_bo_va);
 815                 fpriv->vm.csa_bo_va = NULL;
 816                 amdgpu_bo_unreserve(adev->virt.csa_obj);
 817         }
 818
 819         amdgpu_vm_fini(adev, &fpriv->vm);
 820
 821         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
 822                 amdgpu_bo_list_free(list);
 823
 824         idr_destroy(&fpriv->bo_list_handles);
 825         mutex_destroy(&fpriv->bo_list_lock);
 826
 827         kfree(fpriv);
 828         file_priv->driver_priv = NULL;
 829
 830         pm_runtime_mark_last_busy(dev->dev);
 831         pm_runtime_put_autosuspend(dev->dev);
 832 }
 833
 834 /*
 835  * VBlank related functions.
 836  */
 837 /**
 838  * amdgpu_get_vblank_counter_kms - get frame count
 839  *
 840  * @dev: drm dev pointer
 841  * @pipe: crtc to get the frame count from
 842  *
 843  * Gets the frame count on the requested crtc (all asics).
 844  * Returns frame count on success, -EINVAL on failure.
 845  */
 846 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
 847 {
 848         struct amdgpu_device *adev = dev->dev_private;
 849         int vpos, hpos, stat;
 850         u32 count;
 851
 852         if (pipe >= adev->mode_info.num_crtc) {
 853                 DRM_ERROR("Invalid crtc %u\n", pipe);
 854                 return -EINVAL;
 855         }
 856
 857         /* The hw increments its frame counter at start of vsync, not at start
 858          * of vblank, as is required by DRM core vblank counter handling.
 859          * Cook the hw count here to make it appear to the caller as if it
 860          * incremented at start of vblank. We measure distance to start of
 861          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
 862          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
 863          * result by 1 to give the proper appearance to caller.
 864          */
 865         if (adev->mode_info.crtcs[pipe]) {
 866                 /* Repeat readout if needed to provide stable result if
 867                  * we cross start of vsync during the queries.
 868                  */
 869                 do {
 870                         count = amdgpu_display_vblank_get_counter(adev, pipe);
 871                         /* Ask amdgpu_get_crtc_scanoutpos to return vpos as
 872                          * distance to start of vblank, instead of regular
 873                          * vertical scanout pos.
 874                          */
 875                         stat = amdgpu_get_crtc_scanoutpos(
 876                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
 877                                 &vpos, &hpos, NULL, NULL,
 878                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
 879                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
 880
 881                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
 882                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
 883                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
 884                 } else {
 885                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
 886                                       pipe, vpos);
 887
 888                         /* Bump counter if we are at >= leading edge of vblank,
 889                          * but before vsync where vpos would turn negative and
 890                          * the hw counter really increments.
 891                          */
 892                         if (vpos >= 0)
 893                                 count++;
 894                 }
 895         } else {
 896                 /* Fallback to use value as is. */
 897                 count = amdgpu_display_vblank_get_counter(adev, pipe);
 898                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
 899         }
 900
 901         return count;
 902 }
 903
 904 /**
 905  * amdgpu_enable_vblank_kms - enable vblank interrupt
 906  *
 907  * @dev: drm dev pointer
 908  * @pipe: crtc to enable vblank interrupt for
 909  *
 910  * Enable the interrupt on the requested crtc (all asics).
 911  * Returns 0 on success, -EINVAL on failure.
 912  */
 913 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
 914 {
 915         struct amdgpu_device *adev = dev->dev_private;
 916         int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
 917
 918         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
 919 }
 920
 921 /**
 922  * amdgpu_disable_vblank_kms - disable vblank interrupt
 923  *
 924  * @dev: drm dev pointer
 925  * @pipe: crtc to disable vblank interrupt for
 926  *
 927  * Disable the interrupt on the requested crtc (all asics).
 928  */
 929 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
 930 {
 931         struct amdgpu_device *adev = dev->dev_private;
 932         int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
 933
 934         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
 935 }
 936
 937 /**
 938  * amdgpu_get_vblank_timestamp_kms - get vblank timestamp
 939  *
 940  * @dev: drm dev pointer
 941  * @crtc: crtc to get the timestamp for
 942  * @max_error: max error
 943  * @vblank_time: time value
 944  * @flags: flags passed to the driver
 945  *
 946  * Gets the timestamp on the requested crtc based on the
 947  * scanout position.  (all asics).
 948  * Returns postive status flags on success, negative error on failure.
 949  */
 950 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
 951                                     int *max_error,
 952                                     struct timeval *vblank_time,
 953                                     unsigned flags)
 954 {
 955         struct drm_crtc *crtc;
 956         struct amdgpu_device *adev = dev->dev_private;
 957
 958         if (pipe >= dev->num_crtcs) {
 959                 DRM_ERROR("Invalid crtc %u\n", pipe);
 960                 return -EINVAL;
 961         }
 962
 963         /* Get associated drm_crtc: */
 964         crtc = &adev->mode_info.crtcs[pipe]->base;
 965         if (!crtc) {
 966                 /* This can occur on driver load if some component fails to
 967                  * initialize completely and driver is unloaded */
 968                 DRM_ERROR("Uninitialized crtc %d\n", pipe);
 969                 return -EINVAL;
 970         }
 971
 972         /* Helper routine in DRM core does all the work: */
 973         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 974                                                      vblank_time, flags,
 975                                                      &crtc->hwmode);
 976 }
 977
 978 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
 979         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 980         DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 981         DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 982         /* KMS */
 983         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 984         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 985         DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 986         DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 987         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 988         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 989         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 990         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 991         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 992         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 993 };
 994 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
 995
 996 /*
 997  * Debugfs info
 998  */
 999 #if defined(CONFIG_DEBUG_FS)
1000
1001 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1002 {
1003         struct drm_info_node *node = (struct drm_info_node *) m->private;
1004         struct drm_device *dev = node->minor->dev;
1005         struct amdgpu_device *adev = dev->dev_private;
1006         struct drm_amdgpu_info_firmware fw_info;
1007         struct drm_amdgpu_query_fw query_fw;
1008         int ret, i;
1009
1010         /* VCE */
1011         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1012         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1013         if (ret)
1014                 return ret;
1015         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1016                    fw_info.feature, fw_info.ver);
1017
1018         /* UVD */
1019         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1020         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1021         if (ret)
1022                 return ret;
1023         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1024                    fw_info.feature, fw_info.ver);
1025
1026         /* GMC */
1027         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1028         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1029         if (ret)
1030                 return ret;
1031         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1032                    fw_info.feature, fw_info.ver);
1033
1034         /* ME */
1035         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1036         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1037         if (ret)
1038                 return ret;
1039         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1040                    fw_info.feature, fw_info.ver);
1041
1042         /* PFP */
1043         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1044         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1045         if (ret)
1046                 return ret;
1047         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1048                    fw_info.feature, fw_info.ver);
1049
1050         /* CE */
1051         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1052         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1053         if (ret)
1054                 return ret;
1055         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1056                    fw_info.feature, fw_info.ver);
1057
1058         /* RLC */
1059         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1060         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1061         if (ret)
1062                 return ret;
1063         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1064                    fw_info.feature, fw_info.ver);
1065
1066         /* MEC */
1067         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1068         query_fw.index = 0;
1069         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1070         if (ret)
1071                 return ret;
1072         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1073                    fw_info.feature, fw_info.ver);
1074
1075         /* MEC2 */
1076         if (adev->asic_type == CHIP_KAVERI ||
1077             (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1078                 query_fw.index = 1;
1079                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1080                 if (ret)
1081                         return ret;
1082                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1083                            fw_info.feature, fw_info.ver);
1084         }
1085
1086         /* PSP SOS */
1087         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1088         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1089         if (ret)
1090                 return ret;
1091         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1092                    fw_info.feature, fw_info.ver);
1093
1094
1095         /* PSP ASD */
1096         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1097         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1098         if (ret)
1099                 return ret;
1100         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1101                    fw_info.feature, fw_info.ver);
1102
1103         /* SMC */
1104         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1105         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1106         if (ret)
1107                 return ret;
1108         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1109                    fw_info.feature, fw_info.ver);
1110
1111         /* SDMA */
1112         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1113         for (i = 0; i < adev->sdma.num_instances; i++) {
1114                 query_fw.index = i;
1115                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1116                 if (ret)
1117                         return ret;
1118                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1119                            i, fw_info.feature, fw_info.ver);
1120         }
1121
1122         return 0;
1123 }
1124
1125 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1126         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1127 };
1128 #endif
1129
1130 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1131 {
1132 #if defined(CONFIG_DEBUG_FS)
1133         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1134                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1135 #else
1136         return 0;
1137 #endif
1138 }