drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_drv.h"
  26 #include "amdgpu_pm.h"
  27 #include "amdgpu_dpm.h"
  28 #include "atom.h"
  29 #include <linux/power_supply.h>
  30 #include <linux/hwmon.h>
  31 #include <linux/hwmon-sysfs.h>
  32
  33 #include "amd_powerplay.h"
  34
  35 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  36
  37 static const struct cg_flag_name clocks[] = {
  38         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  39         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  40         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  41         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  42         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  43         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  44         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  46         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  47         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  49         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  50         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  51         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  52         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  54         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  56         {0, NULL},
  57 };
  58
  59 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  60 {
  61         if (adev->pp_enabled)
  62                 /* TODO */
  63                 return;
  64
  65         if (adev->pm.dpm_enabled) {
  66                 mutex_lock(&adev->pm.mutex);
  67                 if (power_supply_is_system_supplied() > 0)
  68                         adev->pm.dpm.ac_power = true;
  69                 else
  70                         adev->pm.dpm.ac_power = false;
  71                 if (adev->pm.funcs->enable_bapm)
  72                         amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
  73                 mutex_unlock(&adev->pm.mutex);
  74         }
  75 }
  76
  77 static ssize_t amdgpu_get_dpm_state(struct device *dev,
  78                                     struct device_attribute *attr,
  79                                     char *buf)
  80 {
  81         struct drm_device *ddev = dev_get_drvdata(dev);
  82         struct amdgpu_device *adev = ddev->dev_private;
  83         enum amd_pm_state_type pm;
  84
  85         if (adev->pp_enabled) {
  86                 pm = amdgpu_dpm_get_current_power_state(adev);
  87         } else
  88                 pm = adev->pm.dpm.user_state;
  89
  90         return snprintf(buf, PAGE_SIZE, "%s\n",
  91                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
  92                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
  93 }
  94
  95 static ssize_t amdgpu_set_dpm_state(struct device *dev,
  96                                     struct device_attribute *attr,
  97                                     const char *buf,
  98                                     size_t count)
  99 {
 100         struct drm_device *ddev = dev_get_drvdata(dev);
 101         struct amdgpu_device *adev = ddev->dev_private;
 102         enum amd_pm_state_type  state;
 103
 104         if (strncmp("battery", buf, strlen("battery")) == 0)
 105                 state = POWER_STATE_TYPE_BATTERY;
 106         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 107                 state = POWER_STATE_TYPE_BALANCED;
 108         else if (strncmp("performance", buf, strlen("performance")) == 0)
 109                 state = POWER_STATE_TYPE_PERFORMANCE;
 110         else {
 111                 count = -EINVAL;
 112                 goto fail;
 113         }
 114
 115         if (adev->pp_enabled) {
 116                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
 117         } else {
 118                 mutex_lock(&adev->pm.mutex);
 119                 adev->pm.dpm.user_state = state;
 120                 mutex_unlock(&adev->pm.mutex);
 121
 122                 /* Can't set dpm state when the card is off */
 123                 if (!(adev->flags & AMD_IS_PX) ||
 124                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 125                         amdgpu_pm_compute_clocks(adev);
 126         }
 127 fail:
 128         return count;
 129 }
 130
 131 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 132                                                 struct device_attribute *attr,
 133                                                                 char *buf)
 134 {
 135         struct drm_device *ddev = dev_get_drvdata(dev);
 136         struct amdgpu_device *adev = ddev->dev_private;
 137         enum amd_dpm_forced_level level;
 138
 139         if  ((adev->flags & AMD_IS_PX) &&
 140              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 141                 return snprintf(buf, PAGE_SIZE, "off\n");
 142
 143         level = amdgpu_dpm_get_performance_level(adev);
 144         return snprintf(buf, PAGE_SIZE, "%s\n",
 145                         (level & (AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 146                         (level & AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 147                         (level & AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 148                         (level & AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 149                         (level & AMD_DPM_FORCED_LEVEL_PROFILING) ? "profiling" :
 150                         "unknown"));
 151 }
 152
 153 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 154                                                        struct device_attribute *attr,
 155                                                        const char *buf,
 156                                                        size_t count)
 157 {
 158         struct drm_device *ddev = dev_get_drvdata(dev);
 159         struct amdgpu_device *adev = ddev->dev_private;
 160         enum amd_dpm_forced_level level;
 161         enum amd_dpm_forced_level current_level;
 162         int ret = 0;
 163
 164         /* Can't force performance level when the card is off */
 165         if  ((adev->flags & AMD_IS_PX) &&
 166              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 167                 return -EINVAL;
 168
 169         current_level = amdgpu_dpm_get_performance_level(adev);
 170
 171         if (strncmp("low", buf, strlen("low")) == 0) {
 172                 level = AMD_DPM_FORCED_LEVEL_LOW;
 173         } else if (strncmp("high", buf, strlen("high")) == 0) {
 174                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 175         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 176                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 177         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 178                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 179         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 180                 level = AMD_DPM_FORCED_LEVEL_PROFILING;
 181         } else {
 182                 count = -EINVAL;
 183                 goto fail;
 184         }
 185
 186         if (current_level == level)
 187                 return count;
 188
 189         if (level == AMD_DPM_FORCED_LEVEL_PROFILING)
 190                 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
 191                                                 AMD_CG_STATE_UNGATE);
 192         else if (level != AMD_DPM_FORCED_LEVEL_PROFILING &&
 193                         current_level == AMD_DPM_FORCED_LEVEL_PROFILING)
 194                 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
 195                                                 AMD_CG_STATE_GATE);
 196
 197         if (adev->pp_enabled)
 198                 amdgpu_dpm_force_performance_level(adev, level);
 199         else {
 200                 mutex_lock(&adev->pm.mutex);
 201                 if (adev->pm.dpm.thermal_active) {
 202                         count = -EINVAL;
 203                         mutex_unlock(&adev->pm.mutex);
 204                         goto fail;
 205                 }
 206                 ret = amdgpu_dpm_force_performance_level(adev, level);
 207                 if (ret)
 208                         count = -EINVAL;
 209                 else
 210                         adev->pm.dpm.forced_level = level;
 211                 mutex_unlock(&adev->pm.mutex);
 212         }
 213 fail:
 214         return count;
 215 }
 216
 217 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 218                 struct device_attribute *attr,
 219                 char *buf)
 220 {
 221         struct drm_device *ddev = dev_get_drvdata(dev);
 222         struct amdgpu_device *adev = ddev->dev_private;
 223         struct pp_states_info data;
 224         int i, buf_len;
 225
 226         if (adev->pp_enabled)
 227                 amdgpu_dpm_get_pp_num_states(adev, &data);
 228
 229         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 230         for (i = 0; i < data.nums; i++)
 231                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 232                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 233                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 234                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 235                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 236
 237         return buf_len;
 238 }
 239
 240 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 241                 struct device_attribute *attr,
 242                 char *buf)
 243 {
 244         struct drm_device *ddev = dev_get_drvdata(dev);
 245         struct amdgpu_device *adev = ddev->dev_private;
 246         struct pp_states_info data;
 247         enum amd_pm_state_type pm = 0;
 248         int i = 0;
 249
 250         if (adev->pp_enabled) {
 251
 252                 pm = amdgpu_dpm_get_current_power_state(adev);
 253                 amdgpu_dpm_get_pp_num_states(adev, &data);
 254
 255                 for (i = 0; i < data.nums; i++) {
 256                         if (pm == data.states[i])
 257                                 break;
 258                 }
 259
 260                 if (i == data.nums)
 261                         i = -EINVAL;
 262         }
 263
 264         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 265 }
 266
 267 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 268                 struct device_attribute *attr,
 269                 char *buf)
 270 {
 271         struct drm_device *ddev = dev_get_drvdata(dev);
 272         struct amdgpu_device *adev = ddev->dev_private;
 273         struct pp_states_info data;
 274         enum amd_pm_state_type pm = 0;
 275         int i;
 276
 277         if (adev->pp_force_state_enabled && adev->pp_enabled) {
 278                 pm = amdgpu_dpm_get_current_power_state(adev);
 279                 amdgpu_dpm_get_pp_num_states(adev, &data);
 280
 281                 for (i = 0; i < data.nums; i++) {
 282                         if (pm == data.states[i])
 283                                 break;
 284                 }
 285
 286                 if (i == data.nums)
 287                         i = -EINVAL;
 288
 289                 return snprintf(buf, PAGE_SIZE, "%d\n", i);
 290
 291         } else
 292                 return snprintf(buf, PAGE_SIZE, "\n");
 293 }
 294
 295 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 296                 struct device_attribute *attr,
 297                 const char *buf,
 298                 size_t count)
 299 {
 300         struct drm_device *ddev = dev_get_drvdata(dev);
 301         struct amdgpu_device *adev = ddev->dev_private;
 302         enum amd_pm_state_type state = 0;
 303         unsigned long idx;
 304         int ret;
 305
 306         if (strlen(buf) == 1)
 307                 adev->pp_force_state_enabled = false;
 308         else if (adev->pp_enabled) {
 309                 struct pp_states_info data;
 310
 311                 ret = kstrtoul(buf, 0, &idx);
 312                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 313                         count = -EINVAL;
 314                         goto fail;
 315                 }
 316
 317                 amdgpu_dpm_get_pp_num_states(adev, &data);
 318                 state = data.states[idx];
 319                 /* only set user selected power states */
 320                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 321                     state != POWER_STATE_TYPE_DEFAULT) {
 322                         amdgpu_dpm_dispatch_task(adev,
 323                                         AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
 324                         adev->pp_force_state_enabled = true;
 325                 }
 326         }
 327 fail:
 328         return count;
 329 }
 330
 331 static ssize_t amdgpu_get_pp_table(struct device *dev,
 332                 struct device_attribute *attr,
 333                 char *buf)
 334 {
 335         struct drm_device *ddev = dev_get_drvdata(dev);
 336         struct amdgpu_device *adev = ddev->dev_private;
 337         char *table = NULL;
 338         int size;
 339
 340         if (adev->pp_enabled)
 341                 size = amdgpu_dpm_get_pp_table(adev, &table);
 342         else
 343                 return 0;
 344
 345         if (size >= PAGE_SIZE)
 346                 size = PAGE_SIZE - 1;
 347
 348         memcpy(buf, table, size);
 349
 350         return size;
 351 }
 352
 353 static ssize_t amdgpu_set_pp_table(struct device *dev,
 354                 struct device_attribute *attr,
 355                 const char *buf,
 356                 size_t count)
 357 {
 358         struct drm_device *ddev = dev_get_drvdata(dev);
 359         struct amdgpu_device *adev = ddev->dev_private;
 360
 361         if (adev->pp_enabled)
 362                 amdgpu_dpm_set_pp_table(adev, buf, count);
 363
 364         return count;
 365 }
 366
 367 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 368                 struct device_attribute *attr,
 369                 char *buf)
 370 {
 371         struct drm_device *ddev = dev_get_drvdata(dev);
 372         struct amdgpu_device *adev = ddev->dev_private;
 373         ssize_t size = 0;
 374
 375         if (adev->pp_enabled)
 376                 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 377         else if (adev->pm.funcs->print_clock_levels)
 378                 size = adev->pm.funcs->print_clock_levels(adev, PP_SCLK, buf);
 379
 380         return size;
 381 }
 382
 383 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 384                 struct device_attribute *attr,
 385                 const char *buf,
 386                 size_t count)
 387 {
 388         struct drm_device *ddev = dev_get_drvdata(dev);
 389         struct amdgpu_device *adev = ddev->dev_private;
 390         int ret;
 391         long level;
 392         uint32_t i, mask = 0;
 393         char sub_str[2];
 394
 395         for (i = 0; i < strlen(buf); i++) {
 396                 if (*(buf + i) == '\n')
 397                         continue;
 398                 sub_str[0] = *(buf + i);
 399                 sub_str[1] = '\0';
 400                 ret = kstrtol(sub_str, 0, &level);
 401
 402                 if (ret) {
 403                         count = -EINVAL;
 404                         goto fail;
 405                 }
 406                 mask |= 1 << level;
 407         }
 408
 409         if (adev->pp_enabled)
 410                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 411         else if (adev->pm.funcs->force_clock_level)
 412                 adev->pm.funcs->force_clock_level(adev, PP_SCLK, mask);
 413 fail:
 414         return count;
 415 }
 416
 417 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 418                 struct device_attribute *attr,
 419                 char *buf)
 420 {
 421         struct drm_device *ddev = dev_get_drvdata(dev);
 422         struct amdgpu_device *adev = ddev->dev_private;
 423         ssize_t size = 0;
 424
 425         if (adev->pp_enabled)
 426                 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 427         else if (adev->pm.funcs->print_clock_levels)
 428                 size = adev->pm.funcs->print_clock_levels(adev, PP_MCLK, buf);
 429
 430         return size;
 431 }
 432
 433 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 434                 struct device_attribute *attr,
 435                 const char *buf,
 436                 size_t count)
 437 {
 438         struct drm_device *ddev = dev_get_drvdata(dev);
 439         struct amdgpu_device *adev = ddev->dev_private;
 440         int ret;
 441         long level;
 442         uint32_t i, mask = 0;
 443         char sub_str[2];
 444
 445         for (i = 0; i < strlen(buf); i++) {
 446                 if (*(buf + i) == '\n')
 447                         continue;
 448                 sub_str[0] = *(buf + i);
 449                 sub_str[1] = '\0';
 450                 ret = kstrtol(sub_str, 0, &level);
 451
 452                 if (ret) {
 453                         count = -EINVAL;
 454                         goto fail;
 455                 }
 456                 mask |= 1 << level;
 457         }
 458
 459         if (adev->pp_enabled)
 460                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 461         else if (adev->pm.funcs->force_clock_level)
 462                 adev->pm.funcs->force_clock_level(adev, PP_MCLK, mask);
 463 fail:
 464         return count;
 465 }
 466
 467 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 468                 struct device_attribute *attr,
 469                 char *buf)
 470 {
 471         struct drm_device *ddev = dev_get_drvdata(dev);
 472         struct amdgpu_device *adev = ddev->dev_private;
 473         ssize_t size = 0;
 474
 475         if (adev->pp_enabled)
 476                 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 477         else if (adev->pm.funcs->print_clock_levels)
 478                 size = adev->pm.funcs->print_clock_levels(adev, PP_PCIE, buf);
 479
 480         return size;
 481 }
 482
 483 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 484                 struct device_attribute *attr,
 485                 const char *buf,
 486                 size_t count)
 487 {
 488         struct drm_device *ddev = dev_get_drvdata(dev);
 489         struct amdgpu_device *adev = ddev->dev_private;
 490         int ret;
 491         long level;
 492         uint32_t i, mask = 0;
 493         char sub_str[2];
 494
 495         for (i = 0; i < strlen(buf); i++) {
 496                 if (*(buf + i) == '\n')
 497                         continue;
 498                 sub_str[0] = *(buf + i);
 499                 sub_str[1] = '\0';
 500                 ret = kstrtol(sub_str, 0, &level);
 501
 502                 if (ret) {
 503                         count = -EINVAL;
 504                         goto fail;
 505                 }
 506                 mask |= 1 << level;
 507         }
 508
 509         if (adev->pp_enabled)
 510                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 511         else if (adev->pm.funcs->force_clock_level)
 512                 adev->pm.funcs->force_clock_level(adev, PP_PCIE, mask);
 513 fail:
 514         return count;
 515 }
 516
 517 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 518                 struct device_attribute *attr,
 519                 char *buf)
 520 {
 521         struct drm_device *ddev = dev_get_drvdata(dev);
 522         struct amdgpu_device *adev = ddev->dev_private;
 523         uint32_t value = 0;
 524
 525         if (adev->pp_enabled)
 526                 value = amdgpu_dpm_get_sclk_od(adev);
 527         else if (adev->pm.funcs->get_sclk_od)
 528                 value = adev->pm.funcs->get_sclk_od(adev);
 529
 530         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 531 }
 532
 533 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
 534                 struct device_attribute *attr,
 535                 const char *buf,
 536                 size_t count)
 537 {
 538         struct drm_device *ddev = dev_get_drvdata(dev);
 539         struct amdgpu_device *adev = ddev->dev_private;
 540         int ret;
 541         long int value;
 542
 543         ret = kstrtol(buf, 0, &value);
 544
 545         if (ret) {
 546                 count = -EINVAL;
 547                 goto fail;
 548         }
 549
 550         if (adev->pp_enabled) {
 551                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
 552                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);
 553         } else if (adev->pm.funcs->set_sclk_od) {
 554                 adev->pm.funcs->set_sclk_od(adev, (uint32_t)value);
 555                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 556                 amdgpu_pm_compute_clocks(adev);
 557         }
 558
 559 fail:
 560         return count;
 561 }
 562
 563 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
 564                 struct device_attribute *attr,
 565                 char *buf)
 566 {
 567         struct drm_device *ddev = dev_get_drvdata(dev);
 568         struct amdgpu_device *adev = ddev->dev_private;
 569         uint32_t value = 0;
 570
 571         if (adev->pp_enabled)
 572                 value = amdgpu_dpm_get_mclk_od(adev);
 573         else if (adev->pm.funcs->get_mclk_od)
 574                 value = adev->pm.funcs->get_mclk_od(adev);
 575
 576         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 577 }
 578
 579 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
 580                 struct device_attribute *attr,
 581                 const char *buf,
 582                 size_t count)
 583 {
 584         struct drm_device *ddev = dev_get_drvdata(dev);
 585         struct amdgpu_device *adev = ddev->dev_private;
 586         int ret;
 587         long int value;
 588
 589         ret = kstrtol(buf, 0, &value);
 590
 591         if (ret) {
 592                 count = -EINVAL;
 593                 goto fail;
 594         }
 595
 596         if (adev->pp_enabled) {
 597                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
 598                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);
 599         } else if (adev->pm.funcs->set_mclk_od) {
 600                 adev->pm.funcs->set_mclk_od(adev, (uint32_t)value);
 601                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 602                 amdgpu_pm_compute_clocks(adev);
 603         }
 604
 605 fail:
 606         return count;
 607 }
 608
 609 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 610 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 611                    amdgpu_get_dpm_forced_performance_level,
 612                    amdgpu_set_dpm_forced_performance_level);
 613 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 614 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 615 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 616                 amdgpu_get_pp_force_state,
 617                 amdgpu_set_pp_force_state);
 618 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 619                 amdgpu_get_pp_table,
 620                 amdgpu_set_pp_table);
 621 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 622                 amdgpu_get_pp_dpm_sclk,
 623                 amdgpu_set_pp_dpm_sclk);
 624 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 625                 amdgpu_get_pp_dpm_mclk,
 626                 amdgpu_set_pp_dpm_mclk);
 627 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 628                 amdgpu_get_pp_dpm_pcie,
 629                 amdgpu_set_pp_dpm_pcie);
 630 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
 631                 amdgpu_get_pp_sclk_od,
 632                 amdgpu_set_pp_sclk_od);
 633 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
 634                 amdgpu_get_pp_mclk_od,
 635                 amdgpu_set_pp_mclk_od);
 636
 637 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 638                                       struct device_attribute *attr,
 639                                       char *buf)
 640 {
 641         struct amdgpu_device *adev = dev_get_drvdata(dev);
 642         struct drm_device *ddev = adev->ddev;
 643         int temp;
 644
 645         /* Can't get temperature when the card is off */
 646         if  ((adev->flags & AMD_IS_PX) &&
 647              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 648                 return -EINVAL;
 649
 650         if (!adev->pp_enabled && !adev->pm.funcs->get_temperature)
 651                 temp = 0;
 652         else
 653                 temp = amdgpu_dpm_get_temperature(adev);
 654
 655         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 656 }
 657
 658 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 659                                              struct device_attribute *attr,
 660                                              char *buf)
 661 {
 662         struct amdgpu_device *adev = dev_get_drvdata(dev);
 663         int hyst = to_sensor_dev_attr(attr)->index;
 664         int temp;
 665
 666         if (hyst)
 667                 temp = adev->pm.dpm.thermal.min_temp;
 668         else
 669                 temp = adev->pm.dpm.thermal.max_temp;
 670
 671         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 672 }
 673
 674 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 675                                             struct device_attribute *attr,
 676                                             char *buf)
 677 {
 678         struct amdgpu_device *adev = dev_get_drvdata(dev);
 679         u32 pwm_mode = 0;
 680
 681         if (!adev->pp_enabled && !adev->pm.funcs->get_fan_control_mode)
 682                 return -EINVAL;
 683
 684         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
 685
 686         /* never 0 (full-speed), fuse or smc-controlled always */
 687         return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
 688 }
 689
 690 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
 691                                             struct device_attribute *attr,
 692                                             const char *buf,
 693                                             size_t count)
 694 {
 695         struct amdgpu_device *adev = dev_get_drvdata(dev);
 696         int err;
 697         int value;
 698
 699         if (!adev->pp_enabled && !adev->pm.funcs->set_fan_control_mode)
 700                 return -EINVAL;
 701
 702         err = kstrtoint(buf, 10, &value);
 703         if (err)
 704                 return err;
 705
 706         switch (value) {
 707         case 1: /* manual, percent-based */
 708                 amdgpu_dpm_set_fan_control_mode(adev, FDO_PWM_MODE_STATIC);
 709                 break;
 710         default: /* disable */
 711                 amdgpu_dpm_set_fan_control_mode(adev, 0);
 712                 break;
 713         }
 714
 715         return count;
 716 }
 717
 718 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
 719                                          struct device_attribute *attr,
 720                                          char *buf)
 721 {
 722         return sprintf(buf, "%i\n", 0);
 723 }
 724
 725 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
 726                                          struct device_attribute *attr,
 727                                          char *buf)
 728 {
 729         return sprintf(buf, "%i\n", 255);
 730 }
 731
 732 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
 733                                      struct device_attribute *attr,
 734                                      const char *buf, size_t count)
 735 {
 736         struct amdgpu_device *adev = dev_get_drvdata(dev);
 737         int err;
 738         u32 value;
 739
 740         err = kstrtou32(buf, 10, &value);
 741         if (err)
 742                 return err;
 743
 744         value = (value * 100) / 255;
 745
 746         err = amdgpu_dpm_set_fan_speed_percent(adev, value);
 747         if (err)
 748                 return err;
 749
 750         return count;
 751 }
 752
 753 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
 754                                      struct device_attribute *attr,
 755                                      char *buf)
 756 {
 757         struct amdgpu_device *adev = dev_get_drvdata(dev);
 758         int err;
 759         u32 speed;
 760
 761         err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
 762         if (err)
 763                 return err;
 764
 765         speed = (speed * 255) / 100;
 766
 767         return sprintf(buf, "%i\n", speed);
 768 }
 769
 770 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
 771                                            struct device_attribute *attr,
 772                                            char *buf)
 773 {
 774         struct amdgpu_device *adev = dev_get_drvdata(dev);
 775         int err;
 776         u32 speed;
 777
 778         err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
 779         if (err)
 780                 return err;
 781
 782         return sprintf(buf, "%i\n", speed);
 783 }
 784
 785 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
 786 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
 787 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
 788 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
 789 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
 790 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
 791 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
 792 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
 793
 794 static struct attribute *hwmon_attributes[] = {
 795         &sensor_dev_attr_temp1_input.dev_attr.attr,
 796         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 797         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
 798         &sensor_dev_attr_pwm1.dev_attr.attr,
 799         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
 800         &sensor_dev_attr_pwm1_min.dev_attr.attr,
 801         &sensor_dev_attr_pwm1_max.dev_attr.attr,
 802         &sensor_dev_attr_fan1_input.dev_attr.attr,
 803         NULL
 804 };
 805
 806 static umode_t hwmon_attributes_visible(struct kobject *kobj,
 807                                         struct attribute *attr, int index)
 808 {
 809         struct device *dev = kobj_to_dev(kobj);
 810         struct amdgpu_device *adev = dev_get_drvdata(dev);
 811         umode_t effective_mode = attr->mode;
 812
 813         /* Skip limit attributes if DPM is not enabled */
 814         if (!adev->pm.dpm_enabled &&
 815             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
 816              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
 817              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 818              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 819              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 820              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 821                 return 0;
 822
 823         if (adev->pp_enabled)
 824                 return effective_mode;
 825
 826         /* Skip fan attributes if fan is not present */
 827         if (adev->pm.no_fan &&
 828             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 829              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 830              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 831              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 832                 return 0;
 833
 834         /* mask fan attributes if we have no bindings for this asic to expose */
 835         if ((!adev->pm.funcs->get_fan_speed_percent &&
 836              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
 837             (!adev->pm.funcs->get_fan_control_mode &&
 838              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
 839                 effective_mode &= ~S_IRUGO;
 840
 841         if ((!adev->pm.funcs->set_fan_speed_percent &&
 842              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
 843             (!adev->pm.funcs->set_fan_control_mode &&
 844              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
 845                 effective_mode &= ~S_IWUSR;
 846
 847         /* hide max/min values if we can't both query and manage the fan */
 848         if ((!adev->pm.funcs->set_fan_speed_percent &&
 849              !adev->pm.funcs->get_fan_speed_percent) &&
 850             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 851              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 852                 return 0;
 853
 854         /* requires powerplay */
 855         if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
 856                 return 0;
 857
 858         return effective_mode;
 859 }
 860
 861 static const struct attribute_group hwmon_attrgroup = {
 862         .attrs = hwmon_attributes,
 863         .is_visible = hwmon_attributes_visible,
 864 };
 865
 866 static const struct attribute_group *hwmon_groups[] = {
 867         &hwmon_attrgroup,
 868         NULL
 869 };
 870
 871 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
 872 {
 873         struct amdgpu_device *adev =
 874                 container_of(work, struct amdgpu_device,
 875                              pm.dpm.thermal.work);
 876         /* switch to the thermal state */
 877         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
 878
 879         if (!adev->pm.dpm_enabled)
 880                 return;
 881
 882         if (adev->pm.funcs->get_temperature) {
 883                 int temp = amdgpu_dpm_get_temperature(adev);
 884
 885                 if (temp < adev->pm.dpm.thermal.min_temp)
 886                         /* switch back the user state */
 887                         dpm_state = adev->pm.dpm.user_state;
 888         } else {
 889                 if (adev->pm.dpm.thermal.high_to_low)
 890                         /* switch back the user state */
 891                         dpm_state = adev->pm.dpm.user_state;
 892         }
 893         mutex_lock(&adev->pm.mutex);
 894         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
 895                 adev->pm.dpm.thermal_active = true;
 896         else
 897                 adev->pm.dpm.thermal_active = false;
 898         adev->pm.dpm.state = dpm_state;
 899         mutex_unlock(&adev->pm.mutex);
 900
 901         amdgpu_pm_compute_clocks(adev);
 902 }
 903
 904 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
 905                                                      enum amd_pm_state_type dpm_state)
 906 {
 907         int i;
 908         struct amdgpu_ps *ps;
 909         u32 ui_class;
 910         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
 911                 true : false;
 912
 913         /* check if the vblank period is too short to adjust the mclk */
 914         if (single_display && adev->pm.funcs->vblank_too_short) {
 915                 if (amdgpu_dpm_vblank_too_short(adev))
 916                         single_display = false;
 917         }
 918
 919         /* certain older asics have a separare 3D performance state,
 920          * so try that first if the user selected performance
 921          */
 922         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
 923                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
 924         /* balanced states don't exist at the moment */
 925         if (dpm_state == POWER_STATE_TYPE_BALANCED)
 926                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 927
 928 restart_search:
 929         /* Pick the best power state based on current conditions */
 930         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
 931                 ps = &adev->pm.dpm.ps[i];
 932                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
 933                 switch (dpm_state) {
 934                 /* user states */
 935                 case POWER_STATE_TYPE_BATTERY:
 936                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
 937                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 938                                         if (single_display)
 939                                                 return ps;
 940                                 } else
 941                                         return ps;
 942                         }
 943                         break;
 944                 case POWER_STATE_TYPE_BALANCED:
 945                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
 946                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 947                                         if (single_display)
 948                                                 return ps;
 949                                 } else
 950                                         return ps;
 951                         }
 952                         break;
 953                 case POWER_STATE_TYPE_PERFORMANCE:
 954                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
 955                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 956                                         if (single_display)
 957                                                 return ps;
 958                                 } else
 959                                         return ps;
 960                         }
 961                         break;
 962                 /* internal states */
 963                 case POWER_STATE_TYPE_INTERNAL_UVD:
 964                         if (adev->pm.dpm.uvd_ps)
 965                                 return adev->pm.dpm.uvd_ps;
 966                         else
 967                                 break;
 968                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 969                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
 970                                 return ps;
 971                         break;
 972                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 973                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
 974                                 return ps;
 975                         break;
 976                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 977                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
 978                                 return ps;
 979                         break;
 980                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 981                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
 982                                 return ps;
 983                         break;
 984                 case POWER_STATE_TYPE_INTERNAL_BOOT:
 985                         return adev->pm.dpm.boot_ps;
 986                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
 987                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
 988                                 return ps;
 989                         break;
 990                 case POWER_STATE_TYPE_INTERNAL_ACPI:
 991                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
 992                                 return ps;
 993                         break;
 994                 case POWER_STATE_TYPE_INTERNAL_ULV:
 995                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
 996                                 return ps;
 997                         break;
 998                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
 999                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1000                                 return ps;
1001                         break;
1002                 default:
1003                         break;
1004                 }
1005         }
1006         /* use a fallback state if we didn't match */
1007         switch (dpm_state) {
1008         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1009                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1010                 goto restart_search;
1011         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1012         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1013         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1014                 if (adev->pm.dpm.uvd_ps) {
1015                         return adev->pm.dpm.uvd_ps;
1016                 } else {
1017                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1018                         goto restart_search;
1019                 }
1020         case POWER_STATE_TYPE_INTERNAL_THERMAL:
1021                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1022                 goto restart_search;
1023         case POWER_STATE_TYPE_INTERNAL_ACPI:
1024                 dpm_state = POWER_STATE_TYPE_BATTERY;
1025                 goto restart_search;
1026         case POWER_STATE_TYPE_BATTERY:
1027         case POWER_STATE_TYPE_BALANCED:
1028         case POWER_STATE_TYPE_INTERNAL_3DPERF:
1029                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1030                 goto restart_search;
1031         default:
1032                 break;
1033         }
1034
1035         return NULL;
1036 }
1037
1038 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1039 {
1040         struct amdgpu_ps *ps;
1041         enum amd_pm_state_type dpm_state;
1042         int ret;
1043         bool equal;
1044
1045         /* if dpm init failed */
1046         if (!adev->pm.dpm_enabled)
1047                 return;
1048
1049         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1050                 /* add other state override checks here */
1051                 if ((!adev->pm.dpm.thermal_active) &&
1052                     (!adev->pm.dpm.uvd_active))
1053                         adev->pm.dpm.state = adev->pm.dpm.user_state;
1054         }
1055         dpm_state = adev->pm.dpm.state;
1056
1057         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1058         if (ps)
1059                 adev->pm.dpm.requested_ps = ps;
1060         else
1061                 return;
1062
1063         if (amdgpu_dpm == 1) {
1064                 printk("switching from power state:\n");
1065                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1066                 printk("switching to power state:\n");
1067                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1068         }
1069
1070         /* update whether vce is active */
1071         ps->vce_active = adev->pm.dpm.vce_active;
1072
1073         amdgpu_dpm_display_configuration_changed(adev);
1074
1075         ret = amdgpu_dpm_pre_set_power_state(adev);
1076         if (ret)
1077                 return;
1078
1079         if ((0 != amgdpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal)))
1080                 equal = false;
1081
1082         if (equal)
1083                 return;
1084
1085         amdgpu_dpm_set_power_state(adev);
1086         amdgpu_dpm_post_set_power_state(adev);
1087
1088         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1089         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1090
1091         if (adev->pm.funcs->force_performance_level) {
1092                 if (adev->pm.dpm.thermal_active) {
1093                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1094                         /* force low perf level for thermal */
1095                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1096                         /* save the user's level */
1097                         adev->pm.dpm.forced_level = level;
1098                 } else {
1099                         /* otherwise, user selected level */
1100                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1101                 }
1102         }
1103 }
1104
1105 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1106 {
1107         if (adev->pp_enabled || adev->pm.funcs->powergate_uvd) {
1108                 /* enable/disable UVD */
1109                 mutex_lock(&adev->pm.mutex);
1110                 amdgpu_dpm_powergate_uvd(adev, !enable);
1111                 mutex_unlock(&adev->pm.mutex);
1112         } else {
1113                 if (enable) {
1114                         mutex_lock(&adev->pm.mutex);
1115                         adev->pm.dpm.uvd_active = true;
1116                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1117                         mutex_unlock(&adev->pm.mutex);
1118                 } else {
1119                         mutex_lock(&adev->pm.mutex);
1120                         adev->pm.dpm.uvd_active = false;
1121                         mutex_unlock(&adev->pm.mutex);
1122                 }
1123                 amdgpu_pm_compute_clocks(adev);
1124         }
1125 }
1126
1127 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1128 {
1129         if (adev->pp_enabled || adev->pm.funcs->powergate_vce) {
1130                 /* enable/disable VCE */
1131                 mutex_lock(&adev->pm.mutex);
1132                 amdgpu_dpm_powergate_vce(adev, !enable);
1133                 mutex_unlock(&adev->pm.mutex);
1134         } else {
1135                 if (enable) {
1136                         mutex_lock(&adev->pm.mutex);
1137                         adev->pm.dpm.vce_active = true;
1138                         /* XXX select vce level based on ring/task */
1139                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1140                         mutex_unlock(&adev->pm.mutex);
1141                 } else {
1142                         mutex_lock(&adev->pm.mutex);
1143                         adev->pm.dpm.vce_active = false;
1144                         mutex_unlock(&adev->pm.mutex);
1145                 }
1146                 amdgpu_pm_compute_clocks(adev);
1147         }
1148 }
1149
1150 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1151 {
1152         int i;
1153
1154         if (adev->pp_enabled)
1155                 /* TO DO */
1156                 return;
1157
1158         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1159                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1160
1161 }
1162
1163 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1164 {
1165         int ret;
1166
1167         if (adev->pm.sysfs_initialized)
1168                 return 0;
1169
1170         if (!adev->pp_enabled) {
1171                 if (adev->pm.funcs->get_temperature == NULL)
1172                         return 0;
1173         }
1174
1175         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1176                                                                    DRIVER_NAME, adev,
1177                                                                    hwmon_groups);
1178         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1179                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1180                 dev_err(adev->dev,
1181                         "Unable to register hwmon device: %d\n", ret);
1182                 return ret;
1183         }
1184
1185         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1186         if (ret) {
1187                 DRM_ERROR("failed to create device file for dpm state\n");
1188                 return ret;
1189         }
1190         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1191         if (ret) {
1192                 DRM_ERROR("failed to create device file for dpm state\n");
1193                 return ret;
1194         }
1195
1196         if (adev->pp_enabled) {
1197                 ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1198                 if (ret) {
1199                         DRM_ERROR("failed to create device file pp_num_states\n");
1200                         return ret;
1201                 }
1202                 ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1203                 if (ret) {
1204                         DRM_ERROR("failed to create device file pp_cur_state\n");
1205                         return ret;
1206                 }
1207                 ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1208                 if (ret) {
1209                         DRM_ERROR("failed to create device file pp_force_state\n");
1210                         return ret;
1211                 }
1212                 ret = device_create_file(adev->dev, &dev_attr_pp_table);
1213                 if (ret) {
1214                         DRM_ERROR("failed to create device file pp_table\n");
1215                         return ret;
1216                 }
1217         }
1218
1219         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1220         if (ret) {
1221                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1222                 return ret;
1223         }
1224         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1225         if (ret) {
1226                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1227                 return ret;
1228         }
1229         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1230         if (ret) {
1231                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1232                 return ret;
1233         }
1234         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1235         if (ret) {
1236                 DRM_ERROR("failed to create device file pp_sclk_od\n");
1237                 return ret;
1238         }
1239         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1240         if (ret) {
1241                 DRM_ERROR("failed to create device file pp_mclk_od\n");
1242                 return ret;
1243         }
1244
1245         ret = amdgpu_debugfs_pm_init(adev);
1246         if (ret) {
1247                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1248                 return ret;
1249         }
1250
1251         adev->pm.sysfs_initialized = true;
1252
1253         return 0;
1254 }
1255
1256 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1257 {
1258         if (adev->pm.int_hwmon_dev)
1259                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1260         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1261         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1262         if (adev->pp_enabled) {
1263                 device_remove_file(adev->dev, &dev_attr_pp_num_states);
1264                 device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1265                 device_remove_file(adev->dev, &dev_attr_pp_force_state);
1266                 device_remove_file(adev->dev, &dev_attr_pp_table);
1267         }
1268         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1269         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1270         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1271         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1272         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1273 }
1274
1275 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1276 {
1277         struct drm_device *ddev = adev->ddev;
1278         struct drm_crtc *crtc;
1279         struct amdgpu_crtc *amdgpu_crtc;
1280         int i = 0;
1281
1282         if (!adev->pm.dpm_enabled)
1283                 return;
1284
1285         amdgpu_display_bandwidth_update(adev);
1286
1287         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1288                 struct amdgpu_ring *ring = adev->rings[i];
1289                 if (ring && ring->ready)
1290                         amdgpu_fence_wait_empty(ring);
1291         }
1292
1293         if (adev->pp_enabled) {
1294                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, NULL, NULL);
1295         } else {
1296                 mutex_lock(&adev->pm.mutex);
1297                 adev->pm.dpm.new_active_crtcs = 0;
1298                 adev->pm.dpm.new_active_crtc_count = 0;
1299                 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
1300                         list_for_each_entry(crtc,
1301                                             &ddev->mode_config.crtc_list, head) {
1302                                 amdgpu_crtc = to_amdgpu_crtc(crtc);
1303                                 if (crtc->enabled) {
1304                                         adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
1305                                         adev->pm.dpm.new_active_crtc_count++;
1306                                 }
1307                         }
1308                 }
1309                 /* update battery/ac status */
1310                 if (power_supply_is_system_supplied() > 0)
1311                         adev->pm.dpm.ac_power = true;
1312                 else
1313                         adev->pm.dpm.ac_power = false;
1314
1315                 amdgpu_dpm_change_power_state_locked(adev);
1316
1317                 mutex_unlock(&adev->pm.mutex);
1318         }
1319 }
1320
1321 /*
1322  * Debugfs info
1323  */
1324 #if defined(CONFIG_DEBUG_FS)
1325
1326 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1327 {
1328         int32_t value;
1329
1330         /* sanity check PP is enabled */
1331         if (!(adev->powerplay.pp_funcs &&
1332               adev->powerplay.pp_funcs->read_sensor))
1333               return -EINVAL;
1334
1335         /* GPU Clocks */
1336         seq_printf(m, "GFX Clocks and Power:\n");
1337         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, &value))
1338                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
1339         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, &value))
1340                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
1341         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, &value))
1342                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1343         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, &value))
1344                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1345         seq_printf(m, "\n");
1346
1347         /* GPU Temp */
1348         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, &value))
1349                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
1350
1351         /* GPU Load */
1352         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value))
1353                 seq_printf(m, "GPU Load: %u %%\n", value);
1354         seq_printf(m, "\n");
1355
1356         /* UVD clocks */
1357         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, &value)) {
1358                 if (!value) {
1359                         seq_printf(m, "UVD: Disabled\n");
1360                 } else {
1361                         seq_printf(m, "UVD: Enabled\n");
1362                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, &value))
1363                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
1364                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, &value))
1365                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
1366                 }
1367         }
1368         seq_printf(m, "\n");
1369
1370         /* VCE clocks */
1371         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, &value)) {
1372                 if (!value) {
1373                         seq_printf(m, "VCE: Disabled\n");
1374                 } else {
1375                         seq_printf(m, "VCE: Enabled\n");
1376                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, &value))
1377                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
1378                 }
1379         }
1380
1381         return 0;
1382 }
1383
1384 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
1385 {
1386         int i;
1387
1388         for (i = 0; clocks[i].flag; i++)
1389                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
1390                            (flags & clocks[i].flag) ? "On" : "Off");
1391 }
1392
1393 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1394 {
1395         struct drm_info_node *node = (struct drm_info_node *) m->private;
1396         struct drm_device *dev = node->minor->dev;
1397         struct amdgpu_device *adev = dev->dev_private;
1398         struct drm_device *ddev = adev->ddev;
1399         u32 flags = 0;
1400
1401         amdgpu_get_clockgating_state(adev, &flags);
1402         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
1403         amdgpu_parse_cg_state(m, flags);
1404         seq_printf(m, "\n");
1405
1406         if (!adev->pm.dpm_enabled) {
1407                 seq_printf(m, "dpm not enabled\n");
1408                 return 0;
1409         }
1410         if  ((adev->flags & AMD_IS_PX) &&
1411              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1412                 seq_printf(m, "PX asic powered off\n");
1413         } else if (adev->pp_enabled) {
1414                 return amdgpu_debugfs_pm_info_pp(m, adev);
1415         } else {
1416                 mutex_lock(&adev->pm.mutex);
1417                 if (adev->pm.funcs->debugfs_print_current_performance_level)
1418                         adev->pm.funcs->debugfs_print_current_performance_level(adev, m);
1419                 else
1420                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1421                 mutex_unlock(&adev->pm.mutex);
1422         }
1423
1424         return 0;
1425 }
1426
1427 static const struct drm_info_list amdgpu_pm_info_list[] = {
1428         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
1429 };
1430 #endif
1431
1432 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
1433 {
1434 #if defined(CONFIG_DEBUG_FS)
1435         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
1436 #else
1437         return 0;
1438 #endif
1439 }