drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include "drmP.h"
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v3_1.h"
  33
  34 static void psp_set_funcs(struct amdgpu_device *adev);
  35
  36 static int psp_early_init(void *handle)
  37 {
  38         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  39
  40         psp_set_funcs(adev);
  41
  42         return 0;
  43 }
  44
  45 static int psp_sw_init(void *handle)
  46 {
  47         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  48         struct psp_context *psp = &adev->psp;
  49         int ret;
  50
  51         switch (adev->asic_type) {
  52         case CHIP_VEGA10:
  53                 psp->init_microcode = psp_v3_1_init_microcode;
  54                 psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
  55                 psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
  56                 psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
  57                 psp->ring_init = psp_v3_1_ring_init;
  58                 psp->ring_create = psp_v3_1_ring_create;
  59                 psp->ring_destroy = psp_v3_1_ring_destroy;
  60                 psp->cmd_submit = psp_v3_1_cmd_submit;
  61                 psp->compare_sram_data = psp_v3_1_compare_sram_data;
  62                 psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
  63                 break;
  64         default:
  65                 return -EINVAL;
  66         }
  67
  68         psp->adev = adev;
  69
  70         ret = psp_init_microcode(psp);
  71         if (ret) {
  72                 DRM_ERROR("Failed to load psp firmware!\n");
  73                 return ret;
  74         }
  75
  76         return 0;
  77 }
  78
  79 static int psp_sw_fini(void *handle)
  80 {
  81         return 0;
  82 }
  83
  84 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
  85                  uint32_t reg_val, uint32_t mask, bool check_changed)
  86 {
  87         uint32_t val;
  88         int i;
  89         struct amdgpu_device *adev = psp->adev;
  90
  91         val = RREG32(reg_index);
  92
  93         for (i = 0; i < adev->usec_timeout; i++) {
  94                 if (check_changed) {
  95                         if (val != reg_val)
  96                                 return 0;
  97                 } else {
  98                         if ((val & mask) == reg_val)
  99                                 return 0;
 100                 }
 101                 udelay(1);
 102         }
 103
 104         return -ETIME;
 105 }
 106
 107 static int
 108 psp_cmd_submit_buf(struct psp_context *psp,
 109                    struct amdgpu_firmware_info *ucode,
 110                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
 111                    int index)
 112 {
 113         int ret;
 114         struct amdgpu_bo *cmd_buf_bo;
 115         uint64_t cmd_buf_mc_addr;
 116         struct psp_gfx_cmd_resp *cmd_buf_mem;
 117         struct amdgpu_device *adev = psp->adev;
 118
 119         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 120                                       AMDGPU_GEM_DOMAIN_VRAM,
 121                                       &cmd_buf_bo, &cmd_buf_mc_addr,
 122                                       (void **)&cmd_buf_mem);
 123         if (ret)
 124                 return ret;
 125
 126         memset(cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 127
 128         memcpy(cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 129
 130         ret = psp_cmd_submit(psp, ucode, cmd_buf_mc_addr,
 131                              fence_mc_addr, index);
 132
 133         while (*((unsigned int *)psp->fence_buf) != index) {
 134                 msleep(1);
 135         }
 136
 137         amdgpu_bo_free_kernel(&cmd_buf_bo,
 138                               &cmd_buf_mc_addr,
 139                               (void **)&cmd_buf_mem);
 140
 141         return ret;
 142 }
 143
 144 static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 145                                  uint64_t tmr_mc, uint32_t size)
 146 {
 147         cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 148         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = (uint32_t)tmr_mc;
 149         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = (uint32_t)(tmr_mc >> 32);
 150         cmd->cmd.cmd_setup_tmr.buf_size = size;
 151 }
 152
 153 /* Set up Trusted Memory Region */
 154 static int psp_tmr_init(struct psp_context *psp)
 155 {
 156         int ret;
 157
 158         /*
 159          * Allocate 3M memory aligned to 1M from Frame Buffer (local
 160          * physical).
 161          *
 162          * Note: this memory need be reserved till the driver
 163          * uninitializes.
 164          */
 165         ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
 166                                       AMDGPU_GEM_DOMAIN_VRAM,
 167                                       &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 168
 169         return ret;
 170 }
 171
 172 static int psp_tmr_load(struct psp_context *psp)
 173 {
 174         int ret;
 175         struct psp_gfx_cmd_resp *cmd;
 176
 177         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 178         if (!cmd)
 179                 return -ENOMEM;
 180
 181         psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
 182
 183         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 184                                  psp->fence_buf_mc_addr, 1);
 185         if (ret)
 186                 goto failed;
 187
 188         kfree(cmd);
 189
 190         return 0;
 191
 192 failed:
 193         kfree(cmd);
 194         return ret;
 195 }
 196
 197 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 198                                  uint64_t asd_mc, uint64_t asd_mc_shared,
 199                                  uint32_t size, uint32_t shared_size)
 200 {
 201         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 202         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 203         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 204         cmd->cmd.cmd_load_ta.app_len = size;
 205
 206         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
 207         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
 208         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 209 }
 210
 211 static int psp_asd_init(struct psp_context *psp)
 212 {
 213         int ret;
 214
 215         /*
 216          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 217          * physical) for shared ASD <-> Driver
 218          */
 219         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
 220                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 221                                       &psp->asd_shared_bo,
 222                                       &psp->asd_shared_mc_addr,
 223                                       &psp->asd_shared_buf);
 224
 225         return ret;
 226 }
 227
 228 static int psp_asd_load(struct psp_context *psp)
 229 {
 230         int ret;
 231         struct psp_gfx_cmd_resp *cmd;
 232
 233         /* If PSP version doesn't match ASD version, asd loading will be failed.
 234          * add workaround to bypass it for sriov now.
 235          * TODO: add version check to make it common
 236          */
 237         if (amdgpu_sriov_vf(psp->adev))
 238                 return 0;
 239
 240         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 241         if (!cmd)
 242                 return -ENOMEM;
 243
 244         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 245         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 246
 247         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
 248                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
 249
 250         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 251                                  psp->fence_buf_mc_addr, 2);
 252
 253         kfree(cmd);
 254
 255         return ret;
 256 }
 257
 258 static int psp_hw_start(struct psp_context *psp)
 259 {
 260         int ret;
 261
 262         ret = psp_bootloader_load_sysdrv(psp);
 263         if (ret)
 264                 return ret;
 265
 266         ret = psp_bootloader_load_sos(psp);
 267         if (ret)
 268                 return ret;
 269
 270         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
 271         if (ret)
 272                 return ret;
 273
 274         ret = psp_tmr_load(psp);
 275         if (ret)
 276                 return ret;
 277
 278         ret = psp_asd_load(psp);
 279         if (ret)
 280                 return ret;
 281
 282         return 0;
 283 }
 284
 285 static int psp_np_fw_load(struct psp_context *psp)
 286 {
 287         int i, ret;
 288         struct amdgpu_firmware_info *ucode;
 289         struct amdgpu_device* adev = psp->adev;
 290
 291         for (i = 0; i < adev->firmware.max_ucodes; i++) {
 292                 ucode = &adev->firmware.ucode[i];
 293                 if (!ucode->fw)
 294                         continue;
 295
 296                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
 297                     psp_smu_reload_quirk(psp))
 298                         continue;
 299                 if (amdgpu_sriov_vf(adev) &&
 300                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
 301                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
 302                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
 303                         /*skip ucode loading in SRIOV VF */
 304                         continue;
 305
 306                 ret = psp_prep_cmd_buf(ucode, psp->cmd);
 307                 if (ret)
 308                         return ret;
 309
 310                 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
 311                                          psp->fence_buf_mc_addr, i + 3);
 312                 if (ret)
 313                         return ret;
 314
 315 #if 0
 316                 /* check if firmware loaded sucessfully */
 317                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
 318                         return -EINVAL;
 319 #endif
 320         }
 321
 322         return 0;
 323 }
 324
 325 static int psp_load_fw(struct amdgpu_device *adev)
 326 {
 327         int ret;
 328         struct psp_context *psp = &adev->psp;
 329         struct psp_gfx_cmd_resp *cmd;
 330
 331         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 332         if (!cmd)
 333                 return -ENOMEM;
 334
 335         psp->cmd = cmd;
 336
 337         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 338                                       AMDGPU_GEM_DOMAIN_GTT,
 339                                       &psp->fw_pri_bo,
 340                                       &psp->fw_pri_mc_addr,
 341                                       &psp->fw_pri_buf);
 342         if (ret)
 343                 goto failed;
 344
 345         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 346                                       AMDGPU_GEM_DOMAIN_VRAM,
 347                                       &psp->fence_buf_bo,
 348                                       &psp->fence_buf_mc_addr,
 349                                       &psp->fence_buf);
 350         if (ret)
 351                 goto failed_mem1;
 352
 353         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
 354
 355         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
 356         if (ret)
 357                 goto failed_mem1;
 358
 359         ret = psp_tmr_init(psp);
 360         if (ret)
 361                 goto failed_mem;
 362
 363         ret = psp_asd_init(psp);
 364         if (ret)
 365                 goto failed_mem;
 366
 367         ret = psp_hw_start(psp);
 368         if (ret)
 369                 goto failed_mem;
 370
 371         ret = psp_np_fw_load(psp);
 372         if (ret)
 373                 goto failed_mem;
 374
 375         kfree(cmd);
 376
 377         return 0;
 378
 379 failed_mem:
 380         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 381                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 382 failed_mem1:
 383         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 384                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 385 failed:
 386         kfree(cmd);
 387         return ret;
 388 }
 389
 390 static int psp_hw_init(void *handle)
 391 {
 392         int ret;
 393         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 394
 395
 396         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 397                 return 0;
 398
 399         mutex_lock(&adev->firmware.mutex);
 400         /*
 401          * This sequence is just used on hw_init only once, no need on
 402          * resume.
 403          */
 404         ret = amdgpu_ucode_init_bo(adev);
 405         if (ret)
 406                 goto failed;
 407
 408         ret = psp_load_fw(adev);
 409         if (ret) {
 410                 DRM_ERROR("PSP firmware loading failed\n");
 411                 goto failed;
 412         }
 413
 414         mutex_unlock(&adev->firmware.mutex);
 415         return 0;
 416
 417 failed:
 418         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
 419         mutex_unlock(&adev->firmware.mutex);
 420         return -EINVAL;
 421 }
 422
 423 static int psp_hw_fini(void *handle)
 424 {
 425         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 426         struct psp_context *psp = &adev->psp;
 427
 428         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 429                 return 0;
 430
 431         amdgpu_ucode_fini_bo(adev);
 432
 433         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 434
 435         if (psp->tmr_buf)
 436                 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 437
 438         if (psp->fw_pri_buf)
 439                 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 440                                       &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 441
 442         if (psp->fence_buf_bo)
 443                 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 444                                       &psp->fence_buf_mc_addr, &psp->fence_buf);
 445
 446         return 0;
 447 }
 448
 449 static int psp_suspend(void *handle)
 450 {
 451         return 0;
 452 }
 453
 454 static int psp_resume(void *handle)
 455 {
 456         int ret;
 457         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 458         struct psp_context *psp = &adev->psp;
 459
 460         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 461                 return 0;
 462
 463         DRM_INFO("PSP is resuming...\n");
 464
 465         mutex_lock(&adev->firmware.mutex);
 466
 467         ret = psp_hw_start(psp);
 468         if (ret)
 469                 goto failed;
 470
 471         ret = psp_np_fw_load(psp);
 472         if (ret)
 473                 goto failed;
 474
 475         mutex_unlock(&adev->firmware.mutex);
 476
 477         return 0;
 478
 479 failed:
 480         DRM_ERROR("PSP resume failed\n");
 481         mutex_unlock(&adev->firmware.mutex);
 482         return ret;
 483 }
 484
 485 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
 486                                         enum AMDGPU_UCODE_ID ucode_type)
 487 {
 488         struct amdgpu_firmware_info *ucode = NULL;
 489
 490         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 491                 DRM_INFO("firmware is not loaded by PSP\n");
 492                 return true;
 493         }
 494
 495         if (!adev->firmware.fw_size)
 496                 return false;
 497
 498         ucode = &adev->firmware.ucode[ucode_type];
 499         if (!ucode->fw || !ucode->ucode_size)
 500                 return false;
 501
 502         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
 503 }
 504
 505 static int psp_set_clockgating_state(void *handle,
 506                                      enum amd_clockgating_state state)
 507 {
 508         return 0;
 509 }
 510
 511 static int psp_set_powergating_state(void *handle,
 512                                      enum amd_powergating_state state)
 513 {
 514         return 0;
 515 }
 516
 517 const struct amd_ip_funcs psp_ip_funcs = {
 518         .name = "psp",
 519         .early_init = psp_early_init,
 520         .late_init = NULL,
 521         .sw_init = psp_sw_init,
 522         .sw_fini = psp_sw_fini,
 523         .hw_init = psp_hw_init,
 524         .hw_fini = psp_hw_fini,
 525         .suspend = psp_suspend,
 526         .resume = psp_resume,
 527         .is_idle = NULL,
 528         .wait_for_idle = NULL,
 529         .soft_reset = NULL,
 530         .set_clockgating_state = psp_set_clockgating_state,
 531         .set_powergating_state = psp_set_powergating_state,
 532 };
 533
 534 static const struct amdgpu_psp_funcs psp_funcs = {
 535         .check_fw_loading_status = psp_check_fw_loading_status,
 536 };
 537
 538 static void psp_set_funcs(struct amdgpu_device *adev)
 539 {
 540         if (NULL == adev->firmware.funcs)
 541                 adev->firmware.funcs = &psp_funcs;
 542 }
 543
 544 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
 545 {
 546         .type = AMD_IP_BLOCK_TYPE_PSP,
 547         .major = 3,
 548         .minor = 1,
 549         .rev = 0,
 550         .funcs = &psp_ip_funcs,
 551 };