2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/firmware.h>
29 #include "amdgpu_psp.h"
30 #include "amdgpu_ucode.h"
31 #include "soc15_common.h"
34 static void psp_set_funcs(struct amdgpu_device *adev);
36 static int psp_early_init(void *handle)
38 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
45 static int psp_sw_init(void *handle)
47 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
48 struct psp_context *psp = &adev->psp;
51 switch (adev->asic_type) {
53 psp->init_microcode = psp_v3_1_init_microcode;
54 psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
55 psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
56 psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
57 psp->ring_init = psp_v3_1_ring_init;
58 psp->ring_create = psp_v3_1_ring_create;
59 psp->ring_destroy = psp_v3_1_ring_destroy;
60 psp->cmd_submit = psp_v3_1_cmd_submit;
61 psp->compare_sram_data = psp_v3_1_compare_sram_data;
62 psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
70 ret = psp_init_microcode(psp);
72 DRM_ERROR("Failed to load psp firmware!\n");
79 static int psp_sw_fini(void *handle)
84 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
85 uint32_t reg_val, uint32_t mask, bool check_changed)
89 struct amdgpu_device *adev = psp->adev;
91 val = RREG32(reg_index);
93 for (i = 0; i < adev->usec_timeout; i++) {
98 if ((val & mask) == reg_val)
108 psp_cmd_submit_buf(struct psp_context *psp,
109 struct amdgpu_firmware_info *ucode,
110 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
114 struct amdgpu_bo *cmd_buf_bo;
115 uint64_t cmd_buf_mc_addr;
116 struct psp_gfx_cmd_resp *cmd_buf_mem;
117 struct amdgpu_device *adev = psp->adev;
119 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
120 AMDGPU_GEM_DOMAIN_VRAM,
121 &cmd_buf_bo, &cmd_buf_mc_addr,
122 (void **)&cmd_buf_mem);
126 memset(cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
128 memcpy(cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
130 ret = psp_cmd_submit(psp, ucode, cmd_buf_mc_addr,
131 fence_mc_addr, index);
133 while (*((unsigned int *)psp->fence_buf) != index) {
137 amdgpu_bo_free_kernel(&cmd_buf_bo,
139 (void **)&cmd_buf_mem);
144 static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
145 uint64_t tmr_mc, uint32_t size)
147 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
148 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = (uint32_t)tmr_mc;
149 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = (uint32_t)(tmr_mc >> 32);
150 cmd->cmd.cmd_setup_tmr.buf_size = size;
153 /* Set up Trusted Memory Region */
154 static int psp_tmr_init(struct psp_context *psp)
159 * Allocate 3M memory aligned to 1M from Frame Buffer (local
162 * Note: this memory need be reserved till the driver
165 ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
166 AMDGPU_GEM_DOMAIN_VRAM,
167 &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
172 static int psp_tmr_load(struct psp_context *psp)
175 struct psp_gfx_cmd_resp *cmd;
177 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
181 psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
183 ret = psp_cmd_submit_buf(psp, NULL, cmd,
184 psp->fence_buf_mc_addr, 1);
197 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
198 uint64_t asd_mc, uint64_t asd_mc_shared,
199 uint32_t size, uint32_t shared_size)
201 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
202 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
203 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
204 cmd->cmd.cmd_load_ta.app_len = size;
206 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
207 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
208 cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
211 static int psp_asd_init(struct psp_context *psp)
216 * Allocate 16k memory aligned to 4k from Frame Buffer (local
217 * physical) for shared ASD <-> Driver
219 ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
220 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
222 &psp->asd_shared_mc_addr,
223 &psp->asd_shared_buf);
228 static int psp_asd_load(struct psp_context *psp)
231 struct psp_gfx_cmd_resp *cmd;
233 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
237 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
238 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
240 psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
241 psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
243 ret = psp_cmd_submit_buf(psp, NULL, cmd,
244 psp->fence_buf_mc_addr, 2);
251 static int psp_hw_start(struct psp_context *psp)
255 ret = psp_bootloader_load_sysdrv(psp);
259 ret = psp_bootloader_load_sos(psp);
263 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
267 ret = psp_tmr_load(psp);
271 ret = psp_asd_load(psp);
278 static int psp_np_fw_load(struct psp_context *psp)
281 struct amdgpu_firmware_info *ucode;
282 struct amdgpu_device* adev = psp->adev;
284 for (i = 0; i < adev->firmware.max_ucodes; i++) {
285 ucode = &adev->firmware.ucode[i];
289 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
290 psp_smu_reload_quirk(psp))
292 if (amdgpu_sriov_vf(adev) &&
293 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
294 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
295 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
296 /*skip ucode loading in SRIOV VF */
299 ret = psp_prep_cmd_buf(ucode, psp->cmd);
303 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
304 psp->fence_buf_mc_addr, i + 3);
309 /* check if firmware loaded sucessfully */
310 if (!amdgpu_psp_check_fw_loading_status(adev, i))
318 static int psp_load_fw(struct amdgpu_device *adev)
321 struct psp_context *psp = &adev->psp;
322 struct psp_gfx_cmd_resp *cmd;
324 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
330 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
331 AMDGPU_GEM_DOMAIN_GTT,
333 &psp->fw_pri_mc_addr,
338 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
339 AMDGPU_GEM_DOMAIN_VRAM,
341 &psp->fence_buf_mc_addr,
346 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
348 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
352 ret = psp_tmr_init(psp);
356 ret = psp_asd_init(psp);
360 ret = psp_hw_start(psp);
364 ret = psp_np_fw_load(psp);
373 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
374 &psp->fence_buf_mc_addr, &psp->fence_buf);
376 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
377 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
383 static int psp_hw_init(void *handle)
386 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
389 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
392 mutex_lock(&adev->firmware.mutex);
394 * This sequence is just used on hw_init only once, no need on
397 ret = amdgpu_ucode_init_bo(adev);
401 ret = psp_load_fw(adev);
403 DRM_ERROR("PSP firmware loading failed\n");
407 mutex_unlock(&adev->firmware.mutex);
411 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
412 mutex_unlock(&adev->firmware.mutex);
416 static int psp_hw_fini(void *handle)
418 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
419 struct psp_context *psp = &adev->psp;
421 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
424 amdgpu_ucode_fini_bo(adev);
426 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
429 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
432 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
433 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
435 if (psp->fence_buf_bo)
436 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
437 &psp->fence_buf_mc_addr, &psp->fence_buf);
442 static int psp_suspend(void *handle)
447 static int psp_resume(void *handle)
450 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
451 struct psp_context *psp = &adev->psp;
453 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
456 DRM_INFO("PSP is resuming...\n");
458 mutex_lock(&adev->firmware.mutex);
460 ret = psp_hw_start(psp);
464 ret = psp_np_fw_load(psp);
468 mutex_unlock(&adev->firmware.mutex);
473 DRM_ERROR("PSP resume failed\n");
474 mutex_unlock(&adev->firmware.mutex);
478 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
479 enum AMDGPU_UCODE_ID ucode_type)
481 struct amdgpu_firmware_info *ucode = NULL;
483 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
484 DRM_INFO("firmware is not loaded by PSP\n");
488 if (!adev->firmware.fw_size)
491 ucode = &adev->firmware.ucode[ucode_type];
492 if (!ucode->fw || !ucode->ucode_size)
495 return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
498 static int psp_set_clockgating_state(void *handle,
499 enum amd_clockgating_state state)
504 static int psp_set_powergating_state(void *handle,
505 enum amd_powergating_state state)
510 const struct amd_ip_funcs psp_ip_funcs = {
512 .early_init = psp_early_init,
514 .sw_init = psp_sw_init,
515 .sw_fini = psp_sw_fini,
516 .hw_init = psp_hw_init,
517 .hw_fini = psp_hw_fini,
518 .suspend = psp_suspend,
519 .resume = psp_resume,
521 .wait_for_idle = NULL,
523 .set_clockgating_state = psp_set_clockgating_state,
524 .set_powergating_state = psp_set_powergating_state,
527 static const struct amdgpu_psp_funcs psp_funcs = {
528 .check_fw_loading_status = psp_check_fw_loading_status,
531 static void psp_set_funcs(struct amdgpu_device *adev)
533 if (NULL == adev->firmware.funcs)
534 adev->firmware.funcs = &psp_funcs;
537 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
539 .type = AMD_IP_BLOCK_TYPE_PSP,
543 .funcs = &psp_ip_funcs,