2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Christian König
24 #ifndef __AMDGPU_RING_H__
25 #define __AMDGPU_RING_H__
27 #include "gpu_scheduler.h"
29 /* max number of rings */
30 #define AMDGPU_MAX_RINGS 18
31 #define AMDGPU_MAX_GFX_RINGS 1
32 #define AMDGPU_MAX_COMPUTE_RINGS 8
33 #define AMDGPU_MAX_VCE_RINGS 3
34 #define AMDGPU_MAX_UVD_ENC_RINGS 2
36 /* some special values for the owner field */
37 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
38 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
40 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
41 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
43 enum amdgpu_ring_type {
45 AMDGPU_RING_TYPE_COMPUTE,
46 AMDGPU_RING_TYPE_SDMA,
55 struct amdgpu_cs_parser;
60 struct amdgpu_fence_driver {
62 volatile uint32_t *cpu_addr;
63 /* sync_seq is protected by ring emission lock */
67 struct amdgpu_irq_src *irq_src;
69 struct timer_list fallback_timer;
70 unsigned num_fences_mask;
72 struct dma_fence **fences;
75 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
76 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
77 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
79 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
80 unsigned num_hw_submission);
81 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
82 struct amdgpu_irq_src *irq_src,
84 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
85 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
86 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence);
87 void amdgpu_fence_process(struct amdgpu_ring *ring);
88 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
89 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
95 /* provided by hw blocks that expose a ring buffer for commands */
96 struct amdgpu_ring_funcs {
97 enum amdgpu_ring_type type;
100 bool support_64bit_ptrs;
102 /* ring read/write ptr handling */
103 u64 (*get_rptr)(struct amdgpu_ring *ring);
104 u64 (*get_wptr)(struct amdgpu_ring *ring);
105 void (*set_wptr)(struct amdgpu_ring *ring);
106 /* validating and patching of IBs */
107 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
108 /* constants to calculate how many DW are needed for an emit */
109 unsigned emit_frame_size;
110 unsigned emit_ib_size;
111 /* command emit functions */
112 void (*emit_ib)(struct amdgpu_ring *ring,
113 struct amdgpu_ib *ib,
114 unsigned vm_id, bool ctx_switch);
115 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
116 uint64_t seq, unsigned flags);
117 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
118 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
120 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
121 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
122 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
123 uint32_t gds_base, uint32_t gds_size,
124 uint32_t gws_base, uint32_t gws_size,
125 uint32_t oa_base, uint32_t oa_size);
126 /* testing functions */
127 int (*test_ring)(struct amdgpu_ring *ring);
128 int (*test_ib)(struct amdgpu_ring *ring, long timeout);
129 /* insert NOP packets */
130 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
131 void (*insert_end)(struct amdgpu_ring *ring);
132 /* pad the indirect buffer to the necessary number of dw */
133 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
134 unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
135 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
136 /* note usage for clock and power gating */
137 void (*begin_use)(struct amdgpu_ring *ring);
138 void (*end_use)(struct amdgpu_ring *ring);
139 void (*emit_switch_buffer) (struct amdgpu_ring *ring);
140 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
141 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
142 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
146 struct amdgpu_device *adev;
147 const struct amdgpu_ring_funcs *funcs;
148 struct amdgpu_fence_driver fence_drv;
149 struct amd_gpu_scheduler sched;
151 struct amdgpu_bo *ring_obj;
152 volatile uint32_t *ring;
167 struct amdgpu_bo *mqd_obj;
168 uint64_t mqd_gpu_addr;
174 uint64_t current_ctx;
176 unsigned cond_exe_offs;
177 u64 cond_exe_gpu_addr;
178 volatile u32 *cond_exe_cpu_addr;
179 #if defined(CONFIG_DEBUG_FS)
184 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
185 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
186 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
187 void amdgpu_ring_commit(struct amdgpu_ring *ring);
188 void amdgpu_ring_undo(struct amdgpu_ring *ring);
189 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
190 unsigned ring_size, struct amdgpu_irq_src *irq_src,
192 void amdgpu_ring_fini(struct amdgpu_ring *ring);
193 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
196 while (i <= ring->ptr_mask)
197 ring->ring[i++] = ring->funcs->nop;