2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
29 #include "amdgpu_ucode.h"
31 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
33 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
34 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
35 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
36 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
37 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
38 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
39 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
40 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
41 DRM_DEBUG("ucode_array_offset_bytes: %u\n",
42 le32_to_cpu(hdr->ucode_array_offset_bytes));
43 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
46 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
48 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
49 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
52 amdgpu_ucode_print_common_hdr(hdr);
54 if (version_major == 1) {
55 const struct mc_firmware_header_v1_0 *mc_hdr =
56 container_of(hdr, struct mc_firmware_header_v1_0, header);
58 DRM_DEBUG("io_debug_size_bytes: %u\n",
59 le32_to_cpu(mc_hdr->io_debug_size_bytes));
60 DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
61 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
63 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
67 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
69 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
70 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
73 amdgpu_ucode_print_common_hdr(hdr);
75 if (version_major == 1) {
76 const struct smc_firmware_header_v1_0 *smc_hdr =
77 container_of(hdr, struct smc_firmware_header_v1_0, header);
79 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr));
81 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
85 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
87 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
88 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
91 amdgpu_ucode_print_common_hdr(hdr);
93 if (version_major == 1) {
94 const struct gfx_firmware_header_v1_0 *gfx_hdr =
95 container_of(hdr, struct gfx_firmware_header_v1_0, header);
97 DRM_DEBUG("ucode_feature_version: %u\n",
98 le32_to_cpu(gfx_hdr->ucode_feature_version));
99 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
100 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
102 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
106 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
108 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
109 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
112 amdgpu_ucode_print_common_hdr(hdr);
114 if (version_major == 1) {
115 const struct rlc_firmware_header_v1_0 *rlc_hdr =
116 container_of(hdr, struct rlc_firmware_header_v1_0, header);
118 DRM_DEBUG("ucode_feature_version: %u\n",
119 le32_to_cpu(rlc_hdr->ucode_feature_version));
120 DRM_DEBUG("save_and_restore_offset: %u\n",
121 le32_to_cpu(rlc_hdr->save_and_restore_offset));
122 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
123 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
124 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
125 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
126 DRM_DEBUG("master_pkt_description_offset: %u\n",
127 le32_to_cpu(rlc_hdr->master_pkt_description_offset));
128 } else if (version_major == 2) {
129 const struct rlc_firmware_header_v2_0 *rlc_hdr =
130 container_of(hdr, struct rlc_firmware_header_v2_0, header);
132 DRM_DEBUG("ucode_feature_version: %u\n",
133 le32_to_cpu(rlc_hdr->ucode_feature_version));
134 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
135 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
136 DRM_DEBUG("save_and_restore_offset: %u\n",
137 le32_to_cpu(rlc_hdr->save_and_restore_offset));
138 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
139 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
140 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
141 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
142 DRM_DEBUG("reg_restore_list_size: %u\n",
143 le32_to_cpu(rlc_hdr->reg_restore_list_size));
144 DRM_DEBUG("reg_list_format_start: %u\n",
145 le32_to_cpu(rlc_hdr->reg_list_format_start));
146 DRM_DEBUG("reg_list_format_separate_start: %u\n",
147 le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
148 DRM_DEBUG("starting_offsets_start: %u\n",
149 le32_to_cpu(rlc_hdr->starting_offsets_start));
150 DRM_DEBUG("reg_list_format_size_bytes: %u\n",
151 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
152 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
153 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
154 DRM_DEBUG("reg_list_size_bytes: %u\n",
155 le32_to_cpu(rlc_hdr->reg_list_size_bytes));
156 DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
157 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
158 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
159 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
160 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
161 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
162 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
163 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
164 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
165 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
167 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
171 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
173 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
174 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
177 amdgpu_ucode_print_common_hdr(hdr);
179 if (version_major == 1) {
180 const struct sdma_firmware_header_v1_0 *sdma_hdr =
181 container_of(hdr, struct sdma_firmware_header_v1_0, header);
183 DRM_DEBUG("ucode_feature_version: %u\n",
184 le32_to_cpu(sdma_hdr->ucode_feature_version));
185 DRM_DEBUG("ucode_change_version: %u\n",
186 le32_to_cpu(sdma_hdr->ucode_change_version));
187 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
188 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
189 if (version_minor >= 1) {
190 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
191 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
192 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
195 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
196 version_major, version_minor);
200 int amdgpu_ucode_validate(const struct firmware *fw)
202 const struct common_firmware_header *hdr =
203 (const struct common_firmware_header *)fw->data;
205 if (fw->size == le32_to_cpu(hdr->size_bytes))
211 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
212 uint16_t hdr_major, uint16_t hdr_minor)
214 if ((hdr->common.header_version_major == hdr_major) &&
215 (hdr->common.header_version_minor == hdr_minor))
220 enum amdgpu_firmware_load_type
221 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
223 switch (adev->asic_type) {
224 #ifdef CONFIG_DRM_AMDGPU_SI
229 return AMDGPU_FW_LOAD_DIRECT;
231 #ifdef CONFIG_DRM_AMDGPU_CIK
237 return AMDGPU_FW_LOAD_DIRECT;
248 return AMDGPU_FW_LOAD_DIRECT;
250 return AMDGPU_FW_LOAD_SMU;
253 return AMDGPU_FW_LOAD_DIRECT;
255 return AMDGPU_FW_LOAD_PSP;
257 DRM_ERROR("Unknow firmware load type\n");
260 return AMDGPU_FW_LOAD_DIRECT;
263 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
264 struct amdgpu_firmware_info *ucode,
265 uint64_t mc_addr, void *kptr)
267 const struct common_firmware_header *header = NULL;
268 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
270 if (NULL == ucode->fw)
273 ucode->mc_addr = mc_addr;
276 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
279 header = (const struct common_firmware_header *)ucode->fw->data;
281 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
283 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
284 (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
285 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
286 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
287 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT)) {
288 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
290 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
291 le32_to_cpu(header->ucode_array_offset_bytes)),
293 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 ||
294 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) {
295 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
296 le32_to_cpu(cp_hdr->jt_size) * 4;
298 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
299 le32_to_cpu(header->ucode_array_offset_bytes)),
301 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
302 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) {
303 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
305 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
306 le32_to_cpu(header->ucode_array_offset_bytes) +
307 le32_to_cpu(cp_hdr->jt_offset) * 4),
314 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
315 uint64_t mc_addr, void *kptr)
317 const struct gfx_firmware_header_v1_0 *header = NULL;
318 const struct common_firmware_header *comm_hdr = NULL;
319 uint8_t* src_addr = NULL;
320 uint8_t* dst_addr = NULL;
322 if (NULL == ucode->fw)
325 comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
326 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
327 dst_addr = ucode->kaddr +
328 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
330 src_addr = (uint8_t *)ucode->fw->data +
331 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
332 (le32_to_cpu(header->jt_offset) * 4);
333 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
335 ucode->ucode_size += le32_to_cpu(header->jt_size) * 4;
340 int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
342 struct amdgpu_bo **bo = &adev->firmware.fw_buf;
344 void *fw_buf_ptr = NULL;
345 uint64_t fw_offset = 0;
347 struct amdgpu_firmware_info *ucode = NULL;
348 const struct common_firmware_header *header = NULL;
350 err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true,
351 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
354 dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err);
358 err = amdgpu_bo_reserve(*bo, false);
360 dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err);
364 err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
367 dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err);
371 err = amdgpu_bo_kmap(*bo, &fw_buf_ptr);
373 dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err);
377 amdgpu_bo_unreserve(*bo);
379 memset(fw_buf_ptr, 0, adev->firmware.fw_size);
382 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
385 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
386 if (amdgpu_sriov_vf(adev))
387 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
389 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
391 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
394 for (i = 0; i < adev->firmware.max_ucodes; i++) {
395 ucode = &adev->firmware.ucode[i];
397 header = (const struct common_firmware_header *)ucode->fw->data;
398 amdgpu_ucode_init_single_fw(adev, ucode, fw_mc_addr + fw_offset,
399 (void *)((uint8_t *)fw_buf_ptr + fw_offset));
400 if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
401 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
402 const struct gfx_firmware_header_v1_0 *cp_hdr;
403 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
404 amdgpu_ucode_patch_jt(ucode, fw_mc_addr + fw_offset,
405 fw_buf_ptr + fw_offset);
406 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
408 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
414 amdgpu_bo_unpin(*bo);
416 amdgpu_bo_unreserve(*bo);
421 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
426 int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
429 struct amdgpu_firmware_info *ucode = NULL;
431 for (i = 0; i < adev->firmware.max_ucodes; i++) {
432 ucode = &adev->firmware.ucode[i];
438 amdgpu_bo_unref(&adev->firmware.fw_buf);
439 adev->firmware.fw_buf = NULL;