2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/dma-fence-array.h>
29 #include <linux/interval_tree_generic.h>
31 #include <drm/amdgpu_drm.h>
33 #include "amdgpu_trace.h"
37 * GPUVM is similar to the legacy gart on older asics, however
38 * rather than there being a single global gart table
39 * for the entire GPU, there are multiple VM page tables active
40 * at any given time. The VM page tables can contain a mix
41 * vram pages and system memory pages and system memory pages
42 * can be mapped as snooped (cached system pages) or unsnooped
43 * (uncached system pages).
44 * Each VM has an ID associated with it and there is a page table
45 * associated with each VMID. When execting a command buffer,
46 * the kernel tells the the ring what VMID to use for that command
47 * buffer. VMIDs are allocated dynamically as commands are submitted.
48 * The userspace drivers maintain their own address space and the kernel
49 * sets up their pages tables accordingly when they submit their
50 * command buffers and a VMID is assigned.
51 * Cayman/Trinity support up to 8 active VMs at any given time;
55 #define START(node) ((node)->start)
56 #define LAST(node) ((node)->last)
58 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
59 START, LAST, static, amdgpu_vm_it)
64 /* Local structure. Encapsulate some VM table update parameters to reduce
65 * the number of function parameters
67 struct amdgpu_pte_update_params {
68 /* amdgpu device we do this update for */
69 struct amdgpu_device *adev;
70 /* optional amdgpu_vm we do this update for */
72 /* address where to copy page table entries from */
74 /* indirect buffer to fill with commands */
76 /* Function which actually does the update */
77 void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe,
78 uint64_t addr, unsigned count, uint32_t incr,
80 /* indicate update pt or its shadow */
84 /* Helper to disable partial resident texture feature from a fence callback */
85 struct amdgpu_prt_cb {
86 struct amdgpu_device *adev;
87 struct dma_fence_cb cb;
91 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
93 * @adev: amdgpu_device pointer
95 * Calculate the number of entries in a page directory or page table.
97 static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
101 /* For the root directory */
102 return adev->vm_manager.max_pfn >>
103 (amdgpu_vm_block_size * adev->vm_manager.num_level);
104 else if (level == adev->vm_manager.num_level)
105 /* For the page tables on the leaves */
106 return AMDGPU_VM_PTE_COUNT;
108 /* Everything in between */
109 return 1 << amdgpu_vm_block_size;
113 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
115 * @adev: amdgpu_device pointer
117 * Calculate the size of the BO for a page directory or page table in bytes.
119 static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
121 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
125 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
127 * @vm: vm providing the BOs
128 * @validated: head of validation list
129 * @entry: entry to add
131 * Add the page directory to the list of BOs to
132 * validate for command submission.
134 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
135 struct list_head *validated,
136 struct amdgpu_bo_list_entry *entry)
138 entry->robj = vm->root.bo;
140 entry->tv.bo = &entry->robj->tbo;
141 entry->tv.shared = true;
142 entry->user_pages = NULL;
143 list_add(&entry->tv.head, validated);
147 * amdgpu_vm_validate_layer - validate a single page table level
149 * @parent: parent page table level
150 * @validate: callback to do the validation
151 * @param: parameter for the validation callback
153 * Validate the page table BOs on command submission if neccessary.
155 static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent,
156 int (*validate)(void *, struct amdgpu_bo *),
162 if (!parent->entries)
165 for (i = 0; i <= parent->last_entry_used; ++i) {
166 struct amdgpu_vm_pt *entry = &parent->entries[i];
171 r = validate(param, entry->bo);
176 * Recurse into the sub directory. This is harmless because we
177 * have only a maximum of 5 layers.
179 r = amdgpu_vm_validate_level(entry, validate, param);
188 * amdgpu_vm_validate_pt_bos - validate the page table BOs
190 * @adev: amdgpu device pointer
191 * @vm: vm providing the BOs
192 * @validate: callback to do the validation
193 * @param: parameter for the validation callback
195 * Validate the page table BOs on command submission if neccessary.
197 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
198 int (*validate)(void *p, struct amdgpu_bo *bo),
201 uint64_t num_evictions;
203 /* We only need to validate the page tables
204 * if they aren't already valid.
206 num_evictions = atomic64_read(&adev->num_evictions);
207 if (num_evictions == vm->last_eviction_counter)
210 return amdgpu_vm_validate_level(&vm->root, validate, param);
214 * amdgpu_vm_move_level_in_lru - move one level of PT BOs to the LRU tail
216 * @adev: amdgpu device instance
217 * @vm: vm providing the BOs
219 * Move the PT BOs to the tail of the LRU.
221 static void amdgpu_vm_move_level_in_lru(struct amdgpu_vm_pt *parent)
225 if (!parent->entries)
228 for (i = 0; i <= parent->last_entry_used; ++i) {
229 struct amdgpu_vm_pt *entry = &parent->entries[i];
234 ttm_bo_move_to_lru_tail(&entry->bo->tbo);
235 amdgpu_vm_move_level_in_lru(entry);
240 * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
242 * @adev: amdgpu device instance
243 * @vm: vm providing the BOs
245 * Move the PT BOs to the tail of the LRU.
247 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
248 struct amdgpu_vm *vm)
250 struct ttm_bo_global *glob = adev->mman.bdev.glob;
252 spin_lock(&glob->lru_lock);
253 amdgpu_vm_move_level_in_lru(&vm->root);
254 spin_unlock(&glob->lru_lock);
258 * amdgpu_vm_alloc_levels - allocate the PD/PT levels
260 * @adev: amdgpu_device pointer
262 * @saddr: start of the address range
263 * @eaddr: end of the address range
265 * Make sure the page directories and page tables are allocated
267 static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
268 struct amdgpu_vm *vm,
269 struct amdgpu_vm_pt *parent,
270 uint64_t saddr, uint64_t eaddr,
273 unsigned shift = (adev->vm_manager.num_level - level) *
274 amdgpu_vm_block_size;
275 unsigned pt_idx, from, to;
278 if (!parent->entries) {
279 unsigned num_entries = amdgpu_vm_num_entries(adev, level);
281 parent->entries = drm_calloc_large(num_entries,
282 sizeof(struct amdgpu_vm_pt));
283 if (!parent->entries)
285 memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt));
288 from = saddr >> shift;
290 if (from >= amdgpu_vm_num_entries(adev, level) ||
291 to >= amdgpu_vm_num_entries(adev, level))
294 if (to > parent->last_entry_used)
295 parent->last_entry_used = to;
298 saddr = saddr & ((1 << shift) - 1);
299 eaddr = eaddr & ((1 << shift) - 1);
301 /* walk over the address space and allocate the page tables */
302 for (pt_idx = from; pt_idx <= to; ++pt_idx) {
303 struct reservation_object *resv = vm->root.bo->tbo.resv;
304 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
305 struct amdgpu_bo *pt;
308 r = amdgpu_bo_create(adev,
309 amdgpu_vm_bo_size(adev, level),
310 AMDGPU_GPU_PAGE_SIZE, true,
311 AMDGPU_GEM_DOMAIN_VRAM,
312 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
313 AMDGPU_GEM_CREATE_SHADOW |
314 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
315 AMDGPU_GEM_CREATE_VRAM_CLEARED,
320 /* Keep a reference to the root directory to avoid
321 * freeing them up in the wrong order.
323 pt->parent = amdgpu_bo_ref(vm->root.bo);
329 if (level < adev->vm_manager.num_level) {
330 uint64_t sub_saddr = (pt_idx == from) ? saddr : 0;
331 uint64_t sub_eaddr = (pt_idx == to) ? eaddr :
333 r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr,
344 * amdgpu_vm_alloc_pts - Allocate page tables.
346 * @adev: amdgpu_device pointer
347 * @vm: VM to allocate page tables for
348 * @saddr: Start address which needs to be allocated
349 * @size: Size from start address we need.
351 * Make sure the page tables are allocated.
353 int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
354 struct amdgpu_vm *vm,
355 uint64_t saddr, uint64_t size)
360 /* validate the parameters */
361 if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK)
364 eaddr = saddr + size - 1;
365 last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
366 if (last_pfn >= adev->vm_manager.max_pfn) {
367 dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
368 last_pfn, adev->vm_manager.max_pfn);
372 saddr /= AMDGPU_GPU_PAGE_SIZE;
373 eaddr /= AMDGPU_GPU_PAGE_SIZE;
375 return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0);
379 * amdgpu_vm_had_gpu_reset - check if reset occured since last use
381 * @adev: amdgpu_device pointer
382 * @id: VMID structure
384 * Check if GPU reset occured since last use of the VMID.
386 static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev,
387 struct amdgpu_vm_id *id)
389 return id->current_gpu_reset_count !=
390 atomic_read(&adev->gpu_reset_counter);
394 * amdgpu_vm_grab_id - allocate the next free VMID
396 * @vm: vm to allocate id for
397 * @ring: ring we want to submit job to
398 * @sync: sync object where we add dependencies
399 * @fence: fence protecting ID from reuse
401 * Allocate an id for the vm, adding fences to the sync obj as necessary.
403 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
404 struct amdgpu_sync *sync, struct dma_fence *fence,
405 struct amdgpu_job *job)
407 struct amdgpu_device *adev = ring->adev;
408 uint64_t fence_context = adev->fence_context + ring->idx;
409 struct dma_fence *updates = sync->last_vm_update;
410 struct amdgpu_vm_id *id, *idle;
411 struct dma_fence **fences;
415 fences = kmalloc_array(sizeof(void *), adev->vm_manager.num_ids,
420 mutex_lock(&adev->vm_manager.lock);
422 /* Check if we have an idle VMID */
424 list_for_each_entry(idle, &adev->vm_manager.ids_lru, list) {
425 fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
431 /* If we can't find a idle VMID to use, wait till one becomes available */
432 if (&idle->list == &adev->vm_manager.ids_lru) {
433 u64 fence_context = adev->vm_manager.fence_context + ring->idx;
434 unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
435 struct dma_fence_array *array;
438 for (j = 0; j < i; ++j)
439 dma_fence_get(fences[j]);
441 array = dma_fence_array_create(i, fences, fence_context,
444 for (j = 0; j < i; ++j)
445 dma_fence_put(fences[j]);
452 r = amdgpu_sync_fence(ring->adev, sync, &array->base);
453 dma_fence_put(&array->base);
457 mutex_unlock(&adev->vm_manager.lock);
463 job->vm_needs_flush = true;
464 /* Check if we can use a VMID already assigned to this VM */
467 struct dma_fence *flushed;
470 if (i == AMDGPU_MAX_RINGS)
473 /* Check all the prerequisites to using this VMID */
476 if (amdgpu_vm_had_gpu_reset(adev, id))
479 if (atomic64_read(&id->owner) != vm->client_id)
482 if (job->vm_pd_addr != id->pd_gpu_addr)
488 if (id->last_flush->context != fence_context &&
489 !dma_fence_is_signaled(id->last_flush))
492 flushed = id->flushed_updates;
494 (!flushed || dma_fence_is_later(updates, flushed)))
497 /* Good we can use this VMID. Remember this submission as
500 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
504 list_move_tail(&id->list, &adev->vm_manager.ids_lru);
505 vm->ids[ring->idx] = id;
507 job->vm_id = id - adev->vm_manager.ids;
508 job->vm_needs_flush = false;
509 trace_amdgpu_vm_grab_id(vm, ring->idx, job);
511 mutex_unlock(&adev->vm_manager.lock);
514 } while (i != ring->idx);
516 /* Still no ID to use? Then use the idle one found earlier */
519 /* Remember this submission as user of the VMID */
520 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
524 dma_fence_put(id->last_flush);
525 id->last_flush = NULL;
527 dma_fence_put(id->flushed_updates);
528 id->flushed_updates = dma_fence_get(updates);
530 id->pd_gpu_addr = job->vm_pd_addr;
531 id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter);
532 list_move_tail(&id->list, &adev->vm_manager.ids_lru);
533 atomic64_set(&id->owner, vm->client_id);
534 vm->ids[ring->idx] = id;
536 job->vm_id = id - adev->vm_manager.ids;
537 trace_amdgpu_vm_grab_id(vm, ring->idx, job);
540 mutex_unlock(&adev->vm_manager.lock);
544 static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring)
546 struct amdgpu_device *adev = ring->adev;
547 const struct amdgpu_ip_block *ip_block;
549 if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
550 /* only compute rings */
553 ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
557 if (ip_block->version->major <= 7) {
558 /* gfx7 has no workaround */
560 } else if (ip_block->version->major == 8) {
561 if (adev->gfx.mec_fw_version >= 673)
562 /* gfx8 is fixed in MEC firmware 673 */
570 static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr)
574 if (adev->gart.gart_funcs->adjust_mc_addr)
575 addr = adev->gart.gart_funcs->adjust_mc_addr(adev, addr);
581 * amdgpu_vm_flush - hardware flush the vm
583 * @ring: ring to use for flush
584 * @vm_id: vmid number to use
585 * @pd_addr: address of the page directory
587 * Emit a VM flush when it is necessary.
589 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
591 struct amdgpu_device *adev = ring->adev;
592 struct amdgpu_vm_id *id = &adev->vm_manager.ids[job->vm_id];
593 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
594 id->gds_base != job->gds_base ||
595 id->gds_size != job->gds_size ||
596 id->gws_base != job->gws_base ||
597 id->gws_size != job->gws_size ||
598 id->oa_base != job->oa_base ||
599 id->oa_size != job->oa_size);
600 bool vm_flush_needed = job->vm_needs_flush ||
601 amdgpu_vm_ring_has_compute_vm_bug(ring);
602 unsigned patch_offset = 0;
605 if (amdgpu_vm_had_gpu_reset(adev, id)) {
606 gds_switch_needed = true;
607 vm_flush_needed = true;
610 if (!vm_flush_needed && !gds_switch_needed)
613 if (ring->funcs->init_cond_exec)
614 patch_offset = amdgpu_ring_init_cond_exec(ring);
616 if (ring->funcs->emit_pipeline_sync)
617 amdgpu_ring_emit_pipeline_sync(ring);
619 if (ring->funcs->emit_vm_flush && vm_flush_needed) {
620 u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);
621 struct dma_fence *fence;
623 trace_amdgpu_vm_flush(pd_addr, ring->idx, job->vm_id);
624 amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr);
626 r = amdgpu_fence_emit(ring, &fence);
630 mutex_lock(&adev->vm_manager.lock);
631 dma_fence_put(id->last_flush);
632 id->last_flush = fence;
633 mutex_unlock(&adev->vm_manager.lock);
636 if (gds_switch_needed) {
637 id->gds_base = job->gds_base;
638 id->gds_size = job->gds_size;
639 id->gws_base = job->gws_base;
640 id->gws_size = job->gws_size;
641 id->oa_base = job->oa_base;
642 id->oa_size = job->oa_size;
643 amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base,
644 job->gds_size, job->gws_base,
645 job->gws_size, job->oa_base,
649 if (ring->funcs->patch_cond_exec)
650 amdgpu_ring_patch_cond_exec(ring, patch_offset);
652 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
653 if (ring->funcs->emit_switch_buffer) {
654 amdgpu_ring_emit_switch_buffer(ring);
655 amdgpu_ring_emit_switch_buffer(ring);
661 * amdgpu_vm_reset_id - reset VMID to zero
663 * @adev: amdgpu device structure
664 * @vm_id: vmid number to use
666 * Reset saved GDW, GWS and OA to force switch on next flush.
668 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id)
670 struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
681 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
684 * @bo: requested buffer object
686 * Find @bo inside the requested vm.
687 * Search inside the @bos vm list for the requested vm
688 * Returns the found bo_va or NULL if none is found
690 * Object has to be reserved!
692 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
693 struct amdgpu_bo *bo)
695 struct amdgpu_bo_va *bo_va;
697 list_for_each_entry(bo_va, &bo->va, bo_list) {
698 if (bo_va->vm == vm) {
706 * amdgpu_vm_do_set_ptes - helper to call the right asic function
708 * @params: see amdgpu_pte_update_params definition
709 * @pe: addr of the page entry
710 * @addr: dst addr to write into pe
711 * @count: number of page entries to update
712 * @incr: increase next addr by incr bytes
713 * @flags: hw access flags
715 * Traces the parameters and calls the right asic functions
716 * to setup the page table using the DMA.
718 static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
719 uint64_t pe, uint64_t addr,
720 unsigned count, uint32_t incr,
723 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
726 amdgpu_vm_write_pte(params->adev, params->ib, pe,
727 addr | flags, count, incr);
730 amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr,
736 * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
738 * @params: see amdgpu_pte_update_params definition
739 * @pe: addr of the page entry
740 * @addr: dst addr to write into pe
741 * @count: number of page entries to update
742 * @incr: increase next addr by incr bytes
743 * @flags: hw access flags
745 * Traces the parameters and calls the DMA function to copy the PTEs.
747 static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
748 uint64_t pe, uint64_t addr,
749 unsigned count, uint32_t incr,
752 uint64_t src = (params->src + (addr >> 12) * 8);
755 trace_amdgpu_vm_copy_ptes(pe, src, count);
757 amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count);
761 * amdgpu_vm_map_gart - Resolve gart mapping of addr
763 * @pages_addr: optional DMA address to use for lookup
764 * @addr: the unmapped addr
766 * Look up the physical address of the page that the pte resolves
767 * to and return the pointer for the page table entry.
769 static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
773 /* page table offset */
774 result = pages_addr[addr >> PAGE_SHIFT];
776 /* in case cpu page size != gpu page size*/
777 result |= addr & (~PAGE_MASK);
779 result &= 0xFFFFFFFFFFFFF000ULL;
785 * amdgpu_vm_update_level - update a single level in the hierarchy
787 * @adev: amdgpu_device pointer
789 * @parent: parent directory
791 * Makes sure all entries in @parent are up to date.
792 * Returns 0 for success, error for failure.
794 static int amdgpu_vm_update_level(struct amdgpu_device *adev,
795 struct amdgpu_vm *vm,
796 struct amdgpu_vm_pt *parent,
799 struct amdgpu_bo *shadow;
800 struct amdgpu_ring *ring;
801 uint64_t pd_addr, shadow_addr;
802 uint32_t incr = amdgpu_vm_bo_size(adev, level + 1);
803 uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0;
804 unsigned count = 0, pt_idx, ndw;
805 struct amdgpu_job *job;
806 struct amdgpu_pte_update_params params;
807 struct dma_fence *fence = NULL;
811 if (!parent->entries)
813 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
818 /* assume the worst case */
819 ndw += parent->last_entry_used * 6;
821 pd_addr = amdgpu_bo_gpu_offset(parent->bo);
823 shadow = parent->bo->shadow;
825 r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem);
828 shadow_addr = amdgpu_bo_gpu_offset(shadow);
834 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
838 memset(¶ms, 0, sizeof(params));
840 params.ib = &job->ibs[0];
842 /* walk over the address space and update the directory */
843 for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
844 struct amdgpu_bo *bo = parent->entries[pt_idx].bo;
851 struct amdgpu_bo *pt_shadow = bo->shadow;
853 r = amdgpu_ttm_bind(&pt_shadow->tbo,
854 &pt_shadow->tbo.mem);
859 pt = amdgpu_bo_gpu_offset(bo);
860 if (parent->entries[pt_idx].addr == pt)
863 parent->entries[pt_idx].addr = pt;
865 pde = pd_addr + pt_idx * 8;
866 if (((last_pde + 8 * count) != pde) ||
867 ((last_pt + incr * count) != pt) ||
868 (count == AMDGPU_VM_MAX_UPDATE_SIZE)) {
872 amdgpu_vm_adjust_mc_addr(adev, last_pt);
875 amdgpu_vm_do_set_ptes(¶ms,
881 amdgpu_vm_do_set_ptes(¶ms, last_pde,
882 pt_addr, count, incr,
888 last_shadow = shadow_addr + pt_idx * 8;
896 uint64_t pt_addr = amdgpu_vm_adjust_mc_addr(adev, last_pt);
898 if (vm->root.bo->shadow)
899 amdgpu_vm_do_set_ptes(¶ms, last_shadow, pt_addr,
900 count, incr, AMDGPU_PTE_VALID);
902 amdgpu_vm_do_set_ptes(¶ms, last_pde, pt_addr,
903 count, incr, AMDGPU_PTE_VALID);
906 if (params.ib->length_dw == 0) {
907 amdgpu_job_free(job);
909 amdgpu_ring_pad_ib(ring, params.ib);
910 amdgpu_sync_resv(adev, &job->sync, parent->bo->tbo.resv,
911 AMDGPU_FENCE_OWNER_VM);
913 amdgpu_sync_resv(adev, &job->sync, shadow->tbo.resv,
914 AMDGPU_FENCE_OWNER_VM);
916 WARN_ON(params.ib->length_dw > ndw);
917 r = amdgpu_job_submit(job, ring, &vm->entity,
918 AMDGPU_FENCE_OWNER_VM, &fence);
922 amdgpu_bo_fence(parent->bo, fence, true);
923 dma_fence_put(vm->last_dir_update);
924 vm->last_dir_update = dma_fence_get(fence);
925 dma_fence_put(fence);
928 * Recurse into the subdirectories. This recursion is harmless because
929 * we only have a maximum of 5 layers.
931 for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
932 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
937 r = amdgpu_vm_update_level(adev, vm, entry, level + 1);
945 amdgpu_job_free(job);
950 * amdgpu_vm_update_directories - make sure that all directories are valid
952 * @adev: amdgpu_device pointer
955 * Makes sure all directories are up to date.
956 * Returns 0 for success, error for failure.
958 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
959 struct amdgpu_vm *vm)
961 return amdgpu_vm_update_level(adev, vm, &vm->root, 0);
965 * amdgpu_vm_find_pt - find the page table for an address
967 * @p: see amdgpu_pte_update_params definition
968 * @addr: virtual address in question
970 * Find the page table BO for a virtual address, return NULL when none found.
972 static struct amdgpu_bo *amdgpu_vm_get_pt(struct amdgpu_pte_update_params *p,
975 struct amdgpu_vm_pt *entry = &p->vm->root;
976 unsigned idx, level = p->adev->vm_manager.num_level;
978 while (entry->entries) {
979 idx = addr >> (amdgpu_vm_block_size * level--);
980 idx %= amdgpu_bo_size(entry->bo) / 8;
981 entry = &entry->entries[idx];
991 * amdgpu_vm_update_ptes - make sure that page tables are valid
993 * @params: see amdgpu_pte_update_params definition
995 * @start: start of GPU address range
996 * @end: end of GPU address range
997 * @dst: destination address to map to, the next dst inside the function
998 * @flags: mapping flags
1000 * Update the page tables in the range @start - @end.
1002 static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
1003 uint64_t start, uint64_t end,
1004 uint64_t dst, uint64_t flags)
1006 const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
1008 uint64_t cur_pe_start, cur_nptes, cur_dst;
1009 uint64_t addr; /* next GPU address to be updated */
1010 struct amdgpu_bo *pt;
1011 unsigned nptes; /* next number of ptes to be updated */
1012 uint64_t next_pe_start;
1014 /* initialize the variables */
1016 pt = amdgpu_vm_get_pt(params, addr);
1018 pr_err("PT not found, aborting update_ptes\n");
1022 if (params->shadow) {
1027 if ((addr & ~mask) == (end & ~mask))
1030 nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
1032 cur_pe_start = amdgpu_bo_gpu_offset(pt);
1033 cur_pe_start += (addr & mask) * 8;
1039 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
1041 /* walk over the address space and update the page tables */
1042 while (addr < end) {
1043 pt = amdgpu_vm_get_pt(params, addr);
1045 pr_err("PT not found, aborting update_ptes\n");
1049 if (params->shadow) {
1055 if ((addr & ~mask) == (end & ~mask))
1058 nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
1060 next_pe_start = amdgpu_bo_gpu_offset(pt);
1061 next_pe_start += (addr & mask) * 8;
1063 if ((cur_pe_start + 8 * cur_nptes) == next_pe_start &&
1064 ((cur_nptes + nptes) <= AMDGPU_VM_MAX_UPDATE_SIZE)) {
1065 /* The next ptb is consecutive to current ptb.
1066 * Don't call the update function now.
1067 * Will update two ptbs together in future.
1071 params->func(params, cur_pe_start, cur_dst, cur_nptes,
1072 AMDGPU_GPU_PAGE_SIZE, flags);
1074 cur_pe_start = next_pe_start;
1081 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
1084 params->func(params, cur_pe_start, cur_dst, cur_nptes,
1085 AMDGPU_GPU_PAGE_SIZE, flags);
1089 * amdgpu_vm_frag_ptes - add fragment information to PTEs
1091 * @params: see amdgpu_pte_update_params definition
1093 * @start: first PTE to handle
1094 * @end: last PTE to handle
1095 * @dst: addr those PTEs should point to
1096 * @flags: hw mapping flags
1098 static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
1099 uint64_t start, uint64_t end,
1100 uint64_t dst, uint64_t flags)
1103 * The MC L1 TLB supports variable sized pages, based on a fragment
1104 * field in the PTE. When this field is set to a non-zero value, page
1105 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1106 * flags are considered valid for all PTEs within the fragment range
1107 * and corresponding mappings are assumed to be physically contiguous.
1109 * The L1 TLB can store a single PTE for the whole fragment,
1110 * significantly increasing the space available for translation
1111 * caching. This leads to large improvements in throughput when the
1112 * TLB is under pressure.
1114 * The L2 TLB distributes small and large fragments into two
1115 * asymmetric partitions. The large fragment cache is significantly
1116 * larger. Thus, we try to use large fragments wherever possible.
1117 * Userspace can support this by aligning virtual base address and
1118 * allocation size to the fragment size.
1121 /* SI and newer are optimized for 64KB */
1122 uint64_t frag_flags = AMDGPU_PTE_FRAG(AMDGPU_LOG2_PAGES_PER_FRAG);
1123 uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG;
1125 uint64_t frag_start = ALIGN(start, frag_align);
1126 uint64_t frag_end = end & ~(frag_align - 1);
1128 /* system pages are non continuously */
1129 if (params->src || !(flags & AMDGPU_PTE_VALID) ||
1130 (frag_start >= frag_end)) {
1132 amdgpu_vm_update_ptes(params, start, end, dst, flags);
1136 /* handle the 4K area at the beginning */
1137 if (start != frag_start) {
1138 amdgpu_vm_update_ptes(params, start, frag_start,
1140 dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE;
1143 /* handle the area in the middle */
1144 amdgpu_vm_update_ptes(params, frag_start, frag_end, dst,
1145 flags | frag_flags);
1147 /* handle the 4K area at the end */
1148 if (frag_end != end) {
1149 dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE;
1150 amdgpu_vm_update_ptes(params, frag_end, end, dst, flags);
1155 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1157 * @adev: amdgpu_device pointer
1158 * @exclusive: fence we need to sync to
1159 * @src: address where to copy page table entries from
1160 * @pages_addr: DMA addresses to use for mapping
1162 * @start: start of mapped range
1163 * @last: last mapped entry
1164 * @flags: flags for the entries
1165 * @addr: addr to set the area to
1166 * @fence: optional resulting fence
1168 * Fill in the page table entries between @start and @last.
1169 * Returns 0 for success, -EINVAL for failure.
1171 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1172 struct dma_fence *exclusive,
1174 dma_addr_t *pages_addr,
1175 struct amdgpu_vm *vm,
1176 uint64_t start, uint64_t last,
1177 uint64_t flags, uint64_t addr,
1178 struct dma_fence **fence)
1180 struct amdgpu_ring *ring;
1181 void *owner = AMDGPU_FENCE_OWNER_VM;
1182 unsigned nptes, ncmds, ndw;
1183 struct amdgpu_job *job;
1184 struct amdgpu_pte_update_params params;
1185 struct dma_fence *f = NULL;
1188 memset(¶ms, 0, sizeof(params));
1193 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
1195 /* sync to everything on unmapping */
1196 if (!(flags & AMDGPU_PTE_VALID))
1197 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
1199 nptes = last - start + 1;
1202 * reserve space for one command every (1 << BLOCK_SIZE)
1203 * entries or 2k dwords (whatever is smaller)
1205 ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1;
1211 /* only copy commands needed */
1214 params.func = amdgpu_vm_do_copy_ptes;
1216 } else if (pages_addr) {
1217 /* copy commands needed */
1223 params.func = amdgpu_vm_do_copy_ptes;
1226 /* set page commands needed */
1229 /* two extra commands for begin/end of fragment */
1232 params.func = amdgpu_vm_do_set_ptes;
1235 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1239 params.ib = &job->ibs[0];
1241 if (!src && pages_addr) {
1245 /* Put the PTEs at the end of the IB. */
1246 i = ndw - nptes * 2;
1247 pte= (uint64_t *)&(job->ibs->ptr[i]);
1248 params.src = job->ibs->gpu_addr + i * 4;
1250 for (i = 0; i < nptes; ++i) {
1251 pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i *
1252 AMDGPU_GPU_PAGE_SIZE);
1258 r = amdgpu_sync_fence(adev, &job->sync, exclusive);
1262 r = amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv,
1267 r = reservation_object_reserve_shared(vm->root.bo->tbo.resv);
1271 params.shadow = true;
1272 amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags);
1273 params.shadow = false;
1274 amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags);
1276 amdgpu_ring_pad_ib(ring, params.ib);
1277 WARN_ON(params.ib->length_dw > ndw);
1278 r = amdgpu_job_submit(job, ring, &vm->entity,
1279 AMDGPU_FENCE_OWNER_VM, &f);
1283 amdgpu_bo_fence(vm->root.bo, f, true);
1284 dma_fence_put(*fence);
1289 amdgpu_job_free(job);
1294 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1296 * @adev: amdgpu_device pointer
1297 * @exclusive: fence we need to sync to
1298 * @gtt_flags: flags as they are used for GTT
1299 * @pages_addr: DMA addresses to use for mapping
1301 * @mapping: mapped range and flags to use for the update
1302 * @flags: HW flags for the mapping
1303 * @nodes: array of drm_mm_nodes with the MC addresses
1304 * @fence: optional resulting fence
1306 * Split the mapping into smaller chunks so that each update fits
1308 * Returns 0 for success, -EINVAL for failure.
1310 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1311 struct dma_fence *exclusive,
1313 dma_addr_t *pages_addr,
1314 struct amdgpu_vm *vm,
1315 struct amdgpu_bo_va_mapping *mapping,
1317 struct drm_mm_node *nodes,
1318 struct dma_fence **fence)
1320 uint64_t pfn, src = 0, start = mapping->start;
1323 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1324 * but in case of something, we filter the flags in first place
1326 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1327 flags &= ~AMDGPU_PTE_READABLE;
1328 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1329 flags &= ~AMDGPU_PTE_WRITEABLE;
1331 flags &= ~AMDGPU_PTE_EXECUTABLE;
1332 flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1334 flags &= ~AMDGPU_PTE_MTYPE_MASK;
1335 flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
1337 trace_amdgpu_vm_bo_update(mapping);
1339 pfn = mapping->offset >> PAGE_SHIFT;
1341 while (pfn >= nodes->size) {
1348 uint64_t max_entries;
1349 uint64_t addr, last;
1352 addr = nodes->start << PAGE_SHIFT;
1353 max_entries = (nodes->size - pfn) *
1354 (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
1357 max_entries = S64_MAX;
1361 if (flags == gtt_flags)
1362 src = adev->gart.table_addr +
1363 (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8;
1365 max_entries = min(max_entries, 16ull * 1024ull);
1367 } else if (flags & AMDGPU_PTE_VALID) {
1368 addr += adev->vm_manager.vram_base_offset;
1370 addr += pfn << PAGE_SHIFT;
1372 last = min((uint64_t)mapping->last, start + max_entries - 1);
1373 r = amdgpu_vm_bo_update_mapping(adev, exclusive,
1374 src, pages_addr, vm,
1375 start, last, flags, addr,
1380 pfn += last - start + 1;
1381 if (nodes && nodes->size == pfn) {
1387 } while (unlikely(start != mapping->last + 1));
1393 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1395 * @adev: amdgpu_device pointer
1396 * @bo_va: requested BO and VM object
1397 * @clear: if true clear the entries
1399 * Fill in the page table entries for @bo_va.
1400 * Returns 0 for success, -EINVAL for failure.
1402 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1403 struct amdgpu_bo_va *bo_va,
1406 struct amdgpu_vm *vm = bo_va->vm;
1407 struct amdgpu_bo_va_mapping *mapping;
1408 dma_addr_t *pages_addr = NULL;
1409 uint64_t gtt_flags, flags;
1410 struct ttm_mem_reg *mem;
1411 struct drm_mm_node *nodes;
1412 struct dma_fence *exclusive;
1415 if (clear || !bo_va->bo) {
1420 struct ttm_dma_tt *ttm;
1422 mem = &bo_va->bo->tbo.mem;
1423 nodes = mem->mm_node;
1424 if (mem->mem_type == TTM_PL_TT) {
1425 ttm = container_of(bo_va->bo->tbo.ttm, struct
1427 pages_addr = ttm->dma_address;
1429 exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv);
1433 flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
1434 gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) &&
1435 adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ?
1442 spin_lock(&vm->status_lock);
1443 if (!list_empty(&bo_va->vm_status))
1444 list_splice_init(&bo_va->valids, &bo_va->invalids);
1445 spin_unlock(&vm->status_lock);
1447 list_for_each_entry(mapping, &bo_va->invalids, list) {
1448 r = amdgpu_vm_bo_split_mapping(adev, exclusive,
1449 gtt_flags, pages_addr, vm,
1450 mapping, flags, nodes,
1451 &bo_va->last_pt_update);
1456 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1457 list_for_each_entry(mapping, &bo_va->valids, list)
1458 trace_amdgpu_vm_bo_mapping(mapping);
1460 list_for_each_entry(mapping, &bo_va->invalids, list)
1461 trace_amdgpu_vm_bo_mapping(mapping);
1464 spin_lock(&vm->status_lock);
1465 list_splice_init(&bo_va->invalids, &bo_va->valids);
1466 list_del_init(&bo_va->vm_status);
1468 list_add(&bo_va->vm_status, &vm->cleared);
1469 spin_unlock(&vm->status_lock);
1475 * amdgpu_vm_update_prt_state - update the global PRT state
1477 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1479 unsigned long flags;
1482 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1483 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1484 adev->gart.gart_funcs->set_prt(adev, enable);
1485 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1489 * amdgpu_vm_prt_get - add a PRT user
1491 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1493 if (!adev->gart.gart_funcs->set_prt)
1496 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1497 amdgpu_vm_update_prt_state(adev);
1501 * amdgpu_vm_prt_put - drop a PRT user
1503 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1505 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1506 amdgpu_vm_update_prt_state(adev);
1510 * amdgpu_vm_prt_cb - callback for updating the PRT status
1512 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1514 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1516 amdgpu_vm_prt_put(cb->adev);
1521 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1523 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1524 struct dma_fence *fence)
1526 struct amdgpu_prt_cb *cb;
1528 if (!adev->gart.gart_funcs->set_prt)
1531 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1533 /* Last resort when we are OOM */
1535 dma_fence_wait(fence, false);
1537 amdgpu_vm_prt_put(adev);
1540 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1542 amdgpu_vm_prt_cb(fence, &cb->cb);
1547 * amdgpu_vm_free_mapping - free a mapping
1549 * @adev: amdgpu_device pointer
1551 * @mapping: mapping to be freed
1552 * @fence: fence of the unmap operation
1554 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1556 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1557 struct amdgpu_vm *vm,
1558 struct amdgpu_bo_va_mapping *mapping,
1559 struct dma_fence *fence)
1561 if (mapping->flags & AMDGPU_PTE_PRT)
1562 amdgpu_vm_add_prt_cb(adev, fence);
1567 * amdgpu_vm_prt_fini - finish all prt mappings
1569 * @adev: amdgpu_device pointer
1572 * Register a cleanup callback to disable PRT support after VM dies.
1574 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1576 struct reservation_object *resv = vm->root.bo->tbo.resv;
1577 struct dma_fence *excl, **shared;
1578 unsigned i, shared_count;
1581 r = reservation_object_get_fences_rcu(resv, &excl,
1582 &shared_count, &shared);
1584 /* Not enough memory to grab the fence list, as last resort
1585 * block for all the fences to complete.
1587 reservation_object_wait_timeout_rcu(resv, true, false,
1588 MAX_SCHEDULE_TIMEOUT);
1592 /* Add a callback for each fence in the reservation object */
1593 amdgpu_vm_prt_get(adev);
1594 amdgpu_vm_add_prt_cb(adev, excl);
1596 for (i = 0; i < shared_count; ++i) {
1597 amdgpu_vm_prt_get(adev);
1598 amdgpu_vm_add_prt_cb(adev, shared[i]);
1605 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1607 * @adev: amdgpu_device pointer
1609 * @fence: optional resulting fence (unchanged if no work needed to be done
1610 * or if an error occurred)
1612 * Make sure all freed BOs are cleared in the PT.
1613 * Returns 0 for success.
1615 * PTs have to be reserved and mutex must be locked!
1617 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1618 struct amdgpu_vm *vm,
1619 struct dma_fence **fence)
1621 struct amdgpu_bo_va_mapping *mapping;
1622 struct dma_fence *f = NULL;
1625 while (!list_empty(&vm->freed)) {
1626 mapping = list_first_entry(&vm->freed,
1627 struct amdgpu_bo_va_mapping, list);
1628 list_del(&mapping->list);
1630 r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, NULL, vm, mapping,
1632 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1640 dma_fence_put(*fence);
1651 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
1653 * @adev: amdgpu_device pointer
1656 * Make sure all invalidated BOs are cleared in the PT.
1657 * Returns 0 for success.
1659 * PTs have to be reserved and mutex must be locked!
1661 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
1662 struct amdgpu_vm *vm, struct amdgpu_sync *sync)
1664 struct amdgpu_bo_va *bo_va = NULL;
1667 spin_lock(&vm->status_lock);
1668 while (!list_empty(&vm->invalidated)) {
1669 bo_va = list_first_entry(&vm->invalidated,
1670 struct amdgpu_bo_va, vm_status);
1671 spin_unlock(&vm->status_lock);
1673 r = amdgpu_vm_bo_update(adev, bo_va, true);
1677 spin_lock(&vm->status_lock);
1679 spin_unlock(&vm->status_lock);
1682 r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update);
1688 * amdgpu_vm_bo_add - add a bo to a specific vm
1690 * @adev: amdgpu_device pointer
1692 * @bo: amdgpu buffer object
1694 * Add @bo into the requested vm.
1695 * Add @bo to the list of bos associated with the vm
1696 * Returns newly added bo_va or NULL for failure
1698 * Object has to be reserved!
1700 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1701 struct amdgpu_vm *vm,
1702 struct amdgpu_bo *bo)
1704 struct amdgpu_bo_va *bo_va;
1706 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1707 if (bo_va == NULL) {
1712 bo_va->ref_count = 1;
1713 INIT_LIST_HEAD(&bo_va->bo_list);
1714 INIT_LIST_HEAD(&bo_va->valids);
1715 INIT_LIST_HEAD(&bo_va->invalids);
1716 INIT_LIST_HEAD(&bo_va->vm_status);
1719 list_add_tail(&bo_va->bo_list, &bo->va);
1725 * amdgpu_vm_bo_map - map bo inside a vm
1727 * @adev: amdgpu_device pointer
1728 * @bo_va: bo_va to store the address
1729 * @saddr: where to map the BO
1730 * @offset: requested offset in the BO
1731 * @flags: attributes of pages (read/write/valid/etc.)
1733 * Add a mapping of the BO at the specefied addr into the VM.
1734 * Returns 0 for success, error for failure.
1736 * Object has to be reserved and unreserved outside!
1738 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1739 struct amdgpu_bo_va *bo_va,
1740 uint64_t saddr, uint64_t offset,
1741 uint64_t size, uint64_t flags)
1743 struct amdgpu_bo_va_mapping *mapping, *tmp;
1744 struct amdgpu_vm *vm = bo_va->vm;
1747 /* validate the parameters */
1748 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1749 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
1752 /* make sure object fit at this offset */
1753 eaddr = saddr + size - 1;
1754 if (saddr >= eaddr ||
1755 (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo)))
1758 saddr /= AMDGPU_GPU_PAGE_SIZE;
1759 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1761 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1763 /* bo and tmp overlap, invalid addr */
1764 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1765 "0x%010Lx-0x%010Lx\n", bo_va->bo, saddr, eaddr,
1766 tmp->start, tmp->last + 1);
1770 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1774 INIT_LIST_HEAD(&mapping->list);
1775 mapping->start = saddr;
1776 mapping->last = eaddr;
1777 mapping->offset = offset;
1778 mapping->flags = flags;
1780 list_add(&mapping->list, &bo_va->invalids);
1781 amdgpu_vm_it_insert(mapping, &vm->va);
1783 if (flags & AMDGPU_PTE_PRT)
1784 amdgpu_vm_prt_get(adev);
1790 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1792 * @adev: amdgpu_device pointer
1793 * @bo_va: bo_va to store the address
1794 * @saddr: where to map the BO
1795 * @offset: requested offset in the BO
1796 * @flags: attributes of pages (read/write/valid/etc.)
1798 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1799 * mappings as we do so.
1800 * Returns 0 for success, error for failure.
1802 * Object has to be reserved and unreserved outside!
1804 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1805 struct amdgpu_bo_va *bo_va,
1806 uint64_t saddr, uint64_t offset,
1807 uint64_t size, uint64_t flags)
1809 struct amdgpu_bo_va_mapping *mapping;
1810 struct amdgpu_vm *vm = bo_va->vm;
1814 /* validate the parameters */
1815 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1816 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
1819 /* make sure object fit at this offset */
1820 eaddr = saddr + size - 1;
1821 if (saddr >= eaddr ||
1822 (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo)))
1825 /* Allocate all the needed memory */
1826 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1830 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->vm, saddr, size);
1836 saddr /= AMDGPU_GPU_PAGE_SIZE;
1837 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1839 mapping->start = saddr;
1840 mapping->last = eaddr;
1841 mapping->offset = offset;
1842 mapping->flags = flags;
1844 list_add(&mapping->list, &bo_va->invalids);
1845 amdgpu_vm_it_insert(mapping, &vm->va);
1847 if (flags & AMDGPU_PTE_PRT)
1848 amdgpu_vm_prt_get(adev);
1854 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1856 * @adev: amdgpu_device pointer
1857 * @bo_va: bo_va to remove the address from
1858 * @saddr: where to the BO is mapped
1860 * Remove a mapping of the BO at the specefied addr from the VM.
1861 * Returns 0 for success, error for failure.
1863 * Object has to be reserved and unreserved outside!
1865 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1866 struct amdgpu_bo_va *bo_va,
1869 struct amdgpu_bo_va_mapping *mapping;
1870 struct amdgpu_vm *vm = bo_va->vm;
1873 saddr /= AMDGPU_GPU_PAGE_SIZE;
1875 list_for_each_entry(mapping, &bo_va->valids, list) {
1876 if (mapping->start == saddr)
1880 if (&mapping->list == &bo_va->valids) {
1883 list_for_each_entry(mapping, &bo_va->invalids, list) {
1884 if (mapping->start == saddr)
1888 if (&mapping->list == &bo_va->invalids)
1892 list_del(&mapping->list);
1893 amdgpu_vm_it_remove(mapping, &vm->va);
1894 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1897 list_add(&mapping->list, &vm->freed);
1899 amdgpu_vm_free_mapping(adev, vm, mapping,
1900 bo_va->last_pt_update);
1906 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
1908 * @adev: amdgpu_device pointer
1909 * @vm: VM structure to use
1910 * @saddr: start of the range
1911 * @size: size of the range
1913 * Remove all mappings in a range, split them as appropriate.
1914 * Returns 0 for success, error for failure.
1916 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
1917 struct amdgpu_vm *vm,
1918 uint64_t saddr, uint64_t size)
1920 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
1924 eaddr = saddr + size - 1;
1925 saddr /= AMDGPU_GPU_PAGE_SIZE;
1926 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1928 /* Allocate all the needed memory */
1929 before = kzalloc(sizeof(*before), GFP_KERNEL);
1932 INIT_LIST_HEAD(&before->list);
1934 after = kzalloc(sizeof(*after), GFP_KERNEL);
1939 INIT_LIST_HEAD(&after->list);
1941 /* Now gather all removed mappings */
1942 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1944 /* Remember mapping split at the start */
1945 if (tmp->start < saddr) {
1946 before->start = tmp->start;
1947 before->last = saddr - 1;
1948 before->offset = tmp->offset;
1949 before->flags = tmp->flags;
1950 list_add(&before->list, &tmp->list);
1953 /* Remember mapping split at the end */
1954 if (tmp->last > eaddr) {
1955 after->start = eaddr + 1;
1956 after->last = tmp->last;
1957 after->offset = tmp->offset;
1958 after->offset += after->start - tmp->start;
1959 after->flags = tmp->flags;
1960 list_add(&after->list, &tmp->list);
1963 list_del(&tmp->list);
1964 list_add(&tmp->list, &removed);
1966 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
1969 /* And free them up */
1970 list_for_each_entry_safe(tmp, next, &removed, list) {
1971 amdgpu_vm_it_remove(tmp, &vm->va);
1972 list_del(&tmp->list);
1974 if (tmp->start < saddr)
1976 if (tmp->last > eaddr)
1979 list_add(&tmp->list, &vm->freed);
1980 trace_amdgpu_vm_bo_unmap(NULL, tmp);
1983 /* Insert partial mapping before the range */
1984 if (!list_empty(&before->list)) {
1985 amdgpu_vm_it_insert(before, &vm->va);
1986 if (before->flags & AMDGPU_PTE_PRT)
1987 amdgpu_vm_prt_get(adev);
1992 /* Insert partial mapping after the range */
1993 if (!list_empty(&after->list)) {
1994 amdgpu_vm_it_insert(after, &vm->va);
1995 if (after->flags & AMDGPU_PTE_PRT)
1996 amdgpu_vm_prt_get(adev);
2005 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2007 * @adev: amdgpu_device pointer
2008 * @bo_va: requested bo_va
2010 * Remove @bo_va->bo from the requested vm.
2012 * Object have to be reserved!
2014 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2015 struct amdgpu_bo_va *bo_va)
2017 struct amdgpu_bo_va_mapping *mapping, *next;
2018 struct amdgpu_vm *vm = bo_va->vm;
2020 list_del(&bo_va->bo_list);
2022 spin_lock(&vm->status_lock);
2023 list_del(&bo_va->vm_status);
2024 spin_unlock(&vm->status_lock);
2026 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2027 list_del(&mapping->list);
2028 amdgpu_vm_it_remove(mapping, &vm->va);
2029 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2030 list_add(&mapping->list, &vm->freed);
2032 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2033 list_del(&mapping->list);
2034 amdgpu_vm_it_remove(mapping, &vm->va);
2035 amdgpu_vm_free_mapping(adev, vm, mapping,
2036 bo_va->last_pt_update);
2039 dma_fence_put(bo_va->last_pt_update);
2044 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2046 * @adev: amdgpu_device pointer
2048 * @bo: amdgpu buffer object
2050 * Mark @bo as invalid.
2052 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2053 struct amdgpu_bo *bo)
2055 struct amdgpu_bo_va *bo_va;
2057 list_for_each_entry(bo_va, &bo->va, bo_list) {
2058 spin_lock(&bo_va->vm->status_lock);
2059 if (list_empty(&bo_va->vm_status))
2060 list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
2061 spin_unlock(&bo_va->vm->status_lock);
2066 * amdgpu_vm_init - initialize a vm instance
2068 * @adev: amdgpu_device pointer
2073 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2075 const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
2076 AMDGPU_VM_PTE_COUNT * 8);
2077 unsigned ring_instance;
2078 struct amdgpu_ring *ring;
2079 struct amd_sched_rq *rq;
2082 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2085 vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
2086 spin_lock_init(&vm->status_lock);
2087 INIT_LIST_HEAD(&vm->invalidated);
2088 INIT_LIST_HEAD(&vm->cleared);
2089 INIT_LIST_HEAD(&vm->freed);
2091 /* create scheduler entity for page table updates */
2093 ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
2094 ring_instance %= adev->vm_manager.vm_pte_num_rings;
2095 ring = adev->vm_manager.vm_pte_rings[ring_instance];
2096 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
2097 r = amd_sched_entity_init(&ring->sched, &vm->entity,
2098 rq, amdgpu_sched_jobs);
2102 vm->last_dir_update = NULL;
2104 r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true,
2105 AMDGPU_GEM_DOMAIN_VRAM,
2106 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
2107 AMDGPU_GEM_CREATE_SHADOW |
2108 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
2109 AMDGPU_GEM_CREATE_VRAM_CLEARED,
2110 NULL, NULL, &vm->root.bo);
2112 goto error_free_sched_entity;
2114 r = amdgpu_bo_reserve(vm->root.bo, false);
2116 goto error_free_root;
2118 vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
2119 amdgpu_bo_unreserve(vm->root.bo);
2124 amdgpu_bo_unref(&vm->root.bo->shadow);
2125 amdgpu_bo_unref(&vm->root.bo);
2128 error_free_sched_entity:
2129 amd_sched_entity_fini(&ring->sched, &vm->entity);
2135 * amdgpu_vm_free_levels - free PD/PT levels
2137 * @level: PD/PT starting level to free
2139 * Free the page directory or page table level and all sub levels.
2141 static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level)
2146 amdgpu_bo_unref(&level->bo->shadow);
2147 amdgpu_bo_unref(&level->bo);
2151 for (i = 0; i <= level->last_entry_used; i++)
2152 amdgpu_vm_free_levels(&level->entries[i]);
2154 drm_free_large(level->entries);
2158 * amdgpu_vm_fini - tear down a vm instance
2160 * @adev: amdgpu_device pointer
2164 * Unbind the VM and remove all bos from the vm bo list
2166 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2168 struct amdgpu_bo_va_mapping *mapping, *tmp;
2169 bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt;
2171 amd_sched_entity_fini(vm->entity.sched, &vm->entity);
2173 if (!RB_EMPTY_ROOT(&vm->va)) {
2174 dev_err(adev->dev, "still active bo inside vm\n");
2176 rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, rb) {
2177 list_del(&mapping->list);
2178 amdgpu_vm_it_remove(mapping, &vm->va);
2181 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2182 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2183 amdgpu_vm_prt_fini(adev, vm);
2184 prt_fini_needed = false;
2187 list_del(&mapping->list);
2188 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2191 amdgpu_vm_free_levels(&vm->root);
2192 dma_fence_put(vm->last_dir_update);
2196 * amdgpu_vm_manager_init - init the VM manager
2198 * @adev: amdgpu_device pointer
2200 * Initialize the VM manager structures
2202 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2206 INIT_LIST_HEAD(&adev->vm_manager.ids_lru);
2208 /* skip over VMID 0, since it is the system VM */
2209 for (i = 1; i < adev->vm_manager.num_ids; ++i) {
2210 amdgpu_vm_reset_id(adev, i);
2211 amdgpu_sync_create(&adev->vm_manager.ids[i].active);
2212 list_add_tail(&adev->vm_manager.ids[i].list,
2213 &adev->vm_manager.ids_lru);
2216 adev->vm_manager.fence_context =
2217 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2218 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2219 adev->vm_manager.seqno[i] = 0;
2221 atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
2222 atomic64_set(&adev->vm_manager.client_counter, 0);
2223 spin_lock_init(&adev->vm_manager.prt_lock);
2224 atomic_set(&adev->vm_manager.num_prt_users, 0);
2228 * amdgpu_vm_manager_fini - cleanup VM manager
2230 * @adev: amdgpu_device pointer
2232 * Cleanup the VM manager and free resources.
2234 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2238 for (i = 0; i < AMDGPU_NUM_VM; ++i) {
2239 struct amdgpu_vm_id *id = &adev->vm_manager.ids[i];
2241 amdgpu_sync_free(&adev->vm_manager.ids[i].active);
2242 dma_fence_put(id->flushed_updates);
2243 dma_fence_put(id->last_flush);