2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_trace.h"
35 * GPUVM is similar to the legacy gart on older asics, however
36 * rather than there being a single global gart table
37 * for the entire GPU, there are multiple VM page tables active
38 * at any given time. The VM page tables can contain a mix
39 * vram pages and system memory pages and system memory pages
40 * can be mapped as snooped (cached system pages) or unsnooped
41 * (uncached system pages).
42 * Each VM has an ID associated with it and there is a page table
43 * associated with each VMID. When execting a command buffer,
44 * the kernel tells the the ring what VMID to use for that command
45 * buffer. VMIDs are allocated dynamically as commands are submitted.
46 * The userspace drivers maintain their own address space and the kernel
47 * sets up their pages tables accordingly when they submit their
48 * command buffers and a VMID is assigned.
49 * Cayman/Trinity support up to 8 active VMs at any given time;
54 * amdgpu_vm_num_pde - return the number of page directory entries
56 * @adev: amdgpu_device pointer
58 * Calculate the number of page directory entries (cayman+).
60 static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev)
62 return adev->vm_manager.max_pfn >> amdgpu_vm_block_size;
66 * amdgpu_vm_directory_size - returns the size of the page directory in bytes
68 * @adev: amdgpu_device pointer
70 * Calculate the size of the page directory in bytes (cayman+).
72 static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
74 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8);
78 * amdgpu_vm_get_bos - add the vm BOs to a validation list
80 * @vm: vm providing the BOs
81 * @head: head of validation list
83 * Add the page directory to the list of BOs to
84 * validate for command submission (cayman+).
86 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
88 struct list_head *head)
90 struct amdgpu_bo_list_entry *list;
93 mutex_lock(&vm->mutex);
94 list = drm_malloc_ab(vm->max_pde_used + 2,
95 sizeof(struct amdgpu_bo_list_entry));
97 mutex_unlock(&vm->mutex);
101 /* add the vm page table to the list */
102 list[0].robj = vm->page_directory;
103 list[0].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
104 list[0].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
105 list[0].priority = 0;
106 list[0].tv.bo = &vm->page_directory->tbo;
107 list[0].tv.shared = true;
108 list_add(&list[0].tv.head, head);
110 for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
111 if (!vm->page_tables[i].bo)
114 list[idx].robj = vm->page_tables[i].bo;
115 list[idx].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
116 list[idx].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
117 list[idx].priority = 0;
118 list[idx].tv.bo = &list[idx].robj->tbo;
119 list[idx].tv.shared = true;
120 list_add(&list[idx++].tv.head, head);
122 mutex_unlock(&vm->mutex);
128 * amdgpu_vm_grab_id - allocate the next free VMID
130 * @vm: vm to allocate id for
131 * @ring: ring we want to submit job to
132 * @sync: sync object where we add dependencies
134 * Allocate an id for the vm, adding fences to the sync obj as necessary.
136 * Global mutex must be locked!
138 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
139 struct amdgpu_sync *sync)
141 struct amdgpu_fence *best[AMDGPU_MAX_RINGS] = {};
142 struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
143 struct amdgpu_device *adev = ring->adev;
145 unsigned choices[2] = {};
148 /* check if the id is still valid */
149 if (vm_id->id && vm_id->last_id_use &&
150 vm_id->last_id_use == adev->vm_manager.active[vm_id->id])
153 /* we definately need to flush */
154 vm_id->pd_gpu_addr = ~0ll;
156 /* skip over VMID 0, since it is the system VM */
157 for (i = 1; i < adev->vm_manager.nvm; ++i) {
158 struct amdgpu_fence *fence = adev->vm_manager.active[i];
161 /* found a free one */
163 trace_amdgpu_vm_grab_id(i, ring->idx);
167 if (amdgpu_fence_is_earlier(fence, best[fence->ring->idx])) {
168 best[fence->ring->idx] = fence;
169 choices[fence->ring == ring ? 0 : 1] = i;
173 for (i = 0; i < 2; ++i) {
175 struct amdgpu_fence *fence;
177 fence = adev->vm_manager.active[choices[i]];
178 vm_id->id = choices[i];
180 trace_amdgpu_vm_grab_id(choices[i], ring->idx);
181 return amdgpu_sync_fence(ring->adev, sync, &fence->base);
185 /* should never happen */
191 * amdgpu_vm_flush - hardware flush the vm
193 * @ring: ring to use for flush
194 * @vm: vm we want to flush
195 * @updates: last vm update that we waited for
197 * Flush the vm (cayman+).
199 * Global and local mutex must be locked!
201 void amdgpu_vm_flush(struct amdgpu_ring *ring,
202 struct amdgpu_vm *vm,
203 struct fence *updates)
205 uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
206 struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
207 struct fence *flushed_updates = vm_id->flushed_updates;
208 bool is_earlier = false;
210 if (flushed_updates && updates) {
211 BUG_ON(flushed_updates->context != updates->context);
212 is_earlier = (updates->seqno - flushed_updates->seqno <=
213 INT_MAX) ? true : false;
216 if (pd_addr != vm_id->pd_gpu_addr || !flushed_updates ||
219 trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id->id);
221 vm_id->flushed_updates = fence_get(updates);
222 fence_put(flushed_updates);
224 if (!flushed_updates)
225 vm_id->flushed_updates = fence_get(updates);
226 vm_id->pd_gpu_addr = pd_addr;
227 amdgpu_ring_emit_vm_flush(ring, vm_id->id, vm_id->pd_gpu_addr);
232 * amdgpu_vm_fence - remember fence for vm
234 * @adev: amdgpu_device pointer
235 * @vm: vm we want to fence
236 * @fence: fence to remember
238 * Fence the vm (cayman+).
239 * Set the fence used to protect page table and id.
241 * Global and local mutex must be locked!
243 void amdgpu_vm_fence(struct amdgpu_device *adev,
244 struct amdgpu_vm *vm,
245 struct amdgpu_fence *fence)
247 unsigned ridx = fence->ring->idx;
248 unsigned vm_id = vm->ids[ridx].id;
250 amdgpu_fence_unref(&adev->vm_manager.active[vm_id]);
251 adev->vm_manager.active[vm_id] = amdgpu_fence_ref(fence);
253 amdgpu_fence_unref(&vm->ids[ridx].last_id_use);
254 vm->ids[ridx].last_id_use = amdgpu_fence_ref(fence);
258 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
261 * @bo: requested buffer object
263 * Find @bo inside the requested vm (cayman+).
264 * Search inside the @bos vm list for the requested vm
265 * Returns the found bo_va or NULL if none is found
267 * Object has to be reserved!
269 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
270 struct amdgpu_bo *bo)
272 struct amdgpu_bo_va *bo_va;
274 list_for_each_entry(bo_va, &bo->va, bo_list) {
275 if (bo_va->vm == vm) {
283 * amdgpu_vm_update_pages - helper to call the right asic function
285 * @adev: amdgpu_device pointer
286 * @ib: indirect buffer to fill with commands
287 * @pe: addr of the page entry
288 * @addr: dst addr to write into pe
289 * @count: number of page entries to update
290 * @incr: increase next addr by incr bytes
291 * @flags: hw access flags
292 * @gtt_flags: GTT hw access flags
294 * Traces the parameters and calls the right asic functions
295 * to setup the page table using the DMA.
297 static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
298 struct amdgpu_ib *ib,
299 uint64_t pe, uint64_t addr,
300 unsigned count, uint32_t incr,
301 uint32_t flags, uint32_t gtt_flags)
303 trace_amdgpu_vm_set_page(pe, addr, count, incr, flags);
305 if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) {
306 uint64_t src = adev->gart.table_addr + (addr >> 12) * 8;
307 amdgpu_vm_copy_pte(adev, ib, pe, src, count);
309 } else if ((flags & AMDGPU_PTE_SYSTEM) || (count < 3)) {
310 amdgpu_vm_write_pte(adev, ib, pe, addr,
314 amdgpu_vm_set_pte_pde(adev, ib, pe, addr,
319 int amdgpu_vm_free_job(struct amdgpu_job *job)
322 for (i = 0; i < job->num_ibs; i++)
323 amdgpu_ib_free(job->adev, &job->ibs[i]);
329 * amdgpu_vm_clear_bo - initially clear the page dir/table
331 * @adev: amdgpu_device pointer
334 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
335 struct amdgpu_bo *bo)
337 struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
338 struct fence *fence = NULL;
339 struct amdgpu_ib *ib;
344 r = amdgpu_bo_reserve(bo, false);
348 r = reservation_object_reserve_shared(bo->tbo.resv);
352 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
354 goto error_unreserve;
356 addr = amdgpu_bo_gpu_offset(bo);
357 entries = amdgpu_bo_size(bo) / 8;
359 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
361 goto error_unreserve;
363 r = amdgpu_ib_get(ring, NULL, entries * 2 + 64, ib);
369 amdgpu_vm_update_pages(adev, ib, addr, 0, entries, 0, 0, 0);
370 amdgpu_vm_pad_ib(adev, ib);
371 WARN_ON(ib->length_dw > 64);
372 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
374 AMDGPU_FENCE_OWNER_VM,
377 amdgpu_bo_fence(bo, fence, true);
379 if (amdgpu_enable_scheduler) {
380 amdgpu_bo_unreserve(bo);
384 amdgpu_ib_free(adev, ib);
388 amdgpu_bo_unreserve(bo);
393 * amdgpu_vm_map_gart - get the physical address of a gart page
395 * @adev: amdgpu_device pointer
396 * @addr: the unmapped addr
398 * Look up the physical address of the page that the pte resolves
400 * Returns the physical address of the page.
402 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr)
406 /* page table offset */
407 result = adev->gart.pages_addr[addr >> PAGE_SHIFT];
409 /* in case cpu page size != gpu page size*/
410 result |= addr & (~PAGE_MASK);
416 * amdgpu_vm_update_pdes - make sure that page directory is valid
418 * @adev: amdgpu_device pointer
420 * @start: start of GPU address range
421 * @end: end of GPU address range
423 * Allocates new page tables if necessary
424 * and updates the page directory (cayman+).
425 * Returns 0 for success, error for failure.
427 * Global and local mutex must be locked!
429 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
430 struct amdgpu_vm *vm)
432 struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
433 struct amdgpu_bo *pd = vm->page_directory;
434 uint64_t pd_addr = amdgpu_bo_gpu_offset(pd);
435 uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
436 uint64_t last_pde = ~0, last_pt = ~0;
437 unsigned count = 0, pt_idx, ndw;
438 struct amdgpu_ib *ib;
439 struct fence *fence = NULL;
446 /* assume the worst case */
447 ndw += vm->max_pde_used * 6;
449 /* update too big for an IB */
453 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
457 r = amdgpu_ib_get(ring, NULL, ndw * 4, ib);
464 /* walk over the address space and update the page directory */
465 for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
466 struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo;
472 pt = amdgpu_bo_gpu_offset(bo);
473 if (vm->page_tables[pt_idx].addr == pt)
475 vm->page_tables[pt_idx].addr = pt;
477 pde = pd_addr + pt_idx * 8;
478 if (((last_pde + 8 * count) != pde) ||
479 ((last_pt + incr * count) != pt)) {
482 amdgpu_vm_update_pages(adev, ib, last_pde,
483 last_pt, count, incr,
484 AMDGPU_PTE_VALID, 0);
496 amdgpu_vm_update_pages(adev, ib, last_pde, last_pt, count,
497 incr, AMDGPU_PTE_VALID, 0);
499 if (ib->length_dw != 0) {
500 amdgpu_vm_pad_ib(adev, ib);
501 amdgpu_sync_resv(adev, &ib->sync, pd->tbo.resv, AMDGPU_FENCE_OWNER_VM);
502 WARN_ON(ib->length_dw > ndw);
503 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
505 AMDGPU_FENCE_OWNER_VM,
510 amdgpu_bo_fence(pd, fence, true);
511 fence_put(vm->page_directory_fence);
512 vm->page_directory_fence = fence_get(fence);
516 if (!amdgpu_enable_scheduler || ib->length_dw == 0) {
517 amdgpu_ib_free(adev, ib);
524 amdgpu_ib_free(adev, ib);
530 * amdgpu_vm_frag_ptes - add fragment information to PTEs
532 * @adev: amdgpu_device pointer
533 * @ib: IB for the update
534 * @pe_start: first PTE to handle
535 * @pe_end: last PTE to handle
536 * @addr: addr those PTEs should point to
537 * @flags: hw mapping flags
538 * @gtt_flags: GTT hw mapping flags
540 * Global and local mutex must be locked!
542 static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
543 struct amdgpu_ib *ib,
544 uint64_t pe_start, uint64_t pe_end,
545 uint64_t addr, uint32_t flags,
549 * The MC L1 TLB supports variable sized pages, based on a fragment
550 * field in the PTE. When this field is set to a non-zero value, page
551 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
552 * flags are considered valid for all PTEs within the fragment range
553 * and corresponding mappings are assumed to be physically contiguous.
555 * The L1 TLB can store a single PTE for the whole fragment,
556 * significantly increasing the space available for translation
557 * caching. This leads to large improvements in throughput when the
558 * TLB is under pressure.
560 * The L2 TLB distributes small and large fragments into two
561 * asymmetric partitions. The large fragment cache is significantly
562 * larger. Thus, we try to use large fragments wherever possible.
563 * Userspace can support this by aligning virtual base address and
564 * allocation size to the fragment size.
567 /* SI and newer are optimized for 64KB */
568 uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB;
569 uint64_t frag_align = 0x80;
571 uint64_t frag_start = ALIGN(pe_start, frag_align);
572 uint64_t frag_end = pe_end & ~(frag_align - 1);
576 /* system pages are non continuously */
577 if ((flags & AMDGPU_PTE_SYSTEM) || !(flags & AMDGPU_PTE_VALID) ||
578 (frag_start >= frag_end)) {
580 count = (pe_end - pe_start) / 8;
581 amdgpu_vm_update_pages(adev, ib, pe_start, addr, count,
582 AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
586 /* handle the 4K area at the beginning */
587 if (pe_start != frag_start) {
588 count = (frag_start - pe_start) / 8;
589 amdgpu_vm_update_pages(adev, ib, pe_start, addr, count,
590 AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
591 addr += AMDGPU_GPU_PAGE_SIZE * count;
594 /* handle the area in the middle */
595 count = (frag_end - frag_start) / 8;
596 amdgpu_vm_update_pages(adev, ib, frag_start, addr, count,
597 AMDGPU_GPU_PAGE_SIZE, flags | frag_flags,
600 /* handle the 4K area at the end */
601 if (frag_end != pe_end) {
602 addr += AMDGPU_GPU_PAGE_SIZE * count;
603 count = (pe_end - frag_end) / 8;
604 amdgpu_vm_update_pages(adev, ib, frag_end, addr, count,
605 AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
610 * amdgpu_vm_update_ptes - make sure that page tables are valid
612 * @adev: amdgpu_device pointer
614 * @start: start of GPU address range
615 * @end: end of GPU address range
616 * @dst: destination address to map to
617 * @flags: mapping flags
619 * Update the page tables in the range @start - @end (cayman+).
621 * Global and local mutex must be locked!
623 static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
624 struct amdgpu_vm *vm,
625 struct amdgpu_ib *ib,
626 uint64_t start, uint64_t end,
627 uint64_t dst, uint32_t flags,
630 uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
631 uint64_t last_pte = ~0, last_dst = ~0;
632 void *owner = AMDGPU_FENCE_OWNER_VM;
636 /* sync to everything on unmapping */
637 if (!(flags & AMDGPU_PTE_VALID))
638 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
640 /* walk over the address space and update the page tables */
641 for (addr = start; addr < end; ) {
642 uint64_t pt_idx = addr >> amdgpu_vm_block_size;
643 struct amdgpu_bo *pt = vm->page_tables[pt_idx].bo;
648 amdgpu_sync_resv(adev, &ib->sync, pt->tbo.resv, owner);
649 r = reservation_object_reserve_shared(pt->tbo.resv);
653 if ((addr & ~mask) == (end & ~mask))
656 nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
658 pte = amdgpu_bo_gpu_offset(pt);
659 pte += (addr & mask) * 8;
661 if ((last_pte + 8 * count) != pte) {
664 amdgpu_vm_frag_ptes(adev, ib, last_pte,
665 last_pte + 8 * count,
678 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
682 amdgpu_vm_frag_ptes(adev, ib, last_pte,
683 last_pte + 8 * count,
684 last_dst, flags, gtt_flags);
691 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
693 * @adev: amdgpu_device pointer
695 * @mapping: mapped range and flags to use for the update
696 * @addr: addr to set the area to
697 * @gtt_flags: flags as they are used for GTT
698 * @fence: optional resulting fence
700 * Fill in the page table entries for @mapping.
701 * Returns 0 for success, -EINVAL for failure.
703 * Object have to be reserved and mutex must be locked!
705 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
706 struct amdgpu_vm *vm,
707 struct amdgpu_bo_va_mapping *mapping,
708 uint64_t addr, uint32_t gtt_flags,
709 struct fence **fence)
711 struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
712 unsigned nptes, ncmds, ndw;
713 uint32_t flags = gtt_flags;
714 struct amdgpu_ib *ib;
715 struct fence *f = NULL;
718 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
719 * but in case of something, we filter the flags in first place
721 if (!(mapping->flags & AMDGPU_PTE_READABLE))
722 flags &= ~AMDGPU_PTE_READABLE;
723 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
724 flags &= ~AMDGPU_PTE_WRITEABLE;
726 trace_amdgpu_vm_bo_update(mapping);
728 nptes = mapping->it.last - mapping->it.start + 1;
731 * reserve space for one command every (1 << BLOCK_SIZE)
732 * entries or 2k dwords (whatever is smaller)
734 ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1;
739 if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) {
740 /* only copy commands needed */
743 } else if (flags & AMDGPU_PTE_SYSTEM) {
744 /* header for write data commands */
747 /* body of write data command */
751 /* set page commands needed */
754 /* two extra commands for begin/end of fragment */
758 /* update too big for an IB */
762 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
766 r = amdgpu_ib_get(ring, NULL, ndw * 4, ib);
774 r = amdgpu_vm_update_ptes(adev, vm, ib, mapping->it.start,
775 mapping->it.last + 1, addr + mapping->offset,
779 amdgpu_ib_free(adev, ib);
784 amdgpu_vm_pad_ib(adev, ib);
785 WARN_ON(ib->length_dw > ndw);
786 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
788 AMDGPU_FENCE_OWNER_VM,
793 amdgpu_bo_fence(vm->page_directory, f, true);
796 *fence = fence_get(f);
799 if (!amdgpu_enable_scheduler) {
800 amdgpu_ib_free(adev, ib);
806 amdgpu_ib_free(adev, ib);
812 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
814 * @adev: amdgpu_device pointer
815 * @bo_va: requested BO and VM object
818 * Fill in the page table entries for @bo_va.
819 * Returns 0 for success, -EINVAL for failure.
821 * Object have to be reserved and mutex must be locked!
823 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
824 struct amdgpu_bo_va *bo_va,
825 struct ttm_mem_reg *mem)
827 struct amdgpu_vm *vm = bo_va->vm;
828 struct amdgpu_bo_va_mapping *mapping;
834 addr = (u64)mem->start << PAGE_SHIFT;
835 if (mem->mem_type != TTM_PL_TT)
836 addr += adev->vm_manager.vram_base_offset;
841 flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
843 spin_lock(&vm->status_lock);
844 if (!list_empty(&bo_va->vm_status))
845 list_splice_init(&bo_va->valids, &bo_va->invalids);
846 spin_unlock(&vm->status_lock);
848 list_for_each_entry(mapping, &bo_va->invalids, list) {
849 r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, addr,
850 flags, &bo_va->last_pt_update);
855 spin_lock(&vm->status_lock);
856 list_splice_init(&bo_va->invalids, &bo_va->valids);
857 list_del_init(&bo_va->vm_status);
859 list_add(&bo_va->vm_status, &vm->cleared);
860 spin_unlock(&vm->status_lock);
866 * amdgpu_vm_clear_freed - clear freed BOs in the PT
868 * @adev: amdgpu_device pointer
871 * Make sure all freed BOs are cleared in the PT.
872 * Returns 0 for success.
874 * PTs have to be reserved and mutex must be locked!
876 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
877 struct amdgpu_vm *vm)
879 struct amdgpu_bo_va_mapping *mapping;
882 while (!list_empty(&vm->freed)) {
883 mapping = list_first_entry(&vm->freed,
884 struct amdgpu_bo_va_mapping, list);
885 list_del(&mapping->list);
887 r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, 0, 0, NULL);
898 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
900 * @adev: amdgpu_device pointer
903 * Make sure all invalidated BOs are cleared in the PT.
904 * Returns 0 for success.
906 * PTs have to be reserved and mutex must be locked!
908 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
909 struct amdgpu_vm *vm, struct amdgpu_sync *sync)
911 struct amdgpu_bo_va *bo_va = NULL;
914 spin_lock(&vm->status_lock);
915 while (!list_empty(&vm->invalidated)) {
916 bo_va = list_first_entry(&vm->invalidated,
917 struct amdgpu_bo_va, vm_status);
918 spin_unlock(&vm->status_lock);
920 r = amdgpu_vm_bo_update(adev, bo_va, NULL);
924 spin_lock(&vm->status_lock);
926 spin_unlock(&vm->status_lock);
929 r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update);
935 * amdgpu_vm_bo_add - add a bo to a specific vm
937 * @adev: amdgpu_device pointer
939 * @bo: amdgpu buffer object
941 * Add @bo into the requested vm (cayman+).
942 * Add @bo to the list of bos associated with the vm
943 * Returns newly added bo_va or NULL for failure
945 * Object has to be reserved!
947 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
948 struct amdgpu_vm *vm,
949 struct amdgpu_bo *bo)
951 struct amdgpu_bo_va *bo_va;
953 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
959 bo_va->ref_count = 1;
960 INIT_LIST_HEAD(&bo_va->bo_list);
961 INIT_LIST_HEAD(&bo_va->valids);
962 INIT_LIST_HEAD(&bo_va->invalids);
963 INIT_LIST_HEAD(&bo_va->vm_status);
965 mutex_lock(&vm->mutex);
966 list_add_tail(&bo_va->bo_list, &bo->va);
967 mutex_unlock(&vm->mutex);
973 * amdgpu_vm_bo_map - map bo inside a vm
975 * @adev: amdgpu_device pointer
976 * @bo_va: bo_va to store the address
977 * @saddr: where to map the BO
978 * @offset: requested offset in the BO
979 * @flags: attributes of pages (read/write/valid/etc.)
981 * Add a mapping of the BO at the specefied addr into the VM.
982 * Returns 0 for success, error for failure.
984 * Object has to be reserved and gets unreserved by this function!
986 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
987 struct amdgpu_bo_va *bo_va,
988 uint64_t saddr, uint64_t offset,
989 uint64_t size, uint32_t flags)
991 struct amdgpu_bo_va_mapping *mapping;
992 struct amdgpu_vm *vm = bo_va->vm;
993 struct interval_tree_node *it;
994 unsigned last_pfn, pt_idx;
998 /* validate the parameters */
999 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1000 size == 0 || size & AMDGPU_GPU_PAGE_MASK) {
1001 amdgpu_bo_unreserve(bo_va->bo);
1005 /* make sure object fit at this offset */
1006 eaddr = saddr + size;
1007 if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) {
1008 amdgpu_bo_unreserve(bo_va->bo);
1012 last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
1013 if (last_pfn > adev->vm_manager.max_pfn) {
1014 dev_err(adev->dev, "va above limit (0x%08X > 0x%08X)\n",
1015 last_pfn, adev->vm_manager.max_pfn);
1016 amdgpu_bo_unreserve(bo_va->bo);
1020 mutex_lock(&vm->mutex);
1022 saddr /= AMDGPU_GPU_PAGE_SIZE;
1023 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1025 it = interval_tree_iter_first(&vm->va, saddr, eaddr - 1);
1027 struct amdgpu_bo_va_mapping *tmp;
1028 tmp = container_of(it, struct amdgpu_bo_va_mapping, it);
1029 /* bo and tmp overlap, invalid addr */
1030 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1031 "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr,
1032 tmp->it.start, tmp->it.last + 1);
1033 amdgpu_bo_unreserve(bo_va->bo);
1038 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1040 amdgpu_bo_unreserve(bo_va->bo);
1045 INIT_LIST_HEAD(&mapping->list);
1046 mapping->it.start = saddr;
1047 mapping->it.last = eaddr - 1;
1048 mapping->offset = offset;
1049 mapping->flags = flags;
1051 list_add(&mapping->list, &bo_va->invalids);
1052 interval_tree_insert(&mapping->it, &vm->va);
1053 trace_amdgpu_vm_bo_map(bo_va, mapping);
1055 /* Make sure the page tables are allocated */
1056 saddr >>= amdgpu_vm_block_size;
1057 eaddr >>= amdgpu_vm_block_size;
1059 BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev));
1061 if (eaddr > vm->max_pde_used)
1062 vm->max_pde_used = eaddr;
1064 amdgpu_bo_unreserve(bo_va->bo);
1066 /* walk over the address space and allocate the page tables */
1067 for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) {
1068 struct reservation_object *resv = vm->page_directory->tbo.resv;
1069 struct amdgpu_bo *pt;
1071 if (vm->page_tables[pt_idx].bo)
1074 /* drop mutex to allocate and clear page table */
1075 mutex_unlock(&vm->mutex);
1077 ww_mutex_lock(&resv->lock, NULL);
1078 r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
1079 AMDGPU_GPU_PAGE_SIZE, true,
1080 AMDGPU_GEM_DOMAIN_VRAM,
1081 AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
1083 ww_mutex_unlock(&resv->lock);
1087 r = amdgpu_vm_clear_bo(adev, pt);
1089 amdgpu_bo_unref(&pt);
1093 /* aquire mutex again */
1094 mutex_lock(&vm->mutex);
1095 if (vm->page_tables[pt_idx].bo) {
1096 /* someone else allocated the pt in the meantime */
1097 mutex_unlock(&vm->mutex);
1098 amdgpu_bo_unref(&pt);
1099 mutex_lock(&vm->mutex);
1103 vm->page_tables[pt_idx].addr = 0;
1104 vm->page_tables[pt_idx].bo = pt;
1107 mutex_unlock(&vm->mutex);
1111 mutex_lock(&vm->mutex);
1112 list_del(&mapping->list);
1113 interval_tree_remove(&mapping->it, &vm->va);
1114 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1118 mutex_unlock(&vm->mutex);
1123 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1125 * @adev: amdgpu_device pointer
1126 * @bo_va: bo_va to remove the address from
1127 * @saddr: where to the BO is mapped
1129 * Remove a mapping of the BO at the specefied addr from the VM.
1130 * Returns 0 for success, error for failure.
1132 * Object has to be reserved and gets unreserved by this function!
1134 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1135 struct amdgpu_bo_va *bo_va,
1138 struct amdgpu_bo_va_mapping *mapping;
1139 struct amdgpu_vm *vm = bo_va->vm;
1142 saddr /= AMDGPU_GPU_PAGE_SIZE;
1144 list_for_each_entry(mapping, &bo_va->valids, list) {
1145 if (mapping->it.start == saddr)
1149 if (&mapping->list == &bo_va->valids) {
1152 list_for_each_entry(mapping, &bo_va->invalids, list) {
1153 if (mapping->it.start == saddr)
1157 if (&mapping->list == &bo_va->invalids) {
1158 amdgpu_bo_unreserve(bo_va->bo);
1163 mutex_lock(&vm->mutex);
1164 list_del(&mapping->list);
1165 interval_tree_remove(&mapping->it, &vm->va);
1166 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1169 list_add(&mapping->list, &vm->freed);
1172 mutex_unlock(&vm->mutex);
1173 amdgpu_bo_unreserve(bo_va->bo);
1179 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
1181 * @adev: amdgpu_device pointer
1182 * @bo_va: requested bo_va
1184 * Remove @bo_va->bo from the requested vm (cayman+).
1186 * Object have to be reserved!
1188 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1189 struct amdgpu_bo_va *bo_va)
1191 struct amdgpu_bo_va_mapping *mapping, *next;
1192 struct amdgpu_vm *vm = bo_va->vm;
1194 list_del(&bo_va->bo_list);
1196 mutex_lock(&vm->mutex);
1198 spin_lock(&vm->status_lock);
1199 list_del(&bo_va->vm_status);
1200 spin_unlock(&vm->status_lock);
1202 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
1203 list_del(&mapping->list);
1204 interval_tree_remove(&mapping->it, &vm->va);
1205 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1206 list_add(&mapping->list, &vm->freed);
1208 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
1209 list_del(&mapping->list);
1210 interval_tree_remove(&mapping->it, &vm->va);
1214 fence_put(bo_va->last_pt_update);
1217 mutex_unlock(&vm->mutex);
1221 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1223 * @adev: amdgpu_device pointer
1225 * @bo: amdgpu buffer object
1227 * Mark @bo as invalid (cayman+).
1229 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1230 struct amdgpu_bo *bo)
1232 struct amdgpu_bo_va *bo_va;
1234 list_for_each_entry(bo_va, &bo->va, bo_list) {
1235 spin_lock(&bo_va->vm->status_lock);
1236 if (list_empty(&bo_va->vm_status))
1237 list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
1238 spin_unlock(&bo_va->vm->status_lock);
1243 * amdgpu_vm_init - initialize a vm instance
1245 * @adev: amdgpu_device pointer
1248 * Init @vm fields (cayman+).
1250 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1252 const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
1253 AMDGPU_VM_PTE_COUNT * 8);
1254 unsigned pd_size, pd_entries, pts_size;
1257 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1259 vm->ids[i].flushed_updates = NULL;
1260 vm->ids[i].last_id_use = NULL;
1262 mutex_init(&vm->mutex);
1264 spin_lock_init(&vm->status_lock);
1265 INIT_LIST_HEAD(&vm->invalidated);
1266 INIT_LIST_HEAD(&vm->cleared);
1267 INIT_LIST_HEAD(&vm->freed);
1269 pd_size = amdgpu_vm_directory_size(adev);
1270 pd_entries = amdgpu_vm_num_pdes(adev);
1272 /* allocate page table array */
1273 pts_size = pd_entries * sizeof(struct amdgpu_vm_pt);
1274 vm->page_tables = kzalloc(pts_size, GFP_KERNEL);
1275 if (vm->page_tables == NULL) {
1276 DRM_ERROR("Cannot allocate memory for page table array\n");
1280 vm->page_directory_fence = NULL;
1282 r = amdgpu_bo_create(adev, pd_size, align, true,
1283 AMDGPU_GEM_DOMAIN_VRAM,
1284 AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
1285 NULL, NULL, &vm->page_directory);
1289 r = amdgpu_vm_clear_bo(adev, vm->page_directory);
1291 amdgpu_bo_unref(&vm->page_directory);
1292 vm->page_directory = NULL;
1300 * amdgpu_vm_fini - tear down a vm instance
1302 * @adev: amdgpu_device pointer
1305 * Tear down @vm (cayman+).
1306 * Unbind the VM and remove all bos from the vm bo list
1308 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1310 struct amdgpu_bo_va_mapping *mapping, *tmp;
1313 if (!RB_EMPTY_ROOT(&vm->va)) {
1314 dev_err(adev->dev, "still active bo inside vm\n");
1316 rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) {
1317 list_del(&mapping->list);
1318 interval_tree_remove(&mapping->it, &vm->va);
1321 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
1322 list_del(&mapping->list);
1326 for (i = 0; i < amdgpu_vm_num_pdes(adev); i++)
1327 amdgpu_bo_unref(&vm->page_tables[i].bo);
1328 kfree(vm->page_tables);
1330 amdgpu_bo_unref(&vm->page_directory);
1331 fence_put(vm->page_directory_fence);
1333 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1334 fence_put(vm->ids[i].flushed_updates);
1335 amdgpu_fence_unref(&vm->ids[i].last_id_use);
1338 mutex_destroy(&vm->mutex);