2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/dma-fence-array.h>
29 #include <linux/interval_tree_generic.h>
31 #include <drm/amdgpu_drm.h>
33 #include "amdgpu_trace.h"
37 * GPUVM is similar to the legacy gart on older asics, however
38 * rather than there being a single global gart table
39 * for the entire GPU, there are multiple VM page tables active
40 * at any given time. The VM page tables can contain a mix
41 * vram pages and system memory pages and system memory pages
42 * can be mapped as snooped (cached system pages) or unsnooped
43 * (uncached system pages).
44 * Each VM has an ID associated with it and there is a page table
45 * associated with each VMID. When execting a command buffer,
46 * the kernel tells the the ring what VMID to use for that command
47 * buffer. VMIDs are allocated dynamically as commands are submitted.
48 * The userspace drivers maintain their own address space and the kernel
49 * sets up their pages tables accordingly when they submit their
50 * command buffers and a VMID is assigned.
51 * Cayman/Trinity support up to 8 active VMs at any given time;
55 #define START(node) ((node)->start)
56 #define LAST(node) ((node)->last)
58 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
59 START, LAST, static, amdgpu_vm_it)
64 /* Local structure. Encapsulate some VM table update parameters to reduce
65 * the number of function parameters
67 struct amdgpu_pte_update_params {
68 /* amdgpu device we do this update for */
69 struct amdgpu_device *adev;
70 /* optional amdgpu_vm we do this update for */
72 /* address where to copy page table entries from */
74 /* indirect buffer to fill with commands */
76 /* Function which actually does the update */
77 void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe,
78 uint64_t addr, unsigned count, uint32_t incr,
80 /* indicate update pt or its shadow */
84 /* Helper to disable partial resident texture feature from a fence callback */
85 struct amdgpu_prt_cb {
86 struct amdgpu_device *adev;
87 struct dma_fence_cb cb;
91 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
93 * @adev: amdgpu_device pointer
95 * Calculate the number of entries in a page directory or page table.
97 static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
101 /* For the root directory */
102 return adev->vm_manager.max_pfn >>
103 (amdgpu_vm_block_size * adev->vm_manager.num_level);
104 else if (level == adev->vm_manager.num_level)
105 /* For the page tables on the leaves */
106 return AMDGPU_VM_PTE_COUNT;
108 /* Everything in between */
109 return 1 << amdgpu_vm_block_size;
113 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
115 * @adev: amdgpu_device pointer
117 * Calculate the size of the BO for a page directory or page table in bytes.
119 static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
121 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
125 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
127 * @vm: vm providing the BOs
128 * @validated: head of validation list
129 * @entry: entry to add
131 * Add the page directory to the list of BOs to
132 * validate for command submission.
134 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
135 struct list_head *validated,
136 struct amdgpu_bo_list_entry *entry)
138 entry->robj = vm->root.bo;
140 entry->tv.bo = &entry->robj->tbo;
141 entry->tv.shared = true;
142 entry->user_pages = NULL;
143 list_add(&entry->tv.head, validated);
147 * amdgpu_vm_validate_layer - validate a single page table level
149 * @parent: parent page table level
150 * @validate: callback to do the validation
151 * @param: parameter for the validation callback
153 * Validate the page table BOs on command submission if neccessary.
155 static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent,
156 int (*validate)(void *, struct amdgpu_bo *),
162 if (!parent->entries)
165 for (i = 0; i <= parent->last_entry_used; ++i) {
166 struct amdgpu_vm_pt *entry = &parent->entries[i];
171 r = validate(param, entry->bo);
176 * Recurse into the sub directory. This is harmless because we
177 * have only a maximum of 5 layers.
179 r = amdgpu_vm_validate_level(entry, validate, param);
188 * amdgpu_vm_validate_pt_bos - validate the page table BOs
190 * @adev: amdgpu device pointer
191 * @vm: vm providing the BOs
192 * @validate: callback to do the validation
193 * @param: parameter for the validation callback
195 * Validate the page table BOs on command submission if neccessary.
197 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
198 int (*validate)(void *p, struct amdgpu_bo *bo),
201 uint64_t num_evictions;
203 /* We only need to validate the page tables
204 * if they aren't already valid.
206 num_evictions = atomic64_read(&adev->num_evictions);
207 if (num_evictions == vm->last_eviction_counter)
210 return amdgpu_vm_validate_level(&vm->root, validate, param);
214 * amdgpu_vm_move_level_in_lru - move one level of PT BOs to the LRU tail
216 * @adev: amdgpu device instance
217 * @vm: vm providing the BOs
219 * Move the PT BOs to the tail of the LRU.
221 static void amdgpu_vm_move_level_in_lru(struct amdgpu_vm_pt *parent)
225 if (!parent->entries)
228 for (i = 0; i <= parent->last_entry_used; ++i) {
229 struct amdgpu_vm_pt *entry = &parent->entries[i];
234 ttm_bo_move_to_lru_tail(&entry->bo->tbo);
235 amdgpu_vm_move_level_in_lru(entry);
240 * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
242 * @adev: amdgpu device instance
243 * @vm: vm providing the BOs
245 * Move the PT BOs to the tail of the LRU.
247 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
248 struct amdgpu_vm *vm)
250 struct ttm_bo_global *glob = adev->mman.bdev.glob;
252 spin_lock(&glob->lru_lock);
253 amdgpu_vm_move_level_in_lru(&vm->root);
254 spin_unlock(&glob->lru_lock);
258 * amdgpu_vm_alloc_levels - allocate the PD/PT levels
260 * @adev: amdgpu_device pointer
262 * @saddr: start of the address range
263 * @eaddr: end of the address range
265 * Make sure the page directories and page tables are allocated
267 static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
268 struct amdgpu_vm *vm,
269 struct amdgpu_vm_pt *parent,
270 uint64_t saddr, uint64_t eaddr,
273 unsigned shift = (adev->vm_manager.num_level - level) *
274 amdgpu_vm_block_size;
275 unsigned pt_idx, from, to;
278 if (!parent->entries) {
279 unsigned num_entries = amdgpu_vm_num_entries(adev, level);
281 parent->entries = drm_calloc_large(num_entries,
282 sizeof(struct amdgpu_vm_pt));
283 if (!parent->entries)
285 memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt));
288 from = saddr >> shift;
290 if (from >= amdgpu_vm_num_entries(adev, level) ||
291 to >= amdgpu_vm_num_entries(adev, level))
294 if (to > parent->last_entry_used)
295 parent->last_entry_used = to;
298 saddr = saddr & ((1 << shift) - 1);
299 eaddr = eaddr & ((1 << shift) - 1);
301 /* walk over the address space and allocate the page tables */
302 for (pt_idx = from; pt_idx <= to; ++pt_idx) {
303 struct reservation_object *resv = vm->root.bo->tbo.resv;
304 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
305 struct amdgpu_bo *pt;
308 r = amdgpu_bo_create(adev,
309 amdgpu_vm_bo_size(adev, level),
310 AMDGPU_GPU_PAGE_SIZE, true,
311 AMDGPU_GEM_DOMAIN_VRAM,
312 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
313 AMDGPU_GEM_CREATE_SHADOW |
314 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
315 AMDGPU_GEM_CREATE_VRAM_CLEARED,
320 /* Keep a reference to the root directory to avoid
321 * freeing them up in the wrong order.
323 pt->parent = amdgpu_bo_ref(vm->root.bo);
329 if (level < adev->vm_manager.num_level) {
330 uint64_t sub_saddr = (pt_idx == from) ? saddr : 0;
331 uint64_t sub_eaddr = (pt_idx == to) ? eaddr :
333 r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr,
344 * amdgpu_vm_alloc_pts - Allocate page tables.
346 * @adev: amdgpu_device pointer
347 * @vm: VM to allocate page tables for
348 * @saddr: Start address which needs to be allocated
349 * @size: Size from start address we need.
351 * Make sure the page tables are allocated.
353 int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
354 struct amdgpu_vm *vm,
355 uint64_t saddr, uint64_t size)
360 /* validate the parameters */
361 if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK)
364 eaddr = saddr + size - 1;
365 last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
366 if (last_pfn >= adev->vm_manager.max_pfn) {
367 dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
368 last_pfn, adev->vm_manager.max_pfn);
372 saddr /= AMDGPU_GPU_PAGE_SIZE;
373 eaddr /= AMDGPU_GPU_PAGE_SIZE;
375 return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0);
378 static bool amdgpu_vm_is_gpu_reset(struct amdgpu_device *adev,
379 struct amdgpu_vm_id *id)
381 return id->current_gpu_reset_count !=
382 atomic_read(&adev->gpu_reset_counter) ? true : false;
386 * amdgpu_vm_grab_id - allocate the next free VMID
388 * @vm: vm to allocate id for
389 * @ring: ring we want to submit job to
390 * @sync: sync object where we add dependencies
391 * @fence: fence protecting ID from reuse
393 * Allocate an id for the vm, adding fences to the sync obj as necessary.
395 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
396 struct amdgpu_sync *sync, struct dma_fence *fence,
397 struct amdgpu_job *job)
399 struct amdgpu_device *adev = ring->adev;
400 uint64_t fence_context = adev->fence_context + ring->idx;
401 struct dma_fence *updates = sync->last_vm_update;
402 struct amdgpu_vm_id *id, *idle;
403 struct dma_fence **fences;
407 fences = kmalloc_array(sizeof(void *), adev->vm_manager.num_ids,
412 mutex_lock(&adev->vm_manager.lock);
414 /* Check if we have an idle VMID */
416 list_for_each_entry(idle, &adev->vm_manager.ids_lru, list) {
417 fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
423 /* If we can't find a idle VMID to use, wait till one becomes available */
424 if (&idle->list == &adev->vm_manager.ids_lru) {
425 u64 fence_context = adev->vm_manager.fence_context + ring->idx;
426 unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
427 struct dma_fence_array *array;
430 for (j = 0; j < i; ++j)
431 dma_fence_get(fences[j]);
433 array = dma_fence_array_create(i, fences, fence_context,
436 for (j = 0; j < i; ++j)
437 dma_fence_put(fences[j]);
444 r = amdgpu_sync_fence(ring->adev, sync, &array->base);
445 dma_fence_put(&array->base);
449 mutex_unlock(&adev->vm_manager.lock);
455 job->vm_needs_flush = true;
456 /* Check if we can use a VMID already assigned to this VM */
459 struct dma_fence *flushed;
462 if (i == AMDGPU_MAX_RINGS)
465 /* Check all the prerequisites to using this VMID */
468 if (amdgpu_vm_is_gpu_reset(adev, id))
471 if (atomic64_read(&id->owner) != vm->client_id)
474 if (job->vm_pd_addr != id->pd_gpu_addr)
480 if (id->last_flush->context != fence_context &&
481 !dma_fence_is_signaled(id->last_flush))
484 flushed = id->flushed_updates;
486 (!flushed || dma_fence_is_later(updates, flushed)))
489 /* Good we can use this VMID. Remember this submission as
492 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
496 id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter);
497 list_move_tail(&id->list, &adev->vm_manager.ids_lru);
498 vm->ids[ring->idx] = id;
500 job->vm_id = id - adev->vm_manager.ids;
501 job->vm_needs_flush = false;
502 trace_amdgpu_vm_grab_id(vm, ring->idx, job);
504 mutex_unlock(&adev->vm_manager.lock);
507 } while (i != ring->idx);
509 /* Still no ID to use? Then use the idle one found earlier */
512 /* Remember this submission as user of the VMID */
513 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
517 dma_fence_put(id->first);
518 id->first = dma_fence_get(fence);
520 dma_fence_put(id->last_flush);
521 id->last_flush = NULL;
523 dma_fence_put(id->flushed_updates);
524 id->flushed_updates = dma_fence_get(updates);
526 id->pd_gpu_addr = job->vm_pd_addr;
527 id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter);
528 list_move_tail(&id->list, &adev->vm_manager.ids_lru);
529 atomic64_set(&id->owner, vm->client_id);
530 vm->ids[ring->idx] = id;
532 job->vm_id = id - adev->vm_manager.ids;
533 trace_amdgpu_vm_grab_id(vm, ring->idx, job);
536 mutex_unlock(&adev->vm_manager.lock);
540 static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring)
542 struct amdgpu_device *adev = ring->adev;
543 const struct amdgpu_ip_block *ip_block;
545 if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
546 /* only compute rings */
549 ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
553 if (ip_block->version->major <= 7) {
554 /* gfx7 has no workaround */
556 } else if (ip_block->version->major == 8) {
557 if (adev->gfx.mec_fw_version >= 673)
558 /* gfx8 is fixed in MEC firmware 673 */
566 static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr)
570 if (adev->mc.mc_funcs && adev->mc.mc_funcs->adjust_mc_addr)
571 addr = adev->mc.mc_funcs->adjust_mc_addr(adev, addr);
577 * amdgpu_vm_flush - hardware flush the vm
579 * @ring: ring to use for flush
580 * @vm_id: vmid number to use
581 * @pd_addr: address of the page directory
583 * Emit a VM flush when it is necessary.
585 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
587 struct amdgpu_device *adev = ring->adev;
588 struct amdgpu_vm_id *id = &adev->vm_manager.ids[job->vm_id];
589 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
590 id->gds_base != job->gds_base ||
591 id->gds_size != job->gds_size ||
592 id->gws_base != job->gws_base ||
593 id->gws_size != job->gws_size ||
594 id->oa_base != job->oa_base ||
595 id->oa_size != job->oa_size);
598 if (job->vm_needs_flush || gds_switch_needed ||
599 amdgpu_vm_is_gpu_reset(adev, id) ||
600 amdgpu_vm_ring_has_compute_vm_bug(ring)) {
601 unsigned patch_offset = 0;
603 if (ring->funcs->init_cond_exec)
604 patch_offset = amdgpu_ring_init_cond_exec(ring);
606 if (ring->funcs->emit_pipeline_sync &&
607 (job->vm_needs_flush || gds_switch_needed ||
608 amdgpu_vm_ring_has_compute_vm_bug(ring)))
609 amdgpu_ring_emit_pipeline_sync(ring);
611 if (ring->funcs->emit_vm_flush && (job->vm_needs_flush ||
612 amdgpu_vm_is_gpu_reset(adev, id))) {
613 struct dma_fence *fence;
614 u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);
616 trace_amdgpu_vm_flush(pd_addr, ring->idx, job->vm_id);
617 amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr);
619 r = amdgpu_fence_emit(ring, &fence);
623 mutex_lock(&adev->vm_manager.lock);
624 dma_fence_put(id->last_flush);
625 id->last_flush = fence;
626 mutex_unlock(&adev->vm_manager.lock);
629 if (gds_switch_needed) {
630 id->gds_base = job->gds_base;
631 id->gds_size = job->gds_size;
632 id->gws_base = job->gws_base;
633 id->gws_size = job->gws_size;
634 id->oa_base = job->oa_base;
635 id->oa_size = job->oa_size;
636 amdgpu_ring_emit_gds_switch(ring, job->vm_id,
637 job->gds_base, job->gds_size,
638 job->gws_base, job->gws_size,
639 job->oa_base, job->oa_size);
642 if (ring->funcs->patch_cond_exec)
643 amdgpu_ring_patch_cond_exec(ring, patch_offset);
645 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
646 if (ring->funcs->emit_switch_buffer) {
647 amdgpu_ring_emit_switch_buffer(ring);
648 amdgpu_ring_emit_switch_buffer(ring);
655 * amdgpu_vm_reset_id - reset VMID to zero
657 * @adev: amdgpu device structure
658 * @vm_id: vmid number to use
660 * Reset saved GDW, GWS and OA to force switch on next flush.
662 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id)
664 struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
675 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
678 * @bo: requested buffer object
680 * Find @bo inside the requested vm.
681 * Search inside the @bos vm list for the requested vm
682 * Returns the found bo_va or NULL if none is found
684 * Object has to be reserved!
686 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
687 struct amdgpu_bo *bo)
689 struct amdgpu_bo_va *bo_va;
691 list_for_each_entry(bo_va, &bo->va, bo_list) {
692 if (bo_va->vm == vm) {
700 * amdgpu_vm_do_set_ptes - helper to call the right asic function
702 * @params: see amdgpu_pte_update_params definition
703 * @pe: addr of the page entry
704 * @addr: dst addr to write into pe
705 * @count: number of page entries to update
706 * @incr: increase next addr by incr bytes
707 * @flags: hw access flags
709 * Traces the parameters and calls the right asic functions
710 * to setup the page table using the DMA.
712 static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
713 uint64_t pe, uint64_t addr,
714 unsigned count, uint32_t incr,
717 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
720 amdgpu_vm_write_pte(params->adev, params->ib, pe,
721 addr | flags, count, incr);
724 amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr,
730 * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
732 * @params: see amdgpu_pte_update_params definition
733 * @pe: addr of the page entry
734 * @addr: dst addr to write into pe
735 * @count: number of page entries to update
736 * @incr: increase next addr by incr bytes
737 * @flags: hw access flags
739 * Traces the parameters and calls the DMA function to copy the PTEs.
741 static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
742 uint64_t pe, uint64_t addr,
743 unsigned count, uint32_t incr,
746 uint64_t src = (params->src + (addr >> 12) * 8);
749 trace_amdgpu_vm_copy_ptes(pe, src, count);
751 amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count);
755 * amdgpu_vm_map_gart - Resolve gart mapping of addr
757 * @pages_addr: optional DMA address to use for lookup
758 * @addr: the unmapped addr
760 * Look up the physical address of the page that the pte resolves
761 * to and return the pointer for the page table entry.
763 static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
767 /* page table offset */
768 result = pages_addr[addr >> PAGE_SHIFT];
770 /* in case cpu page size != gpu page size*/
771 result |= addr & (~PAGE_MASK);
773 result &= 0xFFFFFFFFFFFFF000ULL;
779 * amdgpu_vm_update_level - update a single level in the hierarchy
781 * @adev: amdgpu_device pointer
783 * @parent: parent directory
785 * Makes sure all entries in @parent are up to date.
786 * Returns 0 for success, error for failure.
788 static int amdgpu_vm_update_level(struct amdgpu_device *adev,
789 struct amdgpu_vm *vm,
790 struct amdgpu_vm_pt *parent,
793 struct amdgpu_bo *shadow;
794 struct amdgpu_ring *ring;
795 uint64_t pd_addr, shadow_addr;
796 uint32_t incr = amdgpu_vm_bo_size(adev, level + 1);
797 uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0;
798 unsigned count = 0, pt_idx, ndw;
799 struct amdgpu_job *job;
800 struct amdgpu_pte_update_params params;
801 struct dma_fence *fence = NULL;
805 if (!parent->entries)
807 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
812 /* assume the worst case */
813 ndw += parent->last_entry_used * 6;
815 pd_addr = amdgpu_bo_gpu_offset(parent->bo);
817 shadow = parent->bo->shadow;
819 r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem);
822 shadow_addr = amdgpu_bo_gpu_offset(shadow);
828 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
832 memset(¶ms, 0, sizeof(params));
834 params.ib = &job->ibs[0];
836 /* walk over the address space and update the directory */
837 for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
838 struct amdgpu_bo *bo = parent->entries[pt_idx].bo;
845 struct amdgpu_bo *pt_shadow = bo->shadow;
847 r = amdgpu_ttm_bind(&pt_shadow->tbo,
848 &pt_shadow->tbo.mem);
853 pt = amdgpu_bo_gpu_offset(bo);
854 if (parent->entries[pt_idx].addr == pt)
857 parent->entries[pt_idx].addr = pt;
859 pde = pd_addr + pt_idx * 8;
860 if (((last_pde + 8 * count) != pde) ||
861 ((last_pt + incr * count) != pt) ||
862 (count == AMDGPU_VM_MAX_UPDATE_SIZE)) {
866 amdgpu_vm_adjust_mc_addr(adev, last_pt);
869 amdgpu_vm_do_set_ptes(¶ms,
875 amdgpu_vm_do_set_ptes(¶ms, last_pde,
876 pt_addr, count, incr,
882 last_shadow = shadow_addr + pt_idx * 8;
890 uint64_t pt_addr = amdgpu_vm_adjust_mc_addr(adev, last_pt);
892 if (vm->root.bo->shadow)
893 amdgpu_vm_do_set_ptes(¶ms, last_shadow, pt_addr,
894 count, incr, AMDGPU_PTE_VALID);
896 amdgpu_vm_do_set_ptes(¶ms, last_pde, pt_addr,
897 count, incr, AMDGPU_PTE_VALID);
900 if (params.ib->length_dw == 0) {
901 amdgpu_job_free(job);
903 amdgpu_ring_pad_ib(ring, params.ib);
904 amdgpu_sync_resv(adev, &job->sync, parent->bo->tbo.resv,
905 AMDGPU_FENCE_OWNER_VM);
907 amdgpu_sync_resv(adev, &job->sync, shadow->tbo.resv,
908 AMDGPU_FENCE_OWNER_VM);
910 WARN_ON(params.ib->length_dw > ndw);
911 r = amdgpu_job_submit(job, ring, &vm->entity,
912 AMDGPU_FENCE_OWNER_VM, &fence);
916 amdgpu_bo_fence(parent->bo, fence, true);
917 dma_fence_put(vm->last_dir_update);
918 vm->last_dir_update = dma_fence_get(fence);
919 dma_fence_put(fence);
922 * Recurse into the subdirectories. This recursion is harmless because
923 * we only have a maximum of 5 layers.
925 for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
926 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
931 r = amdgpu_vm_update_level(adev, vm, entry, level + 1);
939 amdgpu_job_free(job);
944 * amdgpu_vm_update_directories - make sure that all directories are valid
946 * @adev: amdgpu_device pointer
949 * Makes sure all directories are up to date.
950 * Returns 0 for success, error for failure.
952 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
953 struct amdgpu_vm *vm)
955 return amdgpu_vm_update_level(adev, vm, &vm->root, 0);
959 * amdgpu_vm_find_pt - find the page table for an address
961 * @p: see amdgpu_pte_update_params definition
962 * @addr: virtual address in question
964 * Find the page table BO for a virtual address, return NULL when none found.
966 static struct amdgpu_bo *amdgpu_vm_get_pt(struct amdgpu_pte_update_params *p,
969 struct amdgpu_vm_pt *entry = &p->vm->root;
970 unsigned idx, level = p->adev->vm_manager.num_level;
972 while (entry->entries) {
973 idx = addr >> (amdgpu_vm_block_size * level--);
974 idx %= amdgpu_bo_size(entry->bo) / 8;
975 entry = &entry->entries[idx];
985 * amdgpu_vm_update_ptes - make sure that page tables are valid
987 * @params: see amdgpu_pte_update_params definition
989 * @start: start of GPU address range
990 * @end: end of GPU address range
991 * @dst: destination address to map to, the next dst inside the function
992 * @flags: mapping flags
994 * Update the page tables in the range @start - @end.
996 static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
997 uint64_t start, uint64_t end,
998 uint64_t dst, uint64_t flags)
1000 const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
1002 uint64_t cur_pe_start, cur_nptes, cur_dst;
1003 uint64_t addr; /* next GPU address to be updated */
1004 struct amdgpu_bo *pt;
1005 unsigned nptes; /* next number of ptes to be updated */
1006 uint64_t next_pe_start;
1008 /* initialize the variables */
1010 pt = amdgpu_vm_get_pt(params, addr);
1012 pr_err("PT not found, aborting update_ptes\n");
1016 if (params->shadow) {
1021 if ((addr & ~mask) == (end & ~mask))
1024 nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
1026 cur_pe_start = amdgpu_bo_gpu_offset(pt);
1027 cur_pe_start += (addr & mask) * 8;
1033 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
1035 /* walk over the address space and update the page tables */
1036 while (addr < end) {
1037 pt = amdgpu_vm_get_pt(params, addr);
1039 pr_err("PT not found, aborting update_ptes\n");
1043 if (params->shadow) {
1049 if ((addr & ~mask) == (end & ~mask))
1052 nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
1054 next_pe_start = amdgpu_bo_gpu_offset(pt);
1055 next_pe_start += (addr & mask) * 8;
1057 if ((cur_pe_start + 8 * cur_nptes) == next_pe_start &&
1058 ((cur_nptes + nptes) <= AMDGPU_VM_MAX_UPDATE_SIZE)) {
1059 /* The next ptb is consecutive to current ptb.
1060 * Don't call the update function now.
1061 * Will update two ptbs together in future.
1065 params->func(params, cur_pe_start, cur_dst, cur_nptes,
1066 AMDGPU_GPU_PAGE_SIZE, flags);
1068 cur_pe_start = next_pe_start;
1075 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
1078 params->func(params, cur_pe_start, cur_dst, cur_nptes,
1079 AMDGPU_GPU_PAGE_SIZE, flags);
1083 * amdgpu_vm_frag_ptes - add fragment information to PTEs
1085 * @params: see amdgpu_pte_update_params definition
1087 * @start: first PTE to handle
1088 * @end: last PTE to handle
1089 * @dst: addr those PTEs should point to
1090 * @flags: hw mapping flags
1092 static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
1093 uint64_t start, uint64_t end,
1094 uint64_t dst, uint64_t flags)
1097 * The MC L1 TLB supports variable sized pages, based on a fragment
1098 * field in the PTE. When this field is set to a non-zero value, page
1099 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1100 * flags are considered valid for all PTEs within the fragment range
1101 * and corresponding mappings are assumed to be physically contiguous.
1103 * The L1 TLB can store a single PTE for the whole fragment,
1104 * significantly increasing the space available for translation
1105 * caching. This leads to large improvements in throughput when the
1106 * TLB is under pressure.
1108 * The L2 TLB distributes small and large fragments into two
1109 * asymmetric partitions. The large fragment cache is significantly
1110 * larger. Thus, we try to use large fragments wherever possible.
1111 * Userspace can support this by aligning virtual base address and
1112 * allocation size to the fragment size.
1115 /* SI and newer are optimized for 64KB */
1116 uint64_t frag_flags = AMDGPU_PTE_FRAG(AMDGPU_LOG2_PAGES_PER_FRAG);
1117 uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG;
1119 uint64_t frag_start = ALIGN(start, frag_align);
1120 uint64_t frag_end = end & ~(frag_align - 1);
1122 /* system pages are non continuously */
1123 if (params->src || !(flags & AMDGPU_PTE_VALID) ||
1124 (frag_start >= frag_end)) {
1126 amdgpu_vm_update_ptes(params, start, end, dst, flags);
1130 /* handle the 4K area at the beginning */
1131 if (start != frag_start) {
1132 amdgpu_vm_update_ptes(params, start, frag_start,
1134 dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE;
1137 /* handle the area in the middle */
1138 amdgpu_vm_update_ptes(params, frag_start, frag_end, dst,
1139 flags | frag_flags);
1141 /* handle the 4K area at the end */
1142 if (frag_end != end) {
1143 dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE;
1144 amdgpu_vm_update_ptes(params, frag_end, end, dst, flags);
1149 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1151 * @adev: amdgpu_device pointer
1152 * @exclusive: fence we need to sync to
1153 * @src: address where to copy page table entries from
1154 * @pages_addr: DMA addresses to use for mapping
1156 * @start: start of mapped range
1157 * @last: last mapped entry
1158 * @flags: flags for the entries
1159 * @addr: addr to set the area to
1160 * @fence: optional resulting fence
1162 * Fill in the page table entries between @start and @last.
1163 * Returns 0 for success, -EINVAL for failure.
1165 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1166 struct dma_fence *exclusive,
1168 dma_addr_t *pages_addr,
1169 struct amdgpu_vm *vm,
1170 uint64_t start, uint64_t last,
1171 uint64_t flags, uint64_t addr,
1172 struct dma_fence **fence)
1174 struct amdgpu_ring *ring;
1175 void *owner = AMDGPU_FENCE_OWNER_VM;
1176 unsigned nptes, ncmds, ndw;
1177 struct amdgpu_job *job;
1178 struct amdgpu_pte_update_params params;
1179 struct dma_fence *f = NULL;
1182 memset(¶ms, 0, sizeof(params));
1187 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
1189 /* sync to everything on unmapping */
1190 if (!(flags & AMDGPU_PTE_VALID))
1191 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
1193 nptes = last - start + 1;
1196 * reserve space for one command every (1 << BLOCK_SIZE)
1197 * entries or 2k dwords (whatever is smaller)
1199 ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1;
1205 /* only copy commands needed */
1208 params.func = amdgpu_vm_do_copy_ptes;
1210 } else if (pages_addr) {
1211 /* copy commands needed */
1217 params.func = amdgpu_vm_do_copy_ptes;
1220 /* set page commands needed */
1223 /* two extra commands for begin/end of fragment */
1226 params.func = amdgpu_vm_do_set_ptes;
1229 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1233 params.ib = &job->ibs[0];
1235 if (!src && pages_addr) {
1239 /* Put the PTEs at the end of the IB. */
1240 i = ndw - nptes * 2;
1241 pte= (uint64_t *)&(job->ibs->ptr[i]);
1242 params.src = job->ibs->gpu_addr + i * 4;
1244 for (i = 0; i < nptes; ++i) {
1245 pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i *
1246 AMDGPU_GPU_PAGE_SIZE);
1252 r = amdgpu_sync_fence(adev, &job->sync, exclusive);
1256 r = amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv,
1261 r = reservation_object_reserve_shared(vm->root.bo->tbo.resv);
1265 params.shadow = true;
1266 amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags);
1267 params.shadow = false;
1268 amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags);
1270 amdgpu_ring_pad_ib(ring, params.ib);
1271 WARN_ON(params.ib->length_dw > ndw);
1272 r = amdgpu_job_submit(job, ring, &vm->entity,
1273 AMDGPU_FENCE_OWNER_VM, &f);
1277 amdgpu_bo_fence(vm->root.bo, f, true);
1278 dma_fence_put(*fence);
1283 amdgpu_job_free(job);
1288 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1290 * @adev: amdgpu_device pointer
1291 * @exclusive: fence we need to sync to
1292 * @gtt_flags: flags as they are used for GTT
1293 * @pages_addr: DMA addresses to use for mapping
1295 * @mapping: mapped range and flags to use for the update
1296 * @flags: HW flags for the mapping
1297 * @nodes: array of drm_mm_nodes with the MC addresses
1298 * @fence: optional resulting fence
1300 * Split the mapping into smaller chunks so that each update fits
1302 * Returns 0 for success, -EINVAL for failure.
1304 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1305 struct dma_fence *exclusive,
1307 dma_addr_t *pages_addr,
1308 struct amdgpu_vm *vm,
1309 struct amdgpu_bo_va_mapping *mapping,
1311 struct drm_mm_node *nodes,
1312 struct dma_fence **fence)
1314 uint64_t pfn, src = 0, start = mapping->start;
1317 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1318 * but in case of something, we filter the flags in first place
1320 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1321 flags &= ~AMDGPU_PTE_READABLE;
1322 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1323 flags &= ~AMDGPU_PTE_WRITEABLE;
1325 flags &= ~AMDGPU_PTE_EXECUTABLE;
1326 flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1328 flags &= ~AMDGPU_PTE_MTYPE_MASK;
1329 flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
1331 trace_amdgpu_vm_bo_update(mapping);
1333 pfn = mapping->offset >> PAGE_SHIFT;
1335 while (pfn >= nodes->size) {
1342 uint64_t max_entries;
1343 uint64_t addr, last;
1346 addr = nodes->start << PAGE_SHIFT;
1347 max_entries = (nodes->size - pfn) *
1348 (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
1351 max_entries = S64_MAX;
1355 if (flags == gtt_flags)
1356 src = adev->gart.table_addr +
1357 (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8;
1359 max_entries = min(max_entries, 16ull * 1024ull);
1361 } else if (flags & AMDGPU_PTE_VALID) {
1362 addr += adev->vm_manager.vram_base_offset;
1364 addr += pfn << PAGE_SHIFT;
1366 last = min((uint64_t)mapping->last, start + max_entries - 1);
1367 r = amdgpu_vm_bo_update_mapping(adev, exclusive,
1368 src, pages_addr, vm,
1369 start, last, flags, addr,
1374 pfn += last - start + 1;
1375 if (nodes && nodes->size == pfn) {
1381 } while (unlikely(start != mapping->last + 1));
1387 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1389 * @adev: amdgpu_device pointer
1390 * @bo_va: requested BO and VM object
1391 * @clear: if true clear the entries
1393 * Fill in the page table entries for @bo_va.
1394 * Returns 0 for success, -EINVAL for failure.
1396 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1397 struct amdgpu_bo_va *bo_va,
1400 struct amdgpu_vm *vm = bo_va->vm;
1401 struct amdgpu_bo_va_mapping *mapping;
1402 dma_addr_t *pages_addr = NULL;
1403 uint64_t gtt_flags, flags;
1404 struct ttm_mem_reg *mem;
1405 struct drm_mm_node *nodes;
1406 struct dma_fence *exclusive;
1409 if (clear || !bo_va->bo) {
1414 struct ttm_dma_tt *ttm;
1416 mem = &bo_va->bo->tbo.mem;
1417 nodes = mem->mm_node;
1418 if (mem->mem_type == TTM_PL_TT) {
1419 ttm = container_of(bo_va->bo->tbo.ttm, struct
1421 pages_addr = ttm->dma_address;
1423 exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv);
1427 flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
1428 gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) &&
1429 adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ?
1436 spin_lock(&vm->status_lock);
1437 if (!list_empty(&bo_va->vm_status))
1438 list_splice_init(&bo_va->valids, &bo_va->invalids);
1439 spin_unlock(&vm->status_lock);
1441 list_for_each_entry(mapping, &bo_va->invalids, list) {
1442 r = amdgpu_vm_bo_split_mapping(adev, exclusive,
1443 gtt_flags, pages_addr, vm,
1444 mapping, flags, nodes,
1445 &bo_va->last_pt_update);
1450 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1451 list_for_each_entry(mapping, &bo_va->valids, list)
1452 trace_amdgpu_vm_bo_mapping(mapping);
1454 list_for_each_entry(mapping, &bo_va->invalids, list)
1455 trace_amdgpu_vm_bo_mapping(mapping);
1458 spin_lock(&vm->status_lock);
1459 list_splice_init(&bo_va->invalids, &bo_va->valids);
1460 list_del_init(&bo_va->vm_status);
1462 list_add(&bo_va->vm_status, &vm->cleared);
1463 spin_unlock(&vm->status_lock);
1469 * amdgpu_vm_update_prt_state - update the global PRT state
1471 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1473 unsigned long flags;
1476 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1477 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1478 adev->gart.gart_funcs->set_prt(adev, enable);
1479 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1483 * amdgpu_vm_prt_get - add a PRT user
1485 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1487 if (!adev->gart.gart_funcs->set_prt)
1490 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1491 amdgpu_vm_update_prt_state(adev);
1495 * amdgpu_vm_prt_put - drop a PRT user
1497 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1499 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1500 amdgpu_vm_update_prt_state(adev);
1504 * amdgpu_vm_prt_cb - callback for updating the PRT status
1506 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1508 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1510 amdgpu_vm_prt_put(cb->adev);
1515 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1517 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1518 struct dma_fence *fence)
1520 struct amdgpu_prt_cb *cb;
1522 if (!adev->gart.gart_funcs->set_prt)
1525 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1527 /* Last resort when we are OOM */
1529 dma_fence_wait(fence, false);
1531 amdgpu_vm_prt_put(cb->adev);
1534 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1536 amdgpu_vm_prt_cb(fence, &cb->cb);
1541 * amdgpu_vm_free_mapping - free a mapping
1543 * @adev: amdgpu_device pointer
1545 * @mapping: mapping to be freed
1546 * @fence: fence of the unmap operation
1548 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1550 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1551 struct amdgpu_vm *vm,
1552 struct amdgpu_bo_va_mapping *mapping,
1553 struct dma_fence *fence)
1555 if (mapping->flags & AMDGPU_PTE_PRT)
1556 amdgpu_vm_add_prt_cb(adev, fence);
1561 * amdgpu_vm_prt_fini - finish all prt mappings
1563 * @adev: amdgpu_device pointer
1566 * Register a cleanup callback to disable PRT support after VM dies.
1568 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1570 struct reservation_object *resv = vm->root.bo->tbo.resv;
1571 struct dma_fence *excl, **shared;
1572 unsigned i, shared_count;
1575 r = reservation_object_get_fences_rcu(resv, &excl,
1576 &shared_count, &shared);
1578 /* Not enough memory to grab the fence list, as last resort
1579 * block for all the fences to complete.
1581 reservation_object_wait_timeout_rcu(resv, true, false,
1582 MAX_SCHEDULE_TIMEOUT);
1586 /* Add a callback for each fence in the reservation object */
1587 amdgpu_vm_prt_get(adev);
1588 amdgpu_vm_add_prt_cb(adev, excl);
1590 for (i = 0; i < shared_count; ++i) {
1591 amdgpu_vm_prt_get(adev);
1592 amdgpu_vm_add_prt_cb(adev, shared[i]);
1599 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1601 * @adev: amdgpu_device pointer
1603 * @fence: optional resulting fence (unchanged if no work needed to be done
1604 * or if an error occurred)
1606 * Make sure all freed BOs are cleared in the PT.
1607 * Returns 0 for success.
1609 * PTs have to be reserved and mutex must be locked!
1611 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1612 struct amdgpu_vm *vm,
1613 struct dma_fence **fence)
1615 struct amdgpu_bo_va_mapping *mapping;
1616 struct dma_fence *f = NULL;
1619 while (!list_empty(&vm->freed)) {
1620 mapping = list_first_entry(&vm->freed,
1621 struct amdgpu_bo_va_mapping, list);
1622 list_del(&mapping->list);
1624 r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, NULL, vm, mapping,
1626 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1634 dma_fence_put(*fence);
1645 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
1647 * @adev: amdgpu_device pointer
1650 * Make sure all invalidated BOs are cleared in the PT.
1651 * Returns 0 for success.
1653 * PTs have to be reserved and mutex must be locked!
1655 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
1656 struct amdgpu_vm *vm, struct amdgpu_sync *sync)
1658 struct amdgpu_bo_va *bo_va = NULL;
1661 spin_lock(&vm->status_lock);
1662 while (!list_empty(&vm->invalidated)) {
1663 bo_va = list_first_entry(&vm->invalidated,
1664 struct amdgpu_bo_va, vm_status);
1665 spin_unlock(&vm->status_lock);
1667 r = amdgpu_vm_bo_update(adev, bo_va, true);
1671 spin_lock(&vm->status_lock);
1673 spin_unlock(&vm->status_lock);
1676 r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update);
1682 * amdgpu_vm_bo_add - add a bo to a specific vm
1684 * @adev: amdgpu_device pointer
1686 * @bo: amdgpu buffer object
1688 * Add @bo into the requested vm.
1689 * Add @bo to the list of bos associated with the vm
1690 * Returns newly added bo_va or NULL for failure
1692 * Object has to be reserved!
1694 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1695 struct amdgpu_vm *vm,
1696 struct amdgpu_bo *bo)
1698 struct amdgpu_bo_va *bo_va;
1700 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1701 if (bo_va == NULL) {
1706 bo_va->ref_count = 1;
1707 INIT_LIST_HEAD(&bo_va->bo_list);
1708 INIT_LIST_HEAD(&bo_va->valids);
1709 INIT_LIST_HEAD(&bo_va->invalids);
1710 INIT_LIST_HEAD(&bo_va->vm_status);
1713 list_add_tail(&bo_va->bo_list, &bo->va);
1719 * amdgpu_vm_bo_map - map bo inside a vm
1721 * @adev: amdgpu_device pointer
1722 * @bo_va: bo_va to store the address
1723 * @saddr: where to map the BO
1724 * @offset: requested offset in the BO
1725 * @flags: attributes of pages (read/write/valid/etc.)
1727 * Add a mapping of the BO at the specefied addr into the VM.
1728 * Returns 0 for success, error for failure.
1730 * Object has to be reserved and unreserved outside!
1732 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1733 struct amdgpu_bo_va *bo_va,
1734 uint64_t saddr, uint64_t offset,
1735 uint64_t size, uint64_t flags)
1737 struct amdgpu_bo_va_mapping *mapping, *tmp;
1738 struct amdgpu_vm *vm = bo_va->vm;
1741 /* validate the parameters */
1742 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1743 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
1746 /* make sure object fit at this offset */
1747 eaddr = saddr + size - 1;
1748 if (saddr >= eaddr ||
1749 (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo)))
1752 saddr /= AMDGPU_GPU_PAGE_SIZE;
1753 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1755 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1757 /* bo and tmp overlap, invalid addr */
1758 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1759 "0x%010Lx-0x%010Lx\n", bo_va->bo, saddr, eaddr,
1760 tmp->start, tmp->last + 1);
1764 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1768 INIT_LIST_HEAD(&mapping->list);
1769 mapping->start = saddr;
1770 mapping->last = eaddr;
1771 mapping->offset = offset;
1772 mapping->flags = flags;
1774 list_add(&mapping->list, &bo_va->invalids);
1775 amdgpu_vm_it_insert(mapping, &vm->va);
1777 if (flags & AMDGPU_PTE_PRT)
1778 amdgpu_vm_prt_get(adev);
1784 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1786 * @adev: amdgpu_device pointer
1787 * @bo_va: bo_va to store the address
1788 * @saddr: where to map the BO
1789 * @offset: requested offset in the BO
1790 * @flags: attributes of pages (read/write/valid/etc.)
1792 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1793 * mappings as we do so.
1794 * Returns 0 for success, error for failure.
1796 * Object has to be reserved and unreserved outside!
1798 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1799 struct amdgpu_bo_va *bo_va,
1800 uint64_t saddr, uint64_t offset,
1801 uint64_t size, uint64_t flags)
1803 struct amdgpu_bo_va_mapping *mapping;
1804 struct amdgpu_vm *vm = bo_va->vm;
1808 /* validate the parameters */
1809 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1810 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
1813 /* make sure object fit at this offset */
1814 eaddr = saddr + size - 1;
1815 if (saddr >= eaddr ||
1816 (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo)))
1819 /* Allocate all the needed memory */
1820 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1824 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->vm, saddr, size);
1830 saddr /= AMDGPU_GPU_PAGE_SIZE;
1831 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1833 mapping->start = saddr;
1834 mapping->last = eaddr;
1835 mapping->offset = offset;
1836 mapping->flags = flags;
1838 list_add(&mapping->list, &bo_va->invalids);
1839 amdgpu_vm_it_insert(mapping, &vm->va);
1841 if (flags & AMDGPU_PTE_PRT)
1842 amdgpu_vm_prt_get(adev);
1848 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1850 * @adev: amdgpu_device pointer
1851 * @bo_va: bo_va to remove the address from
1852 * @saddr: where to the BO is mapped
1854 * Remove a mapping of the BO at the specefied addr from the VM.
1855 * Returns 0 for success, error for failure.
1857 * Object has to be reserved and unreserved outside!
1859 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1860 struct amdgpu_bo_va *bo_va,
1863 struct amdgpu_bo_va_mapping *mapping;
1864 struct amdgpu_vm *vm = bo_va->vm;
1867 saddr /= AMDGPU_GPU_PAGE_SIZE;
1869 list_for_each_entry(mapping, &bo_va->valids, list) {
1870 if (mapping->start == saddr)
1874 if (&mapping->list == &bo_va->valids) {
1877 list_for_each_entry(mapping, &bo_va->invalids, list) {
1878 if (mapping->start == saddr)
1882 if (&mapping->list == &bo_va->invalids)
1886 list_del(&mapping->list);
1887 amdgpu_vm_it_remove(mapping, &vm->va);
1888 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1891 list_add(&mapping->list, &vm->freed);
1893 amdgpu_vm_free_mapping(adev, vm, mapping,
1894 bo_va->last_pt_update);
1900 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
1902 * @adev: amdgpu_device pointer
1903 * @vm: VM structure to use
1904 * @saddr: start of the range
1905 * @size: size of the range
1907 * Remove all mappings in a range, split them as appropriate.
1908 * Returns 0 for success, error for failure.
1910 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
1911 struct amdgpu_vm *vm,
1912 uint64_t saddr, uint64_t size)
1914 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
1918 eaddr = saddr + size - 1;
1919 saddr /= AMDGPU_GPU_PAGE_SIZE;
1920 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1922 /* Allocate all the needed memory */
1923 before = kzalloc(sizeof(*before), GFP_KERNEL);
1926 INIT_LIST_HEAD(&before->list);
1928 after = kzalloc(sizeof(*after), GFP_KERNEL);
1933 INIT_LIST_HEAD(&after->list);
1935 /* Now gather all removed mappings */
1936 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1938 /* Remember mapping split at the start */
1939 if (tmp->start < saddr) {
1940 before->start = tmp->start;
1941 before->last = saddr - 1;
1942 before->offset = tmp->offset;
1943 before->flags = tmp->flags;
1944 list_add(&before->list, &tmp->list);
1947 /* Remember mapping split at the end */
1948 if (tmp->last > eaddr) {
1949 after->start = eaddr + 1;
1950 after->last = tmp->last;
1951 after->offset = tmp->offset;
1952 after->offset += after->start - tmp->start;
1953 after->flags = tmp->flags;
1954 list_add(&after->list, &tmp->list);
1957 list_del(&tmp->list);
1958 list_add(&tmp->list, &removed);
1960 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
1963 /* And free them up */
1964 list_for_each_entry_safe(tmp, next, &removed, list) {
1965 amdgpu_vm_it_remove(tmp, &vm->va);
1966 list_del(&tmp->list);
1968 if (tmp->start < saddr)
1970 if (tmp->last > eaddr)
1973 list_add(&tmp->list, &vm->freed);
1974 trace_amdgpu_vm_bo_unmap(NULL, tmp);
1977 /* Insert partial mapping before the range */
1978 if (!list_empty(&before->list)) {
1979 amdgpu_vm_it_insert(before, &vm->va);
1980 if (before->flags & AMDGPU_PTE_PRT)
1981 amdgpu_vm_prt_get(adev);
1986 /* Insert partial mapping after the range */
1987 if (!list_empty(&after->list)) {
1988 amdgpu_vm_it_insert(after, &vm->va);
1989 if (after->flags & AMDGPU_PTE_PRT)
1990 amdgpu_vm_prt_get(adev);
1999 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2001 * @adev: amdgpu_device pointer
2002 * @bo_va: requested bo_va
2004 * Remove @bo_va->bo from the requested vm.
2006 * Object have to be reserved!
2008 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2009 struct amdgpu_bo_va *bo_va)
2011 struct amdgpu_bo_va_mapping *mapping, *next;
2012 struct amdgpu_vm *vm = bo_va->vm;
2014 list_del(&bo_va->bo_list);
2016 spin_lock(&vm->status_lock);
2017 list_del(&bo_va->vm_status);
2018 spin_unlock(&vm->status_lock);
2020 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2021 list_del(&mapping->list);
2022 amdgpu_vm_it_remove(mapping, &vm->va);
2023 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2024 list_add(&mapping->list, &vm->freed);
2026 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2027 list_del(&mapping->list);
2028 amdgpu_vm_it_remove(mapping, &vm->va);
2029 amdgpu_vm_free_mapping(adev, vm, mapping,
2030 bo_va->last_pt_update);
2033 dma_fence_put(bo_va->last_pt_update);
2038 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2040 * @adev: amdgpu_device pointer
2042 * @bo: amdgpu buffer object
2044 * Mark @bo as invalid.
2046 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2047 struct amdgpu_bo *bo)
2049 struct amdgpu_bo_va *bo_va;
2051 list_for_each_entry(bo_va, &bo->va, bo_list) {
2052 spin_lock(&bo_va->vm->status_lock);
2053 if (list_empty(&bo_va->vm_status))
2054 list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
2055 spin_unlock(&bo_va->vm->status_lock);
2060 * amdgpu_vm_init - initialize a vm instance
2062 * @adev: amdgpu_device pointer
2067 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2069 const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
2070 AMDGPU_VM_PTE_COUNT * 8);
2071 unsigned ring_instance;
2072 struct amdgpu_ring *ring;
2073 struct amd_sched_rq *rq;
2076 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2079 vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
2080 spin_lock_init(&vm->status_lock);
2081 INIT_LIST_HEAD(&vm->invalidated);
2082 INIT_LIST_HEAD(&vm->cleared);
2083 INIT_LIST_HEAD(&vm->freed);
2085 /* create scheduler entity for page table updates */
2087 ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
2088 ring_instance %= adev->vm_manager.vm_pte_num_rings;
2089 ring = adev->vm_manager.vm_pte_rings[ring_instance];
2090 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
2091 r = amd_sched_entity_init(&ring->sched, &vm->entity,
2092 rq, amdgpu_sched_jobs);
2096 vm->last_dir_update = NULL;
2098 r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true,
2099 AMDGPU_GEM_DOMAIN_VRAM,
2100 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
2101 AMDGPU_GEM_CREATE_SHADOW |
2102 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
2103 AMDGPU_GEM_CREATE_VRAM_CLEARED,
2104 NULL, NULL, &vm->root.bo);
2106 goto error_free_sched_entity;
2108 r = amdgpu_bo_reserve(vm->root.bo, false);
2110 goto error_free_root;
2112 vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
2113 amdgpu_bo_unreserve(vm->root.bo);
2118 amdgpu_bo_unref(&vm->root.bo->shadow);
2119 amdgpu_bo_unref(&vm->root.bo);
2122 error_free_sched_entity:
2123 amd_sched_entity_fini(&ring->sched, &vm->entity);
2129 * amdgpu_vm_free_levels - free PD/PT levels
2131 * @level: PD/PT starting level to free
2133 * Free the page directory or page table level and all sub levels.
2135 static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level)
2140 amdgpu_bo_unref(&level->bo->shadow);
2141 amdgpu_bo_unref(&level->bo);
2145 for (i = 0; i <= level->last_entry_used; i++)
2146 amdgpu_vm_free_levels(&level->entries[i]);
2148 drm_free_large(level->entries);
2152 * amdgpu_vm_fini - tear down a vm instance
2154 * @adev: amdgpu_device pointer
2158 * Unbind the VM and remove all bos from the vm bo list
2160 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2162 struct amdgpu_bo_va_mapping *mapping, *tmp;
2163 bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt;
2165 amd_sched_entity_fini(vm->entity.sched, &vm->entity);
2167 if (!RB_EMPTY_ROOT(&vm->va)) {
2168 dev_err(adev->dev, "still active bo inside vm\n");
2170 rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, rb) {
2171 list_del(&mapping->list);
2172 amdgpu_vm_it_remove(mapping, &vm->va);
2175 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2176 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2177 amdgpu_vm_prt_fini(adev, vm);
2178 prt_fini_needed = false;
2181 list_del(&mapping->list);
2182 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2185 amdgpu_vm_free_levels(&vm->root);
2186 dma_fence_put(vm->last_dir_update);
2190 * amdgpu_vm_manager_init - init the VM manager
2192 * @adev: amdgpu_device pointer
2194 * Initialize the VM manager structures
2196 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2200 INIT_LIST_HEAD(&adev->vm_manager.ids_lru);
2202 /* skip over VMID 0, since it is the system VM */
2203 for (i = 1; i < adev->vm_manager.num_ids; ++i) {
2204 amdgpu_vm_reset_id(adev, i);
2205 amdgpu_sync_create(&adev->vm_manager.ids[i].active);
2206 list_add_tail(&adev->vm_manager.ids[i].list,
2207 &adev->vm_manager.ids_lru);
2210 adev->vm_manager.fence_context =
2211 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2212 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2213 adev->vm_manager.seqno[i] = 0;
2215 atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
2216 atomic64_set(&adev->vm_manager.client_counter, 0);
2217 spin_lock_init(&adev->vm_manager.prt_lock);
2218 atomic_set(&adev->vm_manager.num_prt_users, 0);
2222 * amdgpu_vm_manager_fini - cleanup VM manager
2224 * @adev: amdgpu_device pointer
2226 * Cleanup the VM manager and free resources.
2228 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2232 for (i = 0; i < AMDGPU_NUM_VM; ++i) {
2233 struct amdgpu_vm_id *id = &adev->vm_manager.ids[i];
2235 dma_fence_put(adev->vm_manager.ids[i].first);
2236 amdgpu_sync_free(&adev->vm_manager.ids[i].active);
2237 dma_fence_put(id->flushed_updates);
2238 dma_fence_put(id->last_flush);