2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/dma-fence-array.h>
29 #include <linux/interval_tree_generic.h>
31 #include <drm/amdgpu_drm.h>
33 #include "amdgpu_trace.h"
37 * GPUVM is similar to the legacy gart on older asics, however
38 * rather than there being a single global gart table
39 * for the entire GPU, there are multiple VM page tables active
40 * at any given time. The VM page tables can contain a mix
41 * vram pages and system memory pages and system memory pages
42 * can be mapped as snooped (cached system pages) or unsnooped
43 * (uncached system pages).
44 * Each VM has an ID associated with it and there is a page table
45 * associated with each VMID. When execting a command buffer,
46 * the kernel tells the the ring what VMID to use for that command
47 * buffer. VMIDs are allocated dynamically as commands are submitted.
48 * The userspace drivers maintain their own address space and the kernel
49 * sets up their pages tables accordingly when they submit their
50 * command buffers and a VMID is assigned.
51 * Cayman/Trinity support up to 8 active VMs at any given time;
55 #define START(node) ((node)->start)
56 #define LAST(node) ((node)->last)
58 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
59 START, LAST, static, amdgpu_vm_it)
64 /* Local structure. Encapsulate some VM table update parameters to reduce
65 * the number of function parameters
67 struct amdgpu_pte_update_params {
68 /* amdgpu device we do this update for */
69 struct amdgpu_device *adev;
70 /* optional amdgpu_vm we do this update for */
72 /* address where to copy page table entries from */
74 /* indirect buffer to fill with commands */
76 /* Function which actually does the update */
77 void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe,
78 uint64_t addr, unsigned count, uint32_t incr,
80 /* indicate update pt or its shadow */
84 /* Helper to disable partial resident texture feature from a fence callback */
85 struct amdgpu_prt_cb {
86 struct amdgpu_device *adev;
87 struct dma_fence_cb cb;
91 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
93 * @adev: amdgpu_device pointer
95 * Calculate the number of entries in a page directory or page table.
97 static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
101 /* For the root directory */
102 return adev->vm_manager.max_pfn >>
103 (adev->vm_manager.block_size *
104 adev->vm_manager.num_level);
105 else if (level == adev->vm_manager.num_level)
106 /* For the page tables on the leaves */
107 return AMDGPU_VM_PTE_COUNT(adev);
109 /* Everything in between */
110 return 1 << adev->vm_manager.block_size;
114 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
116 * @adev: amdgpu_device pointer
118 * Calculate the size of the BO for a page directory or page table in bytes.
120 static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
122 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
126 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
128 * @vm: vm providing the BOs
129 * @validated: head of validation list
130 * @entry: entry to add
132 * Add the page directory to the list of BOs to
133 * validate for command submission.
135 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
136 struct list_head *validated,
137 struct amdgpu_bo_list_entry *entry)
139 entry->robj = vm->root.bo;
141 entry->tv.bo = &entry->robj->tbo;
142 entry->tv.shared = true;
143 entry->user_pages = NULL;
144 list_add(&entry->tv.head, validated);
148 * amdgpu_vm_validate_layer - validate a single page table level
150 * @parent: parent page table level
151 * @validate: callback to do the validation
152 * @param: parameter for the validation callback
154 * Validate the page table BOs on command submission if neccessary.
156 static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent,
157 int (*validate)(void *, struct amdgpu_bo *),
163 if (!parent->entries)
166 for (i = 0; i <= parent->last_entry_used; ++i) {
167 struct amdgpu_vm_pt *entry = &parent->entries[i];
172 r = validate(param, entry->bo);
177 * Recurse into the sub directory. This is harmless because we
178 * have only a maximum of 5 layers.
180 r = amdgpu_vm_validate_level(entry, validate, param);
189 * amdgpu_vm_validate_pt_bos - validate the page table BOs
191 * @adev: amdgpu device pointer
192 * @vm: vm providing the BOs
193 * @validate: callback to do the validation
194 * @param: parameter for the validation callback
196 * Validate the page table BOs on command submission if neccessary.
198 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
199 int (*validate)(void *p, struct amdgpu_bo *bo),
202 uint64_t num_evictions;
204 /* We only need to validate the page tables
205 * if they aren't already valid.
207 num_evictions = atomic64_read(&adev->num_evictions);
208 if (num_evictions == vm->last_eviction_counter)
211 return amdgpu_vm_validate_level(&vm->root, validate, param);
215 * amdgpu_vm_move_level_in_lru - move one level of PT BOs to the LRU tail
217 * @adev: amdgpu device instance
218 * @vm: vm providing the BOs
220 * Move the PT BOs to the tail of the LRU.
222 static void amdgpu_vm_move_level_in_lru(struct amdgpu_vm_pt *parent)
226 if (!parent->entries)
229 for (i = 0; i <= parent->last_entry_used; ++i) {
230 struct amdgpu_vm_pt *entry = &parent->entries[i];
235 ttm_bo_move_to_lru_tail(&entry->bo->tbo);
236 amdgpu_vm_move_level_in_lru(entry);
241 * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
243 * @adev: amdgpu device instance
244 * @vm: vm providing the BOs
246 * Move the PT BOs to the tail of the LRU.
248 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
249 struct amdgpu_vm *vm)
251 struct ttm_bo_global *glob = adev->mman.bdev.glob;
253 spin_lock(&glob->lru_lock);
254 amdgpu_vm_move_level_in_lru(&vm->root);
255 spin_unlock(&glob->lru_lock);
259 * amdgpu_vm_alloc_levels - allocate the PD/PT levels
261 * @adev: amdgpu_device pointer
263 * @saddr: start of the address range
264 * @eaddr: end of the address range
266 * Make sure the page directories and page tables are allocated
268 static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
269 struct amdgpu_vm *vm,
270 struct amdgpu_vm_pt *parent,
271 uint64_t saddr, uint64_t eaddr,
274 unsigned shift = (adev->vm_manager.num_level - level) *
275 adev->vm_manager.block_size;
276 unsigned pt_idx, from, to;
279 if (!parent->entries) {
280 unsigned num_entries = amdgpu_vm_num_entries(adev, level);
282 parent->entries = drm_calloc_large(num_entries,
283 sizeof(struct amdgpu_vm_pt));
284 if (!parent->entries)
286 memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt));
289 from = saddr >> shift;
291 if (from >= amdgpu_vm_num_entries(adev, level) ||
292 to >= amdgpu_vm_num_entries(adev, level))
295 if (to > parent->last_entry_used)
296 parent->last_entry_used = to;
299 saddr = saddr & ((1 << shift) - 1);
300 eaddr = eaddr & ((1 << shift) - 1);
302 /* walk over the address space and allocate the page tables */
303 for (pt_idx = from; pt_idx <= to; ++pt_idx) {
304 struct reservation_object *resv = vm->root.bo->tbo.resv;
305 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
306 struct amdgpu_bo *pt;
309 r = amdgpu_bo_create(adev,
310 amdgpu_vm_bo_size(adev, level),
311 AMDGPU_GPU_PAGE_SIZE, true,
312 AMDGPU_GEM_DOMAIN_VRAM,
313 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
314 AMDGPU_GEM_CREATE_SHADOW |
315 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
316 AMDGPU_GEM_CREATE_VRAM_CLEARED,
321 /* Keep a reference to the root directory to avoid
322 * freeing them up in the wrong order.
324 pt->parent = amdgpu_bo_ref(vm->root.bo);
330 if (level < adev->vm_manager.num_level) {
331 uint64_t sub_saddr = (pt_idx == from) ? saddr : 0;
332 uint64_t sub_eaddr = (pt_idx == to) ? eaddr :
334 r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr,
345 * amdgpu_vm_alloc_pts - Allocate page tables.
347 * @adev: amdgpu_device pointer
348 * @vm: VM to allocate page tables for
349 * @saddr: Start address which needs to be allocated
350 * @size: Size from start address we need.
352 * Make sure the page tables are allocated.
354 int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
355 struct amdgpu_vm *vm,
356 uint64_t saddr, uint64_t size)
361 /* validate the parameters */
362 if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK)
365 eaddr = saddr + size - 1;
366 last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
367 if (last_pfn >= adev->vm_manager.max_pfn) {
368 dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
369 last_pfn, adev->vm_manager.max_pfn);
373 saddr /= AMDGPU_GPU_PAGE_SIZE;
374 eaddr /= AMDGPU_GPU_PAGE_SIZE;
376 return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0);
380 * amdgpu_vm_had_gpu_reset - check if reset occured since last use
382 * @adev: amdgpu_device pointer
383 * @id: VMID structure
385 * Check if GPU reset occured since last use of the VMID.
387 static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev,
388 struct amdgpu_vm_id *id)
390 return id->current_gpu_reset_count !=
391 atomic_read(&adev->gpu_reset_counter);
395 * amdgpu_vm_grab_id - allocate the next free VMID
397 * @vm: vm to allocate id for
398 * @ring: ring we want to submit job to
399 * @sync: sync object where we add dependencies
400 * @fence: fence protecting ID from reuse
402 * Allocate an id for the vm, adding fences to the sync obj as necessary.
404 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
405 struct amdgpu_sync *sync, struct dma_fence *fence,
406 struct amdgpu_job *job)
408 struct amdgpu_device *adev = ring->adev;
409 unsigned vmhub = ring->funcs->vmhub;
410 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
411 uint64_t fence_context = adev->fence_context + ring->idx;
412 struct dma_fence *updates = sync->last_vm_update;
413 struct amdgpu_vm_id *id, *idle;
414 struct dma_fence **fences;
418 fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL);
422 mutex_lock(&id_mgr->lock);
424 /* Check if we have an idle VMID */
426 list_for_each_entry(idle, &id_mgr->ids_lru, list) {
427 fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
433 /* If we can't find a idle VMID to use, wait till one becomes available */
434 if (&idle->list == &id_mgr->ids_lru) {
435 u64 fence_context = adev->vm_manager.fence_context + ring->idx;
436 unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
437 struct dma_fence_array *array;
440 for (j = 0; j < i; ++j)
441 dma_fence_get(fences[j]);
443 array = dma_fence_array_create(i, fences, fence_context,
446 for (j = 0; j < i; ++j)
447 dma_fence_put(fences[j]);
454 r = amdgpu_sync_fence(ring->adev, sync, &array->base);
455 dma_fence_put(&array->base);
459 mutex_unlock(&id_mgr->lock);
465 job->vm_needs_flush = false;
466 /* Check if we can use a VMID already assigned to this VM */
467 list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) {
468 struct dma_fence *flushed;
469 bool needs_flush = false;
471 /* Check all the prerequisites to using this VMID */
472 if (amdgpu_vm_had_gpu_reset(adev, id))
475 if (atomic64_read(&id->owner) != vm->client_id)
478 if (job->vm_pd_addr != id->pd_gpu_addr)
481 if (!id->last_flush ||
482 (id->last_flush->context != fence_context &&
483 !dma_fence_is_signaled(id->last_flush)))
486 flushed = id->flushed_updates;
487 if (updates && (!flushed || dma_fence_is_later(updates, flushed)))
490 /* Concurrent flushes are only possible starting with Vega10 */
491 if (adev->asic_type < CHIP_VEGA10 && needs_flush)
494 /* Good we can use this VMID. Remember this submission as
497 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
501 if (updates && (!flushed || dma_fence_is_later(updates, flushed))) {
502 dma_fence_put(id->flushed_updates);
503 id->flushed_updates = dma_fence_get(updates);
509 goto no_flush_needed;
513 /* Still no ID to use? Then use the idle one found earlier */
516 /* Remember this submission as user of the VMID */
517 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
521 id->pd_gpu_addr = job->vm_pd_addr;
522 dma_fence_put(id->flushed_updates);
523 id->flushed_updates = dma_fence_get(updates);
524 id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter);
525 atomic64_set(&id->owner, vm->client_id);
528 job->vm_needs_flush = true;
529 dma_fence_put(id->last_flush);
530 id->last_flush = NULL;
533 list_move_tail(&id->list, &id_mgr->ids_lru);
535 job->vm_id = id - id_mgr->ids;
536 trace_amdgpu_vm_grab_id(vm, ring, job);
539 mutex_unlock(&id_mgr->lock);
543 static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring)
545 struct amdgpu_device *adev = ring->adev;
546 const struct amdgpu_ip_block *ip_block;
548 if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
549 /* only compute rings */
552 ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
556 if (ip_block->version->major <= 7) {
557 /* gfx7 has no workaround */
559 } else if (ip_block->version->major == 8) {
560 if (adev->gfx.mec_fw_version >= 673)
561 /* gfx8 is fixed in MEC firmware 673 */
569 static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr)
573 if (adev->gart.gart_funcs->adjust_mc_addr)
574 addr = adev->gart.gart_funcs->adjust_mc_addr(adev, addr);
580 * amdgpu_vm_flush - hardware flush the vm
582 * @ring: ring to use for flush
583 * @vm_id: vmid number to use
584 * @pd_addr: address of the page directory
586 * Emit a VM flush when it is necessary.
588 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
590 struct amdgpu_device *adev = ring->adev;
591 unsigned vmhub = ring->funcs->vmhub;
592 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
593 struct amdgpu_vm_id *id = &id_mgr->ids[job->vm_id];
594 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
595 id->gds_base != job->gds_base ||
596 id->gds_size != job->gds_size ||
597 id->gws_base != job->gws_base ||
598 id->gws_size != job->gws_size ||
599 id->oa_base != job->oa_base ||
600 id->oa_size != job->oa_size);
601 bool vm_flush_needed = job->vm_needs_flush ||
602 amdgpu_vm_ring_has_compute_vm_bug(ring);
603 unsigned patch_offset = 0;
606 if (amdgpu_vm_had_gpu_reset(adev, id)) {
607 gds_switch_needed = true;
608 vm_flush_needed = true;
611 if (!vm_flush_needed && !gds_switch_needed)
614 if (ring->funcs->init_cond_exec)
615 patch_offset = amdgpu_ring_init_cond_exec(ring);
617 if (ring->funcs->emit_pipeline_sync && !job->need_pipeline_sync)
618 amdgpu_ring_emit_pipeline_sync(ring);
620 if (ring->funcs->emit_vm_flush && vm_flush_needed) {
621 u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);
622 struct dma_fence *fence;
624 trace_amdgpu_vm_flush(ring, job->vm_id, pd_addr);
625 amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr);
627 r = amdgpu_fence_emit(ring, &fence);
631 mutex_lock(&id_mgr->lock);
632 dma_fence_put(id->last_flush);
633 id->last_flush = fence;
634 mutex_unlock(&id_mgr->lock);
637 if (gds_switch_needed) {
638 id->gds_base = job->gds_base;
639 id->gds_size = job->gds_size;
640 id->gws_base = job->gws_base;
641 id->gws_size = job->gws_size;
642 id->oa_base = job->oa_base;
643 id->oa_size = job->oa_size;
644 amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base,
645 job->gds_size, job->gws_base,
646 job->gws_size, job->oa_base,
650 if (ring->funcs->patch_cond_exec)
651 amdgpu_ring_patch_cond_exec(ring, patch_offset);
653 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
654 if (ring->funcs->emit_switch_buffer) {
655 amdgpu_ring_emit_switch_buffer(ring);
656 amdgpu_ring_emit_switch_buffer(ring);
662 * amdgpu_vm_reset_id - reset VMID to zero
664 * @adev: amdgpu device structure
665 * @vm_id: vmid number to use
667 * Reset saved GDW, GWS and OA to force switch on next flush.
669 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
672 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
673 struct amdgpu_vm_id *id = &id_mgr->ids[vmid];
684 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
687 * @bo: requested buffer object
689 * Find @bo inside the requested vm.
690 * Search inside the @bos vm list for the requested vm
691 * Returns the found bo_va or NULL if none is found
693 * Object has to be reserved!
695 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
696 struct amdgpu_bo *bo)
698 struct amdgpu_bo_va *bo_va;
700 list_for_each_entry(bo_va, &bo->va, bo_list) {
701 if (bo_va->vm == vm) {
709 * amdgpu_vm_do_set_ptes - helper to call the right asic function
711 * @params: see amdgpu_pte_update_params definition
712 * @pe: addr of the page entry
713 * @addr: dst addr to write into pe
714 * @count: number of page entries to update
715 * @incr: increase next addr by incr bytes
716 * @flags: hw access flags
718 * Traces the parameters and calls the right asic functions
719 * to setup the page table using the DMA.
721 static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
722 uint64_t pe, uint64_t addr,
723 unsigned count, uint32_t incr,
726 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
729 amdgpu_vm_write_pte(params->adev, params->ib, pe,
730 addr | flags, count, incr);
733 amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr,
739 * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
741 * @params: see amdgpu_pte_update_params definition
742 * @pe: addr of the page entry
743 * @addr: dst addr to write into pe
744 * @count: number of page entries to update
745 * @incr: increase next addr by incr bytes
746 * @flags: hw access flags
748 * Traces the parameters and calls the DMA function to copy the PTEs.
750 static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
751 uint64_t pe, uint64_t addr,
752 unsigned count, uint32_t incr,
755 uint64_t src = (params->src + (addr >> 12) * 8);
758 trace_amdgpu_vm_copy_ptes(pe, src, count);
760 amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count);
764 * amdgpu_vm_map_gart - Resolve gart mapping of addr
766 * @pages_addr: optional DMA address to use for lookup
767 * @addr: the unmapped addr
769 * Look up the physical address of the page that the pte resolves
770 * to and return the pointer for the page table entry.
772 static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
776 /* page table offset */
777 result = pages_addr[addr >> PAGE_SHIFT];
779 /* in case cpu page size != gpu page size*/
780 result |= addr & (~PAGE_MASK);
782 result &= 0xFFFFFFFFFFFFF000ULL;
788 * amdgpu_vm_update_level - update a single level in the hierarchy
790 * @adev: amdgpu_device pointer
792 * @parent: parent directory
794 * Makes sure all entries in @parent are up to date.
795 * Returns 0 for success, error for failure.
797 static int amdgpu_vm_update_level(struct amdgpu_device *adev,
798 struct amdgpu_vm *vm,
799 struct amdgpu_vm_pt *parent,
802 struct amdgpu_bo *shadow;
803 struct amdgpu_ring *ring;
804 uint64_t pd_addr, shadow_addr;
805 uint32_t incr = amdgpu_vm_bo_size(adev, level + 1);
806 uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0;
807 unsigned count = 0, pt_idx, ndw;
808 struct amdgpu_job *job;
809 struct amdgpu_pte_update_params params;
810 struct dma_fence *fence = NULL;
814 if (!parent->entries)
816 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
821 /* assume the worst case */
822 ndw += parent->last_entry_used * 6;
824 pd_addr = amdgpu_bo_gpu_offset(parent->bo);
826 shadow = parent->bo->shadow;
828 r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem);
831 shadow_addr = amdgpu_bo_gpu_offset(shadow);
837 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
841 memset(¶ms, 0, sizeof(params));
843 params.ib = &job->ibs[0];
845 /* walk over the address space and update the directory */
846 for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
847 struct amdgpu_bo *bo = parent->entries[pt_idx].bo;
854 struct amdgpu_bo *pt_shadow = bo->shadow;
856 r = amdgpu_ttm_bind(&pt_shadow->tbo,
857 &pt_shadow->tbo.mem);
862 pt = amdgpu_bo_gpu_offset(bo);
863 if (parent->entries[pt_idx].addr == pt)
866 parent->entries[pt_idx].addr = pt;
868 pde = pd_addr + pt_idx * 8;
869 if (((last_pde + 8 * count) != pde) ||
870 ((last_pt + incr * count) != pt) ||
871 (count == AMDGPU_VM_MAX_UPDATE_SIZE)) {
875 amdgpu_vm_adjust_mc_addr(adev, last_pt);
878 amdgpu_vm_do_set_ptes(¶ms,
884 amdgpu_vm_do_set_ptes(¶ms, last_pde,
885 pt_addr, count, incr,
891 last_shadow = shadow_addr + pt_idx * 8;
899 uint64_t pt_addr = amdgpu_vm_adjust_mc_addr(adev, last_pt);
901 if (vm->root.bo->shadow)
902 amdgpu_vm_do_set_ptes(¶ms, last_shadow, pt_addr,
903 count, incr, AMDGPU_PTE_VALID);
905 amdgpu_vm_do_set_ptes(¶ms, last_pde, pt_addr,
906 count, incr, AMDGPU_PTE_VALID);
909 if (params.ib->length_dw == 0) {
910 amdgpu_job_free(job);
912 amdgpu_ring_pad_ib(ring, params.ib);
913 amdgpu_sync_resv(adev, &job->sync, parent->bo->tbo.resv,
914 AMDGPU_FENCE_OWNER_VM);
916 amdgpu_sync_resv(adev, &job->sync, shadow->tbo.resv,
917 AMDGPU_FENCE_OWNER_VM);
919 WARN_ON(params.ib->length_dw > ndw);
920 r = amdgpu_job_submit(job, ring, &vm->entity,
921 AMDGPU_FENCE_OWNER_VM, &fence);
925 amdgpu_bo_fence(parent->bo, fence, true);
926 dma_fence_put(vm->last_dir_update);
927 vm->last_dir_update = dma_fence_get(fence);
928 dma_fence_put(fence);
931 * Recurse into the subdirectories. This recursion is harmless because
932 * we only have a maximum of 5 layers.
934 for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
935 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
940 r = amdgpu_vm_update_level(adev, vm, entry, level + 1);
948 amdgpu_job_free(job);
953 * amdgpu_vm_update_directories - make sure that all directories are valid
955 * @adev: amdgpu_device pointer
958 * Makes sure all directories are up to date.
959 * Returns 0 for success, error for failure.
961 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
962 struct amdgpu_vm *vm)
964 return amdgpu_vm_update_level(adev, vm, &vm->root, 0);
968 * amdgpu_vm_find_pt - find the page table for an address
970 * @p: see amdgpu_pte_update_params definition
971 * @addr: virtual address in question
973 * Find the page table BO for a virtual address, return NULL when none found.
975 static struct amdgpu_bo *amdgpu_vm_get_pt(struct amdgpu_pte_update_params *p,
978 struct amdgpu_vm_pt *entry = &p->vm->root;
979 unsigned idx, level = p->adev->vm_manager.num_level;
981 while (entry->entries) {
982 idx = addr >> (p->adev->vm_manager.block_size * level--);
983 idx %= amdgpu_bo_size(entry->bo) / 8;
984 entry = &entry->entries[idx];
994 * amdgpu_vm_update_ptes - make sure that page tables are valid
996 * @params: see amdgpu_pte_update_params definition
998 * @start: start of GPU address range
999 * @end: end of GPU address range
1000 * @dst: destination address to map to, the next dst inside the function
1001 * @flags: mapping flags
1003 * Update the page tables in the range @start - @end.
1005 static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
1006 uint64_t start, uint64_t end,
1007 uint64_t dst, uint64_t flags)
1009 struct amdgpu_device *adev = params->adev;
1010 const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1;
1012 uint64_t cur_pe_start, cur_nptes, cur_dst;
1013 uint64_t addr; /* next GPU address to be updated */
1014 struct amdgpu_bo *pt;
1015 unsigned nptes; /* next number of ptes to be updated */
1016 uint64_t next_pe_start;
1018 /* initialize the variables */
1020 pt = amdgpu_vm_get_pt(params, addr);
1022 pr_err("PT not found, aborting update_ptes\n");
1026 if (params->shadow) {
1031 if ((addr & ~mask) == (end & ~mask))
1034 nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
1036 cur_pe_start = amdgpu_bo_gpu_offset(pt);
1037 cur_pe_start += (addr & mask) * 8;
1043 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
1045 /* walk over the address space and update the page tables */
1046 while (addr < end) {
1047 pt = amdgpu_vm_get_pt(params, addr);
1049 pr_err("PT not found, aborting update_ptes\n");
1053 if (params->shadow) {
1059 if ((addr & ~mask) == (end & ~mask))
1062 nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
1064 next_pe_start = amdgpu_bo_gpu_offset(pt);
1065 next_pe_start += (addr & mask) * 8;
1067 if ((cur_pe_start + 8 * cur_nptes) == next_pe_start &&
1068 ((cur_nptes + nptes) <= AMDGPU_VM_MAX_UPDATE_SIZE)) {
1069 /* The next ptb is consecutive to current ptb.
1070 * Don't call the update function now.
1071 * Will update two ptbs together in future.
1075 params->func(params, cur_pe_start, cur_dst, cur_nptes,
1076 AMDGPU_GPU_PAGE_SIZE, flags);
1078 cur_pe_start = next_pe_start;
1085 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
1088 params->func(params, cur_pe_start, cur_dst, cur_nptes,
1089 AMDGPU_GPU_PAGE_SIZE, flags);
1093 * amdgpu_vm_frag_ptes - add fragment information to PTEs
1095 * @params: see amdgpu_pte_update_params definition
1097 * @start: first PTE to handle
1098 * @end: last PTE to handle
1099 * @dst: addr those PTEs should point to
1100 * @flags: hw mapping flags
1102 static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
1103 uint64_t start, uint64_t end,
1104 uint64_t dst, uint64_t flags)
1107 * The MC L1 TLB supports variable sized pages, based on a fragment
1108 * field in the PTE. When this field is set to a non-zero value, page
1109 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1110 * flags are considered valid for all PTEs within the fragment range
1111 * and corresponding mappings are assumed to be physically contiguous.
1113 * The L1 TLB can store a single PTE for the whole fragment,
1114 * significantly increasing the space available for translation
1115 * caching. This leads to large improvements in throughput when the
1116 * TLB is under pressure.
1118 * The L2 TLB distributes small and large fragments into two
1119 * asymmetric partitions. The large fragment cache is significantly
1120 * larger. Thus, we try to use large fragments wherever possible.
1121 * Userspace can support this by aligning virtual base address and
1122 * allocation size to the fragment size.
1125 /* SI and newer are optimized for 64KB */
1126 uint64_t frag_flags = AMDGPU_PTE_FRAG(AMDGPU_LOG2_PAGES_PER_FRAG);
1127 uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG;
1129 uint64_t frag_start = ALIGN(start, frag_align);
1130 uint64_t frag_end = end & ~(frag_align - 1);
1132 /* system pages are non continuously */
1133 if (params->src || !(flags & AMDGPU_PTE_VALID) ||
1134 (frag_start >= frag_end)) {
1136 amdgpu_vm_update_ptes(params, start, end, dst, flags);
1140 /* handle the 4K area at the beginning */
1141 if (start != frag_start) {
1142 amdgpu_vm_update_ptes(params, start, frag_start,
1144 dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE;
1147 /* handle the area in the middle */
1148 amdgpu_vm_update_ptes(params, frag_start, frag_end, dst,
1149 flags | frag_flags);
1151 /* handle the 4K area at the end */
1152 if (frag_end != end) {
1153 dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE;
1154 amdgpu_vm_update_ptes(params, frag_end, end, dst, flags);
1159 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1161 * @adev: amdgpu_device pointer
1162 * @exclusive: fence we need to sync to
1163 * @src: address where to copy page table entries from
1164 * @pages_addr: DMA addresses to use for mapping
1166 * @start: start of mapped range
1167 * @last: last mapped entry
1168 * @flags: flags for the entries
1169 * @addr: addr to set the area to
1170 * @fence: optional resulting fence
1172 * Fill in the page table entries between @start and @last.
1173 * Returns 0 for success, -EINVAL for failure.
1175 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1176 struct dma_fence *exclusive,
1178 dma_addr_t *pages_addr,
1179 struct amdgpu_vm *vm,
1180 uint64_t start, uint64_t last,
1181 uint64_t flags, uint64_t addr,
1182 struct dma_fence **fence)
1184 struct amdgpu_ring *ring;
1185 void *owner = AMDGPU_FENCE_OWNER_VM;
1186 unsigned nptes, ncmds, ndw;
1187 struct amdgpu_job *job;
1188 struct amdgpu_pte_update_params params;
1189 struct dma_fence *f = NULL;
1192 memset(¶ms, 0, sizeof(params));
1197 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
1199 /* sync to everything on unmapping */
1200 if (!(flags & AMDGPU_PTE_VALID))
1201 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
1203 nptes = last - start + 1;
1206 * reserve space for one command every (1 << BLOCK_SIZE)
1207 * entries or 2k dwords (whatever is smaller)
1209 ncmds = (nptes >> min(adev->vm_manager.block_size, 11u)) + 1;
1215 /* only copy commands needed */
1218 params.func = amdgpu_vm_do_copy_ptes;
1220 } else if (pages_addr) {
1221 /* copy commands needed */
1227 params.func = amdgpu_vm_do_copy_ptes;
1230 /* set page commands needed */
1233 /* two extra commands for begin/end of fragment */
1236 params.func = amdgpu_vm_do_set_ptes;
1239 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1243 params.ib = &job->ibs[0];
1245 if (!src && pages_addr) {
1249 /* Put the PTEs at the end of the IB. */
1250 i = ndw - nptes * 2;
1251 pte= (uint64_t *)&(job->ibs->ptr[i]);
1252 params.src = job->ibs->gpu_addr + i * 4;
1254 for (i = 0; i < nptes; ++i) {
1255 pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i *
1256 AMDGPU_GPU_PAGE_SIZE);
1262 r = amdgpu_sync_fence(adev, &job->sync, exclusive);
1266 r = amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv,
1271 r = reservation_object_reserve_shared(vm->root.bo->tbo.resv);
1275 params.shadow = true;
1276 amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags);
1277 params.shadow = false;
1278 amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags);
1280 amdgpu_ring_pad_ib(ring, params.ib);
1281 WARN_ON(params.ib->length_dw > ndw);
1282 r = amdgpu_job_submit(job, ring, &vm->entity,
1283 AMDGPU_FENCE_OWNER_VM, &f);
1287 amdgpu_bo_fence(vm->root.bo, f, true);
1288 dma_fence_put(*fence);
1293 amdgpu_job_free(job);
1298 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1300 * @adev: amdgpu_device pointer
1301 * @exclusive: fence we need to sync to
1302 * @gtt_flags: flags as they are used for GTT
1303 * @pages_addr: DMA addresses to use for mapping
1305 * @mapping: mapped range and flags to use for the update
1306 * @flags: HW flags for the mapping
1307 * @nodes: array of drm_mm_nodes with the MC addresses
1308 * @fence: optional resulting fence
1310 * Split the mapping into smaller chunks so that each update fits
1312 * Returns 0 for success, -EINVAL for failure.
1314 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1315 struct dma_fence *exclusive,
1317 dma_addr_t *pages_addr,
1318 struct amdgpu_vm *vm,
1319 struct amdgpu_bo_va_mapping *mapping,
1321 struct drm_mm_node *nodes,
1322 struct dma_fence **fence)
1324 uint64_t pfn, src = 0, start = mapping->start;
1327 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1328 * but in case of something, we filter the flags in first place
1330 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1331 flags &= ~AMDGPU_PTE_READABLE;
1332 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1333 flags &= ~AMDGPU_PTE_WRITEABLE;
1335 flags &= ~AMDGPU_PTE_EXECUTABLE;
1336 flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1338 flags &= ~AMDGPU_PTE_MTYPE_MASK;
1339 flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
1341 if ((mapping->flags & AMDGPU_PTE_PRT) &&
1342 (adev->asic_type >= CHIP_VEGA10)) {
1343 flags |= AMDGPU_PTE_PRT;
1344 flags &= ~AMDGPU_PTE_VALID;
1347 trace_amdgpu_vm_bo_update(mapping);
1349 pfn = mapping->offset >> PAGE_SHIFT;
1351 while (pfn >= nodes->size) {
1358 uint64_t max_entries;
1359 uint64_t addr, last;
1362 addr = nodes->start << PAGE_SHIFT;
1363 max_entries = (nodes->size - pfn) *
1364 (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
1367 max_entries = S64_MAX;
1371 if (flags == gtt_flags)
1372 src = adev->gart.table_addr +
1373 (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8;
1375 max_entries = min(max_entries, 16ull * 1024ull);
1377 } else if (flags & AMDGPU_PTE_VALID) {
1378 addr += adev->vm_manager.vram_base_offset;
1380 addr += pfn << PAGE_SHIFT;
1382 last = min((uint64_t)mapping->last, start + max_entries - 1);
1383 r = amdgpu_vm_bo_update_mapping(adev, exclusive,
1384 src, pages_addr, vm,
1385 start, last, flags, addr,
1390 pfn += last - start + 1;
1391 if (nodes && nodes->size == pfn) {
1397 } while (unlikely(start != mapping->last + 1));
1403 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1405 * @adev: amdgpu_device pointer
1406 * @bo_va: requested BO and VM object
1407 * @clear: if true clear the entries
1409 * Fill in the page table entries for @bo_va.
1410 * Returns 0 for success, -EINVAL for failure.
1412 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1413 struct amdgpu_bo_va *bo_va,
1416 struct amdgpu_vm *vm = bo_va->vm;
1417 struct amdgpu_bo_va_mapping *mapping;
1418 dma_addr_t *pages_addr = NULL;
1419 uint64_t gtt_flags, flags;
1420 struct ttm_mem_reg *mem;
1421 struct drm_mm_node *nodes;
1422 struct dma_fence *exclusive;
1425 if (clear || !bo_va->bo) {
1430 struct ttm_dma_tt *ttm;
1432 mem = &bo_va->bo->tbo.mem;
1433 nodes = mem->mm_node;
1434 if (mem->mem_type == TTM_PL_TT) {
1435 ttm = container_of(bo_va->bo->tbo.ttm, struct
1437 pages_addr = ttm->dma_address;
1439 exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv);
1443 flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
1444 gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) &&
1445 adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ?
1452 spin_lock(&vm->status_lock);
1453 if (!list_empty(&bo_va->vm_status))
1454 list_splice_init(&bo_va->valids, &bo_va->invalids);
1455 spin_unlock(&vm->status_lock);
1457 list_for_each_entry(mapping, &bo_va->invalids, list) {
1458 r = amdgpu_vm_bo_split_mapping(adev, exclusive,
1459 gtt_flags, pages_addr, vm,
1460 mapping, flags, nodes,
1461 &bo_va->last_pt_update);
1466 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1467 list_for_each_entry(mapping, &bo_va->valids, list)
1468 trace_amdgpu_vm_bo_mapping(mapping);
1470 list_for_each_entry(mapping, &bo_va->invalids, list)
1471 trace_amdgpu_vm_bo_mapping(mapping);
1474 spin_lock(&vm->status_lock);
1475 list_splice_init(&bo_va->invalids, &bo_va->valids);
1476 list_del_init(&bo_va->vm_status);
1478 list_add(&bo_va->vm_status, &vm->cleared);
1479 spin_unlock(&vm->status_lock);
1485 * amdgpu_vm_update_prt_state - update the global PRT state
1487 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1489 unsigned long flags;
1492 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1493 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1494 adev->gart.gart_funcs->set_prt(adev, enable);
1495 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1499 * amdgpu_vm_prt_get - add a PRT user
1501 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1503 if (!adev->gart.gart_funcs->set_prt)
1506 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1507 amdgpu_vm_update_prt_state(adev);
1511 * amdgpu_vm_prt_put - drop a PRT user
1513 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1515 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1516 amdgpu_vm_update_prt_state(adev);
1520 * amdgpu_vm_prt_cb - callback for updating the PRT status
1522 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1524 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1526 amdgpu_vm_prt_put(cb->adev);
1531 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1533 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1534 struct dma_fence *fence)
1536 struct amdgpu_prt_cb *cb;
1538 if (!adev->gart.gart_funcs->set_prt)
1541 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1543 /* Last resort when we are OOM */
1545 dma_fence_wait(fence, false);
1547 amdgpu_vm_prt_put(adev);
1550 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1552 amdgpu_vm_prt_cb(fence, &cb->cb);
1557 * amdgpu_vm_free_mapping - free a mapping
1559 * @adev: amdgpu_device pointer
1561 * @mapping: mapping to be freed
1562 * @fence: fence of the unmap operation
1564 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1566 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1567 struct amdgpu_vm *vm,
1568 struct amdgpu_bo_va_mapping *mapping,
1569 struct dma_fence *fence)
1571 if (mapping->flags & AMDGPU_PTE_PRT)
1572 amdgpu_vm_add_prt_cb(adev, fence);
1577 * amdgpu_vm_prt_fini - finish all prt mappings
1579 * @adev: amdgpu_device pointer
1582 * Register a cleanup callback to disable PRT support after VM dies.
1584 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1586 struct reservation_object *resv = vm->root.bo->tbo.resv;
1587 struct dma_fence *excl, **shared;
1588 unsigned i, shared_count;
1591 r = reservation_object_get_fences_rcu(resv, &excl,
1592 &shared_count, &shared);
1594 /* Not enough memory to grab the fence list, as last resort
1595 * block for all the fences to complete.
1597 reservation_object_wait_timeout_rcu(resv, true, false,
1598 MAX_SCHEDULE_TIMEOUT);
1602 /* Add a callback for each fence in the reservation object */
1603 amdgpu_vm_prt_get(adev);
1604 amdgpu_vm_add_prt_cb(adev, excl);
1606 for (i = 0; i < shared_count; ++i) {
1607 amdgpu_vm_prt_get(adev);
1608 amdgpu_vm_add_prt_cb(adev, shared[i]);
1615 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1617 * @adev: amdgpu_device pointer
1619 * @fence: optional resulting fence (unchanged if no work needed to be done
1620 * or if an error occurred)
1622 * Make sure all freed BOs are cleared in the PT.
1623 * Returns 0 for success.
1625 * PTs have to be reserved and mutex must be locked!
1627 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1628 struct amdgpu_vm *vm,
1629 struct dma_fence **fence)
1631 struct amdgpu_bo_va_mapping *mapping;
1632 struct dma_fence *f = NULL;
1635 while (!list_empty(&vm->freed)) {
1636 mapping = list_first_entry(&vm->freed,
1637 struct amdgpu_bo_va_mapping, list);
1638 list_del(&mapping->list);
1640 r = amdgpu_vm_bo_update_mapping(adev, NULL, 0, NULL, vm,
1641 mapping->start, mapping->last,
1643 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1651 dma_fence_put(*fence);
1662 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
1664 * @adev: amdgpu_device pointer
1667 * Make sure all invalidated BOs are cleared in the PT.
1668 * Returns 0 for success.
1670 * PTs have to be reserved and mutex must be locked!
1672 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
1673 struct amdgpu_vm *vm, struct amdgpu_sync *sync)
1675 struct amdgpu_bo_va *bo_va = NULL;
1678 spin_lock(&vm->status_lock);
1679 while (!list_empty(&vm->invalidated)) {
1680 bo_va = list_first_entry(&vm->invalidated,
1681 struct amdgpu_bo_va, vm_status);
1682 spin_unlock(&vm->status_lock);
1684 r = amdgpu_vm_bo_update(adev, bo_va, true);
1688 spin_lock(&vm->status_lock);
1690 spin_unlock(&vm->status_lock);
1693 r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update);
1699 * amdgpu_vm_bo_add - add a bo to a specific vm
1701 * @adev: amdgpu_device pointer
1703 * @bo: amdgpu buffer object
1705 * Add @bo into the requested vm.
1706 * Add @bo to the list of bos associated with the vm
1707 * Returns newly added bo_va or NULL for failure
1709 * Object has to be reserved!
1711 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1712 struct amdgpu_vm *vm,
1713 struct amdgpu_bo *bo)
1715 struct amdgpu_bo_va *bo_va;
1717 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1718 if (bo_va == NULL) {
1723 bo_va->ref_count = 1;
1724 INIT_LIST_HEAD(&bo_va->bo_list);
1725 INIT_LIST_HEAD(&bo_va->valids);
1726 INIT_LIST_HEAD(&bo_va->invalids);
1727 INIT_LIST_HEAD(&bo_va->vm_status);
1730 list_add_tail(&bo_va->bo_list, &bo->va);
1736 * amdgpu_vm_bo_map - map bo inside a vm
1738 * @adev: amdgpu_device pointer
1739 * @bo_va: bo_va to store the address
1740 * @saddr: where to map the BO
1741 * @offset: requested offset in the BO
1742 * @flags: attributes of pages (read/write/valid/etc.)
1744 * Add a mapping of the BO at the specefied addr into the VM.
1745 * Returns 0 for success, error for failure.
1747 * Object has to be reserved and unreserved outside!
1749 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1750 struct amdgpu_bo_va *bo_va,
1751 uint64_t saddr, uint64_t offset,
1752 uint64_t size, uint64_t flags)
1754 struct amdgpu_bo_va_mapping *mapping, *tmp;
1755 struct amdgpu_vm *vm = bo_va->vm;
1758 /* validate the parameters */
1759 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1760 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
1763 /* make sure object fit at this offset */
1764 eaddr = saddr + size - 1;
1765 if (saddr >= eaddr ||
1766 (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo)))
1769 saddr /= AMDGPU_GPU_PAGE_SIZE;
1770 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1772 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1774 /* bo and tmp overlap, invalid addr */
1775 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1776 "0x%010Lx-0x%010Lx\n", bo_va->bo, saddr, eaddr,
1777 tmp->start, tmp->last + 1);
1781 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1785 INIT_LIST_HEAD(&mapping->list);
1786 mapping->start = saddr;
1787 mapping->last = eaddr;
1788 mapping->offset = offset;
1789 mapping->flags = flags;
1791 list_add(&mapping->list, &bo_va->invalids);
1792 amdgpu_vm_it_insert(mapping, &vm->va);
1794 if (flags & AMDGPU_PTE_PRT)
1795 amdgpu_vm_prt_get(adev);
1801 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1803 * @adev: amdgpu_device pointer
1804 * @bo_va: bo_va to store the address
1805 * @saddr: where to map the BO
1806 * @offset: requested offset in the BO
1807 * @flags: attributes of pages (read/write/valid/etc.)
1809 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1810 * mappings as we do so.
1811 * Returns 0 for success, error for failure.
1813 * Object has to be reserved and unreserved outside!
1815 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1816 struct amdgpu_bo_va *bo_va,
1817 uint64_t saddr, uint64_t offset,
1818 uint64_t size, uint64_t flags)
1820 struct amdgpu_bo_va_mapping *mapping;
1821 struct amdgpu_vm *vm = bo_va->vm;
1825 /* validate the parameters */
1826 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1827 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
1830 /* make sure object fit at this offset */
1831 eaddr = saddr + size - 1;
1832 if (saddr >= eaddr ||
1833 (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo)))
1836 /* Allocate all the needed memory */
1837 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1841 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->vm, saddr, size);
1847 saddr /= AMDGPU_GPU_PAGE_SIZE;
1848 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1850 mapping->start = saddr;
1851 mapping->last = eaddr;
1852 mapping->offset = offset;
1853 mapping->flags = flags;
1855 list_add(&mapping->list, &bo_va->invalids);
1856 amdgpu_vm_it_insert(mapping, &vm->va);
1858 if (flags & AMDGPU_PTE_PRT)
1859 amdgpu_vm_prt_get(adev);
1865 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1867 * @adev: amdgpu_device pointer
1868 * @bo_va: bo_va to remove the address from
1869 * @saddr: where to the BO is mapped
1871 * Remove a mapping of the BO at the specefied addr from the VM.
1872 * Returns 0 for success, error for failure.
1874 * Object has to be reserved and unreserved outside!
1876 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1877 struct amdgpu_bo_va *bo_va,
1880 struct amdgpu_bo_va_mapping *mapping;
1881 struct amdgpu_vm *vm = bo_va->vm;
1884 saddr /= AMDGPU_GPU_PAGE_SIZE;
1886 list_for_each_entry(mapping, &bo_va->valids, list) {
1887 if (mapping->start == saddr)
1891 if (&mapping->list == &bo_va->valids) {
1894 list_for_each_entry(mapping, &bo_va->invalids, list) {
1895 if (mapping->start == saddr)
1899 if (&mapping->list == &bo_va->invalids)
1903 list_del(&mapping->list);
1904 amdgpu_vm_it_remove(mapping, &vm->va);
1905 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1908 list_add(&mapping->list, &vm->freed);
1910 amdgpu_vm_free_mapping(adev, vm, mapping,
1911 bo_va->last_pt_update);
1917 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
1919 * @adev: amdgpu_device pointer
1920 * @vm: VM structure to use
1921 * @saddr: start of the range
1922 * @size: size of the range
1924 * Remove all mappings in a range, split them as appropriate.
1925 * Returns 0 for success, error for failure.
1927 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
1928 struct amdgpu_vm *vm,
1929 uint64_t saddr, uint64_t size)
1931 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
1935 eaddr = saddr + size - 1;
1936 saddr /= AMDGPU_GPU_PAGE_SIZE;
1937 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1939 /* Allocate all the needed memory */
1940 before = kzalloc(sizeof(*before), GFP_KERNEL);
1943 INIT_LIST_HEAD(&before->list);
1945 after = kzalloc(sizeof(*after), GFP_KERNEL);
1950 INIT_LIST_HEAD(&after->list);
1952 /* Now gather all removed mappings */
1953 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1955 /* Remember mapping split at the start */
1956 if (tmp->start < saddr) {
1957 before->start = tmp->start;
1958 before->last = saddr - 1;
1959 before->offset = tmp->offset;
1960 before->flags = tmp->flags;
1961 list_add(&before->list, &tmp->list);
1964 /* Remember mapping split at the end */
1965 if (tmp->last > eaddr) {
1966 after->start = eaddr + 1;
1967 after->last = tmp->last;
1968 after->offset = tmp->offset;
1969 after->offset += after->start - tmp->start;
1970 after->flags = tmp->flags;
1971 list_add(&after->list, &tmp->list);
1974 list_del(&tmp->list);
1975 list_add(&tmp->list, &removed);
1977 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
1980 /* And free them up */
1981 list_for_each_entry_safe(tmp, next, &removed, list) {
1982 amdgpu_vm_it_remove(tmp, &vm->va);
1983 list_del(&tmp->list);
1985 if (tmp->start < saddr)
1987 if (tmp->last > eaddr)
1990 list_add(&tmp->list, &vm->freed);
1991 trace_amdgpu_vm_bo_unmap(NULL, tmp);
1994 /* Insert partial mapping before the range */
1995 if (!list_empty(&before->list)) {
1996 amdgpu_vm_it_insert(before, &vm->va);
1997 if (before->flags & AMDGPU_PTE_PRT)
1998 amdgpu_vm_prt_get(adev);
2003 /* Insert partial mapping after the range */
2004 if (!list_empty(&after->list)) {
2005 amdgpu_vm_it_insert(after, &vm->va);
2006 if (after->flags & AMDGPU_PTE_PRT)
2007 amdgpu_vm_prt_get(adev);
2016 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2018 * @adev: amdgpu_device pointer
2019 * @bo_va: requested bo_va
2021 * Remove @bo_va->bo from the requested vm.
2023 * Object have to be reserved!
2025 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2026 struct amdgpu_bo_va *bo_va)
2028 struct amdgpu_bo_va_mapping *mapping, *next;
2029 struct amdgpu_vm *vm = bo_va->vm;
2031 list_del(&bo_va->bo_list);
2033 spin_lock(&vm->status_lock);
2034 list_del(&bo_va->vm_status);
2035 spin_unlock(&vm->status_lock);
2037 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2038 list_del(&mapping->list);
2039 amdgpu_vm_it_remove(mapping, &vm->va);
2040 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2041 list_add(&mapping->list, &vm->freed);
2043 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2044 list_del(&mapping->list);
2045 amdgpu_vm_it_remove(mapping, &vm->va);
2046 amdgpu_vm_free_mapping(adev, vm, mapping,
2047 bo_va->last_pt_update);
2050 dma_fence_put(bo_va->last_pt_update);
2055 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2057 * @adev: amdgpu_device pointer
2059 * @bo: amdgpu buffer object
2061 * Mark @bo as invalid.
2063 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2064 struct amdgpu_bo *bo)
2066 struct amdgpu_bo_va *bo_va;
2068 list_for_each_entry(bo_va, &bo->va, bo_list) {
2069 spin_lock(&bo_va->vm->status_lock);
2070 if (list_empty(&bo_va->vm_status))
2071 list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
2072 spin_unlock(&bo_va->vm->status_lock);
2076 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2078 /* Total bits covered by PD + PTs */
2079 unsigned bits = ilog2(vm_size) + 18;
2081 /* Make sure the PD is 4K in size up to 8GB address space.
2082 Above that split equal between PD and PTs */
2086 return ((bits + 3) / 2);
2090 * amdgpu_vm_adjust_size - adjust vm size and block size
2092 * @adev: amdgpu_device pointer
2093 * @vm_size: the default vm size if it's set auto
2095 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size)
2097 /* adjust vm size firstly */
2098 if (amdgpu_vm_size == -1)
2099 adev->vm_manager.vm_size = vm_size;
2101 adev->vm_manager.vm_size = amdgpu_vm_size;
2103 /* block size depends on vm size */
2104 if (amdgpu_vm_block_size == -1)
2105 adev->vm_manager.block_size =
2106 amdgpu_vm_get_block_size(adev->vm_manager.vm_size);
2108 adev->vm_manager.block_size = amdgpu_vm_block_size;
2110 DRM_INFO("vm size is %llu GB, block size is %u-bit\n",
2111 adev->vm_manager.vm_size, adev->vm_manager.block_size);
2115 * amdgpu_vm_init - initialize a vm instance
2117 * @adev: amdgpu_device pointer
2122 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2124 const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
2125 AMDGPU_VM_PTE_COUNT(adev) * 8);
2126 unsigned ring_instance;
2127 struct amdgpu_ring *ring;
2128 struct amd_sched_rq *rq;
2132 vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
2133 spin_lock_init(&vm->status_lock);
2134 INIT_LIST_HEAD(&vm->invalidated);
2135 INIT_LIST_HEAD(&vm->cleared);
2136 INIT_LIST_HEAD(&vm->freed);
2138 /* create scheduler entity for page table updates */
2140 ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
2141 ring_instance %= adev->vm_manager.vm_pte_num_rings;
2142 ring = adev->vm_manager.vm_pte_rings[ring_instance];
2143 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
2144 r = amd_sched_entity_init(&ring->sched, &vm->entity,
2145 rq, amdgpu_sched_jobs);
2149 vm->last_dir_update = NULL;
2151 r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true,
2152 AMDGPU_GEM_DOMAIN_VRAM,
2153 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
2154 AMDGPU_GEM_CREATE_SHADOW |
2155 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
2156 AMDGPU_GEM_CREATE_VRAM_CLEARED,
2157 NULL, NULL, &vm->root.bo);
2159 goto error_free_sched_entity;
2161 r = amdgpu_bo_reserve(vm->root.bo, false);
2163 goto error_free_root;
2165 vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
2166 amdgpu_bo_unreserve(vm->root.bo);
2171 amdgpu_bo_unref(&vm->root.bo->shadow);
2172 amdgpu_bo_unref(&vm->root.bo);
2175 error_free_sched_entity:
2176 amd_sched_entity_fini(&ring->sched, &vm->entity);
2182 * amdgpu_vm_free_levels - free PD/PT levels
2184 * @level: PD/PT starting level to free
2186 * Free the page directory or page table level and all sub levels.
2188 static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level)
2193 amdgpu_bo_unref(&level->bo->shadow);
2194 amdgpu_bo_unref(&level->bo);
2198 for (i = 0; i <= level->last_entry_used; i++)
2199 amdgpu_vm_free_levels(&level->entries[i]);
2201 drm_free_large(level->entries);
2205 * amdgpu_vm_fini - tear down a vm instance
2207 * @adev: amdgpu_device pointer
2211 * Unbind the VM and remove all bos from the vm bo list
2213 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2215 struct amdgpu_bo_va_mapping *mapping, *tmp;
2216 bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt;
2218 amd_sched_entity_fini(vm->entity.sched, &vm->entity);
2220 if (!RB_EMPTY_ROOT(&vm->va)) {
2221 dev_err(adev->dev, "still active bo inside vm\n");
2223 rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, rb) {
2224 list_del(&mapping->list);
2225 amdgpu_vm_it_remove(mapping, &vm->va);
2228 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2229 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2230 amdgpu_vm_prt_fini(adev, vm);
2231 prt_fini_needed = false;
2234 list_del(&mapping->list);
2235 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2238 amdgpu_vm_free_levels(&vm->root);
2239 dma_fence_put(vm->last_dir_update);
2243 * amdgpu_vm_manager_init - init the VM manager
2245 * @adev: amdgpu_device pointer
2247 * Initialize the VM manager structures
2249 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2253 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
2254 struct amdgpu_vm_id_manager *id_mgr =
2255 &adev->vm_manager.id_mgr[i];
2257 mutex_init(&id_mgr->lock);
2258 INIT_LIST_HEAD(&id_mgr->ids_lru);
2260 /* skip over VMID 0, since it is the system VM */
2261 for (j = 1; j < id_mgr->num_ids; ++j) {
2262 amdgpu_vm_reset_id(adev, i, j);
2263 amdgpu_sync_create(&id_mgr->ids[i].active);
2264 list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
2268 adev->vm_manager.fence_context =
2269 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2270 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2271 adev->vm_manager.seqno[i] = 0;
2274 atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
2275 atomic64_set(&adev->vm_manager.client_counter, 0);
2276 spin_lock_init(&adev->vm_manager.prt_lock);
2277 atomic_set(&adev->vm_manager.num_prt_users, 0);
2281 * amdgpu_vm_manager_fini - cleanup VM manager
2283 * @adev: amdgpu_device pointer
2285 * Cleanup the VM manager and free resources.
2287 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2291 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
2292 struct amdgpu_vm_id_manager *id_mgr =
2293 &adev->vm_manager.id_mgr[i];
2295 mutex_destroy(&id_mgr->lock);
2296 for (j = 0; j < AMDGPU_NUM_VM; ++j) {
2297 struct amdgpu_vm_id *id = &id_mgr->ids[j];
2299 amdgpu_sync_free(&id->active);
2300 dma_fence_put(id->flushed_updates);
2301 dma_fence_put(id->last_flush);