drivers/gpu/drm/amd/amdgpu/cik_sdma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "cikd.h"
  30 #include "cik.h"
  31
  32 #include "bif/bif_4_1_d.h"
  33 #include "bif/bif_4_1_sh_mask.h"
  34
  35 #include "gca/gfx_7_2_d.h"
  36 #include "gca/gfx_7_2_enum.h"
  37 #include "gca/gfx_7_2_sh_mask.h"
  38
  39 #include "gmc/gmc_7_1_d.h"
  40 #include "gmc/gmc_7_1_sh_mask.h"
  41
  42 #include "oss/oss_2_0_d.h"
  43 #include "oss/oss_2_0_sh_mask.h"
  44
  45 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  46 {
  47         SDMA0_REGISTER_OFFSET,
  48         SDMA1_REGISTER_OFFSET
  49 };
  50
  51 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
  52 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
  53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
  54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
  55
  56 MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
  57 MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
  58 MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
  59 MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
  60 MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
  61 MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
  62 MODULE_FIRMWARE("radeon/kabini_sdma.bin");
  63 MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
  64 MODULE_FIRMWARE("radeon/mullins_sdma.bin");
  65 MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
  66
  67 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
  68
  69 /*
  70  * sDMA - System DMA
  71  * Starting with CIK, the GPU has new asynchronous
  72  * DMA engines.  These engines are used for compute
  73  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  74  * and each one supports 1 ring buffer used for gfx
  75  * and 2 queues used for compute.
  76  *
  77  * The programming model is very similar to the CP
  78  * (ring buffer, IBs, etc.), but sDMA has it's own
  79  * packet format that is different from the PM4 format
  80  * used by the CP. sDMA supports copying data, writing
  81  * embedded data, solid fills, and a number of other
  82  * things.  It also has support for tiling/detiling of
  83  * buffers.
  84  */
  85
  86 /**
  87  * cik_sdma_init_microcode - load ucode images from disk
  88  *
  89  * @adev: amdgpu_device pointer
  90  *
  91  * Use the firmware interface to load the ucode images into
  92  * the driver (not loaded into hw).
  93  * Returns 0 on success, error on failure.
  94  */
  95 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
  96 {
  97         const char *chip_name;
  98         char fw_name[30];
  99         int err = 0, i;
 100
 101         DRM_DEBUG("\n");
 102
 103         switch (adev->asic_type) {
 104         case CHIP_BONAIRE:
 105                 chip_name = "bonaire";
 106                 break;
 107         case CHIP_HAWAII:
 108                 chip_name = "hawaii";
 109                 break;
 110         case CHIP_KAVERI:
 111                 chip_name = "kaveri";
 112                 break;
 113         case CHIP_KABINI:
 114                 chip_name = "kabini";
 115                 break;
 116         case CHIP_MULLINS:
 117                 chip_name = "mullins";
 118                 break;
 119         default: BUG();
 120         }
 121
 122         for (i = 0; i < adev->sdma.num_instances; i++) {
 123                 if (i == 0)
 124                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
 125                 else
 126                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
 127                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 128                 if (err)
 129                         goto out;
 130                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 131         }
 132 out:
 133         if (err) {
 134                 printk(KERN_ERR
 135                        "cik_sdma: Failed to load firmware \"%s\"\n",
 136                        fw_name);
 137                 for (i = 0; i < adev->sdma.num_instances; i++) {
 138                         release_firmware(adev->sdma.instance[i].fw);
 139                         adev->sdma.instance[i].fw = NULL;
 140                 }
 141         }
 142         return err;
 143 }
 144
 145 /**
 146  * cik_sdma_ring_get_rptr - get the current read pointer
 147  *
 148  * @ring: amdgpu ring pointer
 149  *
 150  * Get the current rptr from the hardware (CIK+).
 151  */
 152 static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 153 {
 154         u32 rptr;
 155
 156         rptr = ring->adev->wb.wb[ring->rptr_offs];
 157
 158         return (rptr & 0x3fffc) >> 2;
 159 }
 160
 161 /**
 162  * cik_sdma_ring_get_wptr - get the current write pointer
 163  *
 164  * @ring: amdgpu ring pointer
 165  *
 166  * Get the current wptr from the hardware (CIK+).
 167  */
 168 static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 169 {
 170         struct amdgpu_device *adev = ring->adev;
 171         u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 172
 173         return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
 174 }
 175
 176 /**
 177  * cik_sdma_ring_set_wptr - commit the write pointer
 178  *
 179  * @ring: amdgpu ring pointer
 180  *
 181  * Write the wptr back to the hardware (CIK+).
 182  */
 183 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 184 {
 185         struct amdgpu_device *adev = ring->adev;
 186         u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 187
 188         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
 189 }
 190
 191 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 192 {
 193         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 194         int i;
 195
 196         for (i = 0; i < count; i++)
 197                 if (sdma && sdma->burst_nop && (i == 0))
 198                         amdgpu_ring_write(ring, ring->nop |
 199                                           SDMA_NOP_COUNT(count - 1));
 200                 else
 201                         amdgpu_ring_write(ring, ring->nop);
 202 }
 203
 204 /**
 205  * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
 206  *
 207  * @ring: amdgpu ring pointer
 208  * @ib: IB object to schedule
 209  *
 210  * Schedule an IB in the DMA ring (CIK).
 211  */
 212 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
 213                            struct amdgpu_ib *ib)
 214 {
 215         u32 extra_bits = ib->vm_id & 0xf;
 216         u32 next_rptr = ring->wptr + 5;
 217
 218         while ((next_rptr & 7) != 4)
 219                 next_rptr++;
 220
 221         next_rptr += 4;
 222         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 223         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
 224         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
 225         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 226         amdgpu_ring_write(ring, next_rptr);
 227
 228         /* IB packet must end on a 8 DW boundary */
 229         cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8);
 230
 231         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
 232         amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
 233         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
 234         amdgpu_ring_write(ring, ib->length_dw);
 235
 236 }
 237
 238 /**
 239  * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 240  *
 241  * @ring: amdgpu ring pointer
 242  *
 243  * Emit an hdp flush packet on the requested DMA ring.
 244  */
 245 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 246 {
 247         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
 248                           SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
 249         u32 ref_and_mask;
 250
 251         if (ring == &ring->adev->sdma.instance[0].ring)
 252                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
 253         else
 254                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
 255
 256         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 257         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 258         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 259         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 260         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 261         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 262 }
 263
 264 static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 265 {
 266         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 267         amdgpu_ring_write(ring, mmHDP_DEBUG0);
 268         amdgpu_ring_write(ring, 1);
 269 }
 270
 271 /**
 272  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
 273  *
 274  * @ring: amdgpu ring pointer
 275  * @fence: amdgpu fence object
 276  *
 277  * Add a DMA fence packet to the ring to write
 278  * the fence seq number and DMA trap packet to generate
 279  * an interrupt if needed (CIK).
 280  */
 281 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 282                                      unsigned flags)
 283 {
 284         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 285         /* write the fence */
 286         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 287         amdgpu_ring_write(ring, lower_32_bits(addr));
 288         amdgpu_ring_write(ring, upper_32_bits(addr));
 289         amdgpu_ring_write(ring, lower_32_bits(seq));
 290
 291         /* optionally write high bits as well */
 292         if (write64bit) {
 293                 addr += 4;
 294                 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 295                 amdgpu_ring_write(ring, lower_32_bits(addr));
 296                 amdgpu_ring_write(ring, upper_32_bits(addr));
 297                 amdgpu_ring_write(ring, upper_32_bits(seq));
 298         }
 299
 300         /* generate an interrupt */
 301         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
 302 }
 303
 304 /**
 305  * cik_sdma_gfx_stop - stop the gfx async dma engines
 306  *
 307  * @adev: amdgpu_device pointer
 308  *
 309  * Stop the gfx async dma ring buffers (CIK).
 310  */
 311 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
 312 {
 313         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 314         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 315         u32 rb_cntl;
 316         int i;
 317
 318         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 319             (adev->mman.buffer_funcs_ring == sdma1))
 320                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 321
 322         for (i = 0; i < adev->sdma.num_instances; i++) {
 323                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 324                 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
 325                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 326                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
 327         }
 328         sdma0->ready = false;
 329         sdma1->ready = false;
 330 }
 331
 332 /**
 333  * cik_sdma_rlc_stop - stop the compute async dma engines
 334  *
 335  * @adev: amdgpu_device pointer
 336  *
 337  * Stop the compute async dma queues (CIK).
 338  */
 339 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
 340 {
 341         /* XXX todo */
 342 }
 343
 344 /**
 345  * cik_sdma_enable - stop the async dma engines
 346  *
 347  * @adev: amdgpu_device pointer
 348  * @enable: enable/disable the DMA MEs.
 349  *
 350  * Halt or unhalt the async dma engines (CIK).
 351  */
 352 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
 353 {
 354         u32 me_cntl;
 355         int i;
 356
 357         if (enable == false) {
 358                 cik_sdma_gfx_stop(adev);
 359                 cik_sdma_rlc_stop(adev);
 360         }
 361
 362         for (i = 0; i < adev->sdma.num_instances; i++) {
 363                 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 364                 if (enable)
 365                         me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
 366                 else
 367                         me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
 368                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
 369         }
 370 }
 371
 372 /**
 373  * cik_sdma_gfx_resume - setup and start the async dma engines
 374  *
 375  * @adev: amdgpu_device pointer
 376  *
 377  * Set up the gfx DMA ring buffers and enable them (CIK).
 378  * Returns 0 for success, error for failure.
 379  */
 380 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 381 {
 382         struct amdgpu_ring *ring;
 383         u32 rb_cntl, ib_cntl;
 384         u32 rb_bufsz;
 385         u32 wb_offset;
 386         int i, j, r;
 387
 388         for (i = 0; i < adev->sdma.num_instances; i++) {
 389                 ring = &adev->sdma.instance[i].ring;
 390                 wb_offset = (ring->rptr_offs * 4);
 391
 392                 mutex_lock(&adev->srbm_mutex);
 393                 for (j = 0; j < 16; j++) {
 394                         cik_srbm_select(adev, 0, 0, 0, j);
 395                         /* SDMA GFX */
 396                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 397                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 398                         /* XXX SDMA RLC - todo */
 399                 }
 400                 cik_srbm_select(adev, 0, 0, 0, 0);
 401                 mutex_unlock(&adev->srbm_mutex);
 402
 403                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 404                        adev->gfx.config.gb_addr_config & 0x70);
 405
 406                 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
 407                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 408
 409                 /* Set ring buffer size in dwords */
 410                 rb_bufsz = order_base_2(ring->ring_size / 4);
 411                 rb_cntl = rb_bufsz << 1;
 412 #ifdef __BIG_ENDIAN
 413                 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
 414                         SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
 415 #endif
 416                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 417
 418                 /* Initialize the ring buffer's read and write pointers */
 419                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 420                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 421
 422                 /* set the wb address whether it's enabled or not */
 423                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 424                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 425                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 426                        ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
 427
 428                 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
 429
 430                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 431                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 432
 433                 ring->wptr = 0;
 434                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 435
 436                 /* enable DMA RB */
 437                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
 438                        rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
 439
 440                 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
 441 #ifdef __BIG_ENDIAN
 442                 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
 443 #endif
 444                 /* enable DMA IBs */
 445                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 446
 447                 ring->ready = true;
 448
 449                 r = amdgpu_ring_test_ring(ring);
 450                 if (r) {
 451                         ring->ready = false;
 452                         return r;
 453                 }
 454
 455                 if (adev->mman.buffer_funcs_ring == ring)
 456                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 457         }
 458
 459         return 0;
 460 }
 461
 462 /**
 463  * cik_sdma_rlc_resume - setup and start the async dma engines
 464  *
 465  * @adev: amdgpu_device pointer
 466  *
 467  * Set up the compute DMA queues and enable them (CIK).
 468  * Returns 0 for success, error for failure.
 469  */
 470 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
 471 {
 472         /* XXX todo */
 473         return 0;
 474 }
 475
 476 /**
 477  * cik_sdma_load_microcode - load the sDMA ME ucode
 478  *
 479  * @adev: amdgpu_device pointer
 480  *
 481  * Loads the sDMA0/1 ucode.
 482  * Returns 0 for success, -EINVAL if the ucode is not available.
 483  */
 484 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
 485 {
 486         const struct sdma_firmware_header_v1_0 *hdr;
 487         const __le32 *fw_data;
 488         u32 fw_size;
 489         int i, j;
 490
 491         /* halt the MEs */
 492         cik_sdma_enable(adev, false);
 493
 494         for (i = 0; i < adev->sdma.num_instances; i++) {
 495                 if (!adev->sdma.instance[i].fw)
 496                         return -EINVAL;
 497                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 498                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 499                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 500                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 501                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 502                 if (adev->sdma.instance[i].feature_version >= 20)
 503                         adev->sdma.instance[i].burst_nop = true;
 504                 fw_data = (const __le32 *)
 505                         (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 506                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 507                 for (j = 0; j < fw_size; j++)
 508                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 509                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 510         }
 511
 512         return 0;
 513 }
 514
 515 /**
 516  * cik_sdma_start - setup and start the async dma engines
 517  *
 518  * @adev: amdgpu_device pointer
 519  *
 520  * Set up the DMA engines and enable them (CIK).
 521  * Returns 0 for success, error for failure.
 522  */
 523 static int cik_sdma_start(struct amdgpu_device *adev)
 524 {
 525         int r;
 526
 527         r = cik_sdma_load_microcode(adev);
 528         if (r)
 529                 return r;
 530
 531         /* unhalt the MEs */
 532         cik_sdma_enable(adev, true);
 533
 534         /* start the gfx rings and rlc compute queues */
 535         r = cik_sdma_gfx_resume(adev);
 536         if (r)
 537                 return r;
 538         r = cik_sdma_rlc_resume(adev);
 539         if (r)
 540                 return r;
 541
 542         return 0;
 543 }
 544
 545 /**
 546  * cik_sdma_ring_test_ring - simple async dma engine test
 547  *
 548  * @ring: amdgpu_ring structure holding ring information
 549  *
 550  * Test the DMA engine by writing using it to write an
 551  * value to memory. (CIK).
 552  * Returns 0 for success, error for failure.
 553  */
 554 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
 555 {
 556         struct amdgpu_device *adev = ring->adev;
 557         unsigned i;
 558         unsigned index;
 559         int r;
 560         u32 tmp;
 561         u64 gpu_addr;
 562
 563         r = amdgpu_wb_get(adev, &index);
 564         if (r) {
 565                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 566                 return r;
 567         }
 568
 569         gpu_addr = adev->wb.gpu_addr + (index * 4);
 570         tmp = 0xCAFEDEAD;
 571         adev->wb.wb[index] = cpu_to_le32(tmp);
 572
 573         r = amdgpu_ring_alloc(ring, 5);
 574         if (r) {
 575                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 576                 amdgpu_wb_free(adev, index);
 577                 return r;
 578         }
 579         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 580         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 581         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 582         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 583         amdgpu_ring_write(ring, 0xDEADBEEF);
 584         amdgpu_ring_commit(ring);
 585
 586         for (i = 0; i < adev->usec_timeout; i++) {
 587                 tmp = le32_to_cpu(adev->wb.wb[index]);
 588                 if (tmp == 0xDEADBEEF)
 589                         break;
 590                 DRM_UDELAY(1);
 591         }
 592
 593         if (i < adev->usec_timeout) {
 594                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 595         } else {
 596                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 597                           ring->idx, tmp);
 598                 r = -EINVAL;
 599         }
 600         amdgpu_wb_free(adev, index);
 601
 602         return r;
 603 }
 604
 605 /**
 606  * cik_sdma_ring_test_ib - test an IB on the DMA engine
 607  *
 608  * @ring: amdgpu_ring structure holding ring information
 609  *
 610  * Test a simple IB in the DMA ring (CIK).
 611  * Returns 0 on success, error on failure.
 612  */
 613 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
 614 {
 615         struct amdgpu_device *adev = ring->adev;
 616         struct amdgpu_ib ib;
 617         struct fence *f = NULL;
 618         unsigned i;
 619         unsigned index;
 620         int r;
 621         u32 tmp = 0;
 622         u64 gpu_addr;
 623
 624         r = amdgpu_wb_get(adev, &index);
 625         if (r) {
 626                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 627                 return r;
 628         }
 629
 630         gpu_addr = adev->wb.gpu_addr + (index * 4);
 631         tmp = 0xCAFEDEAD;
 632         adev->wb.wb[index] = cpu_to_le32(tmp);
 633         memset(&ib, 0, sizeof(ib));
 634         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 635         if (r) {
 636                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 637                 goto err0;
 638         }
 639
 640         ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 641         ib.ptr[1] = lower_32_bits(gpu_addr);
 642         ib.ptr[2] = upper_32_bits(gpu_addr);
 643         ib.ptr[3] = 1;
 644         ib.ptr[4] = 0xDEADBEEF;
 645         ib.length_dw = 5;
 646         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 647         if (r)
 648                 goto err1;
 649
 650         r = fence_wait(f, false);
 651         if (r) {
 652                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 653                 goto err1;
 654         }
 655         for (i = 0; i < adev->usec_timeout; i++) {
 656                 tmp = le32_to_cpu(adev->wb.wb[index]);
 657                 if (tmp == 0xDEADBEEF)
 658                         break;
 659                 DRM_UDELAY(1);
 660         }
 661         if (i < adev->usec_timeout) {
 662                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 663                          ring->idx, i);
 664                 goto err1;
 665         } else {
 666                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 667                 r = -EINVAL;
 668         }
 669
 670 err1:
 671         fence_put(f);
 672         amdgpu_ib_free(adev, &ib, NULL);
 673         fence_put(f);
 674 err0:
 675         amdgpu_wb_free(adev, index);
 676         return r;
 677 }
 678
 679 /**
 680  * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
 681  *
 682  * @ib: indirect buffer to fill with commands
 683  * @pe: addr of the page entry
 684  * @src: src addr to copy from
 685  * @count: number of page entries to update
 686  *
 687  * Update PTEs by copying them from the GART using sDMA (CIK).
 688  */
 689 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
 690                                  uint64_t pe, uint64_t src,
 691                                  unsigned count)
 692 {
 693         while (count) {
 694                 unsigned bytes = count * 8;
 695                 if (bytes > 0x1FFFF8)
 696                         bytes = 0x1FFFF8;
 697
 698                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
 699                         SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 700                 ib->ptr[ib->length_dw++] = bytes;
 701                 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 702                 ib->ptr[ib->length_dw++] = lower_32_bits(src);
 703                 ib->ptr[ib->length_dw++] = upper_32_bits(src);
 704                 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 705                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 706
 707                 pe += bytes;
 708                 src += bytes;
 709                 count -= bytes / 8;
 710         }
 711 }
 712
 713 /**
 714  * cik_sdma_vm_write_pages - update PTEs by writing them manually
 715  *
 716  * @ib: indirect buffer to fill with commands
 717  * @pe: addr of the page entry
 718  * @addr: dst addr to write into pe
 719  * @count: number of page entries to update
 720  * @incr: increase next addr by incr bytes
 721  * @flags: access flags
 722  *
 723  * Update PTEs by writing them manually using sDMA (CIK).
 724  */
 725 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
 726                                   const dma_addr_t *pages_addr, uint64_t pe,
 727                                   uint64_t addr, unsigned count,
 728                                   uint32_t incr, uint32_t flags)
 729 {
 730         uint64_t value;
 731         unsigned ndw;
 732
 733         while (count) {
 734                 ndw = count * 2;
 735                 if (ndw > 0xFFFFE)
 736                         ndw = 0xFFFFE;
 737
 738                 /* for non-physically contiguous pages (system) */
 739                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 740                         SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 741                 ib->ptr[ib->length_dw++] = pe;
 742                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 743                 ib->ptr[ib->length_dw++] = ndw;
 744                 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 745                         value = amdgpu_vm_map_gart(pages_addr, addr);
 746                         addr += incr;
 747                         value |= flags;
 748                         ib->ptr[ib->length_dw++] = value;
 749                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
 750                 }
 751         }
 752 }
 753
 754 /**
 755  * cik_sdma_vm_set_pages - update the page tables using sDMA
 756  *
 757  * @ib: indirect buffer to fill with commands
 758  * @pe: addr of the page entry
 759  * @addr: dst addr to write into pe
 760  * @count: number of page entries to update
 761  * @incr: increase next addr by incr bytes
 762  * @flags: access flags
 763  *
 764  * Update the page tables using sDMA (CIK).
 765  */
 766 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib,
 767                                     uint64_t pe,
 768                                     uint64_t addr, unsigned count,
 769                                     uint32_t incr, uint32_t flags)
 770 {
 771         uint64_t value;
 772         unsigned ndw;
 773
 774         while (count) {
 775                 ndw = count;
 776                 if (ndw > 0x7FFFF)
 777                         ndw = 0x7FFFF;
 778
 779                 if (flags & AMDGPU_PTE_VALID)
 780                         value = addr;
 781                 else
 782                         value = 0;
 783
 784                 /* for physically contiguous pages (vram) */
 785                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
 786                 ib->ptr[ib->length_dw++] = pe; /* dst addr */
 787                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 788                 ib->ptr[ib->length_dw++] = flags; /* mask */
 789                 ib->ptr[ib->length_dw++] = 0;
 790                 ib->ptr[ib->length_dw++] = value; /* value */
 791                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 792                 ib->ptr[ib->length_dw++] = incr; /* increment size */
 793                 ib->ptr[ib->length_dw++] = 0;
 794                 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
 795
 796                 pe += ndw * 8;
 797                 addr += ndw * incr;
 798                 count -= ndw;
 799         }
 800 }
 801
 802 /**
 803  * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
 804  *
 805  * @ib: indirect buffer to fill with padding
 806  *
 807  */
 808 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 809 {
 810         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 811         u32 pad_count;
 812         int i;
 813
 814         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 815         for (i = 0; i < pad_count; i++)
 816                 if (sdma && sdma->burst_nop && (i == 0))
 817                         ib->ptr[ib->length_dw++] =
 818                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
 819                                         SDMA_NOP_COUNT(pad_count - 1);
 820                 else
 821                         ib->ptr[ib->length_dw++] =
 822                                         SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
 823 }
 824
 825 /**
 826  * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
 827  *
 828  * @ring: amdgpu_ring pointer
 829  *
 830  * Make sure all previous operations are completed (CIK).
 831  */
 832 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 833 {
 834         uint32_t seq = ring->fence_drv.sync_seq;
 835         uint64_t addr = ring->fence_drv.gpu_addr;
 836
 837         /* wait for idle */
 838         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
 839                                             SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 840                                             SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
 841                                             SDMA_POLL_REG_MEM_EXTRA_M));
 842         amdgpu_ring_write(ring, addr & 0xfffffffc);
 843         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 844         amdgpu_ring_write(ring, seq); /* reference */
 845         amdgpu_ring_write(ring, 0xfffffff); /* mask */
 846         amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
 847 }
 848
 849 /**
 850  * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
 851  *
 852  * @ring: amdgpu_ring pointer
 853  * @vm: amdgpu_vm pointer
 854  *
 855  * Update the page table base and flush the VM TLB
 856  * using sDMA (CIK).
 857  */
 858 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 859                                         unsigned vm_id, uint64_t pd_addr)
 860 {
 861         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 862                           SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 863
 864         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 865         if (vm_id < 8) {
 866                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 867         } else {
 868                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 869         }
 870         amdgpu_ring_write(ring, pd_addr >> 12);
 871
 872         /* flush TLB */
 873         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 874         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 875         amdgpu_ring_write(ring, 1 << vm_id);
 876
 877         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 878         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 879         amdgpu_ring_write(ring, 0);
 880         amdgpu_ring_write(ring, 0); /* reference */
 881         amdgpu_ring_write(ring, 0); /* mask */
 882         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 883 }
 884
 885 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
 886                                  bool enable)
 887 {
 888         u32 orig, data;
 889
 890         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
 891                 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
 892                 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
 893         } else {
 894                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
 895                 data |= 0xff000000;
 896                 if (data != orig)
 897                         WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
 898
 899                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
 900                 data |= 0xff000000;
 901                 if (data != orig)
 902                         WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
 903         }
 904 }
 905
 906 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
 907                                  bool enable)
 908 {
 909         u32 orig, data;
 910
 911         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
 912                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 913                 data |= 0x100;
 914                 if (orig != data)
 915                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 916
 917                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 918                 data |= 0x100;
 919                 if (orig != data)
 920                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 921         } else {
 922                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 923                 data &= ~0x100;
 924                 if (orig != data)
 925                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 926
 927                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 928                 data &= ~0x100;
 929                 if (orig != data)
 930                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 931         }
 932 }
 933
 934 static int cik_sdma_early_init(void *handle)
 935 {
 936         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 937
 938         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 939
 940         cik_sdma_set_ring_funcs(adev);
 941         cik_sdma_set_irq_funcs(adev);
 942         cik_sdma_set_buffer_funcs(adev);
 943         cik_sdma_set_vm_pte_funcs(adev);
 944
 945         return 0;
 946 }
 947
 948 static int cik_sdma_sw_init(void *handle)
 949 {
 950         struct amdgpu_ring *ring;
 951         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 952         int r, i;
 953
 954         r = cik_sdma_init_microcode(adev);
 955         if (r) {
 956                 DRM_ERROR("Failed to load sdma firmware!\n");
 957                 return r;
 958         }
 959
 960         /* SDMA trap event */
 961         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
 962         if (r)
 963                 return r;
 964
 965         /* SDMA Privileged inst */
 966         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
 967         if (r)
 968                 return r;
 969
 970         /* SDMA Privileged inst */
 971         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
 972         if (r)
 973                 return r;
 974
 975         for (i = 0; i < adev->sdma.num_instances; i++) {
 976                 ring = &adev->sdma.instance[i].ring;
 977                 ring->ring_obj = NULL;
 978                 sprintf(ring->name, "sdma%d", i);
 979                 r = amdgpu_ring_init(adev, ring, 256 * 1024,
 980                                      SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
 981                                      &adev->sdma.trap_irq,
 982                                      (i == 0) ?
 983                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
 984                                      AMDGPU_RING_TYPE_SDMA);
 985                 if (r)
 986                         return r;
 987         }
 988
 989         return r;
 990 }
 991
 992 static int cik_sdma_sw_fini(void *handle)
 993 {
 994         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 995         int i;
 996
 997         for (i = 0; i < adev->sdma.num_instances; i++)
 998                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 999
1000         return 0;
1001 }
1002
1003 static int cik_sdma_hw_init(void *handle)
1004 {
1005         int r;
1006         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1007
1008         r = cik_sdma_start(adev);
1009         if (r)
1010                 return r;
1011
1012         return r;
1013 }
1014
1015 static int cik_sdma_hw_fini(void *handle)
1016 {
1017         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1018
1019         cik_sdma_enable(adev, false);
1020
1021         return 0;
1022 }
1023
1024 static int cik_sdma_suspend(void *handle)
1025 {
1026         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1027
1028         return cik_sdma_hw_fini(adev);
1029 }
1030
1031 static int cik_sdma_resume(void *handle)
1032 {
1033         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1034
1035         return cik_sdma_hw_init(adev);
1036 }
1037
1038 static bool cik_sdma_is_idle(void *handle)
1039 {
1040         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1041         u32 tmp = RREG32(mmSRBM_STATUS2);
1042
1043         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1044                                 SRBM_STATUS2__SDMA1_BUSY_MASK))
1045             return false;
1046
1047         return true;
1048 }
1049
1050 static int cik_sdma_wait_for_idle(void *handle)
1051 {
1052         unsigned i;
1053         u32 tmp;
1054         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1055
1056         for (i = 0; i < adev->usec_timeout; i++) {
1057                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1058                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1059
1060                 if (!tmp)
1061                         return 0;
1062                 udelay(1);
1063         }
1064         return -ETIMEDOUT;
1065 }
1066
1067 static void cik_sdma_print_status(void *handle)
1068 {
1069         int i, j;
1070         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1071
1072         dev_info(adev->dev, "CIK SDMA registers\n");
1073         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
1074                  RREG32(mmSRBM_STATUS2));
1075         for (i = 0; i < adev->sdma.num_instances; i++) {
1076                 dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
1077                          i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1078                 dev_info(adev->dev, "  SDMA%d_ME_CNTL=0x%08X\n",
1079                          i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1080                 dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
1081                          i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1082                 dev_info(adev->dev, "  SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
1083                          i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i]));
1084                 dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1085                          i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1086                 dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
1087                          i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1088                 dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
1089                          i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1090                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
1091                          i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1092                 dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
1093                          i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1094                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1095                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1096                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1097                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1098                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
1099                          i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1100                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1101                          i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1102                 dev_info(adev->dev, "  SDMA%d_TILING_CONFIG=0x%08X\n",
1103                          i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
1104                 mutex_lock(&adev->srbm_mutex);
1105                 for (j = 0; j < 16; j++) {
1106                         cik_srbm_select(adev, 0, 0, 0, j);
1107                         dev_info(adev->dev, "  VM %d:\n", j);
1108                         dev_info(adev->dev, "  SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
1109                                  RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1110                         dev_info(adev->dev, "  SDMA0_GFX_APE1_CNTL=0x%08X\n",
1111                                  RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1112                 }
1113                 cik_srbm_select(adev, 0, 0, 0, 0);
1114                 mutex_unlock(&adev->srbm_mutex);
1115         }
1116 }
1117
1118 static int cik_sdma_soft_reset(void *handle)
1119 {
1120         u32 srbm_soft_reset = 0;
1121         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1122         u32 tmp = RREG32(mmSRBM_STATUS2);
1123
1124         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1125                 /* sdma0 */
1126                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1127                 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1128                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1129                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1130         }
1131         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1132                 /* sdma1 */
1133                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1134                 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1135                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1136                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1137         }
1138
1139         if (srbm_soft_reset) {
1140                 cik_sdma_print_status((void *)adev);
1141
1142                 tmp = RREG32(mmSRBM_SOFT_RESET);
1143                 tmp |= srbm_soft_reset;
1144                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1145                 WREG32(mmSRBM_SOFT_RESET, tmp);
1146                 tmp = RREG32(mmSRBM_SOFT_RESET);
1147
1148                 udelay(50);
1149
1150                 tmp &= ~srbm_soft_reset;
1151                 WREG32(mmSRBM_SOFT_RESET, tmp);
1152                 tmp = RREG32(mmSRBM_SOFT_RESET);
1153
1154                 /* Wait a little for things to settle down */
1155                 udelay(50);
1156
1157                 cik_sdma_print_status((void *)adev);
1158         }
1159
1160         return 0;
1161 }
1162
1163 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1164                                        struct amdgpu_irq_src *src,
1165                                        unsigned type,
1166                                        enum amdgpu_interrupt_state state)
1167 {
1168         u32 sdma_cntl;
1169
1170         switch (type) {
1171         case AMDGPU_SDMA_IRQ_TRAP0:
1172                 switch (state) {
1173                 case AMDGPU_IRQ_STATE_DISABLE:
1174                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1175                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1176                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1177                         break;
1178                 case AMDGPU_IRQ_STATE_ENABLE:
1179                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1180                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1181                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1182                         break;
1183                 default:
1184                         break;
1185                 }
1186                 break;
1187         case AMDGPU_SDMA_IRQ_TRAP1:
1188                 switch (state) {
1189                 case AMDGPU_IRQ_STATE_DISABLE:
1190                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1191                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1192                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1193                         break;
1194                 case AMDGPU_IRQ_STATE_ENABLE:
1195                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1196                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1197                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1198                         break;
1199                 default:
1200                         break;
1201                 }
1202                 break;
1203         default:
1204                 break;
1205         }
1206         return 0;
1207 }
1208
1209 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1210                                      struct amdgpu_irq_src *source,
1211                                      struct amdgpu_iv_entry *entry)
1212 {
1213         u8 instance_id, queue_id;
1214
1215         instance_id = (entry->ring_id & 0x3) >> 0;
1216         queue_id = (entry->ring_id & 0xc) >> 2;
1217         DRM_DEBUG("IH: SDMA trap\n");
1218         switch (instance_id) {
1219         case 0:
1220                 switch (queue_id) {
1221                 case 0:
1222                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1223                         break;
1224                 case 1:
1225                         /* XXX compute */
1226                         break;
1227                 case 2:
1228                         /* XXX compute */
1229                         break;
1230                 }
1231                 break;
1232         case 1:
1233                 switch (queue_id) {
1234                 case 0:
1235                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1236                         break;
1237                 case 1:
1238                         /* XXX compute */
1239                         break;
1240                 case 2:
1241                         /* XXX compute */
1242                         break;
1243                 }
1244                 break;
1245         }
1246
1247         return 0;
1248 }
1249
1250 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1251                                              struct amdgpu_irq_src *source,
1252                                              struct amdgpu_iv_entry *entry)
1253 {
1254         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1255         schedule_work(&adev->reset_work);
1256         return 0;
1257 }
1258
1259 static int cik_sdma_set_clockgating_state(void *handle,
1260                                           enum amd_clockgating_state state)
1261 {
1262         bool gate = false;
1263         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1264
1265         if (state == AMD_CG_STATE_GATE)
1266                 gate = true;
1267
1268         cik_enable_sdma_mgcg(adev, gate);
1269         cik_enable_sdma_mgls(adev, gate);
1270
1271         return 0;
1272 }
1273
1274 static int cik_sdma_set_powergating_state(void *handle,
1275                                           enum amd_powergating_state state)
1276 {
1277         return 0;
1278 }
1279
1280 const struct amd_ip_funcs cik_sdma_ip_funcs = {
1281         .early_init = cik_sdma_early_init,
1282         .late_init = NULL,
1283         .sw_init = cik_sdma_sw_init,
1284         .sw_fini = cik_sdma_sw_fini,
1285         .hw_init = cik_sdma_hw_init,
1286         .hw_fini = cik_sdma_hw_fini,
1287         .suspend = cik_sdma_suspend,
1288         .resume = cik_sdma_resume,
1289         .is_idle = cik_sdma_is_idle,
1290         .wait_for_idle = cik_sdma_wait_for_idle,
1291         .soft_reset = cik_sdma_soft_reset,
1292         .print_status = cik_sdma_print_status,
1293         .set_clockgating_state = cik_sdma_set_clockgating_state,
1294         .set_powergating_state = cik_sdma_set_powergating_state,
1295 };
1296
1297 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1298         .get_rptr = cik_sdma_ring_get_rptr,
1299         .get_wptr = cik_sdma_ring_get_wptr,
1300         .set_wptr = cik_sdma_ring_set_wptr,
1301         .parse_cs = NULL,
1302         .emit_ib = cik_sdma_ring_emit_ib,
1303         .emit_fence = cik_sdma_ring_emit_fence,
1304         .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1305         .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1306         .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1307         .emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate,
1308         .test_ring = cik_sdma_ring_test_ring,
1309         .test_ib = cik_sdma_ring_test_ib,
1310         .insert_nop = cik_sdma_ring_insert_nop,
1311         .pad_ib = cik_sdma_ring_pad_ib,
1312 };
1313
1314 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1315 {
1316         int i;
1317
1318         for (i = 0; i < adev->sdma.num_instances; i++)
1319                 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1320 }
1321
1322 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1323         .set = cik_sdma_set_trap_irq_state,
1324         .process = cik_sdma_process_trap_irq,
1325 };
1326
1327 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1328         .process = cik_sdma_process_illegal_inst_irq,
1329 };
1330
1331 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1332 {
1333         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1334         adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1335         adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1336 }
1337
1338 /**
1339  * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1340  *
1341  * @ring: amdgpu_ring structure holding ring information
1342  * @src_offset: src GPU address
1343  * @dst_offset: dst GPU address
1344  * @byte_count: number of bytes to xfer
1345  *
1346  * Copy GPU buffers using the DMA engine (CIK).
1347  * Used by the amdgpu ttm implementation to move pages if
1348  * registered as the asic copy callback.
1349  */
1350 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1351                                       uint64_t src_offset,
1352                                       uint64_t dst_offset,
1353                                       uint32_t byte_count)
1354 {
1355         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1356         ib->ptr[ib->length_dw++] = byte_count;
1357         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1358         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1359         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1360         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1361         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1362 }
1363
1364 /**
1365  * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1366  *
1367  * @ring: amdgpu_ring structure holding ring information
1368  * @src_data: value to write to buffer
1369  * @dst_offset: dst GPU address
1370  * @byte_count: number of bytes to xfer
1371  *
1372  * Fill GPU buffers using the DMA engine (CIK).
1373  */
1374 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1375                                       uint32_t src_data,
1376                                       uint64_t dst_offset,
1377                                       uint32_t byte_count)
1378 {
1379         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1380         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1381         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1382         ib->ptr[ib->length_dw++] = src_data;
1383         ib->ptr[ib->length_dw++] = byte_count;
1384 }
1385
1386 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1387         .copy_max_bytes = 0x1fffff,
1388         .copy_num_dw = 7,
1389         .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1390
1391         .fill_max_bytes = 0x1fffff,
1392         .fill_num_dw = 5,
1393         .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1394 };
1395
1396 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1397 {
1398         if (adev->mman.buffer_funcs == NULL) {
1399                 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1400                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1401         }
1402 }
1403
1404 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1405         .copy_pte = cik_sdma_vm_copy_pte,
1406         .write_pte = cik_sdma_vm_write_pte,
1407         .set_pte_pde = cik_sdma_vm_set_pte_pde,
1408 };
1409
1410 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1411 {
1412         unsigned i;
1413
1414         if (adev->vm_manager.vm_pte_funcs == NULL) {
1415                 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1416                 for (i = 0; i < adev->sdma.num_instances; i++)
1417                         adev->vm_manager.vm_pte_rings[i] =
1418                                 &adev->sdma.instance[i].ring;
1419
1420                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1421         }
1422 }