2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
34 #include "dce_v11_0.h"
36 #include "dce/dce_11_0_d.h"
37 #include "dce/dce_11_0_sh_mask.h"
38 #include "dce/dce_11_0_enum.h"
39 #include "oss/oss_3_0_d.h"
40 #include "oss/oss_3_0_sh_mask.h"
41 #include "gmc/gmc_8_1_d.h"
42 #include "gmc/gmc_8_1_sh_mask.h"
44 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
45 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
47 static const u32 crtc_offsets[] =
49 CRTC0_REGISTER_OFFSET,
50 CRTC1_REGISTER_OFFSET,
51 CRTC2_REGISTER_OFFSET,
52 CRTC3_REGISTER_OFFSET,
53 CRTC4_REGISTER_OFFSET,
54 CRTC5_REGISTER_OFFSET,
58 static const u32 hpd_offsets[] =
68 static const uint32_t dig_offsets[] = {
86 } interrupt_status_offsets[] = { {
87 .reg = mmDISP_INTERRUPT_STATUS,
88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
89 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
90 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
92 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
94 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
95 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
99 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
104 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
109 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
114 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
118 static const u32 cz_golden_settings_a11[] =
120 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
121 mmFBC_MISC, 0x1f311fff, 0x14300000,
124 static const u32 cz_mgcg_cgcg_init[] =
126 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
127 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
130 static const u32 stoney_golden_settings_a11[] =
132 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
133 mmFBC_MISC, 0x1f311fff, 0x14302000,
136 static const u32 polaris11_golden_settings_a11[] =
138 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
139 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
140 mmFBC_DEBUG1, 0xffffffff, 0x00000008,
141 mmFBC_MISC, 0x9f313fff, 0x14302008,
142 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
145 static const u32 polaris10_golden_settings_a11[] =
147 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
148 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
149 mmFBC_MISC, 0x9f313fff, 0x14302008,
150 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
153 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
155 switch (adev->asic_type) {
157 amdgpu_program_register_sequence(adev,
159 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
160 amdgpu_program_register_sequence(adev,
161 cz_golden_settings_a11,
162 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
165 amdgpu_program_register_sequence(adev,
166 stoney_golden_settings_a11,
167 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
171 amdgpu_program_register_sequence(adev,
172 polaris11_golden_settings_a11,
173 (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
176 amdgpu_program_register_sequence(adev,
177 polaris10_golden_settings_a11,
178 (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
185 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
186 u32 block_offset, u32 reg)
191 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
192 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
193 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
194 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
199 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
200 u32 block_offset, u32 reg, u32 v)
204 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
205 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
206 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
207 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
210 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
212 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
213 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
219 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
223 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
224 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
233 * dce_v11_0_vblank_wait - vblank wait asic callback.
235 * @adev: amdgpu_device pointer
236 * @crtc: crtc to wait for vblank on
238 * Wait for vblank on the requested crtc (evergreen+).
240 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
244 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
247 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
250 /* depending on when we hit vblank, we may be close to active; if so,
251 * wait for another frame.
253 while (dce_v11_0_is_in_vblank(adev, crtc)) {
256 if (!dce_v11_0_is_counter_moving(adev, crtc))
261 while (!dce_v11_0_is_in_vblank(adev, crtc)) {
264 if (!dce_v11_0_is_counter_moving(adev, crtc))
270 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
272 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
275 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
278 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
282 /* Enable pflip interrupts */
283 for (i = 0; i < adev->mode_info.num_crtc; i++)
284 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
287 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
291 /* Disable pflip interrupts */
292 for (i = 0; i < adev->mode_info.num_crtc; i++)
293 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
297 * dce_v11_0_page_flip - pageflip callback.
299 * @adev: amdgpu_device pointer
300 * @crtc_id: crtc to cleanup pageflip on
301 * @crtc_base: new address of the crtc (GPU MC address)
303 * Triggers the actual pageflip by updating the primary
304 * surface base address.
306 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
307 int crtc_id, u64 crtc_base, bool async)
309 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
312 /* flip immediate for async, default is vsync */
313 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
314 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
315 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
316 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
317 /* update the scanout addresses */
318 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
319 upper_32_bits(crtc_base));
320 /* writing to the low address triggers the update */
321 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
322 lower_32_bits(crtc_base));
324 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
327 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
328 u32 *vbl, u32 *position)
330 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
333 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
334 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
340 * dce_v11_0_hpd_sense - hpd sense callback.
342 * @adev: amdgpu_device pointer
343 * @hpd: hpd (hotplug detect) pin
345 * Checks if a digital monitor is connected (evergreen+).
346 * Returns true if connected, false if not connected.
348 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
349 enum amdgpu_hpd_id hpd)
351 bool connected = false;
353 if (hpd >= adev->mode_info.num_hpd)
356 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
357 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
364 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
366 * @adev: amdgpu_device pointer
367 * @hpd: hpd (hotplug detect) pin
369 * Set the polarity of the hpd pin (evergreen+).
371 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
372 enum amdgpu_hpd_id hpd)
375 bool connected = dce_v11_0_hpd_sense(adev, hpd);
377 if (hpd >= adev->mode_info.num_hpd)
380 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
382 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
384 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
385 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
389 * dce_v11_0_hpd_init - hpd setup callback.
391 * @adev: amdgpu_device pointer
393 * Setup the hpd pins used by the card (evergreen+).
394 * Enable the pin, set the polarity, and enable the hpd interrupts.
396 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
398 struct drm_device *dev = adev->ddev;
399 struct drm_connector *connector;
402 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
403 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
405 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
408 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
409 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
410 /* don't try to enable hpd on eDP or LVDS avoid breaking the
411 * aux dp channel on imac and help (but not completely fix)
412 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
413 * also avoid interrupt storms during dpms.
415 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
416 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
417 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
421 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
422 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
423 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
425 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
426 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
427 DC_HPD_CONNECT_INT_DELAY,
428 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
429 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
430 DC_HPD_DISCONNECT_INT_DELAY,
431 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
432 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
434 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
435 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
440 * dce_v11_0_hpd_fini - hpd tear down callback.
442 * @adev: amdgpu_device pointer
444 * Tear down the hpd pins used by the card (evergreen+).
445 * Disable the hpd interrupts.
447 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
449 struct drm_device *dev = adev->ddev;
450 struct drm_connector *connector;
453 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
454 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
456 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
459 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
460 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
461 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
463 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
467 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
469 return mmDC_GPIO_HPD_A;
472 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
478 for (i = 0; i < adev->mode_info.num_crtc; i++) {
479 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
480 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
481 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
482 crtc_hung |= (1 << i);
486 for (j = 0; j < 10; j++) {
487 for (i = 0; i < adev->mode_info.num_crtc; i++) {
488 if (crtc_hung & (1 << i)) {
489 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
490 if (tmp != crtc_status[i])
491 crtc_hung &= ~(1 << i);
502 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
503 struct amdgpu_mode_mc_save *save)
505 u32 crtc_enabled, tmp;
508 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
509 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
511 /* disable VGA render */
512 tmp = RREG32(mmVGA_RENDER_CONTROL);
513 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
514 WREG32(mmVGA_RENDER_CONTROL, tmp);
516 /* blank the display controllers */
517 for (i = 0; i < adev->mode_info.num_crtc; i++) {
518 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
519 CRTC_CONTROL, CRTC_MASTER_EN);
522 save->crtc_enabled[i] = true;
523 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
524 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
525 /*it is correct only for RGB ; black is 0*/
526 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
527 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
528 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
531 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
532 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
533 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
534 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
535 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
536 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
537 save->crtc_enabled[i] = false;
541 save->crtc_enabled[i] = false;
546 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
547 struct amdgpu_mode_mc_save *save)
552 /* update crtc base addresses */
553 for (i = 0; i < adev->mode_info.num_crtc; i++) {
554 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
555 upper_32_bits(adev->mc.vram_start));
556 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
557 (u32)adev->mc.vram_start);
559 if (save->crtc_enabled[i]) {
560 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
561 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
562 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
566 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
567 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
569 /* Unlock vga access */
570 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
572 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
575 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
580 /* Lockout access through VGA aperture*/
581 tmp = RREG32(mmVGA_HDP_CONTROL);
583 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
585 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
586 WREG32(mmVGA_HDP_CONTROL, tmp);
588 /* disable VGA render */
589 tmp = RREG32(mmVGA_RENDER_CONTROL);
591 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
593 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
594 WREG32(mmVGA_RENDER_CONTROL, tmp);
597 static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
601 switch (adev->asic_type) {
621 void dce_v11_0_disable_dce(struct amdgpu_device *adev)
623 /*Disable VGA render and enabled crtc, if has DCE engine*/
624 if (amdgpu_atombios_has_dce_engine_info(adev)) {
628 dce_v11_0_set_vga_render_state(adev, false);
631 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
632 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
633 CRTC_CONTROL, CRTC_MASTER_EN);
635 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
636 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
637 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
638 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
639 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
645 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
647 struct drm_device *dev = encoder->dev;
648 struct amdgpu_device *adev = dev->dev_private;
649 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
650 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
651 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
654 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
657 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
658 bpc = amdgpu_connector_get_monitor_bpc(connector);
659 dither = amdgpu_connector->dither;
662 /* LVDS/eDP FMT is set up by atom */
663 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
666 /* not needed for analog */
667 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
668 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
676 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
677 /* XXX sort out optimal dither settings */
678 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
679 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
680 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
681 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
683 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
684 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
688 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
689 /* XXX sort out optimal dither settings */
690 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
691 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
692 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
693 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
694 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
696 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
697 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
701 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
702 /* XXX sort out optimal dither settings */
703 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
704 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
705 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
706 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
707 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
709 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
710 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
718 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
722 /* display watermark setup */
724 * dce_v11_0_line_buffer_adjust - Set up the line buffer
726 * @adev: amdgpu_device pointer
727 * @amdgpu_crtc: the selected display controller
728 * @mode: the current display mode on the selected display
731 * Setup up the line buffer allocation for
732 * the selected display controller (CIK).
733 * Returns the line buffer size in pixels.
735 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
736 struct amdgpu_crtc *amdgpu_crtc,
737 struct drm_display_mode *mode)
739 u32 tmp, buffer_alloc, i, mem_cfg;
740 u32 pipe_offset = amdgpu_crtc->crtc_id;
743 * There are 6 line buffers, one for each display controllers.
744 * There are 3 partitions per LB. Select the number of partitions
745 * to enable based on the display width. For display widths larger
746 * than 4096, you need use to use 2 display controllers and combine
747 * them using the stereo blender.
749 if (amdgpu_crtc->base.enabled && mode) {
750 if (mode->crtc_hdisplay < 1920) {
753 } else if (mode->crtc_hdisplay < 2560) {
756 } else if (mode->crtc_hdisplay < 4096) {
758 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
760 DRM_DEBUG_KMS("Mode too big for LB!\n");
762 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
769 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
770 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
771 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
773 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
774 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
775 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
777 for (i = 0; i < adev->usec_timeout; i++) {
778 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
779 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
784 if (amdgpu_crtc->base.enabled && mode) {
796 /* controller not enabled, so no lb used */
801 * cik_get_number_of_dram_channels - get the number of dram channels
803 * @adev: amdgpu_device pointer
805 * Look up the number of video ram channels (CIK).
806 * Used for display watermark bandwidth calculations
807 * Returns the number of dram channels
809 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
811 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
813 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
836 struct dce10_wm_params {
837 u32 dram_channels; /* number of dram channels */
838 u32 yclk; /* bandwidth per dram data pin in kHz */
839 u32 sclk; /* engine clock in kHz */
840 u32 disp_clk; /* display clock in kHz */
841 u32 src_width; /* viewport width */
842 u32 active_time; /* active display time in ns */
843 u32 blank_time; /* blank time in ns */
844 bool interlaced; /* mode is interlaced */
845 fixed20_12 vsc; /* vertical scale ratio */
846 u32 num_heads; /* number of active crtcs */
847 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
848 u32 lb_size; /* line buffer allocated to pipe */
849 u32 vtaps; /* vertical scaler taps */
853 * dce_v11_0_dram_bandwidth - get the dram bandwidth
855 * @wm: watermark calculation data
857 * Calculate the raw dram bandwidth (CIK).
858 * Used for display watermark bandwidth calculations
859 * Returns the dram bandwidth in MBytes/s
861 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
863 /* Calculate raw DRAM Bandwidth */
864 fixed20_12 dram_efficiency; /* 0.7 */
865 fixed20_12 yclk, dram_channels, bandwidth;
868 a.full = dfixed_const(1000);
869 yclk.full = dfixed_const(wm->yclk);
870 yclk.full = dfixed_div(yclk, a);
871 dram_channels.full = dfixed_const(wm->dram_channels * 4);
872 a.full = dfixed_const(10);
873 dram_efficiency.full = dfixed_const(7);
874 dram_efficiency.full = dfixed_div(dram_efficiency, a);
875 bandwidth.full = dfixed_mul(dram_channels, yclk);
876 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
878 return dfixed_trunc(bandwidth);
882 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
884 * @wm: watermark calculation data
886 * Calculate the dram bandwidth used for display (CIK).
887 * Used for display watermark bandwidth calculations
888 * Returns the dram bandwidth for display in MBytes/s
890 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
892 /* Calculate DRAM Bandwidth and the part allocated to display. */
893 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
894 fixed20_12 yclk, dram_channels, bandwidth;
897 a.full = dfixed_const(1000);
898 yclk.full = dfixed_const(wm->yclk);
899 yclk.full = dfixed_div(yclk, a);
900 dram_channels.full = dfixed_const(wm->dram_channels * 4);
901 a.full = dfixed_const(10);
902 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
903 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
904 bandwidth.full = dfixed_mul(dram_channels, yclk);
905 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
907 return dfixed_trunc(bandwidth);
911 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
913 * @wm: watermark calculation data
915 * Calculate the data return bandwidth used for display (CIK).
916 * Used for display watermark bandwidth calculations
917 * Returns the data return bandwidth in MBytes/s
919 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
921 /* Calculate the display Data return Bandwidth */
922 fixed20_12 return_efficiency; /* 0.8 */
923 fixed20_12 sclk, bandwidth;
926 a.full = dfixed_const(1000);
927 sclk.full = dfixed_const(wm->sclk);
928 sclk.full = dfixed_div(sclk, a);
929 a.full = dfixed_const(10);
930 return_efficiency.full = dfixed_const(8);
931 return_efficiency.full = dfixed_div(return_efficiency, a);
932 a.full = dfixed_const(32);
933 bandwidth.full = dfixed_mul(a, sclk);
934 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
936 return dfixed_trunc(bandwidth);
940 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
942 * @wm: watermark calculation data
944 * Calculate the dmif bandwidth used for display (CIK).
945 * Used for display watermark bandwidth calculations
946 * Returns the dmif bandwidth in MBytes/s
948 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
950 /* Calculate the DMIF Request Bandwidth */
951 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
952 fixed20_12 disp_clk, bandwidth;
955 a.full = dfixed_const(1000);
956 disp_clk.full = dfixed_const(wm->disp_clk);
957 disp_clk.full = dfixed_div(disp_clk, a);
958 a.full = dfixed_const(32);
959 b.full = dfixed_mul(a, disp_clk);
961 a.full = dfixed_const(10);
962 disp_clk_request_efficiency.full = dfixed_const(8);
963 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
965 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
967 return dfixed_trunc(bandwidth);
971 * dce_v11_0_available_bandwidth - get the min available bandwidth
973 * @wm: watermark calculation data
975 * Calculate the min available bandwidth used for display (CIK).
976 * Used for display watermark bandwidth calculations
977 * Returns the min available bandwidth in MBytes/s
979 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
981 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
982 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
983 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
984 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
986 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
990 * dce_v11_0_average_bandwidth - get the average available bandwidth
992 * @wm: watermark calculation data
994 * Calculate the average available bandwidth used for display (CIK).
995 * Used for display watermark bandwidth calculations
996 * Returns the average available bandwidth in MBytes/s
998 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
1000 /* Calculate the display mode Average Bandwidth
1001 * DisplayMode should contain the source and destination dimensions,
1005 fixed20_12 line_time;
1006 fixed20_12 src_width;
1007 fixed20_12 bandwidth;
1010 a.full = dfixed_const(1000);
1011 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1012 line_time.full = dfixed_div(line_time, a);
1013 bpp.full = dfixed_const(wm->bytes_per_pixel);
1014 src_width.full = dfixed_const(wm->src_width);
1015 bandwidth.full = dfixed_mul(src_width, bpp);
1016 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1017 bandwidth.full = dfixed_div(bandwidth, line_time);
1019 return dfixed_trunc(bandwidth);
1023 * dce_v11_0_latency_watermark - get the latency watermark
1025 * @wm: watermark calculation data
1027 * Calculate the latency watermark (CIK).
1028 * Used for display watermark bandwidth calculations
1029 * Returns the latency watermark in ns
1031 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1033 /* First calculate the latency in ns */
1034 u32 mc_latency = 2000; /* 2000 ns. */
1035 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1036 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1037 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1038 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1039 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1040 (wm->num_heads * cursor_line_pair_return_time);
1041 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1042 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1043 u32 tmp, dmif_size = 12288;
1046 if (wm->num_heads == 0)
1049 a.full = dfixed_const(2);
1050 b.full = dfixed_const(1);
1051 if ((wm->vsc.full > a.full) ||
1052 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1054 ((wm->vsc.full >= a.full) && wm->interlaced))
1055 max_src_lines_per_dst_line = 4;
1057 max_src_lines_per_dst_line = 2;
1059 a.full = dfixed_const(available_bandwidth);
1060 b.full = dfixed_const(wm->num_heads);
1061 a.full = dfixed_div(a, b);
1063 b.full = dfixed_const(mc_latency + 512);
1064 c.full = dfixed_const(wm->disp_clk);
1065 b.full = dfixed_div(b, c);
1067 c.full = dfixed_const(dmif_size);
1068 b.full = dfixed_div(c, b);
1070 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1072 b.full = dfixed_const(1000);
1073 c.full = dfixed_const(wm->disp_clk);
1074 b.full = dfixed_div(c, b);
1075 c.full = dfixed_const(wm->bytes_per_pixel);
1076 b.full = dfixed_mul(b, c);
1078 lb_fill_bw = min(tmp, dfixed_trunc(b));
1080 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1081 b.full = dfixed_const(1000);
1082 c.full = dfixed_const(lb_fill_bw);
1083 b.full = dfixed_div(c, b);
1084 a.full = dfixed_div(a, b);
1085 line_fill_time = dfixed_trunc(a);
1087 if (line_fill_time < wm->active_time)
1090 return latency + (line_fill_time - wm->active_time);
1095 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1096 * average and available dram bandwidth
1098 * @wm: watermark calculation data
1100 * Check if the display average bandwidth fits in the display
1101 * dram bandwidth (CIK).
1102 * Used for display watermark bandwidth calculations
1103 * Returns true if the display fits, false if not.
1105 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1107 if (dce_v11_0_average_bandwidth(wm) <=
1108 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1115 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1116 * average and available bandwidth
1118 * @wm: watermark calculation data
1120 * Check if the display average bandwidth fits in the display
1121 * available bandwidth (CIK).
1122 * Used for display watermark bandwidth calculations
1123 * Returns true if the display fits, false if not.
1125 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1127 if (dce_v11_0_average_bandwidth(wm) <=
1128 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1135 * dce_v11_0_check_latency_hiding - check latency hiding
1137 * @wm: watermark calculation data
1139 * Check latency hiding (CIK).
1140 * Used for display watermark bandwidth calculations
1141 * Returns true if the display fits, false if not.
1143 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1145 u32 lb_partitions = wm->lb_size / wm->src_width;
1146 u32 line_time = wm->active_time + wm->blank_time;
1147 u32 latency_tolerant_lines;
1151 a.full = dfixed_const(1);
1152 if (wm->vsc.full > a.full)
1153 latency_tolerant_lines = 1;
1155 if (lb_partitions <= (wm->vtaps + 1))
1156 latency_tolerant_lines = 1;
1158 latency_tolerant_lines = 2;
1161 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1163 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1170 * dce_v11_0_program_watermarks - program display watermarks
1172 * @adev: amdgpu_device pointer
1173 * @amdgpu_crtc: the selected display controller
1174 * @lb_size: line buffer size
1175 * @num_heads: number of display controllers in use
1177 * Calculate and program the display watermarks for the
1178 * selected display controller (CIK).
1180 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1181 struct amdgpu_crtc *amdgpu_crtc,
1182 u32 lb_size, u32 num_heads)
1184 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1185 struct dce10_wm_params wm_low, wm_high;
1188 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1189 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1191 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1192 pixel_period = 1000000 / (u32)mode->clock;
1193 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1195 /* watermark for high clocks */
1196 if (adev->pm.dpm_enabled) {
1198 amdgpu_dpm_get_mclk(adev, false) * 10;
1200 amdgpu_dpm_get_sclk(adev, false) * 10;
1202 wm_high.yclk = adev->pm.current_mclk * 10;
1203 wm_high.sclk = adev->pm.current_sclk * 10;
1206 wm_high.disp_clk = mode->clock;
1207 wm_high.src_width = mode->crtc_hdisplay;
1208 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1209 wm_high.blank_time = line_time - wm_high.active_time;
1210 wm_high.interlaced = false;
1211 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1212 wm_high.interlaced = true;
1213 wm_high.vsc = amdgpu_crtc->vsc;
1215 if (amdgpu_crtc->rmx_type != RMX_OFF)
1217 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1218 wm_high.lb_size = lb_size;
1219 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1220 wm_high.num_heads = num_heads;
1222 /* set for high clocks */
1223 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1225 /* possibly force display priority to high */
1226 /* should really do this at mode validation time... */
1227 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1228 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1229 !dce_v11_0_check_latency_hiding(&wm_high) ||
1230 (adev->mode_info.disp_priority == 2)) {
1231 DRM_DEBUG_KMS("force priority to high\n");
1234 /* watermark for low clocks */
1235 if (adev->pm.dpm_enabled) {
1237 amdgpu_dpm_get_mclk(adev, true) * 10;
1239 amdgpu_dpm_get_sclk(adev, true) * 10;
1241 wm_low.yclk = adev->pm.current_mclk * 10;
1242 wm_low.sclk = adev->pm.current_sclk * 10;
1245 wm_low.disp_clk = mode->clock;
1246 wm_low.src_width = mode->crtc_hdisplay;
1247 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1248 wm_low.blank_time = line_time - wm_low.active_time;
1249 wm_low.interlaced = false;
1250 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1251 wm_low.interlaced = true;
1252 wm_low.vsc = amdgpu_crtc->vsc;
1254 if (amdgpu_crtc->rmx_type != RMX_OFF)
1256 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1257 wm_low.lb_size = lb_size;
1258 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1259 wm_low.num_heads = num_heads;
1261 /* set for low clocks */
1262 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1264 /* possibly force display priority to high */
1265 /* should really do this at mode validation time... */
1266 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1267 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1268 !dce_v11_0_check_latency_hiding(&wm_low) ||
1269 (adev->mode_info.disp_priority == 2)) {
1270 DRM_DEBUG_KMS("force priority to high\n");
1272 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1276 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1277 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1278 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1279 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1280 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1281 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1282 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1284 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1285 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1286 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1287 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1288 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1289 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1290 /* restore original selection */
1291 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1293 /* save values for DPM */
1294 amdgpu_crtc->line_time = line_time;
1295 amdgpu_crtc->wm_high = latency_watermark_a;
1296 amdgpu_crtc->wm_low = latency_watermark_b;
1297 /* Save number of lines the linebuffer leads before the scanout */
1298 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1302 * dce_v11_0_bandwidth_update - program display watermarks
1304 * @adev: amdgpu_device pointer
1306 * Calculate and program the display watermarks and line
1307 * buffer allocation (CIK).
1309 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1311 struct drm_display_mode *mode = NULL;
1312 u32 num_heads = 0, lb_size;
1315 amdgpu_update_display_priority(adev);
1317 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1318 if (adev->mode_info.crtcs[i]->base.enabled)
1321 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1322 mode = &adev->mode_info.crtcs[i]->base.mode;
1323 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1324 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1325 lb_size, num_heads);
1329 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1334 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1335 offset = adev->mode_info.audio.pin[i].offset;
1336 tmp = RREG32_AUDIO_ENDPT(offset,
1337 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1339 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1340 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1341 adev->mode_info.audio.pin[i].connected = false;
1343 adev->mode_info.audio.pin[i].connected = true;
1347 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1351 dce_v11_0_audio_get_connected_pins(adev);
1353 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1354 if (adev->mode_info.audio.pin[i].connected)
1355 return &adev->mode_info.audio.pin[i];
1357 DRM_ERROR("No connected audio pins found!\n");
1361 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1363 struct amdgpu_device *adev = encoder->dev->dev_private;
1364 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1365 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1368 if (!dig || !dig->afmt || !dig->afmt->pin)
1371 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1372 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1373 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1376 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1377 struct drm_display_mode *mode)
1379 struct amdgpu_device *adev = encoder->dev->dev_private;
1380 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1381 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1382 struct drm_connector *connector;
1383 struct amdgpu_connector *amdgpu_connector = NULL;
1387 if (!dig || !dig->afmt || !dig->afmt->pin)
1390 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1391 if (connector->encoder == encoder) {
1392 amdgpu_connector = to_amdgpu_connector(connector);
1397 if (!amdgpu_connector) {
1398 DRM_ERROR("Couldn't find encoder's connector\n");
1402 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1404 if (connector->latency_present[interlace]) {
1405 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1406 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1407 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1408 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1410 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1412 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1415 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1416 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1419 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1421 struct amdgpu_device *adev = encoder->dev->dev_private;
1422 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1423 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1424 struct drm_connector *connector;
1425 struct amdgpu_connector *amdgpu_connector = NULL;
1430 if (!dig || !dig->afmt || !dig->afmt->pin)
1433 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1434 if (connector->encoder == encoder) {
1435 amdgpu_connector = to_amdgpu_connector(connector);
1440 if (!amdgpu_connector) {
1441 DRM_ERROR("Couldn't find encoder's connector\n");
1445 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1446 if (sad_count < 0) {
1447 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1451 /* program the speaker allocation */
1452 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1453 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1454 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1457 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1458 HDMI_CONNECTION, 1);
1460 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1461 SPEAKER_ALLOCATION, sadb[0]);
1463 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1464 SPEAKER_ALLOCATION, 5); /* stereo */
1465 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1466 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1471 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1473 struct amdgpu_device *adev = encoder->dev->dev_private;
1474 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1475 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1476 struct drm_connector *connector;
1477 struct amdgpu_connector *amdgpu_connector = NULL;
1478 struct cea_sad *sads;
1481 static const u16 eld_reg_to_type[][2] = {
1482 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1483 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1484 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1485 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1486 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1487 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1488 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1489 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1490 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1491 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1492 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1493 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1496 if (!dig || !dig->afmt || !dig->afmt->pin)
1499 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1500 if (connector->encoder == encoder) {
1501 amdgpu_connector = to_amdgpu_connector(connector);
1506 if (!amdgpu_connector) {
1507 DRM_ERROR("Couldn't find encoder's connector\n");
1511 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1512 if (sad_count <= 0) {
1513 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1518 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1520 u8 stereo_freqs = 0;
1521 int max_channels = -1;
1524 for (j = 0; j < sad_count; j++) {
1525 struct cea_sad *sad = &sads[j];
1527 if (sad->format == eld_reg_to_type[i][1]) {
1528 if (sad->channels > max_channels) {
1529 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1530 MAX_CHANNELS, sad->channels);
1531 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1532 DESCRIPTOR_BYTE_2, sad->byte2);
1533 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1534 SUPPORTED_FREQUENCIES, sad->freq);
1535 max_channels = sad->channels;
1538 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1539 stereo_freqs |= sad->freq;
1545 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1546 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1547 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1553 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1554 struct amdgpu_audio_pin *pin,
1560 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1561 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1564 static const u32 pin_offsets[] =
1566 AUD0_REGISTER_OFFSET,
1567 AUD1_REGISTER_OFFSET,
1568 AUD2_REGISTER_OFFSET,
1569 AUD3_REGISTER_OFFSET,
1570 AUD4_REGISTER_OFFSET,
1571 AUD5_REGISTER_OFFSET,
1572 AUD6_REGISTER_OFFSET,
1573 AUD7_REGISTER_OFFSET,
1576 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1583 adev->mode_info.audio.enabled = true;
1585 switch (adev->asic_type) {
1588 adev->mode_info.audio.num_pins = 7;
1590 case CHIP_POLARIS10:
1591 adev->mode_info.audio.num_pins = 8;
1593 case CHIP_POLARIS11:
1594 case CHIP_POLARIS12:
1595 adev->mode_info.audio.num_pins = 6;
1601 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1602 adev->mode_info.audio.pin[i].channels = -1;
1603 adev->mode_info.audio.pin[i].rate = -1;
1604 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1605 adev->mode_info.audio.pin[i].status_bits = 0;
1606 adev->mode_info.audio.pin[i].category_code = 0;
1607 adev->mode_info.audio.pin[i].connected = false;
1608 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1609 adev->mode_info.audio.pin[i].id = i;
1610 /* disable audio. it will be set up later */
1611 /* XXX remove once we switch to ip funcs */
1612 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1618 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1625 if (!adev->mode_info.audio.enabled)
1628 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1629 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1631 adev->mode_info.audio.enabled = false;
1635 * update the N and CTS parameters for a given pixel clock rate
1637 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1639 struct drm_device *dev = encoder->dev;
1640 struct amdgpu_device *adev = dev->dev_private;
1641 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1642 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1643 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1646 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1647 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1648 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1649 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1650 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1651 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1653 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1654 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1655 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1656 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1657 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1658 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1660 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1661 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1662 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1663 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1664 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1665 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1670 * build a HDMI Video Info Frame
1672 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1673 void *buffer, size_t size)
1675 struct drm_device *dev = encoder->dev;
1676 struct amdgpu_device *adev = dev->dev_private;
1677 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1678 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1679 uint8_t *frame = buffer + 3;
1680 uint8_t *header = buffer;
1682 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1683 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1684 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1685 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1686 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1687 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1688 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1689 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1692 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1694 struct drm_device *dev = encoder->dev;
1695 struct amdgpu_device *adev = dev->dev_private;
1696 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1697 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1698 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1699 u32 dto_phase = 24 * 1000;
1700 u32 dto_modulo = clock;
1703 if (!dig || !dig->afmt)
1706 /* XXX two dtos; generally use dto0 for hdmi */
1707 /* Express [24MHz / target pixel clock] as an exact rational
1708 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1709 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1711 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1712 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1713 amdgpu_crtc->crtc_id);
1714 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1715 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1716 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1720 * update the info frames with the data from the current display mode
1722 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1723 struct drm_display_mode *mode)
1725 struct drm_device *dev = encoder->dev;
1726 struct amdgpu_device *adev = dev->dev_private;
1727 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1728 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1729 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1730 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1731 struct hdmi_avi_infoframe frame;
1736 if (!dig || !dig->afmt)
1739 /* Silent, r600_hdmi_enable will raise WARN for us */
1740 if (!dig->afmt->enabled)
1743 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1744 if (encoder->crtc) {
1745 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1746 bpc = amdgpu_crtc->bpc;
1749 /* disable audio prior to setting up hw */
1750 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1751 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1753 dce_v11_0_audio_set_dto(encoder, mode->clock);
1755 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1756 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1757 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1759 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1761 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1768 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1769 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1770 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1771 connector->name, bpc);
1774 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1775 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1776 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1780 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1781 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1782 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1786 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1788 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1789 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1790 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1791 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1792 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1794 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1795 /* enable audio info frames (frames won't be set until audio is enabled) */
1796 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1797 /* required for audio info values to be updated */
1798 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1799 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1801 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1802 /* required for audio info values to be updated */
1803 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1804 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1806 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1807 /* anything other than 0 */
1808 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1809 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1811 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1813 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1814 /* set the default audio delay */
1815 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1816 /* should be suffient for all audio modes and small enough for all hblanks */
1817 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1818 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1820 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1821 /* allow 60958 channel status fields to be updated */
1822 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1823 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1825 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1827 /* clear SW CTS value */
1828 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1830 /* select SW CTS value */
1831 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1832 /* allow hw to sent ACR packets when required */
1833 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1834 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1836 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1838 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1839 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1840 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1842 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1843 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1844 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1846 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1847 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1848 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1849 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1850 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1851 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1852 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1853 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1855 dce_v11_0_audio_write_speaker_allocation(encoder);
1857 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1858 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1860 dce_v11_0_afmt_audio_select_pin(encoder);
1861 dce_v11_0_audio_write_sad_regs(encoder);
1862 dce_v11_0_audio_write_latency_fields(encoder, mode);
1864 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1866 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1870 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1872 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1876 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1878 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1879 /* enable AVI info frames */
1880 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1881 /* required for audio info values to be updated */
1882 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1883 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1885 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1886 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1887 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1889 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1890 /* send audio packets */
1891 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1892 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1894 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1895 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1896 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1897 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1899 /* enable audio after to setting up hw */
1900 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1903 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1905 struct drm_device *dev = encoder->dev;
1906 struct amdgpu_device *adev = dev->dev_private;
1907 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1908 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1910 if (!dig || !dig->afmt)
1913 /* Silent, r600_hdmi_enable will raise WARN for us */
1914 if (enable && dig->afmt->enabled)
1916 if (!enable && !dig->afmt->enabled)
1919 if (!enable && dig->afmt->pin) {
1920 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1921 dig->afmt->pin = NULL;
1924 dig->afmt->enabled = enable;
1926 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1927 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1930 static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1934 for (i = 0; i < adev->mode_info.num_dig; i++)
1935 adev->mode_info.afmt[i] = NULL;
1937 /* DCE11 has audio blocks tied to DIG encoders */
1938 for (i = 0; i < adev->mode_info.num_dig; i++) {
1939 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1940 if (adev->mode_info.afmt[i]) {
1941 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1942 adev->mode_info.afmt[i]->id = i;
1945 for (j = 0; j < i; j++) {
1946 kfree(adev->mode_info.afmt[j]);
1947 adev->mode_info.afmt[j] = NULL;
1955 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1959 for (i = 0; i < adev->mode_info.num_dig; i++) {
1960 kfree(adev->mode_info.afmt[i]);
1961 adev->mode_info.afmt[i] = NULL;
1965 static const u32 vga_control_regs[6] =
1975 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1977 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1978 struct drm_device *dev = crtc->dev;
1979 struct amdgpu_device *adev = dev->dev_private;
1982 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1984 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1986 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1989 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1991 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1992 struct drm_device *dev = crtc->dev;
1993 struct amdgpu_device *adev = dev->dev_private;
1996 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1998 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2001 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2002 struct drm_framebuffer *fb,
2003 int x, int y, int atomic)
2005 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2006 struct drm_device *dev = crtc->dev;
2007 struct amdgpu_device *adev = dev->dev_private;
2008 struct amdgpu_framebuffer *amdgpu_fb;
2009 struct drm_framebuffer *target_fb;
2010 struct drm_gem_object *obj;
2011 struct amdgpu_bo *abo;
2012 uint64_t fb_location, tiling_flags;
2013 uint32_t fb_format, fb_pitch_pixels;
2014 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2016 u32 tmp, viewport_w, viewport_h;
2018 bool bypass_lut = false;
2019 struct drm_format_name_buf format_name;
2022 if (!atomic && !crtc->primary->fb) {
2023 DRM_DEBUG_KMS("No FB bound\n");
2028 amdgpu_fb = to_amdgpu_framebuffer(fb);
2031 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2032 target_fb = crtc->primary->fb;
2035 /* If atomic, assume fb object is pinned & idle & fenced and
2036 * just update base pointers
2038 obj = amdgpu_fb->obj;
2039 abo = gem_to_amdgpu_bo(obj);
2040 r = amdgpu_bo_reserve(abo, false);
2041 if (unlikely(r != 0))
2045 fb_location = amdgpu_bo_gpu_offset(abo);
2047 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2048 if (unlikely(r != 0)) {
2049 amdgpu_bo_unreserve(abo);
2054 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
2055 amdgpu_bo_unreserve(abo);
2057 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2059 switch (target_fb->format->format) {
2061 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2062 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2064 case DRM_FORMAT_XRGB4444:
2065 case DRM_FORMAT_ARGB4444:
2066 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2067 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2069 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2073 case DRM_FORMAT_XRGB1555:
2074 case DRM_FORMAT_ARGB1555:
2075 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2076 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2078 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2082 case DRM_FORMAT_BGRX5551:
2083 case DRM_FORMAT_BGRA5551:
2084 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2085 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2087 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2091 case DRM_FORMAT_RGB565:
2092 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2093 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2095 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2099 case DRM_FORMAT_XRGB8888:
2100 case DRM_FORMAT_ARGB8888:
2101 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2102 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2104 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2108 case DRM_FORMAT_XRGB2101010:
2109 case DRM_FORMAT_ARGB2101010:
2110 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2111 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2113 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2116 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2119 case DRM_FORMAT_BGRX1010102:
2120 case DRM_FORMAT_BGRA1010102:
2121 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2122 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2124 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2127 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2131 DRM_ERROR("Unsupported screen format %s\n",
2132 drm_get_format_name(target_fb->format->format, &format_name));
2136 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2137 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2139 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2140 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2141 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2142 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2143 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2145 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2146 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2147 ARRAY_2D_TILED_THIN1);
2148 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2150 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2151 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2152 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2154 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2155 ADDR_SURF_MICRO_TILING_DISPLAY);
2156 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2157 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2158 ARRAY_1D_TILED_THIN1);
2161 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2164 dce_v11_0_vga_enable(crtc, false);
2166 /* Make sure surface address is updated at vertical blank rather than
2169 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2170 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2171 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2172 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2174 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2175 upper_32_bits(fb_location));
2176 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2177 upper_32_bits(fb_location));
2178 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2179 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2180 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2181 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2182 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2183 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2186 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2187 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2188 * retain the full precision throughout the pipeline.
2190 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2192 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2194 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2195 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2198 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2200 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2201 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2202 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2203 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2204 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2205 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2207 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2208 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2210 dce_v11_0_grph_enable(crtc, true);
2212 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2217 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2219 viewport_w = crtc->mode.hdisplay;
2220 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2221 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2222 (viewport_w << 16) | viewport_h);
2224 /* set pageflip to happen anywhere in vblank interval */
2225 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2227 if (!atomic && fb && fb != crtc->primary->fb) {
2228 amdgpu_fb = to_amdgpu_framebuffer(fb);
2229 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2230 r = amdgpu_bo_reserve(abo, false);
2231 if (unlikely(r != 0))
2233 amdgpu_bo_unpin(abo);
2234 amdgpu_bo_unreserve(abo);
2237 /* Bytes per pixel may have changed */
2238 dce_v11_0_bandwidth_update(adev);
2243 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2244 struct drm_display_mode *mode)
2246 struct drm_device *dev = crtc->dev;
2247 struct amdgpu_device *adev = dev->dev_private;
2248 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2251 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2252 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2253 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2255 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2256 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2259 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2261 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2262 struct drm_device *dev = crtc->dev;
2263 struct amdgpu_device *adev = dev->dev_private;
2267 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2269 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2270 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2271 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2273 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2274 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2275 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2277 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2278 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2279 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2281 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2283 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2284 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2285 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2287 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2288 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2289 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2291 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2292 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2294 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2295 for (i = 0; i < 256; i++) {
2296 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2297 (amdgpu_crtc->lut_r[i] << 20) |
2298 (amdgpu_crtc->lut_g[i] << 10) |
2299 (amdgpu_crtc->lut_b[i] << 0));
2302 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2303 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2304 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2305 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2306 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2308 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2309 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2310 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2312 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2313 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2314 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2316 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2317 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2318 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2320 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2321 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2322 /* XXX this only needs to be programmed once per crtc at startup,
2323 * not sure where the best place for it is
2325 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2326 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2327 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2330 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2332 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2333 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2335 switch (amdgpu_encoder->encoder_id) {
2336 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2342 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2348 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2354 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2358 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2364 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2368 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2369 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2370 * monitors a dedicated PPLL must be used. If a particular board has
2371 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2372 * as there is no need to program the PLL itself. If we are not able to
2373 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2374 * avoid messing up an existing monitor.
2376 * Asic specific PLL information
2380 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2382 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2385 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2387 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2388 struct drm_device *dev = crtc->dev;
2389 struct amdgpu_device *adev = dev->dev_private;
2393 if ((adev->asic_type == CHIP_POLARIS10) ||
2394 (adev->asic_type == CHIP_POLARIS11) ||
2395 (adev->asic_type == CHIP_POLARIS12)) {
2396 struct amdgpu_encoder *amdgpu_encoder =
2397 to_amdgpu_encoder(amdgpu_crtc->encoder);
2398 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2400 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2403 switch (amdgpu_encoder->encoder_id) {
2404 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2406 return ATOM_COMBOPHY_PLL1;
2408 return ATOM_COMBOPHY_PLL0;
2410 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2412 return ATOM_COMBOPHY_PLL3;
2414 return ATOM_COMBOPHY_PLL2;
2416 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2418 return ATOM_COMBOPHY_PLL5;
2420 return ATOM_COMBOPHY_PLL4;
2423 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2424 return ATOM_PPLL_INVALID;
2428 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2429 if (adev->clock.dp_extclk)
2430 /* skip PPLL programming if using ext clock */
2431 return ATOM_PPLL_INVALID;
2433 /* use the same PPLL for all DP monitors */
2434 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2435 if (pll != ATOM_PPLL_INVALID)
2439 /* use the same PPLL for all monitors with the same clock */
2440 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2441 if (pll != ATOM_PPLL_INVALID)
2445 /* XXX need to determine what plls are available on each DCE11 part */
2446 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2447 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2448 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2450 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2452 DRM_ERROR("unable to allocate a PPLL\n");
2453 return ATOM_PPLL_INVALID;
2455 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2457 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2459 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2461 DRM_ERROR("unable to allocate a PPLL\n");
2462 return ATOM_PPLL_INVALID;
2464 return ATOM_PPLL_INVALID;
2467 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2469 struct amdgpu_device *adev = crtc->dev->dev_private;
2470 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2473 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2475 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2477 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2478 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2481 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2483 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2484 struct amdgpu_device *adev = crtc->dev->dev_private;
2487 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2488 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2489 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2492 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2494 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2495 struct amdgpu_device *adev = crtc->dev->dev_private;
2498 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2499 upper_32_bits(amdgpu_crtc->cursor_addr));
2500 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2501 lower_32_bits(amdgpu_crtc->cursor_addr));
2503 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2504 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2505 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2506 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2509 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2512 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2513 struct amdgpu_device *adev = crtc->dev->dev_private;
2514 int xorigin = 0, yorigin = 0;
2516 amdgpu_crtc->cursor_x = x;
2517 amdgpu_crtc->cursor_y = y;
2519 /* avivo cursor are offset into the total surface */
2522 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2525 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2529 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2533 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2534 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2535 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2536 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2541 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2546 dce_v11_0_lock_cursor(crtc, true);
2547 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2548 dce_v11_0_lock_cursor(crtc, false);
2553 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2554 struct drm_file *file_priv,
2561 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2562 struct drm_gem_object *obj;
2563 struct amdgpu_bo *aobj;
2567 /* turn off cursor */
2568 dce_v11_0_hide_cursor(crtc);
2573 if ((width > amdgpu_crtc->max_cursor_width) ||
2574 (height > amdgpu_crtc->max_cursor_height)) {
2575 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2579 obj = drm_gem_object_lookup(file_priv, handle);
2581 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2585 aobj = gem_to_amdgpu_bo(obj);
2586 ret = amdgpu_bo_reserve(aobj, false);
2588 drm_gem_object_unreference_unlocked(obj);
2592 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2593 amdgpu_bo_unreserve(aobj);
2595 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2596 drm_gem_object_unreference_unlocked(obj);
2600 dce_v11_0_lock_cursor(crtc, true);
2602 if (width != amdgpu_crtc->cursor_width ||
2603 height != amdgpu_crtc->cursor_height ||
2604 hot_x != amdgpu_crtc->cursor_hot_x ||
2605 hot_y != amdgpu_crtc->cursor_hot_y) {
2608 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2609 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2611 dce_v11_0_cursor_move_locked(crtc, x, y);
2613 amdgpu_crtc->cursor_width = width;
2614 amdgpu_crtc->cursor_height = height;
2615 amdgpu_crtc->cursor_hot_x = hot_x;
2616 amdgpu_crtc->cursor_hot_y = hot_y;
2619 dce_v11_0_show_cursor(crtc);
2620 dce_v11_0_lock_cursor(crtc, false);
2623 if (amdgpu_crtc->cursor_bo) {
2624 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2625 ret = amdgpu_bo_reserve(aobj, false);
2626 if (likely(ret == 0)) {
2627 amdgpu_bo_unpin(aobj);
2628 amdgpu_bo_unreserve(aobj);
2630 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2633 amdgpu_crtc->cursor_bo = obj;
2637 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2639 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2641 if (amdgpu_crtc->cursor_bo) {
2642 dce_v11_0_lock_cursor(crtc, true);
2644 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2645 amdgpu_crtc->cursor_y);
2647 dce_v11_0_show_cursor(crtc);
2649 dce_v11_0_lock_cursor(crtc, false);
2653 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2654 u16 *blue, uint32_t size)
2656 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2659 /* userspace palettes are always correct as is */
2660 for (i = 0; i < size; i++) {
2661 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2662 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2663 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2665 dce_v11_0_crtc_load_lut(crtc);
2670 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2672 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2674 drm_crtc_cleanup(crtc);
2678 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2679 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2680 .cursor_move = dce_v11_0_crtc_cursor_move,
2681 .gamma_set = dce_v11_0_crtc_gamma_set,
2682 .set_config = amdgpu_crtc_set_config,
2683 .destroy = dce_v11_0_crtc_destroy,
2684 .page_flip_target = amdgpu_crtc_page_flip_target,
2687 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2689 struct drm_device *dev = crtc->dev;
2690 struct amdgpu_device *adev = dev->dev_private;
2691 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2695 case DRM_MODE_DPMS_ON:
2696 amdgpu_crtc->enabled = true;
2697 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2698 dce_v11_0_vga_enable(crtc, true);
2699 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2700 dce_v11_0_vga_enable(crtc, false);
2701 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2702 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2703 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2704 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2705 drm_crtc_vblank_on(crtc);
2706 dce_v11_0_crtc_load_lut(crtc);
2708 case DRM_MODE_DPMS_STANDBY:
2709 case DRM_MODE_DPMS_SUSPEND:
2710 case DRM_MODE_DPMS_OFF:
2711 drm_crtc_vblank_off(crtc);
2712 if (amdgpu_crtc->enabled) {
2713 dce_v11_0_vga_enable(crtc, true);
2714 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2715 dce_v11_0_vga_enable(crtc, false);
2717 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2718 amdgpu_crtc->enabled = false;
2721 /* adjust pm to dpms */
2722 amdgpu_pm_compute_clocks(adev);
2725 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2727 /* disable crtc pair power gating before programming */
2728 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2729 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2730 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2733 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2735 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2736 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2739 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2741 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2742 struct drm_device *dev = crtc->dev;
2743 struct amdgpu_device *adev = dev->dev_private;
2744 struct amdgpu_atom_ss ss;
2747 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2748 if (crtc->primary->fb) {
2750 struct amdgpu_framebuffer *amdgpu_fb;
2751 struct amdgpu_bo *abo;
2753 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2754 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2755 r = amdgpu_bo_reserve(abo, false);
2757 DRM_ERROR("failed to reserve abo before unpin\n");
2759 amdgpu_bo_unpin(abo);
2760 amdgpu_bo_unreserve(abo);
2763 /* disable the GRPH */
2764 dce_v11_0_grph_enable(crtc, false);
2766 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2768 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2769 if (adev->mode_info.crtcs[i] &&
2770 adev->mode_info.crtcs[i]->enabled &&
2771 i != amdgpu_crtc->crtc_id &&
2772 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2773 /* one other crtc is using this pll don't turn
2780 switch (amdgpu_crtc->pll_id) {
2784 /* disable the ppll */
2785 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2786 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2788 case ATOM_COMBOPHY_PLL0:
2789 case ATOM_COMBOPHY_PLL1:
2790 case ATOM_COMBOPHY_PLL2:
2791 case ATOM_COMBOPHY_PLL3:
2792 case ATOM_COMBOPHY_PLL4:
2793 case ATOM_COMBOPHY_PLL5:
2794 /* disable the ppll */
2795 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2796 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2802 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2803 amdgpu_crtc->adjusted_clock = 0;
2804 amdgpu_crtc->encoder = NULL;
2805 amdgpu_crtc->connector = NULL;
2808 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2809 struct drm_display_mode *mode,
2810 struct drm_display_mode *adjusted_mode,
2811 int x, int y, struct drm_framebuffer *old_fb)
2813 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2814 struct drm_device *dev = crtc->dev;
2815 struct amdgpu_device *adev = dev->dev_private;
2817 if (!amdgpu_crtc->adjusted_clock)
2820 if ((adev->asic_type == CHIP_POLARIS10) ||
2821 (adev->asic_type == CHIP_POLARIS11) ||
2822 (adev->asic_type == CHIP_POLARIS12)) {
2823 struct amdgpu_encoder *amdgpu_encoder =
2824 to_amdgpu_encoder(amdgpu_crtc->encoder);
2826 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2828 /* SetPixelClock calculates the plls and ss values now */
2829 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2830 amdgpu_crtc->pll_id,
2831 encoder_mode, amdgpu_encoder->encoder_id,
2832 adjusted_mode->clock, 0, 0, 0, 0,
2833 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2835 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2837 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2838 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2839 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2840 amdgpu_atombios_crtc_scaler_setup(crtc);
2841 dce_v11_0_cursor_reset(crtc);
2842 /* update the hw version fpr dpm */
2843 amdgpu_crtc->hw_mode = *adjusted_mode;
2848 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2849 const struct drm_display_mode *mode,
2850 struct drm_display_mode *adjusted_mode)
2852 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2853 struct drm_device *dev = crtc->dev;
2854 struct drm_encoder *encoder;
2856 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2857 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2858 if (encoder->crtc == crtc) {
2859 amdgpu_crtc->encoder = encoder;
2860 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2864 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2865 amdgpu_crtc->encoder = NULL;
2866 amdgpu_crtc->connector = NULL;
2869 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2871 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2874 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2875 /* if we can't get a PPLL for a non-DP encoder, fail */
2876 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2877 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2883 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2884 struct drm_framebuffer *old_fb)
2886 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2889 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2890 struct drm_framebuffer *fb,
2891 int x, int y, enum mode_set_atomic state)
2893 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2896 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2897 .dpms = dce_v11_0_crtc_dpms,
2898 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2899 .mode_set = dce_v11_0_crtc_mode_set,
2900 .mode_set_base = dce_v11_0_crtc_set_base,
2901 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2902 .prepare = dce_v11_0_crtc_prepare,
2903 .commit = dce_v11_0_crtc_commit,
2904 .load_lut = dce_v11_0_crtc_load_lut,
2905 .disable = dce_v11_0_crtc_disable,
2908 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2910 struct amdgpu_crtc *amdgpu_crtc;
2913 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2914 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2915 if (amdgpu_crtc == NULL)
2918 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2920 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2921 amdgpu_crtc->crtc_id = index;
2922 adev->mode_info.crtcs[index] = amdgpu_crtc;
2924 amdgpu_crtc->max_cursor_width = 128;
2925 amdgpu_crtc->max_cursor_height = 128;
2926 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2927 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2929 for (i = 0; i < 256; i++) {
2930 amdgpu_crtc->lut_r[i] = i << 2;
2931 amdgpu_crtc->lut_g[i] = i << 2;
2932 amdgpu_crtc->lut_b[i] = i << 2;
2935 switch (amdgpu_crtc->crtc_id) {
2938 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2941 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2944 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2947 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2950 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2953 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2957 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2958 amdgpu_crtc->adjusted_clock = 0;
2959 amdgpu_crtc->encoder = NULL;
2960 amdgpu_crtc->connector = NULL;
2961 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2966 static int dce_v11_0_early_init(void *handle)
2968 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2970 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2971 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2973 dce_v11_0_set_display_funcs(adev);
2974 dce_v11_0_set_irq_funcs(adev);
2976 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2978 switch (adev->asic_type) {
2980 adev->mode_info.num_hpd = 6;
2981 adev->mode_info.num_dig = 9;
2984 adev->mode_info.num_hpd = 6;
2985 adev->mode_info.num_dig = 9;
2987 case CHIP_POLARIS10:
2988 adev->mode_info.num_hpd = 6;
2989 adev->mode_info.num_dig = 6;
2991 case CHIP_POLARIS11:
2992 case CHIP_POLARIS12:
2993 adev->mode_info.num_hpd = 5;
2994 adev->mode_info.num_dig = 5;
2997 /* FIXME: not supported yet */
3004 static int dce_v11_0_sw_init(void *handle)
3007 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3009 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3010 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
3015 for (i = 8; i < 20; i += 2) {
3016 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
3022 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
3026 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
3028 adev->ddev->mode_config.async_page_flip = true;
3030 adev->ddev->mode_config.max_width = 16384;
3031 adev->ddev->mode_config.max_height = 16384;
3033 adev->ddev->mode_config.preferred_depth = 24;
3034 adev->ddev->mode_config.prefer_shadow = 1;
3036 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
3038 r = amdgpu_modeset_create_props(adev);
3042 adev->ddev->mode_config.max_width = 16384;
3043 adev->ddev->mode_config.max_height = 16384;
3046 /* allocate crtcs */
3047 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3048 r = dce_v11_0_crtc_init(adev, i);
3053 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3054 amdgpu_print_display_setup(adev->ddev);
3059 r = dce_v11_0_afmt_init(adev);
3063 r = dce_v11_0_audio_init(adev);
3067 drm_kms_helper_poll_init(adev->ddev);
3069 adev->mode_info.mode_config_initialized = true;
3073 static int dce_v11_0_sw_fini(void *handle)
3075 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3077 kfree(adev->mode_info.bios_hardcoded_edid);
3079 drm_kms_helper_poll_fini(adev->ddev);
3081 dce_v11_0_audio_fini(adev);
3083 dce_v11_0_afmt_fini(adev);
3085 drm_mode_config_cleanup(adev->ddev);
3086 adev->mode_info.mode_config_initialized = false;
3091 static int dce_v11_0_hw_init(void *handle)
3094 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3096 dce_v11_0_init_golden_registers(adev);
3098 /* init dig PHYs, disp eng pll */
3099 amdgpu_atombios_crtc_powergate_init(adev);
3100 amdgpu_atombios_encoder_init_dig(adev);
3101 if ((adev->asic_type == CHIP_POLARIS10) ||
3102 (adev->asic_type == CHIP_POLARIS11) ||
3103 (adev->asic_type == CHIP_POLARIS12)) {
3104 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
3105 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
3106 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3107 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3109 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3112 /* initialize hpd */
3113 dce_v11_0_hpd_init(adev);
3115 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3116 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3119 dce_v11_0_pageflip_interrupt_init(adev);
3124 static int dce_v11_0_hw_fini(void *handle)
3127 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3129 dce_v11_0_hpd_fini(adev);
3131 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3132 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3135 dce_v11_0_pageflip_interrupt_fini(adev);
3140 static int dce_v11_0_suspend(void *handle)
3142 return dce_v11_0_hw_fini(handle);
3145 static int dce_v11_0_resume(void *handle)
3147 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3150 ret = dce_v11_0_hw_init(handle);
3152 /* turn on the BL */
3153 if (adev->mode_info.bl_encoder) {
3154 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3155 adev->mode_info.bl_encoder);
3156 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3163 static bool dce_v11_0_is_idle(void *handle)
3168 static int dce_v11_0_wait_for_idle(void *handle)
3173 static int dce_v11_0_soft_reset(void *handle)
3175 u32 srbm_soft_reset = 0, tmp;
3176 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3178 if (dce_v11_0_is_display_hung(adev))
3179 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3181 if (srbm_soft_reset) {
3182 tmp = RREG32(mmSRBM_SOFT_RESET);
3183 tmp |= srbm_soft_reset;
3184 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3185 WREG32(mmSRBM_SOFT_RESET, tmp);
3186 tmp = RREG32(mmSRBM_SOFT_RESET);
3190 tmp &= ~srbm_soft_reset;
3191 WREG32(mmSRBM_SOFT_RESET, tmp);
3192 tmp = RREG32(mmSRBM_SOFT_RESET);
3194 /* Wait a little for things to settle down */
3200 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3202 enum amdgpu_interrupt_state state)
3204 u32 lb_interrupt_mask;
3206 if (crtc >= adev->mode_info.num_crtc) {
3207 DRM_DEBUG("invalid crtc %d\n", crtc);
3212 case AMDGPU_IRQ_STATE_DISABLE:
3213 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3214 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3215 VBLANK_INTERRUPT_MASK, 0);
3216 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3218 case AMDGPU_IRQ_STATE_ENABLE:
3219 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3220 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3221 VBLANK_INTERRUPT_MASK, 1);
3222 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3229 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3231 enum amdgpu_interrupt_state state)
3233 u32 lb_interrupt_mask;
3235 if (crtc >= adev->mode_info.num_crtc) {
3236 DRM_DEBUG("invalid crtc %d\n", crtc);
3241 case AMDGPU_IRQ_STATE_DISABLE:
3242 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3243 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3244 VLINE_INTERRUPT_MASK, 0);
3245 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3247 case AMDGPU_IRQ_STATE_ENABLE:
3248 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3249 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3250 VLINE_INTERRUPT_MASK, 1);
3251 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3258 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3259 struct amdgpu_irq_src *source,
3261 enum amdgpu_interrupt_state state)
3265 if (hpd >= adev->mode_info.num_hpd) {
3266 DRM_DEBUG("invalid hdp %d\n", hpd);
3271 case AMDGPU_IRQ_STATE_DISABLE:
3272 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3273 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3274 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3276 case AMDGPU_IRQ_STATE_ENABLE:
3277 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3278 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3279 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3288 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3289 struct amdgpu_irq_src *source,
3291 enum amdgpu_interrupt_state state)
3294 case AMDGPU_CRTC_IRQ_VBLANK1:
3295 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3297 case AMDGPU_CRTC_IRQ_VBLANK2:
3298 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3300 case AMDGPU_CRTC_IRQ_VBLANK3:
3301 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3303 case AMDGPU_CRTC_IRQ_VBLANK4:
3304 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3306 case AMDGPU_CRTC_IRQ_VBLANK5:
3307 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3309 case AMDGPU_CRTC_IRQ_VBLANK6:
3310 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3312 case AMDGPU_CRTC_IRQ_VLINE1:
3313 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3315 case AMDGPU_CRTC_IRQ_VLINE2:
3316 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3318 case AMDGPU_CRTC_IRQ_VLINE3:
3319 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3321 case AMDGPU_CRTC_IRQ_VLINE4:
3322 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3324 case AMDGPU_CRTC_IRQ_VLINE5:
3325 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3327 case AMDGPU_CRTC_IRQ_VLINE6:
3328 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3336 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3337 struct amdgpu_irq_src *src,
3339 enum amdgpu_interrupt_state state)
3343 if (type >= adev->mode_info.num_crtc) {
3344 DRM_ERROR("invalid pageflip crtc %d\n", type);
3348 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3349 if (state == AMDGPU_IRQ_STATE_DISABLE)
3350 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3351 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3353 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3354 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3359 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3360 struct amdgpu_irq_src *source,
3361 struct amdgpu_iv_entry *entry)
3363 unsigned long flags;
3365 struct amdgpu_crtc *amdgpu_crtc;
3366 struct amdgpu_flip_work *works;
3368 crtc_id = (entry->src_id - 8) >> 1;
3369 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3371 if (crtc_id >= adev->mode_info.num_crtc) {
3372 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3376 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3377 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3378 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3379 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3381 /* IRQ could occur when in initial stage */
3382 if(amdgpu_crtc == NULL)
3385 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3386 works = amdgpu_crtc->pflip_works;
3387 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3388 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3389 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3390 amdgpu_crtc->pflip_status,
3391 AMDGPU_FLIP_SUBMITTED);
3392 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3396 /* page flip completed. clean up */
3397 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3398 amdgpu_crtc->pflip_works = NULL;
3400 /* wakeup usersapce */
3402 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3404 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3406 drm_crtc_vblank_put(&amdgpu_crtc->base);
3407 schedule_work(&works->unpin_work);
3412 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3417 if (hpd >= adev->mode_info.num_hpd) {
3418 DRM_DEBUG("invalid hdp %d\n", hpd);
3422 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3423 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3424 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3427 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3432 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3433 DRM_DEBUG("invalid crtc %d\n", crtc);
3437 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3438 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3439 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3442 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3447 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3448 DRM_DEBUG("invalid crtc %d\n", crtc);
3452 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3453 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3454 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3457 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3458 struct amdgpu_irq_src *source,
3459 struct amdgpu_iv_entry *entry)
3461 unsigned crtc = entry->src_id - 1;
3462 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3463 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3465 switch (entry->src_data) {
3466 case 0: /* vblank */
3467 if (disp_int & interrupt_status_offsets[crtc].vblank)
3468 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3470 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3472 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3473 drm_handle_vblank(adev->ddev, crtc);
3475 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3479 if (disp_int & interrupt_status_offsets[crtc].vline)
3480 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3482 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3484 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3488 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3495 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3496 struct amdgpu_irq_src *source,
3497 struct amdgpu_iv_entry *entry)
3499 uint32_t disp_int, mask;
3502 if (entry->src_data >= adev->mode_info.num_hpd) {
3503 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3507 hpd = entry->src_data;
3508 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3509 mask = interrupt_status_offsets[hpd].hpd;
3511 if (disp_int & mask) {
3512 dce_v11_0_hpd_int_ack(adev, hpd);
3513 schedule_work(&adev->hotplug_work);
3514 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3520 static int dce_v11_0_set_clockgating_state(void *handle,
3521 enum amd_clockgating_state state)
3526 static int dce_v11_0_set_powergating_state(void *handle,
3527 enum amd_powergating_state state)
3532 static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3533 .name = "dce_v11_0",
3534 .early_init = dce_v11_0_early_init,
3536 .sw_init = dce_v11_0_sw_init,
3537 .sw_fini = dce_v11_0_sw_fini,
3538 .hw_init = dce_v11_0_hw_init,
3539 .hw_fini = dce_v11_0_hw_fini,
3540 .suspend = dce_v11_0_suspend,
3541 .resume = dce_v11_0_resume,
3542 .is_idle = dce_v11_0_is_idle,
3543 .wait_for_idle = dce_v11_0_wait_for_idle,
3544 .soft_reset = dce_v11_0_soft_reset,
3545 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3546 .set_powergating_state = dce_v11_0_set_powergating_state,
3550 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3551 struct drm_display_mode *mode,
3552 struct drm_display_mode *adjusted_mode)
3554 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3556 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3558 /* need to call this here rather than in prepare() since we need some crtc info */
3559 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3561 /* set scaler clears this on some chips */
3562 dce_v11_0_set_interleave(encoder->crtc, mode);
3564 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3565 dce_v11_0_afmt_enable(encoder, true);
3566 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3570 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3572 struct amdgpu_device *adev = encoder->dev->dev_private;
3573 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3574 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3576 if ((amdgpu_encoder->active_device &
3577 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3578 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3579 ENCODER_OBJECT_ID_NONE)) {
3580 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3582 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3583 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3584 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3588 amdgpu_atombios_scratch_regs_lock(adev, true);
3591 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3593 /* select the clock/data port if it uses a router */
3594 if (amdgpu_connector->router.cd_valid)
3595 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3597 /* turn eDP panel on for mode set */
3598 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3599 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3600 ATOM_TRANSMITTER_ACTION_POWER_ON);
3603 /* this is needed for the pll/ss setup to work correctly in some cases */
3604 amdgpu_atombios_encoder_set_crtc_source(encoder);
3605 /* set up the FMT blocks */
3606 dce_v11_0_program_fmt(encoder);
3609 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3611 struct drm_device *dev = encoder->dev;
3612 struct amdgpu_device *adev = dev->dev_private;
3614 /* need to call this here as we need the crtc set up */
3615 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3616 amdgpu_atombios_scratch_regs_lock(adev, false);
3619 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3621 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3622 struct amdgpu_encoder_atom_dig *dig;
3624 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3626 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3627 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3628 dce_v11_0_afmt_enable(encoder, false);
3629 dig = amdgpu_encoder->enc_priv;
3630 dig->dig_encoder = -1;
3632 amdgpu_encoder->active_device = 0;
3635 /* these are handled by the primary encoders */
3636 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3641 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3647 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3648 struct drm_display_mode *mode,
3649 struct drm_display_mode *adjusted_mode)
3654 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3660 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3665 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3666 .dpms = dce_v11_0_ext_dpms,
3667 .prepare = dce_v11_0_ext_prepare,
3668 .mode_set = dce_v11_0_ext_mode_set,
3669 .commit = dce_v11_0_ext_commit,
3670 .disable = dce_v11_0_ext_disable,
3671 /* no detect for TMDS/LVDS yet */
3674 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3675 .dpms = amdgpu_atombios_encoder_dpms,
3676 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3677 .prepare = dce_v11_0_encoder_prepare,
3678 .mode_set = dce_v11_0_encoder_mode_set,
3679 .commit = dce_v11_0_encoder_commit,
3680 .disable = dce_v11_0_encoder_disable,
3681 .detect = amdgpu_atombios_encoder_dig_detect,
3684 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3685 .dpms = amdgpu_atombios_encoder_dpms,
3686 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3687 .prepare = dce_v11_0_encoder_prepare,
3688 .mode_set = dce_v11_0_encoder_mode_set,
3689 .commit = dce_v11_0_encoder_commit,
3690 .detect = amdgpu_atombios_encoder_dac_detect,
3693 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3695 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3696 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3697 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3698 kfree(amdgpu_encoder->enc_priv);
3699 drm_encoder_cleanup(encoder);
3700 kfree(amdgpu_encoder);
3703 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3704 .destroy = dce_v11_0_encoder_destroy,
3707 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3708 uint32_t encoder_enum,
3709 uint32_t supported_device,
3712 struct drm_device *dev = adev->ddev;
3713 struct drm_encoder *encoder;
3714 struct amdgpu_encoder *amdgpu_encoder;
3716 /* see if we already added it */
3717 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3718 amdgpu_encoder = to_amdgpu_encoder(encoder);
3719 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3720 amdgpu_encoder->devices |= supported_device;
3727 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3728 if (!amdgpu_encoder)
3731 encoder = &amdgpu_encoder->base;
3732 switch (adev->mode_info.num_crtc) {
3734 encoder->possible_crtcs = 0x1;
3738 encoder->possible_crtcs = 0x3;
3741 encoder->possible_crtcs = 0x7;
3744 encoder->possible_crtcs = 0xf;
3747 encoder->possible_crtcs = 0x1f;
3750 encoder->possible_crtcs = 0x3f;
3754 amdgpu_encoder->enc_priv = NULL;
3756 amdgpu_encoder->encoder_enum = encoder_enum;
3757 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3758 amdgpu_encoder->devices = supported_device;
3759 amdgpu_encoder->rmx_type = RMX_OFF;
3760 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3761 amdgpu_encoder->is_ext_encoder = false;
3762 amdgpu_encoder->caps = caps;
3764 switch (amdgpu_encoder->encoder_id) {
3765 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3766 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3767 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3768 DRM_MODE_ENCODER_DAC, NULL);
3769 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3771 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3772 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3773 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3774 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3775 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3776 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3777 amdgpu_encoder->rmx_type = RMX_FULL;
3778 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3779 DRM_MODE_ENCODER_LVDS, NULL);
3780 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3781 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3782 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3783 DRM_MODE_ENCODER_DAC, NULL);
3784 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3786 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3787 DRM_MODE_ENCODER_TMDS, NULL);
3788 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3790 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3792 case ENCODER_OBJECT_ID_SI170B:
3793 case ENCODER_OBJECT_ID_CH7303:
3794 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3795 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3796 case ENCODER_OBJECT_ID_TITFP513:
3797 case ENCODER_OBJECT_ID_VT1623:
3798 case ENCODER_OBJECT_ID_HDMI_SI1930:
3799 case ENCODER_OBJECT_ID_TRAVIS:
3800 case ENCODER_OBJECT_ID_NUTMEG:
3801 /* these are handled by the primary encoders */
3802 amdgpu_encoder->is_ext_encoder = true;
3803 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3804 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3805 DRM_MODE_ENCODER_LVDS, NULL);
3806 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3807 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3808 DRM_MODE_ENCODER_DAC, NULL);
3810 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3811 DRM_MODE_ENCODER_TMDS, NULL);
3812 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3817 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3818 .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3819 .bandwidth_update = &dce_v11_0_bandwidth_update,
3820 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3821 .vblank_wait = &dce_v11_0_vblank_wait,
3822 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3823 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3824 .hpd_sense = &dce_v11_0_hpd_sense,
3825 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3826 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3827 .page_flip = &dce_v11_0_page_flip,
3828 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3829 .add_encoder = &dce_v11_0_encoder_add,
3830 .add_connector = &amdgpu_connector_add,
3831 .stop_mc_access = &dce_v11_0_stop_mc_access,
3832 .resume_mc_access = &dce_v11_0_resume_mc_access,
3835 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3837 if (adev->mode_info.funcs == NULL)
3838 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3841 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3842 .set = dce_v11_0_set_crtc_irq_state,
3843 .process = dce_v11_0_crtc_irq,
3846 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3847 .set = dce_v11_0_set_pageflip_irq_state,
3848 .process = dce_v11_0_pageflip_irq,
3851 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3852 .set = dce_v11_0_set_hpd_irq_state,
3853 .process = dce_v11_0_hpd_irq,
3856 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3858 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3859 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3861 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3862 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3864 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3865 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3868 const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3870 .type = AMD_IP_BLOCK_TYPE_DCE,
3874 .funcs = &dce_v11_0_ip_funcs,
3877 const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3879 .type = AMD_IP_BLOCK_TYPE_DCE,
3883 .funcs = &dce_v11_0_ip_funcs,