drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "vid.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34
  35 #include "dce/dce_11_0_d.h"
  36 #include "dce/dce_11_0_sh_mask.h"
  37 #include "dce/dce_11_0_enum.h"
  38 #include "oss/oss_3_0_d.h"
  39 #include "oss/oss_3_0_sh_mask.h"
  40 #include "gmc/gmc_8_1_d.h"
  41 #include "gmc/gmc_8_1_sh_mask.h"
  42
  43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
  44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
  45
  46 static const u32 crtc_offsets[] =
  47 {
  48         CRTC0_REGISTER_OFFSET,
  49         CRTC1_REGISTER_OFFSET,
  50         CRTC2_REGISTER_OFFSET,
  51         CRTC3_REGISTER_OFFSET,
  52         CRTC4_REGISTER_OFFSET,
  53         CRTC5_REGISTER_OFFSET,
  54         CRTC6_REGISTER_OFFSET
  55 };
  56
  57 static const u32 hpd_offsets[] =
  58 {
  59         HPD0_REGISTER_OFFSET,
  60         HPD1_REGISTER_OFFSET,
  61         HPD2_REGISTER_OFFSET,
  62         HPD3_REGISTER_OFFSET,
  63         HPD4_REGISTER_OFFSET,
  64         HPD5_REGISTER_OFFSET
  65 };
  66
  67 static const uint32_t dig_offsets[] = {
  68         DIG0_REGISTER_OFFSET,
  69         DIG1_REGISTER_OFFSET,
  70         DIG2_REGISTER_OFFSET,
  71         DIG3_REGISTER_OFFSET,
  72         DIG4_REGISTER_OFFSET,
  73         DIG5_REGISTER_OFFSET,
  74         DIG6_REGISTER_OFFSET,
  75         DIG7_REGISTER_OFFSET,
  76         DIG8_REGISTER_OFFSET
  77 };
  78
  79 static const struct {
  80         uint32_t        reg;
  81         uint32_t        vblank;
  82         uint32_t        vline;
  83         uint32_t        hpd;
  84
  85 } interrupt_status_offsets[] = { {
  86         .reg = mmDISP_INTERRUPT_STATUS,
  87         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  88         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  89         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  90 }, {
  91         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  92         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  93         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  94         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  95 }, {
  96         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  97         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  98         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  99         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 100 }, {
 101         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 102         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 103         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 104         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 105 }, {
 106         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 107         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 108         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 109         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 110 }, {
 111         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 112         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 113         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 114         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 115 } };
 116
 117 static const u32 cz_golden_settings_a11[] =
 118 {
 119         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 120         mmFBC_MISC, 0x1f311fff, 0x14300000,
 121 };
 122
 123 static const u32 cz_mgcg_cgcg_init[] =
 124 {
 125         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 126         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 127 };
 128
 129 static const u32 stoney_golden_settings_a11[] =
 130 {
 131         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 132         mmFBC_MISC, 0x1f311fff, 0x14302000,
 133 };
 134
 135
 136 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
 137 {
 138         switch (adev->asic_type) {
 139         case CHIP_CARRIZO:
 140                 amdgpu_program_register_sequence(adev,
 141                                                  cz_mgcg_cgcg_init,
 142                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 143                 amdgpu_program_register_sequence(adev,
 144                                                  cz_golden_settings_a11,
 145                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 146                 break;
 147         case CHIP_STONEY:
 148                 amdgpu_program_register_sequence(adev,
 149                                                  stoney_golden_settings_a11,
 150                                                  (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
 151                 break;
 152         default:
 153                 break;
 154         }
 155 }
 156
 157 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
 158                                      u32 block_offset, u32 reg)
 159 {
 160         unsigned long flags;
 161         u32 r;
 162
 163         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 164         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 165         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 166         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 167
 168         return r;
 169 }
 170
 171 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
 172                                       u32 block_offset, u32 reg, u32 v)
 173 {
 174         unsigned long flags;
 175
 176         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 177         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 178         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 179         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 180 }
 181
 182 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 183 {
 184         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 185                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 186                 return true;
 187         else
 188                 return false;
 189 }
 190
 191 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 192 {
 193         u32 pos1, pos2;
 194
 195         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 196         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 197
 198         if (pos1 != pos2)
 199                 return true;
 200         else
 201                 return false;
 202 }
 203
 204 /**
 205  * dce_v11_0_vblank_wait - vblank wait asic callback.
 206  *
 207  * @adev: amdgpu_device pointer
 208  * @crtc: crtc to wait for vblank on
 209  *
 210  * Wait for vblank on the requested crtc (evergreen+).
 211  */
 212 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 213 {
 214         unsigned i = 0;
 215
 216         if (crtc >= adev->mode_info.num_crtc)
 217                 return;
 218
 219         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 220                 return;
 221
 222         /* depending on when we hit vblank, we may be close to active; if so,
 223          * wait for another frame.
 224          */
 225         while (dce_v11_0_is_in_vblank(adev, crtc)) {
 226                 if (i++ % 100 == 0) {
 227                         if (!dce_v11_0_is_counter_moving(adev, crtc))
 228                                 break;
 229                 }
 230         }
 231
 232         while (!dce_v11_0_is_in_vblank(adev, crtc)) {
 233                 if (i++ % 100 == 0) {
 234                         if (!dce_v11_0_is_counter_moving(adev, crtc))
 235                                 break;
 236                 }
 237         }
 238 }
 239
 240 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 241 {
 242         if (crtc >= adev->mode_info.num_crtc)
 243                 return 0;
 244         else
 245                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 246 }
 247
 248 /**
 249  * dce_v11_0_page_flip - pageflip callback.
 250  *
 251  * @adev: amdgpu_device pointer
 252  * @crtc_id: crtc to cleanup pageflip on
 253  * @crtc_base: new address of the crtc (GPU MC address)
 254  *
 255  * Does the actual pageflip (evergreen+).
 256  * During vblank we take the crtc lock and wait for the update_pending
 257  * bit to go high, when it does, we release the lock, and allow the
 258  * double buffered update to take place.
 259  * Returns the current update pending status.
 260  */
 261 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
 262                               int crtc_id, u64 crtc_base)
 263 {
 264         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 265         u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset);
 266         int i;
 267
 268         /* Lock the graphics update lock */
 269         tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
 270         WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
 271
 272         /* update the scanout addresses */
 273         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 274                upper_32_bits(crtc_base));
 275         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 276                lower_32_bits(crtc_base));
 277
 278         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 279                upper_32_bits(crtc_base));
 280         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 281                lower_32_bits(crtc_base));
 282
 283         /* Wait for update_pending to go high. */
 284         for (i = 0; i < adev->usec_timeout; i++) {
 285                 if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) &
 286                                 GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK)
 287                         break;
 288                 udelay(1);
 289         }
 290         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 291
 292         /* Unlock the lock, so double-buffering can take place inside vblank */
 293         tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
 294         WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
 295 }
 296
 297 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 298                                         u32 *vbl, u32 *position)
 299 {
 300         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 301                 return -EINVAL;
 302
 303         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 304         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 305
 306         return 0;
 307 }
 308
 309 /**
 310  * dce_v11_0_hpd_sense - hpd sense callback.
 311  *
 312  * @adev: amdgpu_device pointer
 313  * @hpd: hpd (hotplug detect) pin
 314  *
 315  * Checks if a digital monitor is connected (evergreen+).
 316  * Returns true if connected, false if not connected.
 317  */
 318 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
 319                                enum amdgpu_hpd_id hpd)
 320 {
 321         int idx;
 322         bool connected = false;
 323
 324         switch (hpd) {
 325         case AMDGPU_HPD_1:
 326                 idx = 0;
 327                 break;
 328         case AMDGPU_HPD_2:
 329                 idx = 1;
 330                 break;
 331         case AMDGPU_HPD_3:
 332                 idx = 2;
 333                 break;
 334         case AMDGPU_HPD_4:
 335                 idx = 3;
 336                 break;
 337         case AMDGPU_HPD_5:
 338                 idx = 4;
 339                 break;
 340         case AMDGPU_HPD_6:
 341                 idx = 5;
 342                 break;
 343         default:
 344                 return connected;
 345         }
 346
 347         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
 348             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 349                 connected = true;
 350
 351         return connected;
 352 }
 353
 354 /**
 355  * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
 356  *
 357  * @adev: amdgpu_device pointer
 358  * @hpd: hpd (hotplug detect) pin
 359  *
 360  * Set the polarity of the hpd pin (evergreen+).
 361  */
 362 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
 363                                       enum amdgpu_hpd_id hpd)
 364 {
 365         u32 tmp;
 366         bool connected = dce_v11_0_hpd_sense(adev, hpd);
 367         int idx;
 368
 369         switch (hpd) {
 370         case AMDGPU_HPD_1:
 371                 idx = 0;
 372                 break;
 373         case AMDGPU_HPD_2:
 374                 idx = 1;
 375                 break;
 376         case AMDGPU_HPD_3:
 377                 idx = 2;
 378                 break;
 379         case AMDGPU_HPD_4:
 380                 idx = 3;
 381                 break;
 382         case AMDGPU_HPD_5:
 383                 idx = 4;
 384                 break;
 385         case AMDGPU_HPD_6:
 386                 idx = 5;
 387                 break;
 388         default:
 389                 return;
 390         }
 391
 392         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
 393         if (connected)
 394                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 395         else
 396                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 397         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
 398 }
 399
 400 /**
 401  * dce_v11_0_hpd_init - hpd setup callback.
 402  *
 403  * @adev: amdgpu_device pointer
 404  *
 405  * Setup the hpd pins used by the card (evergreen+).
 406  * Enable the pin, set the polarity, and enable the hpd interrupts.
 407  */
 408 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
 409 {
 410         struct drm_device *dev = adev->ddev;
 411         struct drm_connector *connector;
 412         u32 tmp;
 413         int idx;
 414
 415         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 416                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 417
 418                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 419                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 420                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 421                          * aux dp channel on imac and help (but not completely fix)
 422                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 423                          * also avoid interrupt storms during dpms.
 424                          */
 425                         continue;
 426                 }
 427
 428                 switch (amdgpu_connector->hpd.hpd) {
 429                 case AMDGPU_HPD_1:
 430                         idx = 0;
 431                         break;
 432                 case AMDGPU_HPD_2:
 433                         idx = 1;
 434                         break;
 435                 case AMDGPU_HPD_3:
 436                         idx = 2;
 437                         break;
 438                 case AMDGPU_HPD_4:
 439                         idx = 3;
 440                         break;
 441                 case AMDGPU_HPD_5:
 442                         idx = 4;
 443                         break;
 444                 case AMDGPU_HPD_6:
 445                         idx = 5;
 446                         break;
 447                 default:
 448                         continue;
 449                 }
 450
 451                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 452                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 453                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 454
 455                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
 456                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 457                                     DC_HPD_CONNECT_INT_DELAY,
 458                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 459                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 460                                     DC_HPD_DISCONNECT_INT_DELAY,
 461                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 462                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
 463
 464                 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 465                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 466         }
 467 }
 468
 469 /**
 470  * dce_v11_0_hpd_fini - hpd tear down callback.
 471  *
 472  * @adev: amdgpu_device pointer
 473  *
 474  * Tear down the hpd pins used by the card (evergreen+).
 475  * Disable the hpd interrupts.
 476  */
 477 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
 478 {
 479         struct drm_device *dev = adev->ddev;
 480         struct drm_connector *connector;
 481         u32 tmp;
 482         int idx;
 483
 484         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 485                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 486
 487                 switch (amdgpu_connector->hpd.hpd) {
 488                 case AMDGPU_HPD_1:
 489                         idx = 0;
 490                         break;
 491                 case AMDGPU_HPD_2:
 492                         idx = 1;
 493                         break;
 494                 case AMDGPU_HPD_3:
 495                         idx = 2;
 496                         break;
 497                 case AMDGPU_HPD_4:
 498                         idx = 3;
 499                         break;
 500                 case AMDGPU_HPD_5:
 501                         idx = 4;
 502                         break;
 503                 case AMDGPU_HPD_6:
 504                         idx = 5;
 505                         break;
 506                 default:
 507                         continue;
 508                 }
 509
 510                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 511                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 512                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 513
 514                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 515         }
 516 }
 517
 518 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 519 {
 520         return mmDC_GPIO_HPD_A;
 521 }
 522
 523 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
 524 {
 525         u32 crtc_hung = 0;
 526         u32 crtc_status[6];
 527         u32 i, j, tmp;
 528
 529         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 530                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 531                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 532                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 533                         crtc_hung |= (1 << i);
 534                 }
 535         }
 536
 537         for (j = 0; j < 10; j++) {
 538                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 539                         if (crtc_hung & (1 << i)) {
 540                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 541                                 if (tmp != crtc_status[i])
 542                                         crtc_hung &= ~(1 << i);
 543                         }
 544                 }
 545                 if (crtc_hung == 0)
 546                         return false;
 547                 udelay(100);
 548         }
 549
 550         return true;
 551 }
 552
 553 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
 554                                      struct amdgpu_mode_mc_save *save)
 555 {
 556         u32 crtc_enabled, tmp;
 557         int i;
 558
 559         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 560         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 561
 562         /* disable VGA render */
 563         tmp = RREG32(mmVGA_RENDER_CONTROL);
 564         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 565         WREG32(mmVGA_RENDER_CONTROL, tmp);
 566
 567         /* blank the display controllers */
 568         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 569                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 570                                              CRTC_CONTROL, CRTC_MASTER_EN);
 571                 if (crtc_enabled) {
 572 #if 0
 573                         u32 frame_count;
 574                         int j;
 575
 576                         save->crtc_enabled[i] = true;
 577                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 578                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
 579                                 amdgpu_display_vblank_wait(adev, i);
 580                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 581                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
 582                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 583                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 584                         }
 585                         /* wait for the next frame */
 586                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 587                         for (j = 0; j < adev->usec_timeout; j++) {
 588                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 589                                         break;
 590                                 udelay(1);
 591                         }
 592                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 593                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
 594                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
 595                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 596                         }
 597                         tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
 598                         if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
 599                                 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
 600                                 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 601                         }
 602 #else
 603                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 604                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 605                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 606                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 607                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 608                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 609                         save->crtc_enabled[i] = false;
 610                         /* ***** */
 611 #endif
 612                 } else {
 613                         save->crtc_enabled[i] = false;
 614                 }
 615         }
 616 }
 617
 618 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
 619                                        struct amdgpu_mode_mc_save *save)
 620 {
 621         u32 tmp, frame_count;
 622         int i, j;
 623
 624         /* update crtc base addresses */
 625         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 626                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 627                        upper_32_bits(adev->mc.vram_start));
 628                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 629                        upper_32_bits(adev->mc.vram_start));
 630                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 631                        (u32)adev->mc.vram_start);
 632                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 633                        (u32)adev->mc.vram_start);
 634
 635                 if (save->crtc_enabled[i]) {
 636                         tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]);
 637                         if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
 638                                 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
 639                                 WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
 640                         }
 641                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 642                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
 643                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
 644                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 645                         }
 646                         tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
 647                         if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
 648                                 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
 649                                 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 650                         }
 651                         for (j = 0; j < adev->usec_timeout; j++) {
 652                                 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 653                                 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
 654                                         break;
 655                                 udelay(1);
 656                         }
 657                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 658                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
 659                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 660                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 661                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 662                         /* wait for the next frame */
 663                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 664                         for (j = 0; j < adev->usec_timeout; j++) {
 665                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 666                                         break;
 667                                 udelay(1);
 668                         }
 669                 }
 670         }
 671
 672         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 673         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
 674
 675         /* Unlock vga access */
 676         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 677         mdelay(1);
 678         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 679 }
 680
 681 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
 682                                            bool render)
 683 {
 684         u32 tmp;
 685
 686         /* Lockout access through VGA aperture*/
 687         tmp = RREG32(mmVGA_HDP_CONTROL);
 688         if (render)
 689                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 690         else
 691                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 692         WREG32(mmVGA_HDP_CONTROL, tmp);
 693
 694         /* disable VGA render */
 695         tmp = RREG32(mmVGA_RENDER_CONTROL);
 696         if (render)
 697                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 698         else
 699                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 700         WREG32(mmVGA_RENDER_CONTROL, tmp);
 701 }
 702
 703 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
 704 {
 705         struct drm_device *dev = encoder->dev;
 706         struct amdgpu_device *adev = dev->dev_private;
 707         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 708         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 709         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 710         int bpc = 0;
 711         u32 tmp = 0;
 712         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 713
 714         if (connector) {
 715                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 716                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 717                 dither = amdgpu_connector->dither;
 718         }
 719
 720         /* LVDS/eDP FMT is set up by atom */
 721         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 722                 return;
 723
 724         /* not needed for analog */
 725         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 726             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 727                 return;
 728
 729         if (bpc == 0)
 730                 return;
 731
 732         switch (bpc) {
 733         case 6:
 734                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 735                         /* XXX sort out optimal dither settings */
 736                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 737                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 738                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 739                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 740                 } else {
 741                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 742                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 743                 }
 744                 break;
 745         case 8:
 746                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 747                         /* XXX sort out optimal dither settings */
 748                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 749                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 750                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 751                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 752                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 753                 } else {
 754                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 755                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 756                 }
 757                 break;
 758         case 10:
 759                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 760                         /* XXX sort out optimal dither settings */
 761                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 762                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 763                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 764                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 765                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 766                 } else {
 767                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 768                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 769                 }
 770                 break;
 771         default:
 772                 /* not needed */
 773                 break;
 774         }
 775
 776         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 777 }
 778
 779
 780 /* display watermark setup */
 781 /**
 782  * dce_v11_0_line_buffer_adjust - Set up the line buffer
 783  *
 784  * @adev: amdgpu_device pointer
 785  * @amdgpu_crtc: the selected display controller
 786  * @mode: the current display mode on the selected display
 787  * controller
 788  *
 789  * Setup up the line buffer allocation for
 790  * the selected display controller (CIK).
 791  * Returns the line buffer size in pixels.
 792  */
 793 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
 794                                        struct amdgpu_crtc *amdgpu_crtc,
 795                                        struct drm_display_mode *mode)
 796 {
 797         u32 tmp, buffer_alloc, i, mem_cfg;
 798         u32 pipe_offset = amdgpu_crtc->crtc_id;
 799         /*
 800          * Line Buffer Setup
 801          * There are 6 line buffers, one for each display controllers.
 802          * There are 3 partitions per LB. Select the number of partitions
 803          * to enable based on the display width.  For display widths larger
 804          * than 4096, you need use to use 2 display controllers and combine
 805          * them using the stereo blender.
 806          */
 807         if (amdgpu_crtc->base.enabled && mode) {
 808                 if (mode->crtc_hdisplay < 1920) {
 809                         mem_cfg = 1;
 810                         buffer_alloc = 2;
 811                 } else if (mode->crtc_hdisplay < 2560) {
 812                         mem_cfg = 2;
 813                         buffer_alloc = 2;
 814                 } else if (mode->crtc_hdisplay < 4096) {
 815                         mem_cfg = 0;
 816                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 817                 } else {
 818                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 819                         mem_cfg = 0;
 820                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 821                 }
 822         } else {
 823                 mem_cfg = 1;
 824                 buffer_alloc = 0;
 825         }
 826
 827         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 828         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 829         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 830
 831         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 832         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 833         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 834
 835         for (i = 0; i < adev->usec_timeout; i++) {
 836                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 837                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 838                         break;
 839                 udelay(1);
 840         }
 841
 842         if (amdgpu_crtc->base.enabled && mode) {
 843                 switch (mem_cfg) {
 844                 case 0:
 845                 default:
 846                         return 4096 * 2;
 847                 case 1:
 848                         return 1920 * 2;
 849                 case 2:
 850                         return 2560 * 2;
 851                 }
 852         }
 853
 854         /* controller not enabled, so no lb used */
 855         return 0;
 856 }
 857
 858 /**
 859  * cik_get_number_of_dram_channels - get the number of dram channels
 860  *
 861  * @adev: amdgpu_device pointer
 862  *
 863  * Look up the number of video ram channels (CIK).
 864  * Used for display watermark bandwidth calculations
 865  * Returns the number of dram channels
 866  */
 867 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 868 {
 869         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 870
 871         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 872         case 0:
 873         default:
 874                 return 1;
 875         case 1:
 876                 return 2;
 877         case 2:
 878                 return 4;
 879         case 3:
 880                 return 8;
 881         case 4:
 882                 return 3;
 883         case 5:
 884                 return 6;
 885         case 6:
 886                 return 10;
 887         case 7:
 888                 return 12;
 889         case 8:
 890                 return 16;
 891         }
 892 }
 893
 894 struct dce10_wm_params {
 895         u32 dram_channels; /* number of dram channels */
 896         u32 yclk;          /* bandwidth per dram data pin in kHz */
 897         u32 sclk;          /* engine clock in kHz */
 898         u32 disp_clk;      /* display clock in kHz */
 899         u32 src_width;     /* viewport width */
 900         u32 active_time;   /* active display time in ns */
 901         u32 blank_time;    /* blank time in ns */
 902         bool interlaced;    /* mode is interlaced */
 903         fixed20_12 vsc;    /* vertical scale ratio */
 904         u32 num_heads;     /* number of active crtcs */
 905         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 906         u32 lb_size;       /* line buffer allocated to pipe */
 907         u32 vtaps;         /* vertical scaler taps */
 908 };
 909
 910 /**
 911  * dce_v11_0_dram_bandwidth - get the dram bandwidth
 912  *
 913  * @wm: watermark calculation data
 914  *
 915  * Calculate the raw dram bandwidth (CIK).
 916  * Used for display watermark bandwidth calculations
 917  * Returns the dram bandwidth in MBytes/s
 918  */
 919 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
 920 {
 921         /* Calculate raw DRAM Bandwidth */
 922         fixed20_12 dram_efficiency; /* 0.7 */
 923         fixed20_12 yclk, dram_channels, bandwidth;
 924         fixed20_12 a;
 925
 926         a.full = dfixed_const(1000);
 927         yclk.full = dfixed_const(wm->yclk);
 928         yclk.full = dfixed_div(yclk, a);
 929         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 930         a.full = dfixed_const(10);
 931         dram_efficiency.full = dfixed_const(7);
 932         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 933         bandwidth.full = dfixed_mul(dram_channels, yclk);
 934         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 935
 936         return dfixed_trunc(bandwidth);
 937 }
 938
 939 /**
 940  * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
 941  *
 942  * @wm: watermark calculation data
 943  *
 944  * Calculate the dram bandwidth used for display (CIK).
 945  * Used for display watermark bandwidth calculations
 946  * Returns the dram bandwidth for display in MBytes/s
 947  */
 948 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 949 {
 950         /* Calculate DRAM Bandwidth and the part allocated to display. */
 951         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 952         fixed20_12 yclk, dram_channels, bandwidth;
 953         fixed20_12 a;
 954
 955         a.full = dfixed_const(1000);
 956         yclk.full = dfixed_const(wm->yclk);
 957         yclk.full = dfixed_div(yclk, a);
 958         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 959         a.full = dfixed_const(10);
 960         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 961         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 962         bandwidth.full = dfixed_mul(dram_channels, yclk);
 963         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 964
 965         return dfixed_trunc(bandwidth);
 966 }
 967
 968 /**
 969  * dce_v11_0_data_return_bandwidth - get the data return bandwidth
 970  *
 971  * @wm: watermark calculation data
 972  *
 973  * Calculate the data return bandwidth used for display (CIK).
 974  * Used for display watermark bandwidth calculations
 975  * Returns the data return bandwidth in MBytes/s
 976  */
 977 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
 978 {
 979         /* Calculate the display Data return Bandwidth */
 980         fixed20_12 return_efficiency; /* 0.8 */
 981         fixed20_12 sclk, bandwidth;
 982         fixed20_12 a;
 983
 984         a.full = dfixed_const(1000);
 985         sclk.full = dfixed_const(wm->sclk);
 986         sclk.full = dfixed_div(sclk, a);
 987         a.full = dfixed_const(10);
 988         return_efficiency.full = dfixed_const(8);
 989         return_efficiency.full = dfixed_div(return_efficiency, a);
 990         a.full = dfixed_const(32);
 991         bandwidth.full = dfixed_mul(a, sclk);
 992         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 993
 994         return dfixed_trunc(bandwidth);
 995 }
 996
 997 /**
 998  * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
 999  *
1000  * @wm: watermark calculation data
1001  *
1002  * Calculate the dmif bandwidth used for display (CIK).
1003  * Used for display watermark bandwidth calculations
1004  * Returns the dmif bandwidth in MBytes/s
1005  */
1006 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
1007 {
1008         /* Calculate the DMIF Request Bandwidth */
1009         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1010         fixed20_12 disp_clk, bandwidth;
1011         fixed20_12 a, b;
1012
1013         a.full = dfixed_const(1000);
1014         disp_clk.full = dfixed_const(wm->disp_clk);
1015         disp_clk.full = dfixed_div(disp_clk, a);
1016         a.full = dfixed_const(32);
1017         b.full = dfixed_mul(a, disp_clk);
1018
1019         a.full = dfixed_const(10);
1020         disp_clk_request_efficiency.full = dfixed_const(8);
1021         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1022
1023         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1024
1025         return dfixed_trunc(bandwidth);
1026 }
1027
1028 /**
1029  * dce_v11_0_available_bandwidth - get the min available bandwidth
1030  *
1031  * @wm: watermark calculation data
1032  *
1033  * Calculate the min available bandwidth used for display (CIK).
1034  * Used for display watermark bandwidth calculations
1035  * Returns the min available bandwidth in MBytes/s
1036  */
1037 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
1038 {
1039         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1040         u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
1041         u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
1042         u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
1043
1044         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1045 }
1046
1047 /**
1048  * dce_v11_0_average_bandwidth - get the average available bandwidth
1049  *
1050  * @wm: watermark calculation data
1051  *
1052  * Calculate the average available bandwidth used for display (CIK).
1053  * Used for display watermark bandwidth calculations
1054  * Returns the average available bandwidth in MBytes/s
1055  */
1056 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
1057 {
1058         /* Calculate the display mode Average Bandwidth
1059          * DisplayMode should contain the source and destination dimensions,
1060          * timing, etc.
1061          */
1062         fixed20_12 bpp;
1063         fixed20_12 line_time;
1064         fixed20_12 src_width;
1065         fixed20_12 bandwidth;
1066         fixed20_12 a;
1067
1068         a.full = dfixed_const(1000);
1069         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1070         line_time.full = dfixed_div(line_time, a);
1071         bpp.full = dfixed_const(wm->bytes_per_pixel);
1072         src_width.full = dfixed_const(wm->src_width);
1073         bandwidth.full = dfixed_mul(src_width, bpp);
1074         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1075         bandwidth.full = dfixed_div(bandwidth, line_time);
1076
1077         return dfixed_trunc(bandwidth);
1078 }
1079
1080 /**
1081  * dce_v11_0_latency_watermark - get the latency watermark
1082  *
1083  * @wm: watermark calculation data
1084  *
1085  * Calculate the latency watermark (CIK).
1086  * Used for display watermark bandwidth calculations
1087  * Returns the latency watermark in ns
1088  */
1089 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1090 {
1091         /* First calculate the latency in ns */
1092         u32 mc_latency = 2000; /* 2000 ns. */
1093         u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1094         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1095         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1096         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1097         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1098                 (wm->num_heads * cursor_line_pair_return_time);
1099         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1100         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1101         u32 tmp, dmif_size = 12288;
1102         fixed20_12 a, b, c;
1103
1104         if (wm->num_heads == 0)
1105                 return 0;
1106
1107         a.full = dfixed_const(2);
1108         b.full = dfixed_const(1);
1109         if ((wm->vsc.full > a.full) ||
1110             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1111             (wm->vtaps >= 5) ||
1112             ((wm->vsc.full >= a.full) && wm->interlaced))
1113                 max_src_lines_per_dst_line = 4;
1114         else
1115                 max_src_lines_per_dst_line = 2;
1116
1117         a.full = dfixed_const(available_bandwidth);
1118         b.full = dfixed_const(wm->num_heads);
1119         a.full = dfixed_div(a, b);
1120
1121         b.full = dfixed_const(mc_latency + 512);
1122         c.full = dfixed_const(wm->disp_clk);
1123         b.full = dfixed_div(b, c);
1124
1125         c.full = dfixed_const(dmif_size);
1126         b.full = dfixed_div(c, b);
1127
1128         tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1129
1130         b.full = dfixed_const(1000);
1131         c.full = dfixed_const(wm->disp_clk);
1132         b.full = dfixed_div(c, b);
1133         c.full = dfixed_const(wm->bytes_per_pixel);
1134         b.full = dfixed_mul(b, c);
1135
1136         lb_fill_bw = min(tmp, dfixed_trunc(b));
1137
1138         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1139         b.full = dfixed_const(1000);
1140         c.full = dfixed_const(lb_fill_bw);
1141         b.full = dfixed_div(c, b);
1142         a.full = dfixed_div(a, b);
1143         line_fill_time = dfixed_trunc(a);
1144
1145         if (line_fill_time < wm->active_time)
1146                 return latency;
1147         else
1148                 return latency + (line_fill_time - wm->active_time);
1149
1150 }
1151
1152 /**
1153  * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1154  * average and available dram bandwidth
1155  *
1156  * @wm: watermark calculation data
1157  *
1158  * Check if the display average bandwidth fits in the display
1159  * dram bandwidth (CIK).
1160  * Used for display watermark bandwidth calculations
1161  * Returns true if the display fits, false if not.
1162  */
1163 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1164 {
1165         if (dce_v11_0_average_bandwidth(wm) <=
1166             (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1167                 return true;
1168         else
1169                 return false;
1170 }
1171
1172 /**
1173  * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1174  * average and available bandwidth
1175  *
1176  * @wm: watermark calculation data
1177  *
1178  * Check if the display average bandwidth fits in the display
1179  * available bandwidth (CIK).
1180  * Used for display watermark bandwidth calculations
1181  * Returns true if the display fits, false if not.
1182  */
1183 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1184 {
1185         if (dce_v11_0_average_bandwidth(wm) <=
1186             (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1187                 return true;
1188         else
1189                 return false;
1190 }
1191
1192 /**
1193  * dce_v11_0_check_latency_hiding - check latency hiding
1194  *
1195  * @wm: watermark calculation data
1196  *
1197  * Check latency hiding (CIK).
1198  * Used for display watermark bandwidth calculations
1199  * Returns true if the display fits, false if not.
1200  */
1201 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1202 {
1203         u32 lb_partitions = wm->lb_size / wm->src_width;
1204         u32 line_time = wm->active_time + wm->blank_time;
1205         u32 latency_tolerant_lines;
1206         u32 latency_hiding;
1207         fixed20_12 a;
1208
1209         a.full = dfixed_const(1);
1210         if (wm->vsc.full > a.full)
1211                 latency_tolerant_lines = 1;
1212         else {
1213                 if (lb_partitions <= (wm->vtaps + 1))
1214                         latency_tolerant_lines = 1;
1215                 else
1216                         latency_tolerant_lines = 2;
1217         }
1218
1219         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1220
1221         if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1222                 return true;
1223         else
1224                 return false;
1225 }
1226
1227 /**
1228  * dce_v11_0_program_watermarks - program display watermarks
1229  *
1230  * @adev: amdgpu_device pointer
1231  * @amdgpu_crtc: the selected display controller
1232  * @lb_size: line buffer size
1233  * @num_heads: number of display controllers in use
1234  *
1235  * Calculate and program the display watermarks for the
1236  * selected display controller (CIK).
1237  */
1238 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1239                                         struct amdgpu_crtc *amdgpu_crtc,
1240                                         u32 lb_size, u32 num_heads)
1241 {
1242         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1243         struct dce10_wm_params wm_low, wm_high;
1244         u32 pixel_period;
1245         u32 line_time = 0;
1246         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1247         u32 tmp, wm_mask;
1248
1249         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1250                 pixel_period = 1000000 / (u32)mode->clock;
1251                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1252
1253                 /* watermark for high clocks */
1254                 if (adev->pm.dpm_enabled) {
1255                         wm_high.yclk =
1256                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1257                         wm_high.sclk =
1258                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1259                 } else {
1260                         wm_high.yclk = adev->pm.current_mclk * 10;
1261                         wm_high.sclk = adev->pm.current_sclk * 10;
1262                 }
1263
1264                 wm_high.disp_clk = mode->clock;
1265                 wm_high.src_width = mode->crtc_hdisplay;
1266                 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1267                 wm_high.blank_time = line_time - wm_high.active_time;
1268                 wm_high.interlaced = false;
1269                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1270                         wm_high.interlaced = true;
1271                 wm_high.vsc = amdgpu_crtc->vsc;
1272                 wm_high.vtaps = 1;
1273                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1274                         wm_high.vtaps = 2;
1275                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1276                 wm_high.lb_size = lb_size;
1277                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1278                 wm_high.num_heads = num_heads;
1279
1280                 /* set for high clocks */
1281                 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1282
1283                 /* possibly force display priority to high */
1284                 /* should really do this at mode validation time... */
1285                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1286                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1287                     !dce_v11_0_check_latency_hiding(&wm_high) ||
1288                     (adev->mode_info.disp_priority == 2)) {
1289                         DRM_DEBUG_KMS("force priority to high\n");
1290                 }
1291
1292                 /* watermark for low clocks */
1293                 if (adev->pm.dpm_enabled) {
1294                         wm_low.yclk =
1295                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1296                         wm_low.sclk =
1297                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1298                 } else {
1299                         wm_low.yclk = adev->pm.current_mclk * 10;
1300                         wm_low.sclk = adev->pm.current_sclk * 10;
1301                 }
1302
1303                 wm_low.disp_clk = mode->clock;
1304                 wm_low.src_width = mode->crtc_hdisplay;
1305                 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1306                 wm_low.blank_time = line_time - wm_low.active_time;
1307                 wm_low.interlaced = false;
1308                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1309                         wm_low.interlaced = true;
1310                 wm_low.vsc = amdgpu_crtc->vsc;
1311                 wm_low.vtaps = 1;
1312                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1313                         wm_low.vtaps = 2;
1314                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1315                 wm_low.lb_size = lb_size;
1316                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1317                 wm_low.num_heads = num_heads;
1318
1319                 /* set for low clocks */
1320                 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1321
1322                 /* possibly force display priority to high */
1323                 /* should really do this at mode validation time... */
1324                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1325                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1326                     !dce_v11_0_check_latency_hiding(&wm_low) ||
1327                     (adev->mode_info.disp_priority == 2)) {
1328                         DRM_DEBUG_KMS("force priority to high\n");
1329                 }
1330         }
1331
1332         /* select wm A */
1333         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1334         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1335         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1336         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1337         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1338         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1339         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1340         /* select wm B */
1341         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1342         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1343         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1344         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1345         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1346         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1347         /* restore original selection */
1348         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1349
1350         /* save values for DPM */
1351         amdgpu_crtc->line_time = line_time;
1352         amdgpu_crtc->wm_high = latency_watermark_a;
1353         amdgpu_crtc->wm_low = latency_watermark_b;
1354 }
1355
1356 /**
1357  * dce_v11_0_bandwidth_update - program display watermarks
1358  *
1359  * @adev: amdgpu_device pointer
1360  *
1361  * Calculate and program the display watermarks and line
1362  * buffer allocation (CIK).
1363  */
1364 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1365 {
1366         struct drm_display_mode *mode = NULL;
1367         u32 num_heads = 0, lb_size;
1368         int i;
1369
1370         amdgpu_update_display_priority(adev);
1371
1372         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1373                 if (adev->mode_info.crtcs[i]->base.enabled)
1374                         num_heads++;
1375         }
1376         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1377                 mode = &adev->mode_info.crtcs[i]->base.mode;
1378                 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1379                 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1380                                             lb_size, num_heads);
1381         }
1382 }
1383
1384 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1385 {
1386         int i;
1387         u32 offset, tmp;
1388
1389         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1390                 offset = adev->mode_info.audio.pin[i].offset;
1391                 tmp = RREG32_AUDIO_ENDPT(offset,
1392                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1393                 if (((tmp &
1394                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1395                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1396                         adev->mode_info.audio.pin[i].connected = false;
1397                 else
1398                         adev->mode_info.audio.pin[i].connected = true;
1399         }
1400 }
1401
1402 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1403 {
1404         int i;
1405
1406         dce_v11_0_audio_get_connected_pins(adev);
1407
1408         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1409                 if (adev->mode_info.audio.pin[i].connected)
1410                         return &adev->mode_info.audio.pin[i];
1411         }
1412         DRM_ERROR("No connected audio pins found!\n");
1413         return NULL;
1414 }
1415
1416 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1417 {
1418         struct amdgpu_device *adev = encoder->dev->dev_private;
1419         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1420         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1421         u32 tmp;
1422
1423         if (!dig || !dig->afmt || !dig->afmt->pin)
1424                 return;
1425
1426         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1427         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1428         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1429 }
1430
1431 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1432                                                 struct drm_display_mode *mode)
1433 {
1434         struct amdgpu_device *adev = encoder->dev->dev_private;
1435         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1436         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1437         struct drm_connector *connector;
1438         struct amdgpu_connector *amdgpu_connector = NULL;
1439         u32 tmp;
1440         int interlace = 0;
1441
1442         if (!dig || !dig->afmt || !dig->afmt->pin)
1443                 return;
1444
1445         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1446                 if (connector->encoder == encoder) {
1447                         amdgpu_connector = to_amdgpu_connector(connector);
1448                         break;
1449                 }
1450         }
1451
1452         if (!amdgpu_connector) {
1453                 DRM_ERROR("Couldn't find encoder's connector\n");
1454                 return;
1455         }
1456
1457         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1458                 interlace = 1;
1459         if (connector->latency_present[interlace]) {
1460                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1461                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1462                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1463                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1464         } else {
1465                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1466                                     VIDEO_LIPSYNC, 0);
1467                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1468                                     AUDIO_LIPSYNC, 0);
1469         }
1470         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1471                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1472 }
1473
1474 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1475 {
1476         struct amdgpu_device *adev = encoder->dev->dev_private;
1477         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1478         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1479         struct drm_connector *connector;
1480         struct amdgpu_connector *amdgpu_connector = NULL;
1481         u32 tmp;
1482         u8 *sadb = NULL;
1483         int sad_count;
1484
1485         if (!dig || !dig->afmt || !dig->afmt->pin)
1486                 return;
1487
1488         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1489                 if (connector->encoder == encoder) {
1490                         amdgpu_connector = to_amdgpu_connector(connector);
1491                         break;
1492                 }
1493         }
1494
1495         if (!amdgpu_connector) {
1496                 DRM_ERROR("Couldn't find encoder's connector\n");
1497                 return;
1498         }
1499
1500         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1501         if (sad_count < 0) {
1502                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1503                 sad_count = 0;
1504         }
1505
1506         /* program the speaker allocation */
1507         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1508                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1509         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1510                             DP_CONNECTION, 0);
1511         /* set HDMI mode */
1512         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1513                             HDMI_CONNECTION, 1);
1514         if (sad_count)
1515                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1516                                     SPEAKER_ALLOCATION, sadb[0]);
1517         else
1518                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1519                                     SPEAKER_ALLOCATION, 5); /* stereo */
1520         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1521                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1522
1523         kfree(sadb);
1524 }
1525
1526 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1527 {
1528         struct amdgpu_device *adev = encoder->dev->dev_private;
1529         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1530         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1531         struct drm_connector *connector;
1532         struct amdgpu_connector *amdgpu_connector = NULL;
1533         struct cea_sad *sads;
1534         int i, sad_count;
1535
1536         static const u16 eld_reg_to_type[][2] = {
1537                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1538                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1539                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1540                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1541                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1542                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1543                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1544                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1545                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1546                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1547                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1548                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1549         };
1550
1551         if (!dig || !dig->afmt || !dig->afmt->pin)
1552                 return;
1553
1554         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1555                 if (connector->encoder == encoder) {
1556                         amdgpu_connector = to_amdgpu_connector(connector);
1557                         break;
1558                 }
1559         }
1560
1561         if (!amdgpu_connector) {
1562                 DRM_ERROR("Couldn't find encoder's connector\n");
1563                 return;
1564         }
1565
1566         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1567         if (sad_count <= 0) {
1568                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1569                 return;
1570         }
1571         BUG_ON(!sads);
1572
1573         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1574                 u32 tmp = 0;
1575                 u8 stereo_freqs = 0;
1576                 int max_channels = -1;
1577                 int j;
1578
1579                 for (j = 0; j < sad_count; j++) {
1580                         struct cea_sad *sad = &sads[j];
1581
1582                         if (sad->format == eld_reg_to_type[i][1]) {
1583                                 if (sad->channels > max_channels) {
1584                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1585                                                             MAX_CHANNELS, sad->channels);
1586                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1587                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1588                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1589                                                             SUPPORTED_FREQUENCIES, sad->freq);
1590                                         max_channels = sad->channels;
1591                                 }
1592
1593                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1594                                         stereo_freqs |= sad->freq;
1595                                 else
1596                                         break;
1597                         }
1598                 }
1599
1600                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1601                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1602                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1603         }
1604
1605         kfree(sads);
1606 }
1607
1608 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1609                                   struct amdgpu_audio_pin *pin,
1610                                   bool enable)
1611 {
1612         if (!pin)
1613                 return;
1614
1615         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1616                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1617 }
1618
1619 static const u32 pin_offsets[] =
1620 {
1621         AUD0_REGISTER_OFFSET,
1622         AUD1_REGISTER_OFFSET,
1623         AUD2_REGISTER_OFFSET,
1624         AUD3_REGISTER_OFFSET,
1625         AUD4_REGISTER_OFFSET,
1626         AUD5_REGISTER_OFFSET,
1627         AUD6_REGISTER_OFFSET,
1628 };
1629
1630 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1631 {
1632         int i;
1633
1634         if (!amdgpu_audio)
1635                 return 0;
1636
1637         adev->mode_info.audio.enabled = true;
1638
1639         adev->mode_info.audio.num_pins = 7;
1640
1641         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1642                 adev->mode_info.audio.pin[i].channels = -1;
1643                 adev->mode_info.audio.pin[i].rate = -1;
1644                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1645                 adev->mode_info.audio.pin[i].status_bits = 0;
1646                 adev->mode_info.audio.pin[i].category_code = 0;
1647                 adev->mode_info.audio.pin[i].connected = false;
1648                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1649                 adev->mode_info.audio.pin[i].id = i;
1650                 /* disable audio.  it will be set up later */
1651                 /* XXX remove once we switch to ip funcs */
1652                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1653         }
1654
1655         return 0;
1656 }
1657
1658 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1659 {
1660         int i;
1661
1662         if (!adev->mode_info.audio.enabled)
1663                 return;
1664
1665         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1666                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1667
1668         adev->mode_info.audio.enabled = false;
1669 }
1670
1671 /*
1672  * update the N and CTS parameters for a given pixel clock rate
1673  */
1674 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1675 {
1676         struct drm_device *dev = encoder->dev;
1677         struct amdgpu_device *adev = dev->dev_private;
1678         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1679         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1680         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1681         u32 tmp;
1682
1683         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1684         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1685         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1686         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1687         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1688         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1689
1690         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1691         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1692         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1693         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1694         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1695         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1696
1697         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1698         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1699         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1700         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1701         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1702         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1703
1704 }
1705
1706 /*
1707  * build a HDMI Video Info Frame
1708  */
1709 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1710                                                void *buffer, size_t size)
1711 {
1712         struct drm_device *dev = encoder->dev;
1713         struct amdgpu_device *adev = dev->dev_private;
1714         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1715         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1716         uint8_t *frame = buffer + 3;
1717         uint8_t *header = buffer;
1718
1719         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1720                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1721         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1722                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1723         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1724                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1725         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1726                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1727 }
1728
1729 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1730 {
1731         struct drm_device *dev = encoder->dev;
1732         struct amdgpu_device *adev = dev->dev_private;
1733         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1734         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1735         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1736         u32 dto_phase = 24 * 1000;
1737         u32 dto_modulo = clock;
1738         u32 tmp;
1739
1740         if (!dig || !dig->afmt)
1741                 return;
1742
1743         /* XXX two dtos; generally use dto0 for hdmi */
1744         /* Express [24MHz / target pixel clock] as an exact rational
1745          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1746          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1747          */
1748         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1749         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1750                             amdgpu_crtc->crtc_id);
1751         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1752         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1753         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1754 }
1755
1756 /*
1757  * update the info frames with the data from the current display mode
1758  */
1759 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1760                                   struct drm_display_mode *mode)
1761 {
1762         struct drm_device *dev = encoder->dev;
1763         struct amdgpu_device *adev = dev->dev_private;
1764         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1765         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1766         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1767         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1768         struct hdmi_avi_infoframe frame;
1769         ssize_t err;
1770         u32 tmp;
1771         int bpc = 8;
1772
1773         if (!dig || !dig->afmt)
1774                 return;
1775
1776         /* Silent, r600_hdmi_enable will raise WARN for us */
1777         if (!dig->afmt->enabled)
1778                 return;
1779
1780         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1781         if (encoder->crtc) {
1782                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1783                 bpc = amdgpu_crtc->bpc;
1784         }
1785
1786         /* disable audio prior to setting up hw */
1787         dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1788         dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1789
1790         dce_v11_0_audio_set_dto(encoder, mode->clock);
1791
1792         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1793         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1794         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1795
1796         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1797
1798         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1799         switch (bpc) {
1800         case 0:
1801         case 6:
1802         case 8:
1803         case 16:
1804         default:
1805                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1806                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1807                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1808                           connector->name, bpc);
1809                 break;
1810         case 10:
1811                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1812                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1813                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1814                           connector->name);
1815                 break;
1816         case 12:
1817                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1818                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1819                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1820                           connector->name);
1821                 break;
1822         }
1823         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1824
1825         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1826         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1827         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1828         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1829         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1830
1831         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1832         /* enable audio info frames (frames won't be set until audio is enabled) */
1833         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1834         /* required for audio info values to be updated */
1835         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1836         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1837
1838         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1839         /* required for audio info values to be updated */
1840         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1841         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1842
1843         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1844         /* anything other than 0 */
1845         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1846         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1847
1848         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1849
1850         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1851         /* set the default audio delay */
1852         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1853         /* should be suffient for all audio modes and small enough for all hblanks */
1854         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1855         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1856
1857         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1858         /* allow 60958 channel status fields to be updated */
1859         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1860         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1861
1862         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1863         if (bpc > 8)
1864                 /* clear SW CTS value */
1865                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1866         else
1867                 /* select SW CTS value */
1868                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1869         /* allow hw to sent ACR packets when required */
1870         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1871         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1872
1873         dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1874
1875         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1876         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1877         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1878
1879         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1880         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1881         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1882
1883         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1884         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1885         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1886         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1887         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1888         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1889         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1890         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1891
1892         dce_v11_0_audio_write_speaker_allocation(encoder);
1893
1894         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1895                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1896
1897         dce_v11_0_afmt_audio_select_pin(encoder);
1898         dce_v11_0_audio_write_sad_regs(encoder);
1899         dce_v11_0_audio_write_latency_fields(encoder, mode);
1900
1901         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1902         if (err < 0) {
1903                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1904                 return;
1905         }
1906
1907         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1908         if (err < 0) {
1909                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1910                 return;
1911         }
1912
1913         dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1914
1915         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1916         /* enable AVI info frames */
1917         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1918         /* required for audio info values to be updated */
1919         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1920         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1921
1922         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1923         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1924         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1925
1926         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1927         /* send audio packets */
1928         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1929         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1930
1931         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1932         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1933         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1934         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1935
1936         /* enable audio after to setting up hw */
1937         dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1938 }
1939
1940 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1941 {
1942         struct drm_device *dev = encoder->dev;
1943         struct amdgpu_device *adev = dev->dev_private;
1944         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1945         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1946
1947         if (!dig || !dig->afmt)
1948                 return;
1949
1950         /* Silent, r600_hdmi_enable will raise WARN for us */
1951         if (enable && dig->afmt->enabled)
1952                 return;
1953         if (!enable && !dig->afmt->enabled)
1954                 return;
1955
1956         if (!enable && dig->afmt->pin) {
1957                 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1958                 dig->afmt->pin = NULL;
1959         }
1960
1961         dig->afmt->enabled = enable;
1962
1963         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1964                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1965 }
1966
1967 static void dce_v11_0_afmt_init(struct amdgpu_device *adev)
1968 {
1969         int i;
1970
1971         for (i = 0; i < adev->mode_info.num_dig; i++)
1972                 adev->mode_info.afmt[i] = NULL;
1973
1974         /* DCE11 has audio blocks tied to DIG encoders */
1975         for (i = 0; i < adev->mode_info.num_dig; i++) {
1976                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1977                 if (adev->mode_info.afmt[i]) {
1978                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1979                         adev->mode_info.afmt[i]->id = i;
1980                 }
1981         }
1982 }
1983
1984 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1985 {
1986         int i;
1987
1988         for (i = 0; i < adev->mode_info.num_dig; i++) {
1989                 kfree(adev->mode_info.afmt[i]);
1990                 adev->mode_info.afmt[i] = NULL;
1991         }
1992 }
1993
1994 static const u32 vga_control_regs[6] =
1995 {
1996         mmD1VGA_CONTROL,
1997         mmD2VGA_CONTROL,
1998         mmD3VGA_CONTROL,
1999         mmD4VGA_CONTROL,
2000         mmD5VGA_CONTROL,
2001         mmD6VGA_CONTROL,
2002 };
2003
2004 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
2005 {
2006         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2007         struct drm_device *dev = crtc->dev;
2008         struct amdgpu_device *adev = dev->dev_private;
2009         u32 vga_control;
2010
2011         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2012         if (enable)
2013                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2014         else
2015                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2016 }
2017
2018 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
2019 {
2020         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2021         struct drm_device *dev = crtc->dev;
2022         struct amdgpu_device *adev = dev->dev_private;
2023
2024         if (enable)
2025                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2026         else
2027                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2028 }
2029
2030 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2031                                      struct drm_framebuffer *fb,
2032                                      int x, int y, int atomic)
2033 {
2034         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2035         struct drm_device *dev = crtc->dev;
2036         struct amdgpu_device *adev = dev->dev_private;
2037         struct amdgpu_framebuffer *amdgpu_fb;
2038         struct drm_framebuffer *target_fb;
2039         struct drm_gem_object *obj;
2040         struct amdgpu_bo *rbo;
2041         uint64_t fb_location, tiling_flags;
2042         uint32_t fb_format, fb_pitch_pixels;
2043         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2044         u32 pipe_config;
2045         u32 tmp, viewport_w, viewport_h;
2046         int r;
2047         bool bypass_lut = false;
2048
2049         /* no fb bound */
2050         if (!atomic && !crtc->primary->fb) {
2051                 DRM_DEBUG_KMS("No FB bound\n");
2052                 return 0;
2053         }
2054
2055         if (atomic) {
2056                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2057                 target_fb = fb;
2058         }
2059         else {
2060                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2061                 target_fb = crtc->primary->fb;
2062         }
2063
2064         /* If atomic, assume fb object is pinned & idle & fenced and
2065          * just update base pointers
2066          */
2067         obj = amdgpu_fb->obj;
2068         rbo = gem_to_amdgpu_bo(obj);
2069         r = amdgpu_bo_reserve(rbo, false);
2070         if (unlikely(r != 0))
2071                 return r;
2072
2073         if (atomic)
2074                 fb_location = amdgpu_bo_gpu_offset(rbo);
2075         else {
2076                 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2077                 if (unlikely(r != 0)) {
2078                         amdgpu_bo_unreserve(rbo);
2079                         return -EINVAL;
2080                 }
2081         }
2082
2083         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2084         amdgpu_bo_unreserve(rbo);
2085
2086         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2087
2088         switch (target_fb->pixel_format) {
2089         case DRM_FORMAT_C8:
2090                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2091                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2092                 break;
2093         case DRM_FORMAT_XRGB4444:
2094         case DRM_FORMAT_ARGB4444:
2095                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2096                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2097 #ifdef __BIG_ENDIAN
2098                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2099                                         ENDIAN_8IN16);
2100 #endif
2101                 break;
2102         case DRM_FORMAT_XRGB1555:
2103         case DRM_FORMAT_ARGB1555:
2104                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2105                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2106 #ifdef __BIG_ENDIAN
2107                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2108                                         ENDIAN_8IN16);
2109 #endif
2110                 break;
2111         case DRM_FORMAT_BGRX5551:
2112         case DRM_FORMAT_BGRA5551:
2113                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2114                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2115 #ifdef __BIG_ENDIAN
2116                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2117                                         ENDIAN_8IN16);
2118 #endif
2119                 break;
2120         case DRM_FORMAT_RGB565:
2121                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2122                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2123 #ifdef __BIG_ENDIAN
2124                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2125                                         ENDIAN_8IN16);
2126 #endif
2127                 break;
2128         case DRM_FORMAT_XRGB8888:
2129         case DRM_FORMAT_ARGB8888:
2130                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2131                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2132 #ifdef __BIG_ENDIAN
2133                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2134                                         ENDIAN_8IN32);
2135 #endif
2136                 break;
2137         case DRM_FORMAT_XRGB2101010:
2138         case DRM_FORMAT_ARGB2101010:
2139                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2140                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2141 #ifdef __BIG_ENDIAN
2142                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2143                                         ENDIAN_8IN32);
2144 #endif
2145                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2146                 bypass_lut = true;
2147                 break;
2148         case DRM_FORMAT_BGRX1010102:
2149         case DRM_FORMAT_BGRA1010102:
2150                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2151                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2152 #ifdef __BIG_ENDIAN
2153                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2154                                         ENDIAN_8IN32);
2155 #endif
2156                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2157                 bypass_lut = true;
2158                 break;
2159         default:
2160                 DRM_ERROR("Unsupported screen format %s\n",
2161                         drm_get_format_name(target_fb->pixel_format));
2162                 return -EINVAL;
2163         }
2164
2165         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2166                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2167
2168                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2169                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2170                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2171                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2172                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2173
2174                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2175                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2176                                           ARRAY_2D_TILED_THIN1);
2177                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2178                                           tile_split);
2179                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2180                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2181                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2182                                           mtaspect);
2183                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2184                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2185         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2186                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2187                                           ARRAY_1D_TILED_THIN1);
2188         }
2189
2190         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2191                                   pipe_config);
2192
2193         dce_v11_0_vga_enable(crtc, false);
2194
2195         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2196                upper_32_bits(fb_location));
2197         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2198                upper_32_bits(fb_location));
2199         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2200                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2201         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2202                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2203         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2204         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2205
2206         /*
2207          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2208          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2209          * retain the full precision throughout the pipeline.
2210          */
2211         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2212         if (bypass_lut)
2213                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2214         else
2215                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2216         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2217
2218         if (bypass_lut)
2219                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2220
2221         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2222         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2223         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2224         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2225         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2226         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2227
2228         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2229         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2230
2231         dce_v11_0_grph_enable(crtc, true);
2232
2233         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2234                target_fb->height);
2235
2236         x &= ~3;
2237         y &= ~1;
2238         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2239                (x << 16) | y);
2240         viewport_w = crtc->mode.hdisplay;
2241         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2242         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2243                (viewport_w << 16) | viewport_h);
2244
2245         /* pageflip setup */
2246         /* make sure flip is at vb rather than hb */
2247         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2248         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2249                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2250         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2251
2252         /* set pageflip to happen only at start of vblank interval (front porch) */
2253         WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2254
2255         if (!atomic && fb && fb != crtc->primary->fb) {
2256                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2257                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2258                 r = amdgpu_bo_reserve(rbo, false);
2259                 if (unlikely(r != 0))
2260                         return r;
2261                 amdgpu_bo_unpin(rbo);
2262                 amdgpu_bo_unreserve(rbo);
2263         }
2264
2265         /* Bytes per pixel may have changed */
2266         dce_v11_0_bandwidth_update(adev);
2267
2268         return 0;
2269 }
2270
2271 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2272                                      struct drm_display_mode *mode)
2273 {
2274         struct drm_device *dev = crtc->dev;
2275         struct amdgpu_device *adev = dev->dev_private;
2276         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2277         u32 tmp;
2278
2279         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2280         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2281                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2282         else
2283                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2284         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2285 }
2286
2287 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2288 {
2289         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2290         struct drm_device *dev = crtc->dev;
2291         struct amdgpu_device *adev = dev->dev_private;
2292         int i;
2293         u32 tmp;
2294
2295         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2296
2297         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2298         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2299         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2300
2301         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2302         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2303         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2304
2305         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2306         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2307         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2308
2309         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2310
2311         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2312         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2313         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2314
2315         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2316         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2317         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2318
2319         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2320         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2321
2322         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2323         for (i = 0; i < 256; i++) {
2324                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2325                        (amdgpu_crtc->lut_r[i] << 20) |
2326                        (amdgpu_crtc->lut_g[i] << 10) |
2327                        (amdgpu_crtc->lut_b[i] << 0));
2328         }
2329
2330         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2331         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2332         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2333         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2334         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2335
2336         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2337         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2338         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2339
2340         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2341         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2342         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2343
2344         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2345         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2346         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2347
2348         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2349         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2350         /* XXX this only needs to be programmed once per crtc at startup,
2351          * not sure where the best place for it is
2352          */
2353         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2354         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2355         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2356 }
2357
2358 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2359 {
2360         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2361         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2362
2363         switch (amdgpu_encoder->encoder_id) {
2364         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2365                 if (dig->linkb)
2366                         return 1;
2367                 else
2368                         return 0;
2369                 break;
2370         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2371                 if (dig->linkb)
2372                         return 3;
2373                 else
2374                         return 2;
2375                 break;
2376         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2377                 if (dig->linkb)
2378                         return 5;
2379                 else
2380                         return 4;
2381                 break;
2382         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2383                 return 6;
2384                 break;
2385         default:
2386                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2387                 return 0;
2388         }
2389 }
2390
2391 /**
2392  * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2393  *
2394  * @crtc: drm crtc
2395  *
2396  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2397  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2398  * monitors a dedicated PPLL must be used.  If a particular board has
2399  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2400  * as there is no need to program the PLL itself.  If we are not able to
2401  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2402  * avoid messing up an existing monitor.
2403  *
2404  * Asic specific PLL information
2405  *
2406  * DCE 10.x
2407  * Tonga
2408  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2409  * CI
2410  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2411  *
2412  */
2413 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2414 {
2415         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2416         struct drm_device *dev = crtc->dev;
2417         struct amdgpu_device *adev = dev->dev_private;
2418         u32 pll_in_use;
2419         int pll;
2420
2421         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2422                 if (adev->clock.dp_extclk)
2423                         /* skip PPLL programming if using ext clock */
2424                         return ATOM_PPLL_INVALID;
2425                 else {
2426                         /* use the same PPLL for all DP monitors */
2427                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2428                         if (pll != ATOM_PPLL_INVALID)
2429                                 return pll;
2430                 }
2431         } else {
2432                 /* use the same PPLL for all monitors with the same clock */
2433                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2434                 if (pll != ATOM_PPLL_INVALID)
2435                         return pll;
2436         }
2437
2438         /* XXX need to determine what plls are available on each DCE11 part */
2439         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2440         if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2441                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2442                         return ATOM_PPLL1;
2443                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2444                         return ATOM_PPLL0;
2445                 DRM_ERROR("unable to allocate a PPLL\n");
2446                 return ATOM_PPLL_INVALID;
2447         } else {
2448                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2449                         return ATOM_PPLL2;
2450                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2451                         return ATOM_PPLL1;
2452                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2453                         return ATOM_PPLL0;
2454                 DRM_ERROR("unable to allocate a PPLL\n");
2455                 return ATOM_PPLL_INVALID;
2456         }
2457         return ATOM_PPLL_INVALID;
2458 }
2459
2460 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2461 {
2462         struct amdgpu_device *adev = crtc->dev->dev_private;
2463         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2464         uint32_t cur_lock;
2465
2466         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2467         if (lock)
2468                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2469         else
2470                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2471         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2472 }
2473
2474 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2475 {
2476         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2477         struct amdgpu_device *adev = crtc->dev->dev_private;
2478         u32 tmp;
2479
2480         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2481         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2482         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2483 }
2484
2485 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2486 {
2487         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2488         struct amdgpu_device *adev = crtc->dev->dev_private;
2489         u32 tmp;
2490
2491         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2492                upper_32_bits(amdgpu_crtc->cursor_addr));
2493         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2494                lower_32_bits(amdgpu_crtc->cursor_addr));
2495
2496         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2497         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2498         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2499         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2500 }
2501
2502 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2503                                         int x, int y)
2504 {
2505         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2506         struct amdgpu_device *adev = crtc->dev->dev_private;
2507         int xorigin = 0, yorigin = 0;
2508
2509         /* avivo cursor are offset into the total surface */
2510         x += crtc->x;
2511         y += crtc->y;
2512         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2513
2514         if (x < 0) {
2515                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2516                 x = 0;
2517         }
2518         if (y < 0) {
2519                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2520                 y = 0;
2521         }
2522
2523         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2524         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2525         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2526                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2527
2528         amdgpu_crtc->cursor_x = x;
2529         amdgpu_crtc->cursor_y = y;
2530
2531         return 0;
2532 }
2533
2534 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2535                                       int x, int y)
2536 {
2537         int ret;
2538
2539         dce_v11_0_lock_cursor(crtc, true);
2540         ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2541         dce_v11_0_lock_cursor(crtc, false);
2542
2543         return ret;
2544 }
2545
2546 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2547                                       struct drm_file *file_priv,
2548                                       uint32_t handle,
2549                                       uint32_t width,
2550                                       uint32_t height,
2551                                       int32_t hot_x,
2552                                       int32_t hot_y)
2553 {
2554         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2555         struct drm_gem_object *obj;
2556         struct amdgpu_bo *aobj;
2557         int ret;
2558
2559         if (!handle) {
2560                 /* turn off cursor */
2561                 dce_v11_0_hide_cursor(crtc);
2562                 obj = NULL;
2563                 goto unpin;
2564         }
2565
2566         if ((width > amdgpu_crtc->max_cursor_width) ||
2567             (height > amdgpu_crtc->max_cursor_height)) {
2568                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2569                 return -EINVAL;
2570         }
2571
2572         obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
2573         if (!obj) {
2574                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2575                 return -ENOENT;
2576         }
2577
2578         aobj = gem_to_amdgpu_bo(obj);
2579         ret = amdgpu_bo_reserve(aobj, false);
2580         if (ret != 0) {
2581                 drm_gem_object_unreference_unlocked(obj);
2582                 return ret;
2583         }
2584
2585         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2586         amdgpu_bo_unreserve(aobj);
2587         if (ret) {
2588                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2589                 drm_gem_object_unreference_unlocked(obj);
2590                 return ret;
2591         }
2592
2593         amdgpu_crtc->cursor_width = width;
2594         amdgpu_crtc->cursor_height = height;
2595
2596         dce_v11_0_lock_cursor(crtc, true);
2597
2598         if (hot_x != amdgpu_crtc->cursor_hot_x ||
2599             hot_y != amdgpu_crtc->cursor_hot_y) {
2600                 int x, y;
2601
2602                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2603                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2604
2605                 dce_v11_0_cursor_move_locked(crtc, x, y);
2606
2607                 amdgpu_crtc->cursor_hot_x = hot_x;
2608                 amdgpu_crtc->cursor_hot_y = hot_y;
2609         }
2610
2611         dce_v11_0_show_cursor(crtc);
2612         dce_v11_0_lock_cursor(crtc, false);
2613
2614 unpin:
2615         if (amdgpu_crtc->cursor_bo) {
2616                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2617                 ret = amdgpu_bo_reserve(aobj, false);
2618                 if (likely(ret == 0)) {
2619                         amdgpu_bo_unpin(aobj);
2620                         amdgpu_bo_unreserve(aobj);
2621                 }
2622                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2623         }
2624
2625         amdgpu_crtc->cursor_bo = obj;
2626         return 0;
2627 }
2628
2629 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2630 {
2631         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2632
2633         if (amdgpu_crtc->cursor_bo) {
2634                 dce_v11_0_lock_cursor(crtc, true);
2635
2636                 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2637                                              amdgpu_crtc->cursor_y);
2638
2639                 dce_v11_0_show_cursor(crtc);
2640
2641                 dce_v11_0_lock_cursor(crtc, false);
2642         }
2643 }
2644
2645 static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2646                                     u16 *blue, uint32_t start, uint32_t size)
2647 {
2648         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2649         int end = (start + size > 256) ? 256 : start + size, i;
2650
2651         /* userspace palettes are always correct as is */
2652         for (i = start; i < end; i++) {
2653                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2654                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2655                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2656         }
2657         dce_v11_0_crtc_load_lut(crtc);
2658 }
2659
2660 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2661 {
2662         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2663
2664         drm_crtc_cleanup(crtc);
2665         destroy_workqueue(amdgpu_crtc->pflip_queue);
2666         kfree(amdgpu_crtc);
2667 }
2668
2669 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2670         .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2671         .cursor_move = dce_v11_0_crtc_cursor_move,
2672         .gamma_set = dce_v11_0_crtc_gamma_set,
2673         .set_config = amdgpu_crtc_set_config,
2674         .destroy = dce_v11_0_crtc_destroy,
2675         .page_flip = amdgpu_crtc_page_flip,
2676 };
2677
2678 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2679 {
2680         struct drm_device *dev = crtc->dev;
2681         struct amdgpu_device *adev = dev->dev_private;
2682         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2683         unsigned type;
2684
2685         switch (mode) {
2686         case DRM_MODE_DPMS_ON:
2687                 amdgpu_crtc->enabled = true;
2688                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2689                 dce_v11_0_vga_enable(crtc, true);
2690                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2691                 dce_v11_0_vga_enable(crtc, false);
2692                 /* Make sure VBLANK interrupt is still enabled */
2693                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2694                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2695                 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2696                 dce_v11_0_crtc_load_lut(crtc);
2697                 break;
2698         case DRM_MODE_DPMS_STANDBY:
2699         case DRM_MODE_DPMS_SUSPEND:
2700         case DRM_MODE_DPMS_OFF:
2701                 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
2702                 if (amdgpu_crtc->enabled) {
2703                         dce_v11_0_vga_enable(crtc, true);
2704                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2705                         dce_v11_0_vga_enable(crtc, false);
2706                 }
2707                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2708                 amdgpu_crtc->enabled = false;
2709                 break;
2710         }
2711         /* adjust pm to dpms */
2712         amdgpu_pm_compute_clocks(adev);
2713 }
2714
2715 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2716 {
2717         /* disable crtc pair power gating before programming */
2718         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2719         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2720         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2721 }
2722
2723 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2724 {
2725         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2726         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2727 }
2728
2729 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2730 {
2731         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2732         struct drm_device *dev = crtc->dev;
2733         struct amdgpu_device *adev = dev->dev_private;
2734         struct amdgpu_atom_ss ss;
2735         int i;
2736
2737         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2738         if (crtc->primary->fb) {
2739                 int r;
2740                 struct amdgpu_framebuffer *amdgpu_fb;
2741                 struct amdgpu_bo *rbo;
2742
2743                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2744                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2745                 r = amdgpu_bo_reserve(rbo, false);
2746                 if (unlikely(r))
2747                         DRM_ERROR("failed to reserve rbo before unpin\n");
2748                 else {
2749                         amdgpu_bo_unpin(rbo);
2750                         amdgpu_bo_unreserve(rbo);
2751                 }
2752         }
2753         /* disable the GRPH */
2754         dce_v11_0_grph_enable(crtc, false);
2755
2756         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2757
2758         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2759                 if (adev->mode_info.crtcs[i] &&
2760                     adev->mode_info.crtcs[i]->enabled &&
2761                     i != amdgpu_crtc->crtc_id &&
2762                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2763                         /* one other crtc is using this pll don't turn
2764                          * off the pll
2765                          */
2766                         goto done;
2767                 }
2768         }
2769
2770         switch (amdgpu_crtc->pll_id) {
2771         case ATOM_PPLL0:
2772         case ATOM_PPLL1:
2773         case ATOM_PPLL2:
2774                 /* disable the ppll */
2775                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2776                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2777                 break;
2778         default:
2779                 break;
2780         }
2781 done:
2782         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2783         amdgpu_crtc->adjusted_clock = 0;
2784         amdgpu_crtc->encoder = NULL;
2785         amdgpu_crtc->connector = NULL;
2786 }
2787
2788 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2789                                   struct drm_display_mode *mode,
2790                                   struct drm_display_mode *adjusted_mode,
2791                                   int x, int y, struct drm_framebuffer *old_fb)
2792 {
2793         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2794
2795         if (!amdgpu_crtc->adjusted_clock)
2796                 return -EINVAL;
2797
2798         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2799         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2800         dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2801         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2802         amdgpu_atombios_crtc_scaler_setup(crtc);
2803         dce_v11_0_cursor_reset(crtc);
2804         /* update the hw version fpr dpm */
2805         amdgpu_crtc->hw_mode = *adjusted_mode;
2806
2807         return 0;
2808 }
2809
2810 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2811                                      const struct drm_display_mode *mode,
2812                                      struct drm_display_mode *adjusted_mode)
2813 {
2814         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2815         struct drm_device *dev = crtc->dev;
2816         struct drm_encoder *encoder;
2817
2818         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2819         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2820                 if (encoder->crtc == crtc) {
2821                         amdgpu_crtc->encoder = encoder;
2822                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2823                         break;
2824                 }
2825         }
2826         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2827                 amdgpu_crtc->encoder = NULL;
2828                 amdgpu_crtc->connector = NULL;
2829                 return false;
2830         }
2831         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2832                 return false;
2833         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2834                 return false;
2835         /* pick pll */
2836         amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2837         /* if we can't get a PPLL for a non-DP encoder, fail */
2838         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2839             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2840                 return false;
2841
2842         return true;
2843 }
2844
2845 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2846                                   struct drm_framebuffer *old_fb)
2847 {
2848         return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2849 }
2850
2851 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2852                                          struct drm_framebuffer *fb,
2853                                          int x, int y, enum mode_set_atomic state)
2854 {
2855        return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2856 }
2857
2858 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2859         .dpms = dce_v11_0_crtc_dpms,
2860         .mode_fixup = dce_v11_0_crtc_mode_fixup,
2861         .mode_set = dce_v11_0_crtc_mode_set,
2862         .mode_set_base = dce_v11_0_crtc_set_base,
2863         .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2864         .prepare = dce_v11_0_crtc_prepare,
2865         .commit = dce_v11_0_crtc_commit,
2866         .load_lut = dce_v11_0_crtc_load_lut,
2867         .disable = dce_v11_0_crtc_disable,
2868 };
2869
2870 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2871 {
2872         struct amdgpu_crtc *amdgpu_crtc;
2873         int i;
2874
2875         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2876                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2877         if (amdgpu_crtc == NULL)
2878                 return -ENOMEM;
2879
2880         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2881
2882         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2883         amdgpu_crtc->crtc_id = index;
2884         amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
2885         adev->mode_info.crtcs[index] = amdgpu_crtc;
2886
2887         amdgpu_crtc->max_cursor_width = 128;
2888         amdgpu_crtc->max_cursor_height = 128;
2889         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2890         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2891
2892         for (i = 0; i < 256; i++) {
2893                 amdgpu_crtc->lut_r[i] = i << 2;
2894                 amdgpu_crtc->lut_g[i] = i << 2;
2895                 amdgpu_crtc->lut_b[i] = i << 2;
2896         }
2897
2898         switch (amdgpu_crtc->crtc_id) {
2899         case 0:
2900         default:
2901                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2902                 break;
2903         case 1:
2904                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2905                 break;
2906         case 2:
2907                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2908                 break;
2909         case 3:
2910                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2911                 break;
2912         case 4:
2913                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2914                 break;
2915         case 5:
2916                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2917                 break;
2918         }
2919
2920         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2921         amdgpu_crtc->adjusted_clock = 0;
2922         amdgpu_crtc->encoder = NULL;
2923         amdgpu_crtc->connector = NULL;
2924         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2925
2926         return 0;
2927 }
2928
2929 static int dce_v11_0_early_init(void *handle)
2930 {
2931         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2932
2933         adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2934         adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2935
2936         dce_v11_0_set_display_funcs(adev);
2937         dce_v11_0_set_irq_funcs(adev);
2938
2939         switch (adev->asic_type) {
2940         case CHIP_CARRIZO:
2941                 adev->mode_info.num_crtc = 3;
2942                 adev->mode_info.num_hpd = 6;
2943                 adev->mode_info.num_dig = 9;
2944                 break;
2945         case CHIP_STONEY:
2946                 adev->mode_info.num_crtc = 2;
2947                 adev->mode_info.num_hpd = 6;
2948                 adev->mode_info.num_dig = 9;
2949                 break;
2950         default:
2951                 /* FIXME: not supported yet */
2952                 return -EINVAL;
2953         }
2954
2955         return 0;
2956 }
2957
2958 static int dce_v11_0_sw_init(void *handle)
2959 {
2960         int r, i;
2961         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2962
2963         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2964                 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2965                 if (r)
2966                 return r;
2967         }
2968
2969         for (i = 8; i < 20; i += 2) {
2970                 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2971                 if (r)
2972                         return r;
2973         }
2974
2975         /* HPD hotplug */
2976         r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2977         if (r)
2978         return r;
2979
2980         adev->mode_info.mode_config_initialized = true;
2981
2982         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2983
2984         adev->ddev->mode_config.max_width = 16384;
2985         adev->ddev->mode_config.max_height = 16384;
2986
2987         adev->ddev->mode_config.preferred_depth = 24;
2988         adev->ddev->mode_config.prefer_shadow = 1;
2989
2990         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2991
2992         r = amdgpu_modeset_create_props(adev);
2993         if (r)
2994                 return r;
2995
2996         adev->ddev->mode_config.max_width = 16384;
2997         adev->ddev->mode_config.max_height = 16384;
2998
2999         /* allocate crtcs */
3000         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3001                 r = dce_v11_0_crtc_init(adev, i);
3002                 if (r)
3003                         return r;
3004         }
3005
3006         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3007                 amdgpu_print_display_setup(adev->ddev);
3008         else
3009                 return -EINVAL;
3010
3011         /* setup afmt */
3012         dce_v11_0_afmt_init(adev);
3013
3014         r = dce_v11_0_audio_init(adev);
3015         if (r)
3016                 return r;
3017
3018         drm_kms_helper_poll_init(adev->ddev);
3019
3020         return r;
3021 }
3022
3023 static int dce_v11_0_sw_fini(void *handle)
3024 {
3025         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3026
3027         kfree(adev->mode_info.bios_hardcoded_edid);
3028
3029         drm_kms_helper_poll_fini(adev->ddev);
3030
3031         dce_v11_0_audio_fini(adev);
3032
3033         dce_v11_0_afmt_fini(adev);
3034
3035         adev->mode_info.mode_config_initialized = false;
3036
3037         return 0;
3038 }
3039
3040 static int dce_v11_0_hw_init(void *handle)
3041 {
3042         int i;
3043         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3044
3045         dce_v11_0_init_golden_registers(adev);
3046
3047         /* init dig PHYs, disp eng pll */
3048         amdgpu_atombios_crtc_powergate_init(adev);
3049         amdgpu_atombios_encoder_init_dig(adev);
3050         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3051
3052         /* initialize hpd */
3053         dce_v11_0_hpd_init(adev);
3054
3055         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3056                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3057         }
3058
3059         return 0;
3060 }
3061
3062 static int dce_v11_0_hw_fini(void *handle)
3063 {
3064         int i;
3065         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3066
3067         dce_v11_0_hpd_fini(adev);
3068
3069         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3070                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3071         }
3072
3073         return 0;
3074 }
3075
3076 static int dce_v11_0_suspend(void *handle)
3077 {
3078         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3079
3080         amdgpu_atombios_scratch_regs_save(adev);
3081
3082         return dce_v11_0_hw_fini(handle);
3083 }
3084
3085 static int dce_v11_0_resume(void *handle)
3086 {
3087         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3088         int ret;
3089
3090         ret = dce_v11_0_hw_init(handle);
3091
3092         amdgpu_atombios_scratch_regs_restore(adev);
3093
3094         /* turn on the BL */
3095         if (adev->mode_info.bl_encoder) {
3096                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3097                                                                   adev->mode_info.bl_encoder);
3098                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3099                                                     bl_level);
3100         }
3101
3102         return ret;
3103 }
3104
3105 static bool dce_v11_0_is_idle(void *handle)
3106 {
3107         return true;
3108 }
3109
3110 static int dce_v11_0_wait_for_idle(void *handle)
3111 {
3112         return 0;
3113 }
3114
3115 static void dce_v11_0_print_status(void *handle)
3116 {
3117         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3118
3119         dev_info(adev->dev, "DCE 10.x registers\n");
3120         /* XXX todo */
3121 }
3122
3123 static int dce_v11_0_soft_reset(void *handle)
3124 {
3125         u32 srbm_soft_reset = 0, tmp;
3126         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3127
3128         if (dce_v11_0_is_display_hung(adev))
3129                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3130
3131         if (srbm_soft_reset) {
3132                 dce_v11_0_print_status((void *)adev);
3133
3134                 tmp = RREG32(mmSRBM_SOFT_RESET);
3135                 tmp |= srbm_soft_reset;
3136                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3137                 WREG32(mmSRBM_SOFT_RESET, tmp);
3138                 tmp = RREG32(mmSRBM_SOFT_RESET);
3139
3140                 udelay(50);
3141
3142                 tmp &= ~srbm_soft_reset;
3143                 WREG32(mmSRBM_SOFT_RESET, tmp);
3144                 tmp = RREG32(mmSRBM_SOFT_RESET);
3145
3146                 /* Wait a little for things to settle down */
3147                 udelay(50);
3148                 dce_v11_0_print_status((void *)adev);
3149         }
3150         return 0;
3151 }
3152
3153 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3154                                                      int crtc,
3155                                                      enum amdgpu_interrupt_state state)
3156 {
3157         u32 lb_interrupt_mask;
3158
3159         if (crtc >= adev->mode_info.num_crtc) {
3160                 DRM_DEBUG("invalid crtc %d\n", crtc);
3161                 return;
3162         }
3163
3164         switch (state) {
3165         case AMDGPU_IRQ_STATE_DISABLE:
3166                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3167                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3168                                                   VBLANK_INTERRUPT_MASK, 0);
3169                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3170                 break;
3171         case AMDGPU_IRQ_STATE_ENABLE:
3172                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3173                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3174                                                   VBLANK_INTERRUPT_MASK, 1);
3175                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3176                 break;
3177         default:
3178                 break;
3179         }
3180 }
3181
3182 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3183                                                     int crtc,
3184                                                     enum amdgpu_interrupt_state state)
3185 {
3186         u32 lb_interrupt_mask;
3187
3188         if (crtc >= adev->mode_info.num_crtc) {
3189                 DRM_DEBUG("invalid crtc %d\n", crtc);
3190                 return;
3191         }
3192
3193         switch (state) {
3194         case AMDGPU_IRQ_STATE_DISABLE:
3195                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3196                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3197                                                   VLINE_INTERRUPT_MASK, 0);
3198                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3199                 break;
3200         case AMDGPU_IRQ_STATE_ENABLE:
3201                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3202                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3203                                                   VLINE_INTERRUPT_MASK, 1);
3204                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3205                 break;
3206         default:
3207                 break;
3208         }
3209 }
3210
3211 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3212                                         struct amdgpu_irq_src *source,
3213                                         unsigned hpd,
3214                                         enum amdgpu_interrupt_state state)
3215 {
3216         u32 tmp;
3217
3218         if (hpd >= adev->mode_info.num_hpd) {
3219                 DRM_DEBUG("invalid hdp %d\n", hpd);
3220                 return 0;
3221         }
3222
3223         switch (state) {
3224         case AMDGPU_IRQ_STATE_DISABLE:
3225                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3226                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3227                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3228                 break;
3229         case AMDGPU_IRQ_STATE_ENABLE:
3230                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3231                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3232                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3233                 break;
3234         default:
3235                 break;
3236         }
3237
3238         return 0;
3239 }
3240
3241 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3242                                         struct amdgpu_irq_src *source,
3243                                         unsigned type,
3244                                         enum amdgpu_interrupt_state state)
3245 {
3246         switch (type) {
3247         case AMDGPU_CRTC_IRQ_VBLANK1:
3248                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3249                 break;
3250         case AMDGPU_CRTC_IRQ_VBLANK2:
3251                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3252                 break;
3253         case AMDGPU_CRTC_IRQ_VBLANK3:
3254                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3255                 break;
3256         case AMDGPU_CRTC_IRQ_VBLANK4:
3257                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3258                 break;
3259         case AMDGPU_CRTC_IRQ_VBLANK5:
3260                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3261                 break;
3262         case AMDGPU_CRTC_IRQ_VBLANK6:
3263                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3264                 break;
3265         case AMDGPU_CRTC_IRQ_VLINE1:
3266                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3267                 break;
3268         case AMDGPU_CRTC_IRQ_VLINE2:
3269                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3270                 break;
3271         case AMDGPU_CRTC_IRQ_VLINE3:
3272                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3273                 break;
3274         case AMDGPU_CRTC_IRQ_VLINE4:
3275                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3276                 break;
3277         case AMDGPU_CRTC_IRQ_VLINE5:
3278                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3279                 break;
3280          case AMDGPU_CRTC_IRQ_VLINE6:
3281                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3282                 break;
3283         default:
3284                 break;
3285         }
3286         return 0;
3287 }
3288
3289 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3290                                             struct amdgpu_irq_src *src,
3291                                             unsigned type,
3292                                             enum amdgpu_interrupt_state state)
3293 {
3294         u32 reg;
3295
3296         if (type >= adev->mode_info.num_crtc) {
3297                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3298                 return -EINVAL;
3299         }
3300
3301         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3302         if (state == AMDGPU_IRQ_STATE_DISABLE)
3303                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3304                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3305         else
3306                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3307                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3308
3309         return 0;
3310 }
3311
3312 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3313                                   struct amdgpu_irq_src *source,
3314                                   struct amdgpu_iv_entry *entry)
3315 {
3316         unsigned long flags;
3317         unsigned crtc_id;
3318         struct amdgpu_crtc *amdgpu_crtc;
3319         struct amdgpu_flip_work *works;
3320
3321         crtc_id = (entry->src_id - 8) >> 1;
3322         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3323
3324         if (crtc_id >= adev->mode_info.num_crtc) {
3325                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3326                 return -EINVAL;
3327         }
3328
3329         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3330             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3331                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3332                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3333
3334         /* IRQ could occur when in initial stage */
3335         if(amdgpu_crtc == NULL)
3336                 return 0;
3337
3338         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3339         works = amdgpu_crtc->pflip_works;
3340         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3341                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3342                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3343                                                  amdgpu_crtc->pflip_status,
3344                                                  AMDGPU_FLIP_SUBMITTED);
3345                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3346                 return 0;
3347         }
3348
3349         /* page flip completed. clean up */
3350         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3351         amdgpu_crtc->pflip_works = NULL;
3352
3353         /* wakeup usersapce */
3354         if(works->event)
3355                 drm_send_vblank_event(adev->ddev, crtc_id, works->event);
3356
3357         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3358
3359         drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
3360         amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id);
3361         queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
3362
3363         return 0;
3364 }
3365
3366 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3367                                   int hpd)
3368 {
3369         u32 tmp;
3370
3371         if (hpd >= adev->mode_info.num_hpd) {
3372                 DRM_DEBUG("invalid hdp %d\n", hpd);
3373                 return;
3374         }
3375
3376         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3377         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3378         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3379 }
3380
3381 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3382                                           int crtc)
3383 {
3384         u32 tmp;
3385
3386         if (crtc >= adev->mode_info.num_crtc) {
3387                 DRM_DEBUG("invalid crtc %d\n", crtc);
3388                 return;
3389         }
3390
3391         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3392         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3393         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3394 }
3395
3396 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3397                                          int crtc)
3398 {
3399         u32 tmp;
3400
3401         if (crtc >= adev->mode_info.num_crtc) {
3402                 DRM_DEBUG("invalid crtc %d\n", crtc);
3403                 return;
3404         }
3405
3406         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3407         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3408         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3409 }
3410
3411 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3412                                 struct amdgpu_irq_src *source,
3413                                 struct amdgpu_iv_entry *entry)
3414 {
3415         unsigned crtc = entry->src_id - 1;
3416         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3417         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3418
3419         switch (entry->src_data) {
3420         case 0: /* vblank */
3421                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3422                         dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3423                 else
3424                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3425
3426                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3427                         drm_handle_vblank(adev->ddev, crtc);
3428                 }
3429                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3430
3431                 break;
3432         case 1: /* vline */
3433                 if (disp_int & interrupt_status_offsets[crtc].vline)
3434                         dce_v11_0_crtc_vline_int_ack(adev, crtc);
3435                 else
3436                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3437
3438                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3439
3440                 break;
3441         default:
3442                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3443                 break;
3444         }
3445
3446         return 0;
3447 }
3448
3449 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3450                              struct amdgpu_irq_src *source,
3451                              struct amdgpu_iv_entry *entry)
3452 {
3453         uint32_t disp_int, mask;
3454         unsigned hpd;
3455
3456         if (entry->src_data >= adev->mode_info.num_hpd) {
3457                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3458                 return 0;
3459         }
3460
3461         hpd = entry->src_data;
3462         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3463         mask = interrupt_status_offsets[hpd].hpd;
3464
3465         if (disp_int & mask) {
3466                 dce_v11_0_hpd_int_ack(adev, hpd);
3467                 schedule_work(&adev->hotplug_work);
3468                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3469         }
3470
3471         return 0;
3472 }
3473
3474 static int dce_v11_0_set_clockgating_state(void *handle,
3475                                           enum amd_clockgating_state state)
3476 {
3477         return 0;
3478 }
3479
3480 static int dce_v11_0_set_powergating_state(void *handle,
3481                                           enum amd_powergating_state state)
3482 {
3483         return 0;
3484 }
3485
3486 const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3487         .early_init = dce_v11_0_early_init,
3488         .late_init = NULL,
3489         .sw_init = dce_v11_0_sw_init,
3490         .sw_fini = dce_v11_0_sw_fini,
3491         .hw_init = dce_v11_0_hw_init,
3492         .hw_fini = dce_v11_0_hw_fini,
3493         .suspend = dce_v11_0_suspend,
3494         .resume = dce_v11_0_resume,
3495         .is_idle = dce_v11_0_is_idle,
3496         .wait_for_idle = dce_v11_0_wait_for_idle,
3497         .soft_reset = dce_v11_0_soft_reset,
3498         .print_status = dce_v11_0_print_status,
3499         .set_clockgating_state = dce_v11_0_set_clockgating_state,
3500         .set_powergating_state = dce_v11_0_set_powergating_state,
3501 };
3502
3503 static void
3504 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3505                           struct drm_display_mode *mode,
3506                           struct drm_display_mode *adjusted_mode)
3507 {
3508         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3509
3510         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3511
3512         /* need to call this here rather than in prepare() since we need some crtc info */
3513         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3514
3515         /* set scaler clears this on some chips */
3516         dce_v11_0_set_interleave(encoder->crtc, mode);
3517
3518         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3519                 dce_v11_0_afmt_enable(encoder, true);
3520                 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3521         }
3522 }
3523
3524 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3525 {
3526         struct amdgpu_device *adev = encoder->dev->dev_private;
3527         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3528         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3529
3530         if ((amdgpu_encoder->active_device &
3531              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3532             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3533              ENCODER_OBJECT_ID_NONE)) {
3534                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3535                 if (dig) {
3536                         dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3537                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3538                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3539                 }
3540         }
3541
3542         amdgpu_atombios_scratch_regs_lock(adev, true);
3543
3544         if (connector) {
3545                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3546
3547                 /* select the clock/data port if it uses a router */
3548                 if (amdgpu_connector->router.cd_valid)
3549                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3550
3551                 /* turn eDP panel on for mode set */
3552                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3553                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3554                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3555         }
3556
3557         /* this is needed for the pll/ss setup to work correctly in some cases */
3558         amdgpu_atombios_encoder_set_crtc_source(encoder);
3559         /* set up the FMT blocks */
3560         dce_v11_0_program_fmt(encoder);
3561 }
3562
3563 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3564 {
3565         struct drm_device *dev = encoder->dev;
3566         struct amdgpu_device *adev = dev->dev_private;
3567
3568         /* need to call this here as we need the crtc set up */
3569         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3570         amdgpu_atombios_scratch_regs_lock(adev, false);
3571 }
3572
3573 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3574 {
3575         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3576         struct amdgpu_encoder_atom_dig *dig;
3577
3578         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3579
3580         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3581                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3582                         dce_v11_0_afmt_enable(encoder, false);
3583                 dig = amdgpu_encoder->enc_priv;
3584                 dig->dig_encoder = -1;
3585         }
3586         amdgpu_encoder->active_device = 0;
3587 }
3588
3589 /* these are handled by the primary encoders */
3590 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3591 {
3592
3593 }
3594
3595 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3596 {
3597
3598 }
3599
3600 static void
3601 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3602                       struct drm_display_mode *mode,
3603                       struct drm_display_mode *adjusted_mode)
3604 {
3605
3606 }
3607
3608 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3609 {
3610
3611 }
3612
3613 static void
3614 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3615 {
3616
3617 }
3618
3619 static bool dce_v11_0_ext_mode_fixup(struct drm_encoder *encoder,
3620                                     const struct drm_display_mode *mode,
3621                                     struct drm_display_mode *adjusted_mode)
3622 {
3623         return true;
3624 }
3625
3626 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3627         .dpms = dce_v11_0_ext_dpms,
3628         .mode_fixup = dce_v11_0_ext_mode_fixup,
3629         .prepare = dce_v11_0_ext_prepare,
3630         .mode_set = dce_v11_0_ext_mode_set,
3631         .commit = dce_v11_0_ext_commit,
3632         .disable = dce_v11_0_ext_disable,
3633         /* no detect for TMDS/LVDS yet */
3634 };
3635
3636 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3637         .dpms = amdgpu_atombios_encoder_dpms,
3638         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3639         .prepare = dce_v11_0_encoder_prepare,
3640         .mode_set = dce_v11_0_encoder_mode_set,
3641         .commit = dce_v11_0_encoder_commit,
3642         .disable = dce_v11_0_encoder_disable,
3643         .detect = amdgpu_atombios_encoder_dig_detect,
3644 };
3645
3646 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3647         .dpms = amdgpu_atombios_encoder_dpms,
3648         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3649         .prepare = dce_v11_0_encoder_prepare,
3650         .mode_set = dce_v11_0_encoder_mode_set,
3651         .commit = dce_v11_0_encoder_commit,
3652         .detect = amdgpu_atombios_encoder_dac_detect,
3653 };
3654
3655 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3656 {
3657         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3658         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3659                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3660         kfree(amdgpu_encoder->enc_priv);
3661         drm_encoder_cleanup(encoder);
3662         kfree(amdgpu_encoder);
3663 }
3664
3665 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3666         .destroy = dce_v11_0_encoder_destroy,
3667 };
3668
3669 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3670                                  uint32_t encoder_enum,
3671                                  uint32_t supported_device,
3672                                  u16 caps)
3673 {
3674         struct drm_device *dev = adev->ddev;
3675         struct drm_encoder *encoder;
3676         struct amdgpu_encoder *amdgpu_encoder;
3677
3678         /* see if we already added it */
3679         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3680                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3681                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3682                         amdgpu_encoder->devices |= supported_device;
3683                         return;
3684                 }
3685
3686         }
3687
3688         /* add a new one */
3689         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3690         if (!amdgpu_encoder)
3691                 return;
3692
3693         encoder = &amdgpu_encoder->base;
3694         switch (adev->mode_info.num_crtc) {
3695         case 1:
3696                 encoder->possible_crtcs = 0x1;
3697                 break;
3698         case 2:
3699         default:
3700                 encoder->possible_crtcs = 0x3;
3701                 break;
3702         case 4:
3703                 encoder->possible_crtcs = 0xf;
3704                 break;
3705         case 6:
3706                 encoder->possible_crtcs = 0x3f;
3707                 break;
3708         }
3709
3710         amdgpu_encoder->enc_priv = NULL;
3711
3712         amdgpu_encoder->encoder_enum = encoder_enum;
3713         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3714         amdgpu_encoder->devices = supported_device;
3715         amdgpu_encoder->rmx_type = RMX_OFF;
3716         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3717         amdgpu_encoder->is_ext_encoder = false;
3718         amdgpu_encoder->caps = caps;
3719
3720         switch (amdgpu_encoder->encoder_id) {
3721         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3722         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3723                 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3724                                  DRM_MODE_ENCODER_DAC);
3725                 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3726                 break;
3727         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3728         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3729         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3730         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3731         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3732                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3733                         amdgpu_encoder->rmx_type = RMX_FULL;
3734                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3735                                          DRM_MODE_ENCODER_LVDS);
3736                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3737                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3738                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3739                                          DRM_MODE_ENCODER_DAC);
3740                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3741                 } else {
3742                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3743                                          DRM_MODE_ENCODER_TMDS);
3744                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3745                 }
3746                 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3747                 break;
3748         case ENCODER_OBJECT_ID_SI170B:
3749         case ENCODER_OBJECT_ID_CH7303:
3750         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3751         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3752         case ENCODER_OBJECT_ID_TITFP513:
3753         case ENCODER_OBJECT_ID_VT1623:
3754         case ENCODER_OBJECT_ID_HDMI_SI1930:
3755         case ENCODER_OBJECT_ID_TRAVIS:
3756         case ENCODER_OBJECT_ID_NUTMEG:
3757                 /* these are handled by the primary encoders */
3758                 amdgpu_encoder->is_ext_encoder = true;
3759                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3760                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3761                                          DRM_MODE_ENCODER_LVDS);
3762                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3763                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3764                                          DRM_MODE_ENCODER_DAC);
3765                 else
3766                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3767                                          DRM_MODE_ENCODER_TMDS);
3768                 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3769                 break;
3770         }
3771 }
3772
3773 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3774         .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3775         .bandwidth_update = &dce_v11_0_bandwidth_update,
3776         .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3777         .vblank_wait = &dce_v11_0_vblank_wait,
3778         .is_display_hung = &dce_v11_0_is_display_hung,
3779         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3780         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3781         .hpd_sense = &dce_v11_0_hpd_sense,
3782         .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3783         .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3784         .page_flip = &dce_v11_0_page_flip,
3785         .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3786         .add_encoder = &dce_v11_0_encoder_add,
3787         .add_connector = &amdgpu_connector_add,
3788         .stop_mc_access = &dce_v11_0_stop_mc_access,
3789         .resume_mc_access = &dce_v11_0_resume_mc_access,
3790 };
3791
3792 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3793 {
3794         if (adev->mode_info.funcs == NULL)
3795                 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3796 }
3797
3798 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3799         .set = dce_v11_0_set_crtc_irq_state,
3800         .process = dce_v11_0_crtc_irq,
3801 };
3802
3803 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3804         .set = dce_v11_0_set_pageflip_irq_state,
3805         .process = dce_v11_0_pageflip_irq,
3806 };
3807
3808 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3809         .set = dce_v11_0_set_hpd_irq_state,
3810         .process = dce_v11_0_hpd_irq,
3811 };
3812
3813 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3814 {
3815         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3816         adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3817
3818         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3819         adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3820
3821         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3822         adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3823 }