2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
34 #include "dce_v11_0.h"
36 #include "dce/dce_11_0_d.h"
37 #include "dce/dce_11_0_sh_mask.h"
38 #include "dce/dce_11_0_enum.h"
39 #include "oss/oss_3_0_d.h"
40 #include "oss/oss_3_0_sh_mask.h"
41 #include "gmc/gmc_8_1_d.h"
42 #include "gmc/gmc_8_1_sh_mask.h"
44 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
45 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
47 static const u32 crtc_offsets[] =
49 CRTC0_REGISTER_OFFSET,
50 CRTC1_REGISTER_OFFSET,
51 CRTC2_REGISTER_OFFSET,
52 CRTC3_REGISTER_OFFSET,
53 CRTC4_REGISTER_OFFSET,
54 CRTC5_REGISTER_OFFSET,
58 static const u32 hpd_offsets[] =
68 static const uint32_t dig_offsets[] = {
86 } interrupt_status_offsets[] = { {
87 .reg = mmDISP_INTERRUPT_STATUS,
88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
89 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
90 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
92 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
94 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
95 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
99 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
104 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
109 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
114 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
118 static const u32 cz_golden_settings_a11[] =
120 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
121 mmFBC_MISC, 0x1f311fff, 0x14300000,
124 static const u32 cz_mgcg_cgcg_init[] =
126 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
127 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
130 static const u32 stoney_golden_settings_a11[] =
132 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
133 mmFBC_MISC, 0x1f311fff, 0x14302000,
136 static const u32 polaris11_golden_settings_a11[] =
138 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
139 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
140 mmFBC_DEBUG1, 0xffffffff, 0x00000008,
141 mmFBC_MISC, 0x9f313fff, 0x14302008,
142 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
145 static const u32 polaris10_golden_settings_a11[] =
147 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
148 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
149 mmFBC_MISC, 0x9f313fff, 0x14302008,
150 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
153 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
155 switch (adev->asic_type) {
157 amdgpu_program_register_sequence(adev,
159 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
160 amdgpu_program_register_sequence(adev,
161 cz_golden_settings_a11,
162 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
165 amdgpu_program_register_sequence(adev,
166 stoney_golden_settings_a11,
167 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
171 amdgpu_program_register_sequence(adev,
172 polaris11_golden_settings_a11,
173 (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
176 amdgpu_program_register_sequence(adev,
177 polaris10_golden_settings_a11,
178 (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
185 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
186 u32 block_offset, u32 reg)
191 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
192 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
193 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
194 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
199 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
200 u32 block_offset, u32 reg, u32 v)
204 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
205 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
206 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
207 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
210 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
212 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
213 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
219 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
223 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
224 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
233 * dce_v11_0_vblank_wait - vblank wait asic callback.
235 * @adev: amdgpu_device pointer
236 * @crtc: crtc to wait for vblank on
238 * Wait for vblank on the requested crtc (evergreen+).
240 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
244 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
247 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
250 /* depending on when we hit vblank, we may be close to active; if so,
251 * wait for another frame.
253 while (dce_v11_0_is_in_vblank(adev, crtc)) {
256 if (!dce_v11_0_is_counter_moving(adev, crtc))
261 while (!dce_v11_0_is_in_vblank(adev, crtc)) {
264 if (!dce_v11_0_is_counter_moving(adev, crtc))
270 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
272 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
275 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
278 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
282 /* Enable pflip interrupts */
283 for (i = 0; i < adev->mode_info.num_crtc; i++)
284 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
287 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
291 /* Disable pflip interrupts */
292 for (i = 0; i < adev->mode_info.num_crtc; i++)
293 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
297 * dce_v11_0_page_flip - pageflip callback.
299 * @adev: amdgpu_device pointer
300 * @crtc_id: crtc to cleanup pageflip on
301 * @crtc_base: new address of the crtc (GPU MC address)
303 * Triggers the actual pageflip by updating the primary
304 * surface base address.
306 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
307 int crtc_id, u64 crtc_base, bool async)
309 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
312 /* flip immediate for async, default is vsync */
313 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
314 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
315 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
316 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
317 /* update the scanout addresses */
318 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
319 upper_32_bits(crtc_base));
320 /* writing to the low address triggers the update */
321 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
322 lower_32_bits(crtc_base));
324 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
327 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
328 u32 *vbl, u32 *position)
330 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
333 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
334 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
340 * dce_v11_0_hpd_sense - hpd sense callback.
342 * @adev: amdgpu_device pointer
343 * @hpd: hpd (hotplug detect) pin
345 * Checks if a digital monitor is connected (evergreen+).
346 * Returns true if connected, false if not connected.
348 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
349 enum amdgpu_hpd_id hpd)
351 bool connected = false;
353 if (hpd >= adev->mode_info.num_hpd)
356 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
357 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
364 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
366 * @adev: amdgpu_device pointer
367 * @hpd: hpd (hotplug detect) pin
369 * Set the polarity of the hpd pin (evergreen+).
371 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
372 enum amdgpu_hpd_id hpd)
375 bool connected = dce_v11_0_hpd_sense(adev, hpd);
377 if (hpd >= adev->mode_info.num_hpd)
380 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
382 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
384 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
385 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
389 * dce_v11_0_hpd_init - hpd setup callback.
391 * @adev: amdgpu_device pointer
393 * Setup the hpd pins used by the card (evergreen+).
394 * Enable the pin, set the polarity, and enable the hpd interrupts.
396 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
398 struct drm_device *dev = adev->ddev;
399 struct drm_connector *connector;
402 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
403 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
405 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
408 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
409 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
410 /* don't try to enable hpd on eDP or LVDS avoid breaking the
411 * aux dp channel on imac and help (but not completely fix)
412 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
413 * also avoid interrupt storms during dpms.
415 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
416 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
417 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
421 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
422 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
423 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
425 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
426 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
427 DC_HPD_CONNECT_INT_DELAY,
428 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
429 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
430 DC_HPD_DISCONNECT_INT_DELAY,
431 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
432 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
434 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
435 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
440 * dce_v11_0_hpd_fini - hpd tear down callback.
442 * @adev: amdgpu_device pointer
444 * Tear down the hpd pins used by the card (evergreen+).
445 * Disable the hpd interrupts.
447 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
449 struct drm_device *dev = adev->ddev;
450 struct drm_connector *connector;
453 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
454 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
456 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
459 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
460 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
461 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
463 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
467 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
469 return mmDC_GPIO_HPD_A;
472 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
478 for (i = 0; i < adev->mode_info.num_crtc; i++) {
479 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
480 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
481 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
482 crtc_hung |= (1 << i);
486 for (j = 0; j < 10; j++) {
487 for (i = 0; i < adev->mode_info.num_crtc; i++) {
488 if (crtc_hung & (1 << i)) {
489 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
490 if (tmp != crtc_status[i])
491 crtc_hung &= ~(1 << i);
502 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
503 struct amdgpu_mode_mc_save *save)
505 u32 crtc_enabled, tmp;
508 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
509 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
511 /* disable VGA render */
512 tmp = RREG32(mmVGA_RENDER_CONTROL);
513 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
514 WREG32(mmVGA_RENDER_CONTROL, tmp);
516 /* blank the display controllers */
517 for (i = 0; i < adev->mode_info.num_crtc; i++) {
518 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
519 CRTC_CONTROL, CRTC_MASTER_EN);
522 save->crtc_enabled[i] = true;
523 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
524 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
525 /*it is correct only for RGB ; black is 0*/
526 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
527 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
528 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
531 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
532 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
533 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
534 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
535 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
536 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
537 save->crtc_enabled[i] = false;
541 save->crtc_enabled[i] = false;
546 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
547 struct amdgpu_mode_mc_save *save)
552 /* update crtc base addresses */
553 for (i = 0; i < adev->mode_info.num_crtc; i++) {
554 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
555 upper_32_bits(adev->mc.vram_start));
556 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
557 (u32)adev->mc.vram_start);
559 if (save->crtc_enabled[i]) {
560 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
561 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
562 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
566 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
567 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
569 /* Unlock vga access */
570 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
572 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
575 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
580 /* Lockout access through VGA aperture*/
581 tmp = RREG32(mmVGA_HDP_CONTROL);
583 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
585 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
586 WREG32(mmVGA_HDP_CONTROL, tmp);
588 /* disable VGA render */
589 tmp = RREG32(mmVGA_RENDER_CONTROL);
591 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
593 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
594 WREG32(mmVGA_RENDER_CONTROL, tmp);
597 static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
601 switch (adev->asic_type) {
621 void dce_v11_0_disable_dce(struct amdgpu_device *adev)
623 /*Disable VGA render and enabled crtc, if has DCE engine*/
624 if (amdgpu_atombios_has_dce_engine_info(adev)) {
628 dce_v11_0_set_vga_render_state(adev, false);
631 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
632 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
633 CRTC_CONTROL, CRTC_MASTER_EN);
635 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
636 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
637 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
638 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
639 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
645 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
647 struct drm_device *dev = encoder->dev;
648 struct amdgpu_device *adev = dev->dev_private;
649 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
650 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
651 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
654 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
657 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
658 bpc = amdgpu_connector_get_monitor_bpc(connector);
659 dither = amdgpu_connector->dither;
662 /* LVDS/eDP FMT is set up by atom */
663 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
666 /* not needed for analog */
667 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
668 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
676 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
677 /* XXX sort out optimal dither settings */
678 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
679 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
680 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
681 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
683 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
684 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
688 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
689 /* XXX sort out optimal dither settings */
690 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
691 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
692 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
693 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
694 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
696 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
697 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
701 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
702 /* XXX sort out optimal dither settings */
703 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
704 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
705 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
706 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
707 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
709 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
710 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
718 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
722 /* display watermark setup */
724 * dce_v11_0_line_buffer_adjust - Set up the line buffer
726 * @adev: amdgpu_device pointer
727 * @amdgpu_crtc: the selected display controller
728 * @mode: the current display mode on the selected display
731 * Setup up the line buffer allocation for
732 * the selected display controller (CIK).
733 * Returns the line buffer size in pixels.
735 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
736 struct amdgpu_crtc *amdgpu_crtc,
737 struct drm_display_mode *mode)
739 u32 tmp, buffer_alloc, i, mem_cfg;
740 u32 pipe_offset = amdgpu_crtc->crtc_id;
743 * There are 6 line buffers, one for each display controllers.
744 * There are 3 partitions per LB. Select the number of partitions
745 * to enable based on the display width. For display widths larger
746 * than 4096, you need use to use 2 display controllers and combine
747 * them using the stereo blender.
749 if (amdgpu_crtc->base.enabled && mode) {
750 if (mode->crtc_hdisplay < 1920) {
753 } else if (mode->crtc_hdisplay < 2560) {
756 } else if (mode->crtc_hdisplay < 4096) {
758 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
760 DRM_DEBUG_KMS("Mode too big for LB!\n");
762 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
769 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
770 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
771 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
773 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
774 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
775 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
777 for (i = 0; i < adev->usec_timeout; i++) {
778 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
779 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
784 if (amdgpu_crtc->base.enabled && mode) {
796 /* controller not enabled, so no lb used */
801 * cik_get_number_of_dram_channels - get the number of dram channels
803 * @adev: amdgpu_device pointer
805 * Look up the number of video ram channels (CIK).
806 * Used for display watermark bandwidth calculations
807 * Returns the number of dram channels
809 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
811 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
813 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
836 struct dce10_wm_params {
837 u32 dram_channels; /* number of dram channels */
838 u32 yclk; /* bandwidth per dram data pin in kHz */
839 u32 sclk; /* engine clock in kHz */
840 u32 disp_clk; /* display clock in kHz */
841 u32 src_width; /* viewport width */
842 u32 active_time; /* active display time in ns */
843 u32 blank_time; /* blank time in ns */
844 bool interlaced; /* mode is interlaced */
845 fixed20_12 vsc; /* vertical scale ratio */
846 u32 num_heads; /* number of active crtcs */
847 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
848 u32 lb_size; /* line buffer allocated to pipe */
849 u32 vtaps; /* vertical scaler taps */
853 * dce_v11_0_dram_bandwidth - get the dram bandwidth
855 * @wm: watermark calculation data
857 * Calculate the raw dram bandwidth (CIK).
858 * Used for display watermark bandwidth calculations
859 * Returns the dram bandwidth in MBytes/s
861 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
863 /* Calculate raw DRAM Bandwidth */
864 fixed20_12 dram_efficiency; /* 0.7 */
865 fixed20_12 yclk, dram_channels, bandwidth;
868 a.full = dfixed_const(1000);
869 yclk.full = dfixed_const(wm->yclk);
870 yclk.full = dfixed_div(yclk, a);
871 dram_channels.full = dfixed_const(wm->dram_channels * 4);
872 a.full = dfixed_const(10);
873 dram_efficiency.full = dfixed_const(7);
874 dram_efficiency.full = dfixed_div(dram_efficiency, a);
875 bandwidth.full = dfixed_mul(dram_channels, yclk);
876 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
878 return dfixed_trunc(bandwidth);
882 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
884 * @wm: watermark calculation data
886 * Calculate the dram bandwidth used for display (CIK).
887 * Used for display watermark bandwidth calculations
888 * Returns the dram bandwidth for display in MBytes/s
890 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
892 /* Calculate DRAM Bandwidth and the part allocated to display. */
893 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
894 fixed20_12 yclk, dram_channels, bandwidth;
897 a.full = dfixed_const(1000);
898 yclk.full = dfixed_const(wm->yclk);
899 yclk.full = dfixed_div(yclk, a);
900 dram_channels.full = dfixed_const(wm->dram_channels * 4);
901 a.full = dfixed_const(10);
902 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
903 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
904 bandwidth.full = dfixed_mul(dram_channels, yclk);
905 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
907 return dfixed_trunc(bandwidth);
911 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
913 * @wm: watermark calculation data
915 * Calculate the data return bandwidth used for display (CIK).
916 * Used for display watermark bandwidth calculations
917 * Returns the data return bandwidth in MBytes/s
919 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
921 /* Calculate the display Data return Bandwidth */
922 fixed20_12 return_efficiency; /* 0.8 */
923 fixed20_12 sclk, bandwidth;
926 a.full = dfixed_const(1000);
927 sclk.full = dfixed_const(wm->sclk);
928 sclk.full = dfixed_div(sclk, a);
929 a.full = dfixed_const(10);
930 return_efficiency.full = dfixed_const(8);
931 return_efficiency.full = dfixed_div(return_efficiency, a);
932 a.full = dfixed_const(32);
933 bandwidth.full = dfixed_mul(a, sclk);
934 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
936 return dfixed_trunc(bandwidth);
940 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
942 * @wm: watermark calculation data
944 * Calculate the dmif bandwidth used for display (CIK).
945 * Used for display watermark bandwidth calculations
946 * Returns the dmif bandwidth in MBytes/s
948 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
950 /* Calculate the DMIF Request Bandwidth */
951 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
952 fixed20_12 disp_clk, bandwidth;
955 a.full = dfixed_const(1000);
956 disp_clk.full = dfixed_const(wm->disp_clk);
957 disp_clk.full = dfixed_div(disp_clk, a);
958 a.full = dfixed_const(32);
959 b.full = dfixed_mul(a, disp_clk);
961 a.full = dfixed_const(10);
962 disp_clk_request_efficiency.full = dfixed_const(8);
963 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
965 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
967 return dfixed_trunc(bandwidth);
971 * dce_v11_0_available_bandwidth - get the min available bandwidth
973 * @wm: watermark calculation data
975 * Calculate the min available bandwidth used for display (CIK).
976 * Used for display watermark bandwidth calculations
977 * Returns the min available bandwidth in MBytes/s
979 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
981 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
982 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
983 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
984 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
986 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
990 * dce_v11_0_average_bandwidth - get the average available bandwidth
992 * @wm: watermark calculation data
994 * Calculate the average available bandwidth used for display (CIK).
995 * Used for display watermark bandwidth calculations
996 * Returns the average available bandwidth in MBytes/s
998 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
1000 /* Calculate the display mode Average Bandwidth
1001 * DisplayMode should contain the source and destination dimensions,
1005 fixed20_12 line_time;
1006 fixed20_12 src_width;
1007 fixed20_12 bandwidth;
1010 a.full = dfixed_const(1000);
1011 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1012 line_time.full = dfixed_div(line_time, a);
1013 bpp.full = dfixed_const(wm->bytes_per_pixel);
1014 src_width.full = dfixed_const(wm->src_width);
1015 bandwidth.full = dfixed_mul(src_width, bpp);
1016 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1017 bandwidth.full = dfixed_div(bandwidth, line_time);
1019 return dfixed_trunc(bandwidth);
1023 * dce_v11_0_latency_watermark - get the latency watermark
1025 * @wm: watermark calculation data
1027 * Calculate the latency watermark (CIK).
1028 * Used for display watermark bandwidth calculations
1029 * Returns the latency watermark in ns
1031 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1033 /* First calculate the latency in ns */
1034 u32 mc_latency = 2000; /* 2000 ns. */
1035 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1036 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1037 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1038 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1039 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1040 (wm->num_heads * cursor_line_pair_return_time);
1041 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1042 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1043 u32 tmp, dmif_size = 12288;
1046 if (wm->num_heads == 0)
1049 a.full = dfixed_const(2);
1050 b.full = dfixed_const(1);
1051 if ((wm->vsc.full > a.full) ||
1052 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1054 ((wm->vsc.full >= a.full) && wm->interlaced))
1055 max_src_lines_per_dst_line = 4;
1057 max_src_lines_per_dst_line = 2;
1059 a.full = dfixed_const(available_bandwidth);
1060 b.full = dfixed_const(wm->num_heads);
1061 a.full = dfixed_div(a, b);
1062 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
1063 tmp = min(dfixed_trunc(a), tmp);
1065 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
1067 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1068 b.full = dfixed_const(1000);
1069 c.full = dfixed_const(lb_fill_bw);
1070 b.full = dfixed_div(c, b);
1071 a.full = dfixed_div(a, b);
1072 line_fill_time = dfixed_trunc(a);
1074 if (line_fill_time < wm->active_time)
1077 return latency + (line_fill_time - wm->active_time);
1082 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1083 * average and available dram bandwidth
1085 * @wm: watermark calculation data
1087 * Check if the display average bandwidth fits in the display
1088 * dram bandwidth (CIK).
1089 * Used for display watermark bandwidth calculations
1090 * Returns true if the display fits, false if not.
1092 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1094 if (dce_v11_0_average_bandwidth(wm) <=
1095 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1102 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1103 * average and available bandwidth
1105 * @wm: watermark calculation data
1107 * Check if the display average bandwidth fits in the display
1108 * available bandwidth (CIK).
1109 * Used for display watermark bandwidth calculations
1110 * Returns true if the display fits, false if not.
1112 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1114 if (dce_v11_0_average_bandwidth(wm) <=
1115 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1122 * dce_v11_0_check_latency_hiding - check latency hiding
1124 * @wm: watermark calculation data
1126 * Check latency hiding (CIK).
1127 * Used for display watermark bandwidth calculations
1128 * Returns true if the display fits, false if not.
1130 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1132 u32 lb_partitions = wm->lb_size / wm->src_width;
1133 u32 line_time = wm->active_time + wm->blank_time;
1134 u32 latency_tolerant_lines;
1138 a.full = dfixed_const(1);
1139 if (wm->vsc.full > a.full)
1140 latency_tolerant_lines = 1;
1142 if (lb_partitions <= (wm->vtaps + 1))
1143 latency_tolerant_lines = 1;
1145 latency_tolerant_lines = 2;
1148 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1150 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1157 * dce_v11_0_program_watermarks - program display watermarks
1159 * @adev: amdgpu_device pointer
1160 * @amdgpu_crtc: the selected display controller
1161 * @lb_size: line buffer size
1162 * @num_heads: number of display controllers in use
1164 * Calculate and program the display watermarks for the
1165 * selected display controller (CIK).
1167 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1168 struct amdgpu_crtc *amdgpu_crtc,
1169 u32 lb_size, u32 num_heads)
1171 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1172 struct dce10_wm_params wm_low, wm_high;
1175 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1176 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1178 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1179 active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
1180 line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
1182 /* watermark for high clocks */
1183 if (adev->pm.dpm_enabled) {
1185 amdgpu_dpm_get_mclk(adev, false) * 10;
1187 amdgpu_dpm_get_sclk(adev, false) * 10;
1189 wm_high.yclk = adev->pm.current_mclk * 10;
1190 wm_high.sclk = adev->pm.current_sclk * 10;
1193 wm_high.disp_clk = mode->clock;
1194 wm_high.src_width = mode->crtc_hdisplay;
1195 wm_high.active_time = active_time;
1196 wm_high.blank_time = line_time - wm_high.active_time;
1197 wm_high.interlaced = false;
1198 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1199 wm_high.interlaced = true;
1200 wm_high.vsc = amdgpu_crtc->vsc;
1202 if (amdgpu_crtc->rmx_type != RMX_OFF)
1204 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1205 wm_high.lb_size = lb_size;
1206 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1207 wm_high.num_heads = num_heads;
1209 /* set for high clocks */
1210 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1212 /* possibly force display priority to high */
1213 /* should really do this at mode validation time... */
1214 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1215 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1216 !dce_v11_0_check_latency_hiding(&wm_high) ||
1217 (adev->mode_info.disp_priority == 2)) {
1218 DRM_DEBUG_KMS("force priority to high\n");
1221 /* watermark for low clocks */
1222 if (adev->pm.dpm_enabled) {
1224 amdgpu_dpm_get_mclk(adev, true) * 10;
1226 amdgpu_dpm_get_sclk(adev, true) * 10;
1228 wm_low.yclk = adev->pm.current_mclk * 10;
1229 wm_low.sclk = adev->pm.current_sclk * 10;
1232 wm_low.disp_clk = mode->clock;
1233 wm_low.src_width = mode->crtc_hdisplay;
1234 wm_low.active_time = active_time;
1235 wm_low.blank_time = line_time - wm_low.active_time;
1236 wm_low.interlaced = false;
1237 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1238 wm_low.interlaced = true;
1239 wm_low.vsc = amdgpu_crtc->vsc;
1241 if (amdgpu_crtc->rmx_type != RMX_OFF)
1243 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1244 wm_low.lb_size = lb_size;
1245 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1246 wm_low.num_heads = num_heads;
1248 /* set for low clocks */
1249 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1251 /* possibly force display priority to high */
1252 /* should really do this at mode validation time... */
1253 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1254 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1255 !dce_v11_0_check_latency_hiding(&wm_low) ||
1256 (adev->mode_info.disp_priority == 2)) {
1257 DRM_DEBUG_KMS("force priority to high\n");
1259 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1263 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1264 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1265 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1266 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1267 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1268 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1269 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1271 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1272 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1273 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1274 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1275 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1276 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1277 /* restore original selection */
1278 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1280 /* save values for DPM */
1281 amdgpu_crtc->line_time = line_time;
1282 amdgpu_crtc->wm_high = latency_watermark_a;
1283 amdgpu_crtc->wm_low = latency_watermark_b;
1284 /* Save number of lines the linebuffer leads before the scanout */
1285 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1289 * dce_v11_0_bandwidth_update - program display watermarks
1291 * @adev: amdgpu_device pointer
1293 * Calculate and program the display watermarks and line
1294 * buffer allocation (CIK).
1296 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1298 struct drm_display_mode *mode = NULL;
1299 u32 num_heads = 0, lb_size;
1302 amdgpu_update_display_priority(adev);
1304 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1305 if (adev->mode_info.crtcs[i]->base.enabled)
1308 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1309 mode = &adev->mode_info.crtcs[i]->base.mode;
1310 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1311 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1312 lb_size, num_heads);
1316 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1321 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1322 offset = adev->mode_info.audio.pin[i].offset;
1323 tmp = RREG32_AUDIO_ENDPT(offset,
1324 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1326 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1327 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1328 adev->mode_info.audio.pin[i].connected = false;
1330 adev->mode_info.audio.pin[i].connected = true;
1334 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1338 dce_v11_0_audio_get_connected_pins(adev);
1340 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1341 if (adev->mode_info.audio.pin[i].connected)
1342 return &adev->mode_info.audio.pin[i];
1344 DRM_ERROR("No connected audio pins found!\n");
1348 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1350 struct amdgpu_device *adev = encoder->dev->dev_private;
1351 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1352 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1355 if (!dig || !dig->afmt || !dig->afmt->pin)
1358 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1359 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1360 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1363 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1364 struct drm_display_mode *mode)
1366 struct amdgpu_device *adev = encoder->dev->dev_private;
1367 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1368 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1369 struct drm_connector *connector;
1370 struct amdgpu_connector *amdgpu_connector = NULL;
1374 if (!dig || !dig->afmt || !dig->afmt->pin)
1377 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1378 if (connector->encoder == encoder) {
1379 amdgpu_connector = to_amdgpu_connector(connector);
1384 if (!amdgpu_connector) {
1385 DRM_ERROR("Couldn't find encoder's connector\n");
1389 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1391 if (connector->latency_present[interlace]) {
1392 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1393 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1394 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1395 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1397 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1399 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1402 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1403 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1406 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1408 struct amdgpu_device *adev = encoder->dev->dev_private;
1409 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1410 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1411 struct drm_connector *connector;
1412 struct amdgpu_connector *amdgpu_connector = NULL;
1417 if (!dig || !dig->afmt || !dig->afmt->pin)
1420 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1421 if (connector->encoder == encoder) {
1422 amdgpu_connector = to_amdgpu_connector(connector);
1427 if (!amdgpu_connector) {
1428 DRM_ERROR("Couldn't find encoder's connector\n");
1432 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1433 if (sad_count < 0) {
1434 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1438 /* program the speaker allocation */
1439 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1440 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1441 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1444 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1445 HDMI_CONNECTION, 1);
1447 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1448 SPEAKER_ALLOCATION, sadb[0]);
1450 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1451 SPEAKER_ALLOCATION, 5); /* stereo */
1452 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1453 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1458 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1460 struct amdgpu_device *adev = encoder->dev->dev_private;
1461 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1462 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1463 struct drm_connector *connector;
1464 struct amdgpu_connector *amdgpu_connector = NULL;
1465 struct cea_sad *sads;
1468 static const u16 eld_reg_to_type[][2] = {
1469 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1470 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1471 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1472 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1473 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1474 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1475 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1476 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1477 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1478 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1479 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1480 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1483 if (!dig || !dig->afmt || !dig->afmt->pin)
1486 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1487 if (connector->encoder == encoder) {
1488 amdgpu_connector = to_amdgpu_connector(connector);
1493 if (!amdgpu_connector) {
1494 DRM_ERROR("Couldn't find encoder's connector\n");
1498 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1499 if (sad_count <= 0) {
1500 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1505 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1507 u8 stereo_freqs = 0;
1508 int max_channels = -1;
1511 for (j = 0; j < sad_count; j++) {
1512 struct cea_sad *sad = &sads[j];
1514 if (sad->format == eld_reg_to_type[i][1]) {
1515 if (sad->channels > max_channels) {
1516 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1517 MAX_CHANNELS, sad->channels);
1518 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1519 DESCRIPTOR_BYTE_2, sad->byte2);
1520 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1521 SUPPORTED_FREQUENCIES, sad->freq);
1522 max_channels = sad->channels;
1525 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1526 stereo_freqs |= sad->freq;
1532 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1533 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1534 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1540 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1541 struct amdgpu_audio_pin *pin,
1547 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1548 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1551 static const u32 pin_offsets[] =
1553 AUD0_REGISTER_OFFSET,
1554 AUD1_REGISTER_OFFSET,
1555 AUD2_REGISTER_OFFSET,
1556 AUD3_REGISTER_OFFSET,
1557 AUD4_REGISTER_OFFSET,
1558 AUD5_REGISTER_OFFSET,
1559 AUD6_REGISTER_OFFSET,
1560 AUD7_REGISTER_OFFSET,
1563 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1570 adev->mode_info.audio.enabled = true;
1572 switch (adev->asic_type) {
1575 adev->mode_info.audio.num_pins = 7;
1577 case CHIP_POLARIS10:
1578 adev->mode_info.audio.num_pins = 8;
1580 case CHIP_POLARIS11:
1581 case CHIP_POLARIS12:
1582 adev->mode_info.audio.num_pins = 6;
1588 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1589 adev->mode_info.audio.pin[i].channels = -1;
1590 adev->mode_info.audio.pin[i].rate = -1;
1591 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1592 adev->mode_info.audio.pin[i].status_bits = 0;
1593 adev->mode_info.audio.pin[i].category_code = 0;
1594 adev->mode_info.audio.pin[i].connected = false;
1595 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1596 adev->mode_info.audio.pin[i].id = i;
1597 /* disable audio. it will be set up later */
1598 /* XXX remove once we switch to ip funcs */
1599 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1605 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1612 if (!adev->mode_info.audio.enabled)
1615 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1616 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1618 adev->mode_info.audio.enabled = false;
1622 * update the N and CTS parameters for a given pixel clock rate
1624 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1626 struct drm_device *dev = encoder->dev;
1627 struct amdgpu_device *adev = dev->dev_private;
1628 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1629 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1630 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1633 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1634 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1635 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1636 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1637 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1638 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1640 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1641 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1642 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1643 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1644 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1645 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1647 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1648 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1649 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1650 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1651 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1652 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1657 * build a HDMI Video Info Frame
1659 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1660 void *buffer, size_t size)
1662 struct drm_device *dev = encoder->dev;
1663 struct amdgpu_device *adev = dev->dev_private;
1664 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1665 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1666 uint8_t *frame = buffer + 3;
1667 uint8_t *header = buffer;
1669 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1670 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1671 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1672 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1673 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1674 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1675 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1676 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1679 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1681 struct drm_device *dev = encoder->dev;
1682 struct amdgpu_device *adev = dev->dev_private;
1683 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1684 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1685 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1686 u32 dto_phase = 24 * 1000;
1687 u32 dto_modulo = clock;
1690 if (!dig || !dig->afmt)
1693 /* XXX two dtos; generally use dto0 for hdmi */
1694 /* Express [24MHz / target pixel clock] as an exact rational
1695 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1696 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1698 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1699 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1700 amdgpu_crtc->crtc_id);
1701 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1702 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1703 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1707 * update the info frames with the data from the current display mode
1709 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1710 struct drm_display_mode *mode)
1712 struct drm_device *dev = encoder->dev;
1713 struct amdgpu_device *adev = dev->dev_private;
1714 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1715 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1716 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1717 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1718 struct hdmi_avi_infoframe frame;
1723 if (!dig || !dig->afmt)
1726 /* Silent, r600_hdmi_enable will raise WARN for us */
1727 if (!dig->afmt->enabled)
1730 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1731 if (encoder->crtc) {
1732 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1733 bpc = amdgpu_crtc->bpc;
1736 /* disable audio prior to setting up hw */
1737 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1738 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1740 dce_v11_0_audio_set_dto(encoder, mode->clock);
1742 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1743 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1744 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1746 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1748 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1755 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1756 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1757 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1758 connector->name, bpc);
1761 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1762 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1763 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1767 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1768 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1769 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1773 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1775 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1776 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1777 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1778 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1779 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1781 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1782 /* enable audio info frames (frames won't be set until audio is enabled) */
1783 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1784 /* required for audio info values to be updated */
1785 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1786 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1788 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1789 /* required for audio info values to be updated */
1790 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1791 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1793 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1794 /* anything other than 0 */
1795 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1796 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1798 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1800 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1801 /* set the default audio delay */
1802 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1803 /* should be suffient for all audio modes and small enough for all hblanks */
1804 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1805 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1807 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1808 /* allow 60958 channel status fields to be updated */
1809 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1810 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1812 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1814 /* clear SW CTS value */
1815 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1817 /* select SW CTS value */
1818 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1819 /* allow hw to sent ACR packets when required */
1820 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1821 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1823 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1825 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1826 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1827 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1829 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1830 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1831 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1833 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1834 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1835 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1836 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1837 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1838 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1839 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1840 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1842 dce_v11_0_audio_write_speaker_allocation(encoder);
1844 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1845 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1847 dce_v11_0_afmt_audio_select_pin(encoder);
1848 dce_v11_0_audio_write_sad_regs(encoder);
1849 dce_v11_0_audio_write_latency_fields(encoder, mode);
1851 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1853 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1857 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1859 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1863 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1865 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1866 /* enable AVI info frames */
1867 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1868 /* required for audio info values to be updated */
1869 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1870 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1872 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1873 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1874 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1876 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1877 /* send audio packets */
1878 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1879 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1881 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1882 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1883 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1884 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1886 /* enable audio after to setting up hw */
1887 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1890 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1892 struct drm_device *dev = encoder->dev;
1893 struct amdgpu_device *adev = dev->dev_private;
1894 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1895 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1897 if (!dig || !dig->afmt)
1900 /* Silent, r600_hdmi_enable will raise WARN for us */
1901 if (enable && dig->afmt->enabled)
1903 if (!enable && !dig->afmt->enabled)
1906 if (!enable && dig->afmt->pin) {
1907 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1908 dig->afmt->pin = NULL;
1911 dig->afmt->enabled = enable;
1913 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1914 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1917 static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1921 for (i = 0; i < adev->mode_info.num_dig; i++)
1922 adev->mode_info.afmt[i] = NULL;
1924 /* DCE11 has audio blocks tied to DIG encoders */
1925 for (i = 0; i < adev->mode_info.num_dig; i++) {
1926 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1927 if (adev->mode_info.afmt[i]) {
1928 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1929 adev->mode_info.afmt[i]->id = i;
1932 for (j = 0; j < i; j++) {
1933 kfree(adev->mode_info.afmt[j]);
1934 adev->mode_info.afmt[j] = NULL;
1942 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1946 for (i = 0; i < adev->mode_info.num_dig; i++) {
1947 kfree(adev->mode_info.afmt[i]);
1948 adev->mode_info.afmt[i] = NULL;
1952 static const u32 vga_control_regs[6] =
1962 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1964 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1965 struct drm_device *dev = crtc->dev;
1966 struct amdgpu_device *adev = dev->dev_private;
1969 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1971 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1973 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1976 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1978 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1979 struct drm_device *dev = crtc->dev;
1980 struct amdgpu_device *adev = dev->dev_private;
1983 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1985 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1988 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
1989 struct drm_framebuffer *fb,
1990 int x, int y, int atomic)
1992 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1993 struct drm_device *dev = crtc->dev;
1994 struct amdgpu_device *adev = dev->dev_private;
1995 struct amdgpu_framebuffer *amdgpu_fb;
1996 struct drm_framebuffer *target_fb;
1997 struct drm_gem_object *obj;
1998 struct amdgpu_bo *abo;
1999 uint64_t fb_location, tiling_flags;
2000 uint32_t fb_format, fb_pitch_pixels;
2001 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2003 u32 tmp, viewport_w, viewport_h;
2005 bool bypass_lut = false;
2006 struct drm_format_name_buf format_name;
2009 if (!atomic && !crtc->primary->fb) {
2010 DRM_DEBUG_KMS("No FB bound\n");
2015 amdgpu_fb = to_amdgpu_framebuffer(fb);
2018 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2019 target_fb = crtc->primary->fb;
2022 /* If atomic, assume fb object is pinned & idle & fenced and
2023 * just update base pointers
2025 obj = amdgpu_fb->obj;
2026 abo = gem_to_amdgpu_bo(obj);
2027 r = amdgpu_bo_reserve(abo, false);
2028 if (unlikely(r != 0))
2032 fb_location = amdgpu_bo_gpu_offset(abo);
2034 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2035 if (unlikely(r != 0)) {
2036 amdgpu_bo_unreserve(abo);
2041 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
2042 amdgpu_bo_unreserve(abo);
2044 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2046 switch (target_fb->format->format) {
2048 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2049 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2051 case DRM_FORMAT_XRGB4444:
2052 case DRM_FORMAT_ARGB4444:
2053 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2054 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2056 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2060 case DRM_FORMAT_XRGB1555:
2061 case DRM_FORMAT_ARGB1555:
2062 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2063 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2065 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2069 case DRM_FORMAT_BGRX5551:
2070 case DRM_FORMAT_BGRA5551:
2071 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2072 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2074 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2078 case DRM_FORMAT_RGB565:
2079 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2080 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2082 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2086 case DRM_FORMAT_XRGB8888:
2087 case DRM_FORMAT_ARGB8888:
2088 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2089 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2091 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2095 case DRM_FORMAT_XRGB2101010:
2096 case DRM_FORMAT_ARGB2101010:
2097 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2098 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2100 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2103 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2106 case DRM_FORMAT_BGRX1010102:
2107 case DRM_FORMAT_BGRA1010102:
2108 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2109 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2111 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2114 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2118 DRM_ERROR("Unsupported screen format %s\n",
2119 drm_get_format_name(target_fb->format->format, &format_name));
2123 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2124 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2126 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2127 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2128 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2129 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2130 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2132 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2133 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2134 ARRAY_2D_TILED_THIN1);
2135 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2137 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2138 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2139 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2141 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2142 ADDR_SURF_MICRO_TILING_DISPLAY);
2143 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2144 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2145 ARRAY_1D_TILED_THIN1);
2148 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2151 dce_v11_0_vga_enable(crtc, false);
2153 /* Make sure surface address is updated at vertical blank rather than
2156 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2157 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2158 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2159 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2161 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2162 upper_32_bits(fb_location));
2163 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2164 upper_32_bits(fb_location));
2165 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2166 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2167 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2168 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2169 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2170 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2173 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2174 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2175 * retain the full precision throughout the pipeline.
2177 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2179 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2181 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2182 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2185 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2187 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2188 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2189 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2190 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2191 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2192 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2194 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2195 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2197 dce_v11_0_grph_enable(crtc, true);
2199 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2204 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2206 viewport_w = crtc->mode.hdisplay;
2207 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2208 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2209 (viewport_w << 16) | viewport_h);
2211 /* set pageflip to happen anywhere in vblank interval */
2212 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2214 if (!atomic && fb && fb != crtc->primary->fb) {
2215 amdgpu_fb = to_amdgpu_framebuffer(fb);
2216 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2217 r = amdgpu_bo_reserve(abo, false);
2218 if (unlikely(r != 0))
2220 amdgpu_bo_unpin(abo);
2221 amdgpu_bo_unreserve(abo);
2224 /* Bytes per pixel may have changed */
2225 dce_v11_0_bandwidth_update(adev);
2230 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2231 struct drm_display_mode *mode)
2233 struct drm_device *dev = crtc->dev;
2234 struct amdgpu_device *adev = dev->dev_private;
2235 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2238 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2239 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2240 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2242 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2243 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2246 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2248 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2249 struct drm_device *dev = crtc->dev;
2250 struct amdgpu_device *adev = dev->dev_private;
2254 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2256 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2257 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2258 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2260 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2261 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2262 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2264 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2265 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2266 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2268 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2270 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2271 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2272 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2274 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2275 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2276 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2278 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2279 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2281 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2282 for (i = 0; i < 256; i++) {
2283 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2284 (amdgpu_crtc->lut_r[i] << 20) |
2285 (amdgpu_crtc->lut_g[i] << 10) |
2286 (amdgpu_crtc->lut_b[i] << 0));
2289 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2290 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2291 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2292 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2293 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2295 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2296 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2297 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2299 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2300 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2301 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2303 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2304 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2305 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2307 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2308 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2309 /* XXX this only needs to be programmed once per crtc at startup,
2310 * not sure where the best place for it is
2312 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2313 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2314 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2317 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2319 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2320 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2322 switch (amdgpu_encoder->encoder_id) {
2323 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2329 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2335 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2341 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2345 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2351 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2355 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2356 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2357 * monitors a dedicated PPLL must be used. If a particular board has
2358 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2359 * as there is no need to program the PLL itself. If we are not able to
2360 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2361 * avoid messing up an existing monitor.
2363 * Asic specific PLL information
2367 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2369 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2372 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2374 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2375 struct drm_device *dev = crtc->dev;
2376 struct amdgpu_device *adev = dev->dev_private;
2380 if ((adev->asic_type == CHIP_POLARIS10) ||
2381 (adev->asic_type == CHIP_POLARIS11) ||
2382 (adev->asic_type == CHIP_POLARIS12)) {
2383 struct amdgpu_encoder *amdgpu_encoder =
2384 to_amdgpu_encoder(amdgpu_crtc->encoder);
2385 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2387 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2390 switch (amdgpu_encoder->encoder_id) {
2391 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2393 return ATOM_COMBOPHY_PLL1;
2395 return ATOM_COMBOPHY_PLL0;
2397 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2399 return ATOM_COMBOPHY_PLL3;
2401 return ATOM_COMBOPHY_PLL2;
2403 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2405 return ATOM_COMBOPHY_PLL5;
2407 return ATOM_COMBOPHY_PLL4;
2410 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2411 return ATOM_PPLL_INVALID;
2415 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2416 if (adev->clock.dp_extclk)
2417 /* skip PPLL programming if using ext clock */
2418 return ATOM_PPLL_INVALID;
2420 /* use the same PPLL for all DP monitors */
2421 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2422 if (pll != ATOM_PPLL_INVALID)
2426 /* use the same PPLL for all monitors with the same clock */
2427 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2428 if (pll != ATOM_PPLL_INVALID)
2432 /* XXX need to determine what plls are available on each DCE11 part */
2433 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2434 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2435 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2437 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2439 DRM_ERROR("unable to allocate a PPLL\n");
2440 return ATOM_PPLL_INVALID;
2442 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2444 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2446 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2448 DRM_ERROR("unable to allocate a PPLL\n");
2449 return ATOM_PPLL_INVALID;
2451 return ATOM_PPLL_INVALID;
2454 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2456 struct amdgpu_device *adev = crtc->dev->dev_private;
2457 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2460 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2462 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2464 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2465 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2468 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2470 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2471 struct amdgpu_device *adev = crtc->dev->dev_private;
2474 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2475 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2476 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2479 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2481 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2482 struct amdgpu_device *adev = crtc->dev->dev_private;
2485 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2486 upper_32_bits(amdgpu_crtc->cursor_addr));
2487 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2488 lower_32_bits(amdgpu_crtc->cursor_addr));
2490 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2491 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2492 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2493 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2496 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2499 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2500 struct amdgpu_device *adev = crtc->dev->dev_private;
2501 int xorigin = 0, yorigin = 0;
2503 amdgpu_crtc->cursor_x = x;
2504 amdgpu_crtc->cursor_y = y;
2506 /* avivo cursor are offset into the total surface */
2509 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2512 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2516 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2520 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2521 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2522 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2523 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2528 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2533 dce_v11_0_lock_cursor(crtc, true);
2534 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2535 dce_v11_0_lock_cursor(crtc, false);
2540 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2541 struct drm_file *file_priv,
2548 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2549 struct drm_gem_object *obj;
2550 struct amdgpu_bo *aobj;
2554 /* turn off cursor */
2555 dce_v11_0_hide_cursor(crtc);
2560 if ((width > amdgpu_crtc->max_cursor_width) ||
2561 (height > amdgpu_crtc->max_cursor_height)) {
2562 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2566 obj = drm_gem_object_lookup(file_priv, handle);
2568 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2572 aobj = gem_to_amdgpu_bo(obj);
2573 ret = amdgpu_bo_reserve(aobj, false);
2575 drm_gem_object_unreference_unlocked(obj);
2579 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2580 amdgpu_bo_unreserve(aobj);
2582 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2583 drm_gem_object_unreference_unlocked(obj);
2587 dce_v11_0_lock_cursor(crtc, true);
2589 if (width != amdgpu_crtc->cursor_width ||
2590 height != amdgpu_crtc->cursor_height ||
2591 hot_x != amdgpu_crtc->cursor_hot_x ||
2592 hot_y != amdgpu_crtc->cursor_hot_y) {
2595 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2596 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2598 dce_v11_0_cursor_move_locked(crtc, x, y);
2600 amdgpu_crtc->cursor_width = width;
2601 amdgpu_crtc->cursor_height = height;
2602 amdgpu_crtc->cursor_hot_x = hot_x;
2603 amdgpu_crtc->cursor_hot_y = hot_y;
2606 dce_v11_0_show_cursor(crtc);
2607 dce_v11_0_lock_cursor(crtc, false);
2610 if (amdgpu_crtc->cursor_bo) {
2611 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2612 ret = amdgpu_bo_reserve(aobj, false);
2613 if (likely(ret == 0)) {
2614 amdgpu_bo_unpin(aobj);
2615 amdgpu_bo_unreserve(aobj);
2617 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2620 amdgpu_crtc->cursor_bo = obj;
2624 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2626 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2628 if (amdgpu_crtc->cursor_bo) {
2629 dce_v11_0_lock_cursor(crtc, true);
2631 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2632 amdgpu_crtc->cursor_y);
2634 dce_v11_0_show_cursor(crtc);
2636 dce_v11_0_lock_cursor(crtc, false);
2640 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2641 u16 *blue, uint32_t size,
2642 struct drm_modeset_acquire_ctx *ctx)
2644 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2647 /* userspace palettes are always correct as is */
2648 for (i = 0; i < size; i++) {
2649 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2650 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2651 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2653 dce_v11_0_crtc_load_lut(crtc);
2658 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2660 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2662 drm_crtc_cleanup(crtc);
2666 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2667 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2668 .cursor_move = dce_v11_0_crtc_cursor_move,
2669 .gamma_set = dce_v11_0_crtc_gamma_set,
2670 .set_config = amdgpu_crtc_set_config,
2671 .destroy = dce_v11_0_crtc_destroy,
2672 .page_flip_target = amdgpu_crtc_page_flip_target,
2675 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2677 struct drm_device *dev = crtc->dev;
2678 struct amdgpu_device *adev = dev->dev_private;
2679 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2683 case DRM_MODE_DPMS_ON:
2684 amdgpu_crtc->enabled = true;
2685 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2686 dce_v11_0_vga_enable(crtc, true);
2687 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2688 dce_v11_0_vga_enable(crtc, false);
2689 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2690 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2691 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2692 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2693 drm_crtc_vblank_on(crtc);
2694 dce_v11_0_crtc_load_lut(crtc);
2696 case DRM_MODE_DPMS_STANDBY:
2697 case DRM_MODE_DPMS_SUSPEND:
2698 case DRM_MODE_DPMS_OFF:
2699 drm_crtc_vblank_off(crtc);
2700 if (amdgpu_crtc->enabled) {
2701 dce_v11_0_vga_enable(crtc, true);
2702 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2703 dce_v11_0_vga_enable(crtc, false);
2705 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2706 amdgpu_crtc->enabled = false;
2709 /* adjust pm to dpms */
2710 amdgpu_pm_compute_clocks(adev);
2713 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2715 /* disable crtc pair power gating before programming */
2716 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2717 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2718 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2721 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2723 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2724 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2727 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2729 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2730 struct drm_device *dev = crtc->dev;
2731 struct amdgpu_device *adev = dev->dev_private;
2732 struct amdgpu_atom_ss ss;
2735 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2736 if (crtc->primary->fb) {
2738 struct amdgpu_framebuffer *amdgpu_fb;
2739 struct amdgpu_bo *abo;
2741 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2742 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2743 r = amdgpu_bo_reserve(abo, false);
2745 DRM_ERROR("failed to reserve abo before unpin\n");
2747 amdgpu_bo_unpin(abo);
2748 amdgpu_bo_unreserve(abo);
2751 /* disable the GRPH */
2752 dce_v11_0_grph_enable(crtc, false);
2754 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2756 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2757 if (adev->mode_info.crtcs[i] &&
2758 adev->mode_info.crtcs[i]->enabled &&
2759 i != amdgpu_crtc->crtc_id &&
2760 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2761 /* one other crtc is using this pll don't turn
2768 switch (amdgpu_crtc->pll_id) {
2772 /* disable the ppll */
2773 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2774 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2776 case ATOM_COMBOPHY_PLL0:
2777 case ATOM_COMBOPHY_PLL1:
2778 case ATOM_COMBOPHY_PLL2:
2779 case ATOM_COMBOPHY_PLL3:
2780 case ATOM_COMBOPHY_PLL4:
2781 case ATOM_COMBOPHY_PLL5:
2782 /* disable the ppll */
2783 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2784 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2790 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2791 amdgpu_crtc->adjusted_clock = 0;
2792 amdgpu_crtc->encoder = NULL;
2793 amdgpu_crtc->connector = NULL;
2796 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2797 struct drm_display_mode *mode,
2798 struct drm_display_mode *adjusted_mode,
2799 int x, int y, struct drm_framebuffer *old_fb)
2801 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2802 struct drm_device *dev = crtc->dev;
2803 struct amdgpu_device *adev = dev->dev_private;
2805 if (!amdgpu_crtc->adjusted_clock)
2808 if ((adev->asic_type == CHIP_POLARIS10) ||
2809 (adev->asic_type == CHIP_POLARIS11) ||
2810 (adev->asic_type == CHIP_POLARIS12)) {
2811 struct amdgpu_encoder *amdgpu_encoder =
2812 to_amdgpu_encoder(amdgpu_crtc->encoder);
2814 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2816 /* SetPixelClock calculates the plls and ss values now */
2817 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2818 amdgpu_crtc->pll_id,
2819 encoder_mode, amdgpu_encoder->encoder_id,
2820 adjusted_mode->clock, 0, 0, 0, 0,
2821 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2823 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2825 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2826 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2827 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2828 amdgpu_atombios_crtc_scaler_setup(crtc);
2829 dce_v11_0_cursor_reset(crtc);
2830 /* update the hw version fpr dpm */
2831 amdgpu_crtc->hw_mode = *adjusted_mode;
2836 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2837 const struct drm_display_mode *mode,
2838 struct drm_display_mode *adjusted_mode)
2840 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2841 struct drm_device *dev = crtc->dev;
2842 struct drm_encoder *encoder;
2844 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2845 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2846 if (encoder->crtc == crtc) {
2847 amdgpu_crtc->encoder = encoder;
2848 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2852 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2853 amdgpu_crtc->encoder = NULL;
2854 amdgpu_crtc->connector = NULL;
2857 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2859 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2862 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2863 /* if we can't get a PPLL for a non-DP encoder, fail */
2864 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2865 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2871 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2872 struct drm_framebuffer *old_fb)
2874 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2877 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2878 struct drm_framebuffer *fb,
2879 int x, int y, enum mode_set_atomic state)
2881 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2884 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2885 .dpms = dce_v11_0_crtc_dpms,
2886 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2887 .mode_set = dce_v11_0_crtc_mode_set,
2888 .mode_set_base = dce_v11_0_crtc_set_base,
2889 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2890 .prepare = dce_v11_0_crtc_prepare,
2891 .commit = dce_v11_0_crtc_commit,
2892 .load_lut = dce_v11_0_crtc_load_lut,
2893 .disable = dce_v11_0_crtc_disable,
2896 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2898 struct amdgpu_crtc *amdgpu_crtc;
2901 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2902 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2903 if (amdgpu_crtc == NULL)
2906 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2908 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2909 amdgpu_crtc->crtc_id = index;
2910 adev->mode_info.crtcs[index] = amdgpu_crtc;
2912 amdgpu_crtc->max_cursor_width = 128;
2913 amdgpu_crtc->max_cursor_height = 128;
2914 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2915 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2917 for (i = 0; i < 256; i++) {
2918 amdgpu_crtc->lut_r[i] = i << 2;
2919 amdgpu_crtc->lut_g[i] = i << 2;
2920 amdgpu_crtc->lut_b[i] = i << 2;
2923 switch (amdgpu_crtc->crtc_id) {
2926 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2929 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2932 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2935 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2938 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2941 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2945 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2946 amdgpu_crtc->adjusted_clock = 0;
2947 amdgpu_crtc->encoder = NULL;
2948 amdgpu_crtc->connector = NULL;
2949 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2954 static int dce_v11_0_early_init(void *handle)
2956 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2958 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2959 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2961 dce_v11_0_set_display_funcs(adev);
2962 dce_v11_0_set_irq_funcs(adev);
2964 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2966 switch (adev->asic_type) {
2968 adev->mode_info.num_hpd = 6;
2969 adev->mode_info.num_dig = 9;
2972 adev->mode_info.num_hpd = 6;
2973 adev->mode_info.num_dig = 9;
2975 case CHIP_POLARIS10:
2976 adev->mode_info.num_hpd = 6;
2977 adev->mode_info.num_dig = 6;
2979 case CHIP_POLARIS11:
2980 case CHIP_POLARIS12:
2981 adev->mode_info.num_hpd = 5;
2982 adev->mode_info.num_dig = 5;
2985 /* FIXME: not supported yet */
2992 static int dce_v11_0_sw_init(void *handle)
2995 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2997 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2998 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
3003 for (i = 8; i < 20; i += 2) {
3004 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
3010 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
3014 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
3016 adev->ddev->mode_config.async_page_flip = true;
3018 adev->ddev->mode_config.max_width = 16384;
3019 adev->ddev->mode_config.max_height = 16384;
3021 adev->ddev->mode_config.preferred_depth = 24;
3022 adev->ddev->mode_config.prefer_shadow = 1;
3024 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
3026 r = amdgpu_modeset_create_props(adev);
3030 adev->ddev->mode_config.max_width = 16384;
3031 adev->ddev->mode_config.max_height = 16384;
3034 /* allocate crtcs */
3035 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3036 r = dce_v11_0_crtc_init(adev, i);
3041 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3042 amdgpu_print_display_setup(adev->ddev);
3047 r = dce_v11_0_afmt_init(adev);
3051 r = dce_v11_0_audio_init(adev);
3055 drm_kms_helper_poll_init(adev->ddev);
3057 adev->mode_info.mode_config_initialized = true;
3061 static int dce_v11_0_sw_fini(void *handle)
3063 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3065 kfree(adev->mode_info.bios_hardcoded_edid);
3067 drm_kms_helper_poll_fini(adev->ddev);
3069 dce_v11_0_audio_fini(adev);
3071 dce_v11_0_afmt_fini(adev);
3073 drm_mode_config_cleanup(adev->ddev);
3074 adev->mode_info.mode_config_initialized = false;
3079 static int dce_v11_0_hw_init(void *handle)
3082 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3084 dce_v11_0_init_golden_registers(adev);
3086 /* init dig PHYs, disp eng pll */
3087 amdgpu_atombios_crtc_powergate_init(adev);
3088 amdgpu_atombios_encoder_init_dig(adev);
3089 if ((adev->asic_type == CHIP_POLARIS10) ||
3090 (adev->asic_type == CHIP_POLARIS11) ||
3091 (adev->asic_type == CHIP_POLARIS12)) {
3092 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
3093 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
3094 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3095 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3097 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3100 /* initialize hpd */
3101 dce_v11_0_hpd_init(adev);
3103 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3104 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3107 dce_v11_0_pageflip_interrupt_init(adev);
3112 static int dce_v11_0_hw_fini(void *handle)
3115 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3117 dce_v11_0_hpd_fini(adev);
3119 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3120 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3123 dce_v11_0_pageflip_interrupt_fini(adev);
3128 static int dce_v11_0_suspend(void *handle)
3130 return dce_v11_0_hw_fini(handle);
3133 static int dce_v11_0_resume(void *handle)
3135 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3138 ret = dce_v11_0_hw_init(handle);
3140 /* turn on the BL */
3141 if (adev->mode_info.bl_encoder) {
3142 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3143 adev->mode_info.bl_encoder);
3144 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3151 static bool dce_v11_0_is_idle(void *handle)
3156 static int dce_v11_0_wait_for_idle(void *handle)
3161 static int dce_v11_0_soft_reset(void *handle)
3163 u32 srbm_soft_reset = 0, tmp;
3164 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3166 if (dce_v11_0_is_display_hung(adev))
3167 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3169 if (srbm_soft_reset) {
3170 tmp = RREG32(mmSRBM_SOFT_RESET);
3171 tmp |= srbm_soft_reset;
3172 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3173 WREG32(mmSRBM_SOFT_RESET, tmp);
3174 tmp = RREG32(mmSRBM_SOFT_RESET);
3178 tmp &= ~srbm_soft_reset;
3179 WREG32(mmSRBM_SOFT_RESET, tmp);
3180 tmp = RREG32(mmSRBM_SOFT_RESET);
3182 /* Wait a little for things to settle down */
3188 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3190 enum amdgpu_interrupt_state state)
3192 u32 lb_interrupt_mask;
3194 if (crtc >= adev->mode_info.num_crtc) {
3195 DRM_DEBUG("invalid crtc %d\n", crtc);
3200 case AMDGPU_IRQ_STATE_DISABLE:
3201 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3202 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3203 VBLANK_INTERRUPT_MASK, 0);
3204 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3206 case AMDGPU_IRQ_STATE_ENABLE:
3207 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3208 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3209 VBLANK_INTERRUPT_MASK, 1);
3210 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3217 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3219 enum amdgpu_interrupt_state state)
3221 u32 lb_interrupt_mask;
3223 if (crtc >= adev->mode_info.num_crtc) {
3224 DRM_DEBUG("invalid crtc %d\n", crtc);
3229 case AMDGPU_IRQ_STATE_DISABLE:
3230 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3231 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3232 VLINE_INTERRUPT_MASK, 0);
3233 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3235 case AMDGPU_IRQ_STATE_ENABLE:
3236 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3237 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3238 VLINE_INTERRUPT_MASK, 1);
3239 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3246 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3247 struct amdgpu_irq_src *source,
3249 enum amdgpu_interrupt_state state)
3253 if (hpd >= adev->mode_info.num_hpd) {
3254 DRM_DEBUG("invalid hdp %d\n", hpd);
3259 case AMDGPU_IRQ_STATE_DISABLE:
3260 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3261 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3262 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3264 case AMDGPU_IRQ_STATE_ENABLE:
3265 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3266 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3267 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3276 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3277 struct amdgpu_irq_src *source,
3279 enum amdgpu_interrupt_state state)
3282 case AMDGPU_CRTC_IRQ_VBLANK1:
3283 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3285 case AMDGPU_CRTC_IRQ_VBLANK2:
3286 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3288 case AMDGPU_CRTC_IRQ_VBLANK3:
3289 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3291 case AMDGPU_CRTC_IRQ_VBLANK4:
3292 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3294 case AMDGPU_CRTC_IRQ_VBLANK5:
3295 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3297 case AMDGPU_CRTC_IRQ_VBLANK6:
3298 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3300 case AMDGPU_CRTC_IRQ_VLINE1:
3301 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3303 case AMDGPU_CRTC_IRQ_VLINE2:
3304 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3306 case AMDGPU_CRTC_IRQ_VLINE3:
3307 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3309 case AMDGPU_CRTC_IRQ_VLINE4:
3310 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3312 case AMDGPU_CRTC_IRQ_VLINE5:
3313 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3315 case AMDGPU_CRTC_IRQ_VLINE6:
3316 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3324 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3325 struct amdgpu_irq_src *src,
3327 enum amdgpu_interrupt_state state)
3331 if (type >= adev->mode_info.num_crtc) {
3332 DRM_ERROR("invalid pageflip crtc %d\n", type);
3336 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3337 if (state == AMDGPU_IRQ_STATE_DISABLE)
3338 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3339 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3341 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3342 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3347 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3348 struct amdgpu_irq_src *source,
3349 struct amdgpu_iv_entry *entry)
3351 unsigned long flags;
3353 struct amdgpu_crtc *amdgpu_crtc;
3354 struct amdgpu_flip_work *works;
3356 crtc_id = (entry->src_id - 8) >> 1;
3357 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3359 if (crtc_id >= adev->mode_info.num_crtc) {
3360 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3364 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3365 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3366 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3367 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3369 /* IRQ could occur when in initial stage */
3370 if(amdgpu_crtc == NULL)
3373 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3374 works = amdgpu_crtc->pflip_works;
3375 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3376 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3377 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3378 amdgpu_crtc->pflip_status,
3379 AMDGPU_FLIP_SUBMITTED);
3380 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3384 /* page flip completed. clean up */
3385 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3386 amdgpu_crtc->pflip_works = NULL;
3388 /* wakeup usersapce */
3390 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3392 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3394 drm_crtc_vblank_put(&amdgpu_crtc->base);
3395 schedule_work(&works->unpin_work);
3400 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3405 if (hpd >= adev->mode_info.num_hpd) {
3406 DRM_DEBUG("invalid hdp %d\n", hpd);
3410 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3411 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3412 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3415 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3420 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3421 DRM_DEBUG("invalid crtc %d\n", crtc);
3425 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3426 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3427 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3430 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3435 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3436 DRM_DEBUG("invalid crtc %d\n", crtc);
3440 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3441 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3442 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3445 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3446 struct amdgpu_irq_src *source,
3447 struct amdgpu_iv_entry *entry)
3449 unsigned crtc = entry->src_id - 1;
3450 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3451 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3453 switch (entry->src_data[0]) {
3454 case 0: /* vblank */
3455 if (disp_int & interrupt_status_offsets[crtc].vblank)
3456 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3458 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3460 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3461 drm_handle_vblank(adev->ddev, crtc);
3463 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3467 if (disp_int & interrupt_status_offsets[crtc].vline)
3468 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3470 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3472 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3476 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3483 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3484 struct amdgpu_irq_src *source,
3485 struct amdgpu_iv_entry *entry)
3487 uint32_t disp_int, mask;
3490 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3491 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3495 hpd = entry->src_data[0];
3496 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3497 mask = interrupt_status_offsets[hpd].hpd;
3499 if (disp_int & mask) {
3500 dce_v11_0_hpd_int_ack(adev, hpd);
3501 schedule_work(&adev->hotplug_work);
3502 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3508 static int dce_v11_0_set_clockgating_state(void *handle,
3509 enum amd_clockgating_state state)
3514 static int dce_v11_0_set_powergating_state(void *handle,
3515 enum amd_powergating_state state)
3520 static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3521 .name = "dce_v11_0",
3522 .early_init = dce_v11_0_early_init,
3524 .sw_init = dce_v11_0_sw_init,
3525 .sw_fini = dce_v11_0_sw_fini,
3526 .hw_init = dce_v11_0_hw_init,
3527 .hw_fini = dce_v11_0_hw_fini,
3528 .suspend = dce_v11_0_suspend,
3529 .resume = dce_v11_0_resume,
3530 .is_idle = dce_v11_0_is_idle,
3531 .wait_for_idle = dce_v11_0_wait_for_idle,
3532 .soft_reset = dce_v11_0_soft_reset,
3533 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3534 .set_powergating_state = dce_v11_0_set_powergating_state,
3538 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3539 struct drm_display_mode *mode,
3540 struct drm_display_mode *adjusted_mode)
3542 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3544 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3546 /* need to call this here rather than in prepare() since we need some crtc info */
3547 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3549 /* set scaler clears this on some chips */
3550 dce_v11_0_set_interleave(encoder->crtc, mode);
3552 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3553 dce_v11_0_afmt_enable(encoder, true);
3554 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3558 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3560 struct amdgpu_device *adev = encoder->dev->dev_private;
3561 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3562 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3564 if ((amdgpu_encoder->active_device &
3565 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3566 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3567 ENCODER_OBJECT_ID_NONE)) {
3568 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3570 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3571 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3572 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3576 amdgpu_atombios_scratch_regs_lock(adev, true);
3579 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3581 /* select the clock/data port if it uses a router */
3582 if (amdgpu_connector->router.cd_valid)
3583 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3585 /* turn eDP panel on for mode set */
3586 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3587 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3588 ATOM_TRANSMITTER_ACTION_POWER_ON);
3591 /* this is needed for the pll/ss setup to work correctly in some cases */
3592 amdgpu_atombios_encoder_set_crtc_source(encoder);
3593 /* set up the FMT blocks */
3594 dce_v11_0_program_fmt(encoder);
3597 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3599 struct drm_device *dev = encoder->dev;
3600 struct amdgpu_device *adev = dev->dev_private;
3602 /* need to call this here as we need the crtc set up */
3603 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3604 amdgpu_atombios_scratch_regs_lock(adev, false);
3607 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3609 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3610 struct amdgpu_encoder_atom_dig *dig;
3612 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3614 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3615 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3616 dce_v11_0_afmt_enable(encoder, false);
3617 dig = amdgpu_encoder->enc_priv;
3618 dig->dig_encoder = -1;
3620 amdgpu_encoder->active_device = 0;
3623 /* these are handled by the primary encoders */
3624 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3629 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3635 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3636 struct drm_display_mode *mode,
3637 struct drm_display_mode *adjusted_mode)
3642 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3648 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3653 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3654 .dpms = dce_v11_0_ext_dpms,
3655 .prepare = dce_v11_0_ext_prepare,
3656 .mode_set = dce_v11_0_ext_mode_set,
3657 .commit = dce_v11_0_ext_commit,
3658 .disable = dce_v11_0_ext_disable,
3659 /* no detect for TMDS/LVDS yet */
3662 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3663 .dpms = amdgpu_atombios_encoder_dpms,
3664 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3665 .prepare = dce_v11_0_encoder_prepare,
3666 .mode_set = dce_v11_0_encoder_mode_set,
3667 .commit = dce_v11_0_encoder_commit,
3668 .disable = dce_v11_0_encoder_disable,
3669 .detect = amdgpu_atombios_encoder_dig_detect,
3672 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3673 .dpms = amdgpu_atombios_encoder_dpms,
3674 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3675 .prepare = dce_v11_0_encoder_prepare,
3676 .mode_set = dce_v11_0_encoder_mode_set,
3677 .commit = dce_v11_0_encoder_commit,
3678 .detect = amdgpu_atombios_encoder_dac_detect,
3681 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3683 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3684 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3685 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3686 kfree(amdgpu_encoder->enc_priv);
3687 drm_encoder_cleanup(encoder);
3688 kfree(amdgpu_encoder);
3691 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3692 .destroy = dce_v11_0_encoder_destroy,
3695 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3696 uint32_t encoder_enum,
3697 uint32_t supported_device,
3700 struct drm_device *dev = adev->ddev;
3701 struct drm_encoder *encoder;
3702 struct amdgpu_encoder *amdgpu_encoder;
3704 /* see if we already added it */
3705 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3706 amdgpu_encoder = to_amdgpu_encoder(encoder);
3707 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3708 amdgpu_encoder->devices |= supported_device;
3715 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3716 if (!amdgpu_encoder)
3719 encoder = &amdgpu_encoder->base;
3720 switch (adev->mode_info.num_crtc) {
3722 encoder->possible_crtcs = 0x1;
3726 encoder->possible_crtcs = 0x3;
3729 encoder->possible_crtcs = 0x7;
3732 encoder->possible_crtcs = 0xf;
3735 encoder->possible_crtcs = 0x1f;
3738 encoder->possible_crtcs = 0x3f;
3742 amdgpu_encoder->enc_priv = NULL;
3744 amdgpu_encoder->encoder_enum = encoder_enum;
3745 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3746 amdgpu_encoder->devices = supported_device;
3747 amdgpu_encoder->rmx_type = RMX_OFF;
3748 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3749 amdgpu_encoder->is_ext_encoder = false;
3750 amdgpu_encoder->caps = caps;
3752 switch (amdgpu_encoder->encoder_id) {
3753 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3754 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3755 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3756 DRM_MODE_ENCODER_DAC, NULL);
3757 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3759 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3760 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3761 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3762 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3763 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3764 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3765 amdgpu_encoder->rmx_type = RMX_FULL;
3766 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3767 DRM_MODE_ENCODER_LVDS, NULL);
3768 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3769 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3770 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3771 DRM_MODE_ENCODER_DAC, NULL);
3772 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3774 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3775 DRM_MODE_ENCODER_TMDS, NULL);
3776 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3778 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3780 case ENCODER_OBJECT_ID_SI170B:
3781 case ENCODER_OBJECT_ID_CH7303:
3782 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3783 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3784 case ENCODER_OBJECT_ID_TITFP513:
3785 case ENCODER_OBJECT_ID_VT1623:
3786 case ENCODER_OBJECT_ID_HDMI_SI1930:
3787 case ENCODER_OBJECT_ID_TRAVIS:
3788 case ENCODER_OBJECT_ID_NUTMEG:
3789 /* these are handled by the primary encoders */
3790 amdgpu_encoder->is_ext_encoder = true;
3791 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3792 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3793 DRM_MODE_ENCODER_LVDS, NULL);
3794 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3795 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3796 DRM_MODE_ENCODER_DAC, NULL);
3798 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3799 DRM_MODE_ENCODER_TMDS, NULL);
3800 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3805 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3806 .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3807 .bandwidth_update = &dce_v11_0_bandwidth_update,
3808 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3809 .vblank_wait = &dce_v11_0_vblank_wait,
3810 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3811 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3812 .hpd_sense = &dce_v11_0_hpd_sense,
3813 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3814 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3815 .page_flip = &dce_v11_0_page_flip,
3816 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3817 .add_encoder = &dce_v11_0_encoder_add,
3818 .add_connector = &amdgpu_connector_add,
3819 .stop_mc_access = &dce_v11_0_stop_mc_access,
3820 .resume_mc_access = &dce_v11_0_resume_mc_access,
3823 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3825 if (adev->mode_info.funcs == NULL)
3826 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3829 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3830 .set = dce_v11_0_set_crtc_irq_state,
3831 .process = dce_v11_0_crtc_irq,
3834 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3835 .set = dce_v11_0_set_pageflip_irq_state,
3836 .process = dce_v11_0_pageflip_irq,
3839 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3840 .set = dce_v11_0_set_hpd_irq_state,
3841 .process = dce_v11_0_hpd_irq,
3844 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3846 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3847 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3849 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3850 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3852 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3853 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3856 const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3858 .type = AMD_IP_BLOCK_TYPE_DCE,
3862 .funcs = &dce_v11_0_ip_funcs,
3865 const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3867 .type = AMD_IP_BLOCK_TYPE_DCE,
3871 .funcs = &dce_v11_0_ip_funcs,