drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "atom.h"
  28 #include "amdgpu_atombios.h"
  29 #include "atombios_crtc.h"
  30 #include "atombios_encoders.h"
  31 #include "amdgpu_pll.h"
  32 #include "amdgpu_connectors.h"
  33
  34 #include "bif/bif_3_0_d.h"
  35 #include "bif/bif_3_0_sh_mask.h"
  36 #include "oss/oss_1_0_d.h"
  37 #include "oss/oss_1_0_sh_mask.h"
  38 #include "gca/gfx_6_0_d.h"
  39 #include "gca/gfx_6_0_sh_mask.h"
  40 #include "gmc/gmc_6_0_d.h"
  41 #include "gmc/gmc_6_0_sh_mask.h"
  42 #include "dce/dce_6_0_d.h"
  43 #include "dce/dce_6_0_sh_mask.h"
  44 #include "gca/gfx_7_2_enum.h"
  45 #include "si_enums.h"
  46
  47 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);
  48 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  49
  50 static const u32 crtc_offsets[6] =
  51 {
  52         SI_CRTC0_REGISTER_OFFSET,
  53         SI_CRTC1_REGISTER_OFFSET,
  54         SI_CRTC2_REGISTER_OFFSET,
  55         SI_CRTC3_REGISTER_OFFSET,
  56         SI_CRTC4_REGISTER_OFFSET,
  57         SI_CRTC5_REGISTER_OFFSET
  58 };
  59
  60 static const u32 hpd_offsets[] =
  61 {
  62         mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
  63         mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
  64         mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,
  65         mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,
  66         mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,
  67         mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,
  68 };
  69
  70 static const uint32_t dig_offsets[] = {
  71         SI_CRTC0_REGISTER_OFFSET,
  72         SI_CRTC1_REGISTER_OFFSET,
  73         SI_CRTC2_REGISTER_OFFSET,
  74         SI_CRTC3_REGISTER_OFFSET,
  75         SI_CRTC4_REGISTER_OFFSET,
  76         SI_CRTC5_REGISTER_OFFSET,
  77         (0x13830 - 0x7030) >> 2,
  78 };
  79
  80 static const struct {
  81         uint32_t        reg;
  82         uint32_t        vblank;
  83         uint32_t        vline;
  84         uint32_t        hpd;
  85
  86 } interrupt_status_offsets[6] = { {
  87         .reg = mmDISP_INTERRUPT_STATUS,
  88         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  89         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  90         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  91 }, {
  92         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  93         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  94         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  95         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  96 }, {
  97         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  98         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  99         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
 100         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 101 }, {
 102         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 103         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 104         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 105         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 106 }, {
 107         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 108         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 109         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 110         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 111 }, {
 112         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 113         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 114         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 115         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 116 } };
 117
 118 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
 119                                      u32 block_offset, u32 reg)
 120 {
 121         DRM_INFO("xxxx: dce_v6_0_audio_endpt_rreg ----no impl!!!!\n");
 122         return 0;
 123 }
 124
 125 static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
 126                                       u32 block_offset, u32 reg, u32 v)
 127 {
 128         DRM_INFO("xxxx: dce_v6_0_audio_endpt_wreg ----no impl!!!!\n");
 129 }
 130
 131 static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 132 {
 133         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & CRTC_STATUS__CRTC_V_BLANK_MASK)
 134                 return true;
 135         else
 136                 return false;
 137 }
 138
 139 static bool dce_v6_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 140 {
 141         u32 pos1, pos2;
 142
 143         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 144         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 145
 146         if (pos1 != pos2)
 147                 return true;
 148         else
 149                 return false;
 150 }
 151
 152 /**
 153  * dce_v6_0_wait_for_vblank - vblank wait asic callback.
 154  *
 155  * @crtc: crtc to wait for vblank on
 156  *
 157  * Wait for vblank on the requested crtc (evergreen+).
 158  */
 159 static void dce_v6_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 160 {
 161         unsigned i = 100;
 162
 163         if (crtc >= adev->mode_info.num_crtc)
 164                 return;
 165
 166         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 167                 return;
 168
 169         /* depending on when we hit vblank, we may be close to active; if so,
 170          * wait for another frame.
 171          */
 172         while (dce_v6_0_is_in_vblank(adev, crtc)) {
 173                 if (i++ == 100) {
 174                         i = 0;
 175                         if (!dce_v6_0_is_counter_moving(adev, crtc))
 176                                 break;
 177                 }
 178         }
 179
 180         while (!dce_v6_0_is_in_vblank(adev, crtc)) {
 181                 if (i++ == 100) {
 182                         i = 0;
 183                         if (!dce_v6_0_is_counter_moving(adev, crtc))
 184                                 break;
 185                 }
 186         }
 187 }
 188
 189 static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 190 {
 191         if (crtc >= adev->mode_info.num_crtc)
 192                 return 0;
 193         else
 194                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 195 }
 196
 197 static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 198 {
 199         unsigned i;
 200
 201         /* Enable pflip interrupts */
 202         for (i = 0; i < adev->mode_info.num_crtc; i++)
 203                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 204 }
 205
 206 static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 207 {
 208         unsigned i;
 209
 210         /* Disable pflip interrupts */
 211         for (i = 0; i < adev->mode_info.num_crtc; i++)
 212                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 213 }
 214
 215 /**
 216  * dce_v6_0_page_flip - pageflip callback.
 217  *
 218  * @adev: amdgpu_device pointer
 219  * @crtc_id: crtc to cleanup pageflip on
 220  * @crtc_base: new address of the crtc (GPU MC address)
 221  *
 222  * Does the actual pageflip (evergreen+).
 223  * During vblank we take the crtc lock and wait for the update_pending
 224  * bit to go high, when it does, we release the lock, and allow the
 225  * double buffered update to take place.
 226  * Returns the current update pending status.
 227  */
 228 static void dce_v6_0_page_flip(struct amdgpu_device *adev,
 229                                int crtc_id, u64 crtc_base, bool async)
 230 {
 231         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 232
 233         /* flip at hsync for async, default is vsync */
 234         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
 235                GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
 236         /* update the scanout addresses */
 237         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 238                upper_32_bits(crtc_base));
 239         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 240                (u32)crtc_base);
 241
 242         /* post the write */
 243         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 244 }
 245
 246 static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 247                                         u32 *vbl, u32 *position)
 248 {
 249         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 250                 return -EINVAL;
 251         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 252         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 253
 254         return 0;
 255
 256 }
 257
 258 /**
 259  * dce_v6_0_hpd_sense - hpd sense callback.
 260  *
 261  * @adev: amdgpu_device pointer
 262  * @hpd: hpd (hotplug detect) pin
 263  *
 264  * Checks if a digital monitor is connected (evergreen+).
 265  * Returns true if connected, false if not connected.
 266  */
 267 static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev,
 268                                enum amdgpu_hpd_id hpd)
 269 {
 270         bool connected = false;
 271
 272         if (hpd >= adev->mode_info.num_hpd)
 273                 return connected;
 274
 275         if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
 276                 connected = true;
 277
 278         return connected;
 279 }
 280
 281 /**
 282  * dce_v6_0_hpd_set_polarity - hpd set polarity callback.
 283  *
 284  * @adev: amdgpu_device pointer
 285  * @hpd: hpd (hotplug detect) pin
 286  *
 287  * Set the polarity of the hpd pin (evergreen+).
 288  */
 289 static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev,
 290                                       enum amdgpu_hpd_id hpd)
 291 {
 292         u32 tmp;
 293         bool connected = dce_v6_0_hpd_sense(adev, hpd);
 294
 295         if (hpd >= adev->mode_info.num_hpd)
 296                 return;
 297
 298         tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
 299         if (connected)
 300                 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 301         else
 302                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 303         WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
 304 }
 305
 306 /**
 307  * dce_v6_0_hpd_init - hpd setup callback.
 308  *
 309  * @adev: amdgpu_device pointer
 310  *
 311  * Setup the hpd pins used by the card (evergreen+).
 312  * Enable the pin, set the polarity, and enable the hpd interrupts.
 313  */
 314 static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
 315 {
 316         struct drm_device *dev = adev->ddev;
 317         struct drm_connector *connector;
 318         u32 tmp;
 319
 320         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 321                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 322
 323                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 324                         continue;
 325
 326                 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 327                 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
 328                 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 329
 330                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 331                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 332                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 333                          * aux dp channel on imac and help (but not completely fix)
 334                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 335                          * also avoid interrupt storms during dpms.
 336                          */
 337                         tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 338                         tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
 339                         WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 340                         continue;
 341                 }
 342
 343                 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 344                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 345         }
 346
 347 }
 348
 349 /**
 350  * dce_v6_0_hpd_fini - hpd tear down callback.
 351  *
 352  * @adev: amdgpu_device pointer
 353  *
 354  * Tear down the hpd pins used by the card (evergreen+).
 355  * Disable the hpd interrupts.
 356  */
 357 static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
 358 {
 359         struct drm_device *dev = adev->ddev;
 360         struct drm_connector *connector;
 361         u32 tmp;
 362
 363         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 364                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 365
 366                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 367                         continue;
 368
 369                 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 370                 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
 371                 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
 372
 373                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 374         }
 375 }
 376
 377 static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 378 {
 379         return mmDC_GPIO_HPD_A;
 380 }
 381
 382 static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc)
 383 {
 384         if (crtc >= adev->mode_info.num_crtc)
 385                 return 0;
 386         else
 387                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 388 }
 389
 390 static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
 391                                     struct amdgpu_mode_mc_save *save)
 392 {
 393         u32 crtc_enabled, tmp, frame_count;
 394         int i, j;
 395
 396         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 397         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 398
 399         /* disable VGA render */
 400         WREG32(mmVGA_RENDER_CONTROL, 0);
 401
 402         /* blank the display controllers */
 403         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 404                 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK;
 405                 if (crtc_enabled) {
 406                         save->crtc_enabled[i] = true;
 407                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 408
 409                         if (!(tmp & CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK)) {
 410                                 dce_v6_0_vblank_wait(adev, i);
 411                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 412                                 tmp |= CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK;
 413                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 414                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 415                         }
 416                         /* wait for the next frame */
 417                         frame_count = evergreen_get_vblank_counter(adev, i);
 418                         for (j = 0; j < adev->usec_timeout; j++) {
 419                                 if (evergreen_get_vblank_counter(adev, i) != frame_count)
 420                                         break;
 421                                 udelay(1);
 422                         }
 423
 424                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 425                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 426                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 427                         tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
 428                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 429                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 430                         save->crtc_enabled[i] = false;
 431                         /* ***** */
 432                 } else {
 433                         save->crtc_enabled[i] = false;
 434                 }
 435         }
 436 }
 437
 438 static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
 439                                       struct amdgpu_mode_mc_save *save)
 440 {
 441         u32 tmp;
 442         int i, j;
 443
 444         /* update crtc base addresses */
 445         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 446                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 447                        upper_32_bits(adev->mc.vram_start));
 448                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 449                        upper_32_bits(adev->mc.vram_start));
 450                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 451                        (u32)adev->mc.vram_start);
 452                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 453                        (u32)adev->mc.vram_start);
 454         }
 455
 456         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 457         WREG32(mmVGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start);
 458
 459         /* unlock regs and wait for update */
 460         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 461                 if (save->crtc_enabled[i]) {
 462                         tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
 463                         if ((tmp & 0x7) != 0) {
 464                                 tmp &= ~0x7;
 465                                 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
 466                         }
 467                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 468                         if (tmp & GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK) {
 469                                 tmp &= ~GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK;
 470                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 471                         }
 472                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
 473                         if (tmp & 1) {
 474                                 tmp &= ~1;
 475                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 476                         }
 477                         for (j = 0; j < adev->usec_timeout; j++) {
 478                                 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 479                                 if ((tmp & GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) == 0)
 480                                         break;
 481                                 udelay(1);
 482                         }
 483                 }
 484         }
 485
 486         /* Unlock vga access */
 487         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 488         mdelay(1);
 489         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 490
 491 }
 492
 493 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
 494                                           bool render)
 495 {
 496         if (!render)
 497                 WREG32(mmVGA_RENDER_CONTROL,
 498                         RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL);
 499
 500 }
 501
 502 static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev)
 503 {
 504         int num_crtc = 0;
 505
 506         switch (adev->asic_type) {
 507         case CHIP_TAHITI:
 508         case CHIP_PITCAIRN:
 509         case CHIP_VERDE:
 510                 num_crtc = 6;
 511                 break;
 512         case CHIP_OLAND:
 513                 num_crtc = 2;
 514                 break;
 515         default:
 516                 num_crtc = 0;
 517         }
 518         return num_crtc;
 519 }
 520
 521 void dce_v6_0_disable_dce(struct amdgpu_device *adev)
 522 {
 523         /*Disable VGA render and enabled crtc, if has DCE engine*/
 524         if (amdgpu_atombios_has_dce_engine_info(adev)) {
 525                 u32 tmp;
 526                 int crtc_enabled, i;
 527
 528                 dce_v6_0_set_vga_render_state(adev, false);
 529
 530                 /*Disable crtc*/
 531                 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
 532                         crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) &
 533                                 CRTC_CONTROL__CRTC_MASTER_EN_MASK;
 534                         if (crtc_enabled) {
 535                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 536                                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 537                                 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
 538                                 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 539                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 540                         }
 541                 }
 542         }
 543 }
 544
 545 static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
 546 {
 547
 548         struct drm_device *dev = encoder->dev;
 549         struct amdgpu_device *adev = dev->dev_private;
 550         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 551         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 552         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 553         int bpc = 0;
 554         u32 tmp = 0;
 555         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 556
 557         if (connector) {
 558                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 559                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 560                 dither = amdgpu_connector->dither;
 561         }
 562
 563         /* LVDS FMT is set up by atom */
 564         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 565                 return;
 566
 567         if (bpc == 0)
 568                 return;
 569
 570
 571         switch (bpc) {
 572         case 6:
 573                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 574                         /* XXX sort out optimal dither settings */
 575                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 576                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 577                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK);
 578                 else
 579                         tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK;
 580                 break;
 581         case 8:
 582                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 583                         /* XXX sort out optimal dither settings */
 584                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 585                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 586                                 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
 587                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 588                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK);
 589                 else
 590                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 591                                 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK);
 592                 break;
 593         case 10:
 594         default:
 595                 /* not needed */
 596                 break;
 597         }
 598
 599         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 600 }
 601
 602 /**
 603  * cik_get_number_of_dram_channels - get the number of dram channels
 604  *
 605  * @adev: amdgpu_device pointer
 606  *
 607  * Look up the number of video ram channels (CIK).
 608  * Used for display watermark bandwidth calculations
 609  * Returns the number of dram channels
 610  */
 611 static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev)
 612 {
 613         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 614
 615         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 616         case 0:
 617         default:
 618                 return 1;
 619         case 1:
 620                 return 2;
 621         case 2:
 622                 return 4;
 623         case 3:
 624                 return 8;
 625         case 4:
 626                 return 3;
 627         case 5:
 628                 return 6;
 629         case 6:
 630                 return 10;
 631         case 7:
 632                 return 12;
 633         case 8:
 634                 return 16;
 635         }
 636 }
 637
 638 struct dce6_wm_params {
 639         u32 dram_channels; /* number of dram channels */
 640         u32 yclk;          /* bandwidth per dram data pin in kHz */
 641         u32 sclk;          /* engine clock in kHz */
 642         u32 disp_clk;      /* display clock in kHz */
 643         u32 src_width;     /* viewport width */
 644         u32 active_time;   /* active display time in ns */
 645         u32 blank_time;    /* blank time in ns */
 646         bool interlaced;    /* mode is interlaced */
 647         fixed20_12 vsc;    /* vertical scale ratio */
 648         u32 num_heads;     /* number of active crtcs */
 649         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 650         u32 lb_size;       /* line buffer allocated to pipe */
 651         u32 vtaps;         /* vertical scaler taps */
 652 };
 653
 654 /**
 655  * dce_v6_0_dram_bandwidth - get the dram bandwidth
 656  *
 657  * @wm: watermark calculation data
 658  *
 659  * Calculate the raw dram bandwidth (CIK).
 660  * Used for display watermark bandwidth calculations
 661  * Returns the dram bandwidth in MBytes/s
 662  */
 663 static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm)
 664 {
 665         /* Calculate raw DRAM Bandwidth */
 666         fixed20_12 dram_efficiency; /* 0.7 */
 667         fixed20_12 yclk, dram_channels, bandwidth;
 668         fixed20_12 a;
 669
 670         a.full = dfixed_const(1000);
 671         yclk.full = dfixed_const(wm->yclk);
 672         yclk.full = dfixed_div(yclk, a);
 673         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 674         a.full = dfixed_const(10);
 675         dram_efficiency.full = dfixed_const(7);
 676         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 677         bandwidth.full = dfixed_mul(dram_channels, yclk);
 678         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 679
 680         return dfixed_trunc(bandwidth);
 681 }
 682
 683 /**
 684  * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display
 685  *
 686  * @wm: watermark calculation data
 687  *
 688  * Calculate the dram bandwidth used for display (CIK).
 689  * Used for display watermark bandwidth calculations
 690  * Returns the dram bandwidth for display in MBytes/s
 691  */
 692 static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm)
 693 {
 694         /* Calculate DRAM Bandwidth and the part allocated to display. */
 695         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 696         fixed20_12 yclk, dram_channels, bandwidth;
 697         fixed20_12 a;
 698
 699         a.full = dfixed_const(1000);
 700         yclk.full = dfixed_const(wm->yclk);
 701         yclk.full = dfixed_div(yclk, a);
 702         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 703         a.full = dfixed_const(10);
 704         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 705         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 706         bandwidth.full = dfixed_mul(dram_channels, yclk);
 707         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 708
 709         return dfixed_trunc(bandwidth);
 710 }
 711
 712 /**
 713  * dce_v6_0_data_return_bandwidth - get the data return bandwidth
 714  *
 715  * @wm: watermark calculation data
 716  *
 717  * Calculate the data return bandwidth used for display (CIK).
 718  * Used for display watermark bandwidth calculations
 719  * Returns the data return bandwidth in MBytes/s
 720  */
 721 static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm)
 722 {
 723         /* Calculate the display Data return Bandwidth */
 724         fixed20_12 return_efficiency; /* 0.8 */
 725         fixed20_12 sclk, bandwidth;
 726         fixed20_12 a;
 727
 728         a.full = dfixed_const(1000);
 729         sclk.full = dfixed_const(wm->sclk);
 730         sclk.full = dfixed_div(sclk, a);
 731         a.full = dfixed_const(10);
 732         return_efficiency.full = dfixed_const(8);
 733         return_efficiency.full = dfixed_div(return_efficiency, a);
 734         a.full = dfixed_const(32);
 735         bandwidth.full = dfixed_mul(a, sclk);
 736         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 737
 738         return dfixed_trunc(bandwidth);
 739 }
 740
 741 /**
 742  * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth
 743  *
 744  * @wm: watermark calculation data
 745  *
 746  * Calculate the dmif bandwidth used for display (CIK).
 747  * Used for display watermark bandwidth calculations
 748  * Returns the dmif bandwidth in MBytes/s
 749  */
 750 static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm)
 751 {
 752         /* Calculate the DMIF Request Bandwidth */
 753         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 754         fixed20_12 disp_clk, bandwidth;
 755         fixed20_12 a, b;
 756
 757         a.full = dfixed_const(1000);
 758         disp_clk.full = dfixed_const(wm->disp_clk);
 759         disp_clk.full = dfixed_div(disp_clk, a);
 760         a.full = dfixed_const(32);
 761         b.full = dfixed_mul(a, disp_clk);
 762
 763         a.full = dfixed_const(10);
 764         disp_clk_request_efficiency.full = dfixed_const(8);
 765         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 766
 767         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
 768
 769         return dfixed_trunc(bandwidth);
 770 }
 771
 772 /**
 773  * dce_v6_0_available_bandwidth - get the min available bandwidth
 774  *
 775  * @wm: watermark calculation data
 776  *
 777  * Calculate the min available bandwidth used for display (CIK).
 778  * Used for display watermark bandwidth calculations
 779  * Returns the min available bandwidth in MBytes/s
 780  */
 781 static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm)
 782 {
 783         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 784         u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm);
 785         u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm);
 786         u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm);
 787
 788         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 789 }
 790
 791 /**
 792  * dce_v6_0_average_bandwidth - get the average available bandwidth
 793  *
 794  * @wm: watermark calculation data
 795  *
 796  * Calculate the average available bandwidth used for display (CIK).
 797  * Used for display watermark bandwidth calculations
 798  * Returns the average available bandwidth in MBytes/s
 799  */
 800 static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm)
 801 {
 802         /* Calculate the display mode Average Bandwidth
 803          * DisplayMode should contain the source and destination dimensions,
 804          * timing, etc.
 805          */
 806         fixed20_12 bpp;
 807         fixed20_12 line_time;
 808         fixed20_12 src_width;
 809         fixed20_12 bandwidth;
 810         fixed20_12 a;
 811
 812         a.full = dfixed_const(1000);
 813         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 814         line_time.full = dfixed_div(line_time, a);
 815         bpp.full = dfixed_const(wm->bytes_per_pixel);
 816         src_width.full = dfixed_const(wm->src_width);
 817         bandwidth.full = dfixed_mul(src_width, bpp);
 818         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 819         bandwidth.full = dfixed_div(bandwidth, line_time);
 820
 821         return dfixed_trunc(bandwidth);
 822 }
 823
 824 /**
 825  * dce_v6_0_latency_watermark - get the latency watermark
 826  *
 827  * @wm: watermark calculation data
 828  *
 829  * Calculate the latency watermark (CIK).
 830  * Used for display watermark bandwidth calculations
 831  * Returns the latency watermark in ns
 832  */
 833 static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm)
 834 {
 835         /* First calculate the latency in ns */
 836         u32 mc_latency = 2000; /* 2000 ns. */
 837         u32 available_bandwidth = dce_v6_0_available_bandwidth(wm);
 838         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 839         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 840         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 841         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 842                 (wm->num_heads * cursor_line_pair_return_time);
 843         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 844         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 845         u32 tmp, dmif_size = 12288;
 846         fixed20_12 a, b, c;
 847
 848         if (wm->num_heads == 0)
 849                 return 0;
 850
 851         a.full = dfixed_const(2);
 852         b.full = dfixed_const(1);
 853         if ((wm->vsc.full > a.full) ||
 854             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 855             (wm->vtaps >= 5) ||
 856             ((wm->vsc.full >= a.full) && wm->interlaced))
 857                 max_src_lines_per_dst_line = 4;
 858         else
 859                 max_src_lines_per_dst_line = 2;
 860
 861         a.full = dfixed_const(available_bandwidth);
 862         b.full = dfixed_const(wm->num_heads);
 863         a.full = dfixed_div(a, b);
 864         tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
 865         tmp = min(dfixed_trunc(a), tmp);
 866
 867         lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
 868
 869         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 870         b.full = dfixed_const(1000);
 871         c.full = dfixed_const(lb_fill_bw);
 872         b.full = dfixed_div(c, b);
 873         a.full = dfixed_div(a, b);
 874         line_fill_time = dfixed_trunc(a);
 875
 876         if (line_fill_time < wm->active_time)
 877                 return latency;
 878         else
 879                 return latency + (line_fill_time - wm->active_time);
 880
 881 }
 882
 883 /**
 884  * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check
 885  * average and available dram bandwidth
 886  *
 887  * @wm: watermark calculation data
 888  *
 889  * Check if the display average bandwidth fits in the display
 890  * dram bandwidth (CIK).
 891  * Used for display watermark bandwidth calculations
 892  * Returns true if the display fits, false if not.
 893  */
 894 static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
 895 {
 896         if (dce_v6_0_average_bandwidth(wm) <=
 897             (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads))
 898                 return true;
 899         else
 900                 return false;
 901 }
 902
 903 /**
 904  * dce_v6_0_average_bandwidth_vs_available_bandwidth - check
 905  * average and available bandwidth
 906  *
 907  * @wm: watermark calculation data
 908  *
 909  * Check if the display average bandwidth fits in the display
 910  * available bandwidth (CIK).
 911  * Used for display watermark bandwidth calculations
 912  * Returns true if the display fits, false if not.
 913  */
 914 static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
 915 {
 916         if (dce_v6_0_average_bandwidth(wm) <=
 917             (dce_v6_0_available_bandwidth(wm) / wm->num_heads))
 918                 return true;
 919         else
 920                 return false;
 921 }
 922
 923 /**
 924  * dce_v6_0_check_latency_hiding - check latency hiding
 925  *
 926  * @wm: watermark calculation data
 927  *
 928  * Check latency hiding (CIK).
 929  * Used for display watermark bandwidth calculations
 930  * Returns true if the display fits, false if not.
 931  */
 932 static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm)
 933 {
 934         u32 lb_partitions = wm->lb_size / wm->src_width;
 935         u32 line_time = wm->active_time + wm->blank_time;
 936         u32 latency_tolerant_lines;
 937         u32 latency_hiding;
 938         fixed20_12 a;
 939
 940         a.full = dfixed_const(1);
 941         if (wm->vsc.full > a.full)
 942                 latency_tolerant_lines = 1;
 943         else {
 944                 if (lb_partitions <= (wm->vtaps + 1))
 945                         latency_tolerant_lines = 1;
 946                 else
 947                         latency_tolerant_lines = 2;
 948         }
 949
 950         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 951
 952         if (dce_v6_0_latency_watermark(wm) <= latency_hiding)
 953                 return true;
 954         else
 955                 return false;
 956 }
 957
 958 /**
 959  * dce_v6_0_program_watermarks - program display watermarks
 960  *
 961  * @adev: amdgpu_device pointer
 962  * @amdgpu_crtc: the selected display controller
 963  * @lb_size: line buffer size
 964  * @num_heads: number of display controllers in use
 965  *
 966  * Calculate and program the display watermarks for the
 967  * selected display controller (CIK).
 968  */
 969 static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
 970                                         struct amdgpu_crtc *amdgpu_crtc,
 971                                         u32 lb_size, u32 num_heads)
 972 {
 973         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
 974         struct dce6_wm_params wm_low, wm_high;
 975         u32 dram_channels;
 976         u32 active_time;
 977         u32 line_time = 0;
 978         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 979         u32 priority_a_mark = 0, priority_b_mark = 0;
 980         u32 priority_a_cnt = PRIORITY_OFF;
 981         u32 priority_b_cnt = PRIORITY_OFF;
 982         u32 tmp, arb_control3;
 983         fixed20_12 a, b, c;
 984
 985         if (amdgpu_crtc->base.enabled && num_heads && mode) {
 986                 active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
 987                 line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
 988                 priority_a_cnt = 0;
 989                 priority_b_cnt = 0;
 990
 991                 dram_channels = si_get_number_of_dram_channels(adev);
 992
 993                 /* watermark for high clocks */
 994                 if (adev->pm.dpm_enabled) {
 995                         wm_high.yclk =
 996                                 amdgpu_dpm_get_mclk(adev, false) * 10;
 997                         wm_high.sclk =
 998                                 amdgpu_dpm_get_sclk(adev, false) * 10;
 999                 } else {
1000                         wm_high.yclk = adev->pm.current_mclk * 10;
1001                         wm_high.sclk = adev->pm.current_sclk * 10;
1002                 }
1003
1004                 wm_high.disp_clk = mode->clock;
1005                 wm_high.src_width = mode->crtc_hdisplay;
1006                 wm_high.active_time = active_time;
1007                 wm_high.blank_time = line_time - wm_high.active_time;
1008                 wm_high.interlaced = false;
1009                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1010                         wm_high.interlaced = true;
1011                 wm_high.vsc = amdgpu_crtc->vsc;
1012                 wm_high.vtaps = 1;
1013                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1014                         wm_high.vtaps = 2;
1015                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1016                 wm_high.lb_size = lb_size;
1017                 wm_high.dram_channels = dram_channels;
1018                 wm_high.num_heads = num_heads;
1019
1020                 if (adev->pm.dpm_enabled) {
1021                 /* watermark for low clocks */
1022                         wm_low.yclk =
1023                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1024                         wm_low.sclk =
1025                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1026                 } else {
1027                         wm_low.yclk = adev->pm.current_mclk * 10;
1028                         wm_low.sclk = adev->pm.current_sclk * 10;
1029                 }
1030
1031                 wm_low.disp_clk = mode->clock;
1032                 wm_low.src_width = mode->crtc_hdisplay;
1033                 wm_low.active_time = active_time;
1034                 wm_low.blank_time = line_time - wm_low.active_time;
1035                 wm_low.interlaced = false;
1036                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1037                         wm_low.interlaced = true;
1038                 wm_low.vsc = amdgpu_crtc->vsc;
1039                 wm_low.vtaps = 1;
1040                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1041                         wm_low.vtaps = 2;
1042                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1043                 wm_low.lb_size = lb_size;
1044                 wm_low.dram_channels = dram_channels;
1045                 wm_low.num_heads = num_heads;
1046
1047                 /* set for high clocks */
1048                 latency_watermark_a = min(dce_v6_0_latency_watermark(&wm_high), (u32)65535);
1049                 /* set for low clocks */
1050                 latency_watermark_b = min(dce_v6_0_latency_watermark(&wm_low), (u32)65535);
1051
1052                 /* possibly force display priority to high */
1053                 /* should really do this at mode validation time... */
1054                 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1055                     !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1056                     !dce_v6_0_check_latency_hiding(&wm_high) ||
1057                     (adev->mode_info.disp_priority == 2)) {
1058                         DRM_DEBUG_KMS("force priority to high\n");
1059                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
1060                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
1061                 }
1062                 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1063                     !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1064                     !dce_v6_0_check_latency_hiding(&wm_low) ||
1065                     (adev->mode_info.disp_priority == 2)) {
1066                         DRM_DEBUG_KMS("force priority to high\n");
1067                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
1068                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
1069                 }
1070
1071                 a.full = dfixed_const(1000);
1072                 b.full = dfixed_const(mode->clock);
1073                 b.full = dfixed_div(b, a);
1074                 c.full = dfixed_const(latency_watermark_a);
1075                 c.full = dfixed_mul(c, b);
1076                 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
1077                 c.full = dfixed_div(c, a);
1078                 a.full = dfixed_const(16);
1079                 c.full = dfixed_div(c, a);
1080                 priority_a_mark = dfixed_trunc(c);
1081                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
1082
1083                 a.full = dfixed_const(1000);
1084                 b.full = dfixed_const(mode->clock);
1085                 b.full = dfixed_div(b, a);
1086                 c.full = dfixed_const(latency_watermark_b);
1087                 c.full = dfixed_mul(c, b);
1088                 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
1089                 c.full = dfixed_div(c, a);
1090                 a.full = dfixed_const(16);
1091                 c.full = dfixed_div(c, a);
1092                 priority_b_mark = dfixed_trunc(c);
1093                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
1094         }
1095
1096         /* select wm A */
1097         arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
1098         tmp = arb_control3;
1099         tmp &= ~LATENCY_WATERMARK_MASK(3);
1100         tmp |= LATENCY_WATERMARK_MASK(1);
1101         WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
1102         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1103                ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT)  |
1104                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1105         /* select wm B */
1106         tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
1107         tmp &= ~LATENCY_WATERMARK_MASK(3);
1108         tmp |= LATENCY_WATERMARK_MASK(2);
1109         WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
1110         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1111                ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1112                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1113         /* restore original selection */
1114         WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);
1115
1116         /* write the priority marks */
1117         WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);
1118         WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);
1119
1120         /* save values for DPM */
1121         amdgpu_crtc->line_time = line_time;
1122         amdgpu_crtc->wm_high = latency_watermark_a;
1123 }
1124
1125 /* watermark setup */
1126 static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
1127                                    struct amdgpu_crtc *amdgpu_crtc,
1128                                    struct drm_display_mode *mode,
1129                                    struct drm_display_mode *other_mode)
1130 {
1131         u32 tmp, buffer_alloc, i;
1132         u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
1133         /*
1134          * Line Buffer Setup
1135          * There are 3 line buffers, each one shared by 2 display controllers.
1136          * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between
1137          * the display controllers.  The paritioning is done via one of four
1138          * preset allocations specified in bits 21:20:
1139          *  0 - half lb
1140          *  2 - whole lb, other crtc must be disabled
1141          */
1142         /* this can get tricky if we have two large displays on a paired group
1143          * of crtcs.  Ideally for multiple large displays we'd assign them to
1144          * non-linked crtcs for maximum line buffer allocation.
1145          */
1146         if (amdgpu_crtc->base.enabled && mode) {
1147                 if (other_mode) {
1148                         tmp = 0; /* 1/2 */
1149                         buffer_alloc = 1;
1150                 } else {
1151                         tmp = 2; /* whole */
1152                         buffer_alloc = 2;
1153                 }
1154         } else {
1155                 tmp = 0;
1156                 buffer_alloc = 0;
1157         }
1158
1159         WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,
1160                DC_LB_MEMORY_CONFIG(tmp));
1161
1162         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1163                (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
1164         for (i = 0; i < adev->usec_timeout; i++) {
1165                 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
1166                     PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
1167                         break;
1168                 udelay(1);
1169         }
1170
1171         if (amdgpu_crtc->base.enabled && mode) {
1172                 switch (tmp) {
1173                 case 0:
1174                 default:
1175                         return 4096 * 2;
1176                 case 2:
1177                         return 8192 * 2;
1178                 }
1179         }
1180
1181         /* controller not enabled, so no lb used */
1182         return 0;
1183 }
1184
1185
1186 /**
1187  *
1188  * dce_v6_0_bandwidth_update - program display watermarks
1189  *
1190  * @adev: amdgpu_device pointer
1191  *
1192  * Calculate and program the display watermarks and line
1193  * buffer allocation (CIK).
1194  */
1195 static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev)
1196 {
1197         struct drm_display_mode *mode0 = NULL;
1198         struct drm_display_mode *mode1 = NULL;
1199         u32 num_heads = 0, lb_size;
1200         int i;
1201
1202         if (!adev->mode_info.mode_config_initialized)
1203                 return;
1204
1205         amdgpu_update_display_priority(adev);
1206
1207         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1208                 if (adev->mode_info.crtcs[i]->base.enabled)
1209                         num_heads++;
1210         }
1211         for (i = 0; i < adev->mode_info.num_crtc; i += 2) {
1212                 mode0 = &adev->mode_info.crtcs[i]->base.mode;
1213                 mode1 = &adev->mode_info.crtcs[i+1]->base.mode;
1214                 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1);
1215                 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads);
1216                 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0);
1217                 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads);
1218         }
1219 }
1220 /*
1221 static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev)
1222 {
1223         int i;
1224         u32 offset, tmp;
1225
1226         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1227                 offset = adev->mode_info.audio.pin[i].offset;
1228                 tmp = RREG32_AUDIO_ENDPT(offset,
1229                                       AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1230                 if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
1231                         adev->mode_info.audio.pin[i].connected = false;
1232                 else
1233                         adev->mode_info.audio.pin[i].connected = true;
1234         }
1235
1236 }
1237
1238 static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev)
1239 {
1240         int i;
1241
1242         dce_v6_0_audio_get_connected_pins(adev);
1243
1244         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1245                 if (adev->mode_info.audio.pin[i].connected)
1246                         return &adev->mode_info.audio.pin[i];
1247         }
1248         DRM_ERROR("No connected audio pins found!\n");
1249         return NULL;
1250 }
1251
1252 static void dce_v6_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1253 {
1254         struct amdgpu_device *adev = encoder->dev->dev_private;
1255         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1256         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1257         u32 offset;
1258
1259         if (!dig || !dig->afmt || !dig->afmt->pin)
1260                 return;
1261
1262         offset = dig->afmt->offset;
1263
1264         WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
1265                AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
1266
1267 }
1268
1269 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder,
1270                                                 struct drm_display_mode *mode)
1271 {
1272         DRM_INFO("xxxx: dce_v6_0_audio_write_latency_fields---no imp!!!!!\n");
1273 }
1274
1275 static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1276 {
1277         DRM_INFO("xxxx: dce_v6_0_audio_write_speaker_allocation---no imp!!!!!\n");
1278 }
1279
1280 static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)
1281 {
1282         DRM_INFO("xxxx: dce_v6_0_audio_write_sad_regs---no imp!!!!!\n");
1283
1284 }
1285 */
1286 static void dce_v6_0_audio_enable(struct amdgpu_device *adev,
1287                                   struct amdgpu_audio_pin *pin,
1288                                   bool enable)
1289 {
1290         DRM_INFO("xxxx: dce_v6_0_audio_enable---no imp!!!!!\n");
1291 }
1292
1293 static const u32 pin_offsets[7] =
1294 {
1295         (0x1780 - 0x1780),
1296         (0x1786 - 0x1780),
1297         (0x178c - 0x1780),
1298         (0x1792 - 0x1780),
1299         (0x1798 - 0x1780),
1300         (0x179d - 0x1780),
1301         (0x17a4 - 0x1780),
1302 };
1303
1304 static int dce_v6_0_audio_init(struct amdgpu_device *adev)
1305 {
1306         return 0;
1307 }
1308
1309 static void dce_v6_0_audio_fini(struct amdgpu_device *adev)
1310 {
1311
1312 }
1313
1314 /*
1315 static void dce_v6_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1316 {
1317         DRM_INFO("xxxx: dce_v6_0_afmt_update_ACR---no imp!!!!!\n");
1318 }
1319 */
1320 /*
1321  * build a HDMI Video Info Frame
1322  */
1323 /*
1324 static void dce_v6_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1325                                                void *buffer, size_t size)
1326 {
1327         DRM_INFO("xxxx: dce_v6_0_afmt_update_avi_infoframe---no imp!!!!!\n");
1328 }
1329
1330 static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1331 {
1332         DRM_INFO("xxxx: dce_v6_0_audio_set_dto---no imp!!!!!\n");
1333 }
1334 */
1335 /*
1336  * update the info frames with the data from the current display mode
1337  */
1338 static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder,
1339                                   struct drm_display_mode *mode)
1340 {
1341         DRM_INFO("xxxx: dce_v6_0_afmt_setmode ----no impl !!!!!!!!\n");
1342 }
1343
1344 static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1345 {
1346         struct drm_device *dev = encoder->dev;
1347         struct amdgpu_device *adev = dev->dev_private;
1348         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1349         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1350
1351         if (!dig || !dig->afmt)
1352                 return;
1353
1354         /* Silent, r600_hdmi_enable will raise WARN for us */
1355         if (enable && dig->afmt->enabled)
1356                 return;
1357         if (!enable && !dig->afmt->enabled)
1358                 return;
1359
1360         if (!enable && dig->afmt->pin) {
1361                 dce_v6_0_audio_enable(adev, dig->afmt->pin, false);
1362                 dig->afmt->pin = NULL;
1363         }
1364
1365         dig->afmt->enabled = enable;
1366
1367         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1368                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1369 }
1370
1371 static int dce_v6_0_afmt_init(struct amdgpu_device *adev)
1372 {
1373         int i, j;
1374
1375         for (i = 0; i < adev->mode_info.num_dig; i++)
1376                 adev->mode_info.afmt[i] = NULL;
1377
1378         /* DCE6 has audio blocks tied to DIG encoders */
1379         for (i = 0; i < adev->mode_info.num_dig; i++) {
1380                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1381                 if (adev->mode_info.afmt[i]) {
1382                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1383                         adev->mode_info.afmt[i]->id = i;
1384                 } else {
1385                         for (j = 0; j < i; j++) {
1386                                 kfree(adev->mode_info.afmt[j]);
1387                                 adev->mode_info.afmt[j] = NULL;
1388                         }
1389                         DRM_ERROR("Out of memory allocating afmt table\n");
1390                         return -ENOMEM;
1391                 }
1392         }
1393         return 0;
1394 }
1395
1396 static void dce_v6_0_afmt_fini(struct amdgpu_device *adev)
1397 {
1398         int i;
1399
1400         for (i = 0; i < adev->mode_info.num_dig; i++) {
1401                 kfree(adev->mode_info.afmt[i]);
1402                 adev->mode_info.afmt[i] = NULL;
1403         }
1404 }
1405
1406 static const u32 vga_control_regs[6] =
1407 {
1408         mmD1VGA_CONTROL,
1409         mmD2VGA_CONTROL,
1410         mmD3VGA_CONTROL,
1411         mmD4VGA_CONTROL,
1412         mmD5VGA_CONTROL,
1413         mmD6VGA_CONTROL,
1414 };
1415
1416 static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
1417 {
1418         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1419         struct drm_device *dev = crtc->dev;
1420         struct amdgpu_device *adev = dev->dev_private;
1421         u32 vga_control;
1422
1423         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1424         WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));
1425 }
1426
1427 static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
1428 {
1429         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1430         struct drm_device *dev = crtc->dev;
1431         struct amdgpu_device *adev = dev->dev_private;
1432
1433         WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
1434 }
1435
1436 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
1437                                      struct drm_framebuffer *fb,
1438                                      int x, int y, int atomic)
1439 {
1440         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1441         struct drm_device *dev = crtc->dev;
1442         struct amdgpu_device *adev = dev->dev_private;
1443         struct amdgpu_framebuffer *amdgpu_fb;
1444         struct drm_framebuffer *target_fb;
1445         struct drm_gem_object *obj;
1446         struct amdgpu_bo *abo;
1447         uint64_t fb_location, tiling_flags;
1448         uint32_t fb_format, fb_pitch_pixels, pipe_config;
1449         u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE);
1450         u32 viewport_w, viewport_h;
1451         int r;
1452         bool bypass_lut = false;
1453         struct drm_format_name_buf format_name;
1454
1455         /* no fb bound */
1456         if (!atomic && !crtc->primary->fb) {
1457                 DRM_DEBUG_KMS("No FB bound\n");
1458                 return 0;
1459         }
1460
1461         if (atomic) {
1462                 amdgpu_fb = to_amdgpu_framebuffer(fb);
1463                 target_fb = fb;
1464         } else {
1465                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1466                 target_fb = crtc->primary->fb;
1467         }
1468
1469         /* If atomic, assume fb object is pinned & idle & fenced and
1470          * just update base pointers
1471          */
1472         obj = amdgpu_fb->obj;
1473         abo = gem_to_amdgpu_bo(obj);
1474         r = amdgpu_bo_reserve(abo, false);
1475         if (unlikely(r != 0))
1476                 return r;
1477
1478         if (atomic) {
1479                 fb_location = amdgpu_bo_gpu_offset(abo);
1480         } else {
1481                 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1482                 if (unlikely(r != 0)) {
1483                         amdgpu_bo_unreserve(abo);
1484                         return -EINVAL;
1485                 }
1486         }
1487
1488         amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1489         amdgpu_bo_unreserve(abo);
1490
1491         switch (target_fb->format->format) {
1492         case DRM_FORMAT_C8:
1493                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) |
1494                              GRPH_FORMAT(GRPH_FORMAT_INDEXED));
1495                 break;
1496         case DRM_FORMAT_XRGB4444:
1497         case DRM_FORMAT_ARGB4444:
1498                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1499                              GRPH_FORMAT(GRPH_FORMAT_ARGB4444));
1500 #ifdef __BIG_ENDIAN
1501                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1502 #endif
1503                 break;
1504         case DRM_FORMAT_XRGB1555:
1505         case DRM_FORMAT_ARGB1555:
1506                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1507                              GRPH_FORMAT(GRPH_FORMAT_ARGB1555));
1508 #ifdef __BIG_ENDIAN
1509                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1510 #endif
1511                 break;
1512         case DRM_FORMAT_BGRX5551:
1513         case DRM_FORMAT_BGRA5551:
1514                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1515                              GRPH_FORMAT(GRPH_FORMAT_BGRA5551));
1516 #ifdef __BIG_ENDIAN
1517                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1518 #endif
1519                 break;
1520         case DRM_FORMAT_RGB565:
1521                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1522                              GRPH_FORMAT(GRPH_FORMAT_ARGB565));
1523 #ifdef __BIG_ENDIAN
1524                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1525 #endif
1526                 break;
1527         case DRM_FORMAT_XRGB8888:
1528         case DRM_FORMAT_ARGB8888:
1529                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1530                              GRPH_FORMAT(GRPH_FORMAT_ARGB8888));
1531 #ifdef __BIG_ENDIAN
1532                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1533 #endif
1534                 break;
1535         case DRM_FORMAT_XRGB2101010:
1536         case DRM_FORMAT_ARGB2101010:
1537                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1538                              GRPH_FORMAT(GRPH_FORMAT_ARGB2101010));
1539 #ifdef __BIG_ENDIAN
1540                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1541 #endif
1542                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1543                 bypass_lut = true;
1544                 break;
1545         case DRM_FORMAT_BGRX1010102:
1546         case DRM_FORMAT_BGRA1010102:
1547                 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1548                              GRPH_FORMAT(GRPH_FORMAT_BGRA1010102));
1549 #ifdef __BIG_ENDIAN
1550                 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1551 #endif
1552                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1553                 bypass_lut = true;
1554                 break;
1555         default:
1556                 DRM_ERROR("Unsupported screen format %s\n",
1557                           drm_get_format_name(target_fb->format->format, &format_name));
1558                 return -EINVAL;
1559         }
1560
1561         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1562                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1563
1564                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1565                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1566                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1567                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1568                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1569
1570                 fb_format |= GRPH_NUM_BANKS(num_banks);
1571                 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1);
1572                 fb_format |= GRPH_TILE_SPLIT(tile_split);
1573                 fb_format |= GRPH_BANK_WIDTH(bankw);
1574                 fb_format |= GRPH_BANK_HEIGHT(bankh);
1575                 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect);
1576         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1577                 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1);
1578         }
1579
1580         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1581         fb_format |= GRPH_PIPE_CONFIG(pipe_config);
1582
1583         dce_v6_0_vga_enable(crtc, false);
1584
1585         /* Make sure surface address is updated at vertical blank rather than
1586          * horizontal blank
1587          */
1588         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1589
1590         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1591                upper_32_bits(fb_location));
1592         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1593                upper_32_bits(fb_location));
1594         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1595                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1596         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1597                (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1598         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1599         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1600
1601         /*
1602          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1603          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1604          * retain the full precision throughout the pipeline.
1605          */
1606         WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset,
1607                  (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0),
1608                  ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK);
1609
1610         if (bypass_lut)
1611                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1612
1613         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1614         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1615         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1616         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1617         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1618         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1619
1620         fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1621         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1622
1623         dce_v6_0_grph_enable(crtc, true);
1624
1625         WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1626                        target_fb->height);
1627         x &= ~3;
1628         y &= ~1;
1629         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
1630                (x << 16) | y);
1631         viewport_w = crtc->mode.hdisplay;
1632         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1633
1634         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
1635                (viewport_w << 16) | viewport_h);
1636
1637         /* set pageflip to happen anywhere in vblank interval */
1638         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
1639
1640         if (!atomic && fb && fb != crtc->primary->fb) {
1641                 amdgpu_fb = to_amdgpu_framebuffer(fb);
1642                 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1643                 r = amdgpu_bo_reserve(abo, false);
1644                 if (unlikely(r != 0))
1645                         return r;
1646                 amdgpu_bo_unpin(abo);
1647                 amdgpu_bo_unreserve(abo);
1648         }
1649
1650         /* Bytes per pixel may have changed */
1651         dce_v6_0_bandwidth_update(adev);
1652
1653         return 0;
1654
1655 }
1656
1657 static void dce_v6_0_set_interleave(struct drm_crtc *crtc,
1658                                     struct drm_display_mode *mode)
1659 {
1660         struct drm_device *dev = crtc->dev;
1661         struct amdgpu_device *adev = dev->dev_private;
1662         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1663
1664         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1665                 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset,
1666                        INTERLEAVE_EN);
1667         else
1668                 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
1669 }
1670
1671 static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)
1672 {
1673
1674         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1675         struct drm_device *dev = crtc->dev;
1676         struct amdgpu_device *adev = dev->dev_private;
1677         int i;
1678
1679         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
1680
1681         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
1682                ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
1683                 (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
1684         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
1685                PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
1686         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
1687                PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
1688         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1689                ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
1690                 (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
1691
1692         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
1693
1694         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
1695         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
1696         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
1697
1698         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
1699         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
1700         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
1701
1702         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
1703         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
1704
1705         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
1706         for (i = 0; i < 256; i++) {
1707                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
1708                        (amdgpu_crtc->lut_r[i] << 20) |
1709                        (amdgpu_crtc->lut_g[i] << 10) |
1710                        (amdgpu_crtc->lut_b[i] << 0));
1711         }
1712
1713         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1714                ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
1715                 (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
1716                 ICON_DEGAMMA_MODE(0) |
1717                 (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
1718         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
1719                ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
1720                 (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
1721         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1722                ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
1723                 (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
1724         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
1725                ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
1726                 (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
1727         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
1728         WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
1729
1730
1731 }
1732
1733 static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder)
1734 {
1735         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1736         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1737
1738         switch (amdgpu_encoder->encoder_id) {
1739         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1740                 return dig->linkb ? 1 : 0;
1741         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1742                 return dig->linkb ? 3 : 2;
1743         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1744                 return dig->linkb ? 5 : 4;
1745         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1746                 return 6;
1747         default:
1748                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
1749                 return 0;
1750         }
1751 }
1752
1753 /**
1754  * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc.
1755  *
1756  * @crtc: drm crtc
1757  *
1758  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
1759  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
1760  * monitors a dedicated PPLL must be used.  If a particular board has
1761  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1762  * as there is no need to program the PLL itself.  If we are not able to
1763  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1764  * avoid messing up an existing monitor.
1765  *
1766  *
1767  */
1768 static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc)
1769 {
1770         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1771         struct drm_device *dev = crtc->dev;
1772         struct amdgpu_device *adev = dev->dev_private;
1773         u32 pll_in_use;
1774         int pll;
1775
1776         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
1777                 if (adev->clock.dp_extclk)
1778                         /* skip PPLL programming if using ext clock */
1779                         return ATOM_PPLL_INVALID;
1780                 else
1781                         return ATOM_PPLL0;
1782         } else {
1783                 /* use the same PPLL for all monitors with the same clock */
1784                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
1785                 if (pll != ATOM_PPLL_INVALID)
1786                         return pll;
1787         }
1788
1789         /*  PPLL1, and PPLL2 */
1790         pll_in_use = amdgpu_pll_get_use_mask(crtc);
1791         if (!(pll_in_use & (1 << ATOM_PPLL2)))
1792                 return ATOM_PPLL2;
1793         if (!(pll_in_use & (1 << ATOM_PPLL1)))
1794                 return ATOM_PPLL1;
1795         DRM_ERROR("unable to allocate a PPLL\n");
1796         return ATOM_PPLL_INVALID;
1797 }
1798
1799 static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock)
1800 {
1801         struct amdgpu_device *adev = crtc->dev->dev_private;
1802         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1803         uint32_t cur_lock;
1804
1805         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
1806         if (lock)
1807                 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
1808         else
1809                 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
1810         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
1811 }
1812
1813 static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
1814 {
1815         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1816         struct amdgpu_device *adev = crtc->dev->dev_private;
1817
1818         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
1819                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
1820                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
1821
1822
1823 }
1824
1825 static void dce_v6_0_show_cursor(struct drm_crtc *crtc)
1826 {
1827         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1828         struct amdgpu_device *adev = crtc->dev->dev_private;
1829
1830         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1831                upper_32_bits(amdgpu_crtc->cursor_addr));
1832         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1833                lower_32_bits(amdgpu_crtc->cursor_addr));
1834
1835         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
1836                    CUR_CONTROL__CURSOR_EN_MASK |
1837                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
1838                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
1839
1840 }
1841
1842 static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,
1843                                        int x, int y)
1844 {
1845         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1846         struct amdgpu_device *adev = crtc->dev->dev_private;
1847         int xorigin = 0, yorigin = 0;
1848
1849         int w = amdgpu_crtc->cursor_width;
1850
1851         amdgpu_crtc->cursor_x = x;
1852         amdgpu_crtc->cursor_y = y;
1853
1854         /* avivo cursor are offset into the total surface */
1855         x += crtc->x;
1856         y += crtc->y;
1857         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
1858
1859         if (x < 0) {
1860                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
1861                 x = 0;
1862         }
1863         if (y < 0) {
1864                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
1865                 y = 0;
1866         }
1867
1868         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
1869         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
1870         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
1871                ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
1872
1873         return 0;
1874 }
1875
1876 static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc,
1877                                      int x, int y)
1878 {
1879         int ret;
1880
1881         dce_v6_0_lock_cursor(crtc, true);
1882         ret = dce_v6_0_cursor_move_locked(crtc, x, y);
1883         dce_v6_0_lock_cursor(crtc, false);
1884
1885         return ret;
1886 }
1887
1888 static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
1889                                      struct drm_file *file_priv,
1890                                      uint32_t handle,
1891                                      uint32_t width,
1892                                      uint32_t height,
1893                                      int32_t hot_x,
1894                                      int32_t hot_y)
1895 {
1896         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1897         struct drm_gem_object *obj;
1898         struct amdgpu_bo *aobj;
1899         int ret;
1900
1901         if (!handle) {
1902                 /* turn off cursor */
1903                 dce_v6_0_hide_cursor(crtc);
1904                 obj = NULL;
1905                 goto unpin;
1906         }
1907
1908         if ((width > amdgpu_crtc->max_cursor_width) ||
1909             (height > amdgpu_crtc->max_cursor_height)) {
1910                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
1911                 return -EINVAL;
1912         }
1913
1914         obj = drm_gem_object_lookup(file_priv, handle);
1915         if (!obj) {
1916                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
1917                 return -ENOENT;
1918         }
1919
1920         aobj = gem_to_amdgpu_bo(obj);
1921         ret = amdgpu_bo_reserve(aobj, false);
1922         if (ret != 0) {
1923                 drm_gem_object_unreference_unlocked(obj);
1924                 return ret;
1925         }
1926
1927         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
1928         amdgpu_bo_unreserve(aobj);
1929         if (ret) {
1930                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
1931                 drm_gem_object_unreference_unlocked(obj);
1932                 return ret;
1933         }
1934
1935         dce_v6_0_lock_cursor(crtc, true);
1936
1937         if (width != amdgpu_crtc->cursor_width ||
1938             height != amdgpu_crtc->cursor_height ||
1939             hot_x != amdgpu_crtc->cursor_hot_x ||
1940             hot_y != amdgpu_crtc->cursor_hot_y) {
1941                 int x, y;
1942
1943                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
1944                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
1945
1946                 dce_v6_0_cursor_move_locked(crtc, x, y);
1947
1948                 amdgpu_crtc->cursor_width = width;
1949                 amdgpu_crtc->cursor_height = height;
1950                 amdgpu_crtc->cursor_hot_x = hot_x;
1951                 amdgpu_crtc->cursor_hot_y = hot_y;
1952         }
1953
1954         dce_v6_0_show_cursor(crtc);
1955         dce_v6_0_lock_cursor(crtc, false);
1956
1957 unpin:
1958         if (amdgpu_crtc->cursor_bo) {
1959                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1960                 ret = amdgpu_bo_reserve(aobj, false);
1961                 if (likely(ret == 0)) {
1962                         amdgpu_bo_unpin(aobj);
1963                         amdgpu_bo_unreserve(aobj);
1964                 }
1965                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
1966         }
1967
1968         amdgpu_crtc->cursor_bo = obj;
1969         return 0;
1970 }
1971
1972 static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
1973 {
1974         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1975
1976         if (amdgpu_crtc->cursor_bo) {
1977                 dce_v6_0_lock_cursor(crtc, true);
1978
1979                 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
1980                                             amdgpu_crtc->cursor_y);
1981
1982                 dce_v6_0_show_cursor(crtc);
1983                 dce_v6_0_lock_cursor(crtc, false);
1984         }
1985 }
1986
1987 static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1988                                    u16 *blue, uint32_t size,
1989                                    struct drm_modeset_acquire_ctx *ctx)
1990 {
1991         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1992         int i;
1993
1994         /* userspace palettes are always correct as is */
1995         for (i = 0; i < size; i++) {
1996                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
1997                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
1998                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
1999         }
2000         dce_v6_0_crtc_load_lut(crtc);
2001
2002         return 0;
2003 }
2004
2005 static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc)
2006 {
2007         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2008
2009         drm_crtc_cleanup(crtc);
2010         kfree(amdgpu_crtc);
2011 }
2012
2013 static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = {
2014         .cursor_set2 = dce_v6_0_crtc_cursor_set2,
2015         .cursor_move = dce_v6_0_crtc_cursor_move,
2016         .gamma_set = dce_v6_0_crtc_gamma_set,
2017         .set_config = amdgpu_crtc_set_config,
2018         .destroy = dce_v6_0_crtc_destroy,
2019         .page_flip_target = amdgpu_crtc_page_flip_target,
2020 };
2021
2022 static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2023 {
2024         struct drm_device *dev = crtc->dev;
2025         struct amdgpu_device *adev = dev->dev_private;
2026         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2027         unsigned type;
2028
2029         switch (mode) {
2030         case DRM_MODE_DPMS_ON:
2031                 amdgpu_crtc->enabled = true;
2032                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2033                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2034                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2035                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2036                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2037                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2038                 drm_crtc_vblank_on(crtc);
2039                 dce_v6_0_crtc_load_lut(crtc);
2040                 break;
2041         case DRM_MODE_DPMS_STANDBY:
2042         case DRM_MODE_DPMS_SUSPEND:
2043         case DRM_MODE_DPMS_OFF:
2044                 drm_crtc_vblank_off(crtc);
2045                 if (amdgpu_crtc->enabled)
2046                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2047                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2048                 amdgpu_crtc->enabled = false;
2049                 break;
2050         }
2051         /* adjust pm to dpms */
2052         amdgpu_pm_compute_clocks(adev);
2053 }
2054
2055 static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc)
2056 {
2057         /* disable crtc pair power gating before programming */
2058         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2059         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2060         dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2061 }
2062
2063 static void dce_v6_0_crtc_commit(struct drm_crtc *crtc)
2064 {
2065         dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2066         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2067 }
2068
2069 static void dce_v6_0_crtc_disable(struct drm_crtc *crtc)
2070 {
2071
2072         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2073         struct drm_device *dev = crtc->dev;
2074         struct amdgpu_device *adev = dev->dev_private;
2075         struct amdgpu_atom_ss ss;
2076         int i;
2077
2078         dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2079         if (crtc->primary->fb) {
2080                 int r;
2081                 struct amdgpu_framebuffer *amdgpu_fb;
2082                 struct amdgpu_bo *abo;
2083
2084                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2085                 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2086                 r = amdgpu_bo_reserve(abo, false);
2087                 if (unlikely(r))
2088                         DRM_ERROR("failed to reserve abo before unpin\n");
2089                 else {
2090                         amdgpu_bo_unpin(abo);
2091                         amdgpu_bo_unreserve(abo);
2092                 }
2093         }
2094         /* disable the GRPH */
2095         dce_v6_0_grph_enable(crtc, false);
2096
2097         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2098
2099         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2100                 if (adev->mode_info.crtcs[i] &&
2101                     adev->mode_info.crtcs[i]->enabled &&
2102                     i != amdgpu_crtc->crtc_id &&
2103                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2104                         /* one other crtc is using this pll don't turn
2105                          * off the pll
2106                          */
2107                         goto done;
2108                 }
2109         }
2110
2111         switch (amdgpu_crtc->pll_id) {
2112         case ATOM_PPLL1:
2113         case ATOM_PPLL2:
2114                 /* disable the ppll */
2115                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2116                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2117                 break;
2118         default:
2119                 break;
2120         }
2121 done:
2122         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2123         amdgpu_crtc->adjusted_clock = 0;
2124         amdgpu_crtc->encoder = NULL;
2125         amdgpu_crtc->connector = NULL;
2126 }
2127
2128 static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc,
2129                                   struct drm_display_mode *mode,
2130                                   struct drm_display_mode *adjusted_mode,
2131                                   int x, int y, struct drm_framebuffer *old_fb)
2132 {
2133         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2134
2135         if (!amdgpu_crtc->adjusted_clock)
2136                 return -EINVAL;
2137
2138         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2139         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2140         dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2141         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2142         amdgpu_atombios_crtc_scaler_setup(crtc);
2143         dce_v6_0_cursor_reset(crtc);
2144         /* update the hw version fpr dpm */
2145         amdgpu_crtc->hw_mode = *adjusted_mode;
2146
2147         return 0;
2148 }
2149
2150 static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc,
2151                                      const struct drm_display_mode *mode,
2152                                      struct drm_display_mode *adjusted_mode)
2153 {
2154
2155         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2156         struct drm_device *dev = crtc->dev;
2157         struct drm_encoder *encoder;
2158
2159         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2160         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2161                 if (encoder->crtc == crtc) {
2162                         amdgpu_crtc->encoder = encoder;
2163                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2164                         break;
2165                 }
2166         }
2167         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2168                 amdgpu_crtc->encoder = NULL;
2169                 amdgpu_crtc->connector = NULL;
2170                 return false;
2171         }
2172         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2173                 return false;
2174         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2175                 return false;
2176         /* pick pll */
2177         amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc);
2178         /* if we can't get a PPLL for a non-DP encoder, fail */
2179         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2180             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2181                 return false;
2182
2183         return true;
2184 }
2185
2186 static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2187                                   struct drm_framebuffer *old_fb)
2188 {
2189         return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2190 }
2191
2192 static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2193                                          struct drm_framebuffer *fb,
2194                                          int x, int y, enum mode_set_atomic state)
2195 {
2196        return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1);
2197 }
2198
2199 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = {
2200         .dpms = dce_v6_0_crtc_dpms,
2201         .mode_fixup = dce_v6_0_crtc_mode_fixup,
2202         .mode_set = dce_v6_0_crtc_mode_set,
2203         .mode_set_base = dce_v6_0_crtc_set_base,
2204         .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic,
2205         .prepare = dce_v6_0_crtc_prepare,
2206         .commit = dce_v6_0_crtc_commit,
2207         .load_lut = dce_v6_0_crtc_load_lut,
2208         .disable = dce_v6_0_crtc_disable,
2209 };
2210
2211 static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index)
2212 {
2213         struct amdgpu_crtc *amdgpu_crtc;
2214         int i;
2215
2216         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2217                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2218         if (amdgpu_crtc == NULL)
2219                 return -ENOMEM;
2220
2221         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v6_0_crtc_funcs);
2222
2223         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2224         amdgpu_crtc->crtc_id = index;
2225         adev->mode_info.crtcs[index] = amdgpu_crtc;
2226
2227         amdgpu_crtc->max_cursor_width = CURSOR_WIDTH;
2228         amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT;
2229         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2230         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2231
2232         for (i = 0; i < 256; i++) {
2233                 amdgpu_crtc->lut_r[i] = i << 2;
2234                 amdgpu_crtc->lut_g[i] = i << 2;
2235                 amdgpu_crtc->lut_b[i] = i << 2;
2236         }
2237
2238         amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2239
2240         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2241         amdgpu_crtc->adjusted_clock = 0;
2242         amdgpu_crtc->encoder = NULL;
2243         amdgpu_crtc->connector = NULL;
2244         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs);
2245
2246         return 0;
2247 }
2248
2249 static int dce_v6_0_early_init(void *handle)
2250 {
2251         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2252
2253         adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg;
2254         adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg;
2255
2256         dce_v6_0_set_display_funcs(adev);
2257         dce_v6_0_set_irq_funcs(adev);
2258
2259         adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
2260
2261         switch (adev->asic_type) {
2262         case CHIP_TAHITI:
2263         case CHIP_PITCAIRN:
2264         case CHIP_VERDE:
2265                 adev->mode_info.num_hpd = 6;
2266                 adev->mode_info.num_dig = 6;
2267                 break;
2268         case CHIP_OLAND:
2269                 adev->mode_info.num_hpd = 2;
2270                 adev->mode_info.num_dig = 2;
2271                 break;
2272         default:
2273                 return -EINVAL;
2274         }
2275
2276         return 0;
2277 }
2278
2279 static int dce_v6_0_sw_init(void *handle)
2280 {
2281         int r, i;
2282         bool ret;
2283         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2284
2285         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2286                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2287                 if (r)
2288                         return r;
2289         }
2290
2291         for (i = 8; i < 20; i += 2) {
2292                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2293                 if (r)
2294                         return r;
2295         }
2296
2297         /* HPD hotplug */
2298         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2299         if (r)
2300                 return r;
2301
2302         adev->mode_info.mode_config_initialized = true;
2303
2304         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2305         adev->ddev->mode_config.async_page_flip = true;
2306         adev->ddev->mode_config.max_width = 16384;
2307         adev->ddev->mode_config.max_height = 16384;
2308         adev->ddev->mode_config.preferred_depth = 24;
2309         adev->ddev->mode_config.prefer_shadow = 1;
2310         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2311
2312         r = amdgpu_modeset_create_props(adev);
2313         if (r)
2314                 return r;
2315
2316         adev->ddev->mode_config.max_width = 16384;
2317         adev->ddev->mode_config.max_height = 16384;
2318
2319         /* allocate crtcs */
2320         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2321                 r = dce_v6_0_crtc_init(adev, i);
2322                 if (r)
2323                         return r;
2324         }
2325
2326         ret = amdgpu_atombios_get_connector_info_from_object_table(adev);
2327         if (ret)
2328                 amdgpu_print_display_setup(adev->ddev);
2329         else
2330                 return -EINVAL;
2331
2332         /* setup afmt */
2333         r = dce_v6_0_afmt_init(adev);
2334         if (r)
2335                 return r;
2336
2337         r = dce_v6_0_audio_init(adev);
2338         if (r)
2339                 return r;
2340
2341         drm_kms_helper_poll_init(adev->ddev);
2342
2343         return r;
2344 }
2345
2346 static int dce_v6_0_sw_fini(void *handle)
2347 {
2348         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2349
2350         kfree(adev->mode_info.bios_hardcoded_edid);
2351
2352         drm_kms_helper_poll_fini(adev->ddev);
2353
2354         dce_v6_0_audio_fini(adev);
2355         dce_v6_0_afmt_fini(adev);
2356
2357         drm_mode_config_cleanup(adev->ddev);
2358         adev->mode_info.mode_config_initialized = false;
2359
2360         return 0;
2361 }
2362
2363 static int dce_v6_0_hw_init(void *handle)
2364 {
2365         int i;
2366         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2367
2368         /* init dig PHYs, disp eng pll */
2369         amdgpu_atombios_encoder_init_dig(adev);
2370         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2371
2372         /* initialize hpd */
2373         dce_v6_0_hpd_init(adev);
2374
2375         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2376                 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2377         }
2378
2379         dce_v6_0_pageflip_interrupt_init(adev);
2380
2381         return 0;
2382 }
2383
2384 static int dce_v6_0_hw_fini(void *handle)
2385 {
2386         int i;
2387         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2388
2389         dce_v6_0_hpd_fini(adev);
2390
2391         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2392                 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2393         }
2394
2395         dce_v6_0_pageflip_interrupt_fini(adev);
2396
2397         return 0;
2398 }
2399
2400 static int dce_v6_0_suspend(void *handle)
2401 {
2402         return dce_v6_0_hw_fini(handle);
2403 }
2404
2405 static int dce_v6_0_resume(void *handle)
2406 {
2407         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2408         int ret;
2409
2410         ret = dce_v6_0_hw_init(handle);
2411
2412         /* turn on the BL */
2413         if (adev->mode_info.bl_encoder) {
2414                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2415                                                                   adev->mode_info.bl_encoder);
2416                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2417                                                     bl_level);
2418         }
2419
2420         return ret;
2421 }
2422
2423 static bool dce_v6_0_is_idle(void *handle)
2424 {
2425         return true;
2426 }
2427
2428 static int dce_v6_0_wait_for_idle(void *handle)
2429 {
2430         return 0;
2431 }
2432
2433 static int dce_v6_0_soft_reset(void *handle)
2434 {
2435         DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n");
2436         return 0;
2437 }
2438
2439 static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2440                                                      int crtc,
2441                                                      enum amdgpu_interrupt_state state)
2442 {
2443         u32 reg_block, interrupt_mask;
2444
2445         if (crtc >= adev->mode_info.num_crtc) {
2446                 DRM_DEBUG("invalid crtc %d\n", crtc);
2447                 return;
2448         }
2449
2450         switch (crtc) {
2451         case 0:
2452                 reg_block = SI_CRTC0_REGISTER_OFFSET;
2453                 break;
2454         case 1:
2455                 reg_block = SI_CRTC1_REGISTER_OFFSET;
2456                 break;
2457         case 2:
2458                 reg_block = SI_CRTC2_REGISTER_OFFSET;
2459                 break;
2460         case 3:
2461                 reg_block = SI_CRTC3_REGISTER_OFFSET;
2462                 break;
2463         case 4:
2464                 reg_block = SI_CRTC4_REGISTER_OFFSET;
2465                 break;
2466         case 5:
2467                 reg_block = SI_CRTC5_REGISTER_OFFSET;
2468                 break;
2469         default:
2470                 DRM_DEBUG("invalid crtc %d\n", crtc);
2471                 return;
2472         }
2473
2474         switch (state) {
2475         case AMDGPU_IRQ_STATE_DISABLE:
2476                 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2477                 interrupt_mask &= ~VBLANK_INT_MASK;
2478                 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2479                 break;
2480         case AMDGPU_IRQ_STATE_ENABLE:
2481                 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2482                 interrupt_mask |= VBLANK_INT_MASK;
2483                 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2484                 break;
2485         default:
2486                 break;
2487         }
2488 }
2489
2490 static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2491                                                     int crtc,
2492                                                     enum amdgpu_interrupt_state state)
2493 {
2494
2495 }
2496
2497 static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2498                                             struct amdgpu_irq_src *src,
2499                                             unsigned type,
2500                                             enum amdgpu_interrupt_state state)
2501 {
2502         u32 dc_hpd_int_cntl;
2503
2504         if (type >= adev->mode_info.num_hpd) {
2505                 DRM_DEBUG("invalid hdp %d\n", type);
2506                 return 0;
2507         }
2508
2509         switch (state) {
2510         case AMDGPU_IRQ_STATE_DISABLE:
2511                 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2512                 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN;
2513                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2514                 break;
2515         case AMDGPU_IRQ_STATE_ENABLE:
2516                 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2517                 dc_hpd_int_cntl |= DC_HPDx_INT_EN;
2518                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2519                 break;
2520         default:
2521                 break;
2522         }
2523
2524         return 0;
2525 }
2526
2527 static int dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
2528                                              struct amdgpu_irq_src *src,
2529                                              unsigned type,
2530                                              enum amdgpu_interrupt_state state)
2531 {
2532         switch (type) {
2533         case AMDGPU_CRTC_IRQ_VBLANK1:
2534                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state);
2535                 break;
2536         case AMDGPU_CRTC_IRQ_VBLANK2:
2537                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state);
2538                 break;
2539         case AMDGPU_CRTC_IRQ_VBLANK3:
2540                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state);
2541                 break;
2542         case AMDGPU_CRTC_IRQ_VBLANK4:
2543                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state);
2544                 break;
2545         case AMDGPU_CRTC_IRQ_VBLANK5:
2546                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state);
2547                 break;
2548         case AMDGPU_CRTC_IRQ_VBLANK6:
2549                 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state);
2550                 break;
2551         case AMDGPU_CRTC_IRQ_VLINE1:
2552                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state);
2553                 break;
2554         case AMDGPU_CRTC_IRQ_VLINE2:
2555                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state);
2556                 break;
2557         case AMDGPU_CRTC_IRQ_VLINE3:
2558                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state);
2559                 break;
2560         case AMDGPU_CRTC_IRQ_VLINE4:
2561                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state);
2562                 break;
2563         case AMDGPU_CRTC_IRQ_VLINE5:
2564                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state);
2565                 break;
2566         case AMDGPU_CRTC_IRQ_VLINE6:
2567                 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state);
2568                 break;
2569         default:
2570                 break;
2571         }
2572         return 0;
2573 }
2574
2575 static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
2576                              struct amdgpu_irq_src *source,
2577                              struct amdgpu_iv_entry *entry)
2578 {
2579         unsigned crtc = entry->src_id - 1;
2580         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
2581         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
2582
2583         switch (entry->src_data[0]) {
2584         case 0: /* vblank */
2585                 if (disp_int & interrupt_status_offsets[crtc].vblank)
2586                         WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);
2587                 else
2588                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2589
2590                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
2591                         drm_handle_vblank(adev->ddev, crtc);
2592                 }
2593                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
2594                 break;
2595         case 1: /* vline */
2596                 if (disp_int & interrupt_status_offsets[crtc].vline)
2597                         WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);
2598                 else
2599                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2600
2601                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
2602                 break;
2603         default:
2604                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
2605                 break;
2606         }
2607
2608         return 0;
2609 }
2610
2611 static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
2612                                                  struct amdgpu_irq_src *src,
2613                                                  unsigned type,
2614                                                  enum amdgpu_interrupt_state state)
2615 {
2616         u32 reg;
2617
2618         if (type >= adev->mode_info.num_crtc) {
2619                 DRM_ERROR("invalid pageflip crtc %d\n", type);
2620                 return -EINVAL;
2621         }
2622
2623         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
2624         if (state == AMDGPU_IRQ_STATE_DISABLE)
2625                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
2626                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
2627         else
2628                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
2629                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
2630
2631         return 0;
2632 }
2633
2634 static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev,
2635                                  struct amdgpu_irq_src *source,
2636                                  struct amdgpu_iv_entry *entry)
2637 {
2638                 unsigned long flags;
2639         unsigned crtc_id;
2640         struct amdgpu_crtc *amdgpu_crtc;
2641         struct amdgpu_flip_work *works;
2642
2643         crtc_id = (entry->src_id - 8) >> 1;
2644         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
2645
2646         if (crtc_id >= adev->mode_info.num_crtc) {
2647                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
2648                 return -EINVAL;
2649         }
2650
2651         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
2652             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
2653                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
2654                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
2655
2656         /* IRQ could occur when in initial stage */
2657         if (amdgpu_crtc == NULL)
2658                 return 0;
2659
2660         spin_lock_irqsave(&adev->ddev->event_lock, flags);
2661         works = amdgpu_crtc->pflip_works;
2662         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
2663                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
2664                                                 "AMDGPU_FLIP_SUBMITTED(%d)\n",
2665                                                 amdgpu_crtc->pflip_status,
2666                                                 AMDGPU_FLIP_SUBMITTED);
2667                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
2668                 return 0;
2669         }
2670
2671         /* page flip completed. clean up */
2672         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
2673         amdgpu_crtc->pflip_works = NULL;
2674
2675         /* wakeup usersapce */
2676         if (works->event)
2677                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
2678
2679         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
2680
2681         drm_crtc_vblank_put(&amdgpu_crtc->base);
2682         schedule_work(&works->unpin_work);
2683
2684         return 0;
2685 }
2686
2687 static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
2688                             struct amdgpu_irq_src *source,
2689                             struct amdgpu_iv_entry *entry)
2690 {
2691         uint32_t disp_int, mask, tmp;
2692         unsigned hpd;
2693
2694         if (entry->src_data[0] >= adev->mode_info.num_hpd) {
2695                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
2696                 return 0;
2697         }
2698
2699         hpd = entry->src_data[0];
2700         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
2701         mask = interrupt_status_offsets[hpd].hpd;
2702
2703         if (disp_int & mask) {
2704                 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
2705                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
2706                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
2707                 schedule_work(&adev->hotplug_work);
2708                 DRM_INFO("IH: HPD%d\n", hpd + 1);
2709         }
2710
2711         return 0;
2712
2713 }
2714
2715 static int dce_v6_0_set_clockgating_state(void *handle,
2716                                           enum amd_clockgating_state state)
2717 {
2718         return 0;
2719 }
2720
2721 static int dce_v6_0_set_powergating_state(void *handle,
2722                                           enum amd_powergating_state state)
2723 {
2724         return 0;
2725 }
2726
2727 static const struct amd_ip_funcs dce_v6_0_ip_funcs = {
2728         .name = "dce_v6_0",
2729         .early_init = dce_v6_0_early_init,
2730         .late_init = NULL,
2731         .sw_init = dce_v6_0_sw_init,
2732         .sw_fini = dce_v6_0_sw_fini,
2733         .hw_init = dce_v6_0_hw_init,
2734         .hw_fini = dce_v6_0_hw_fini,
2735         .suspend = dce_v6_0_suspend,
2736         .resume = dce_v6_0_resume,
2737         .is_idle = dce_v6_0_is_idle,
2738         .wait_for_idle = dce_v6_0_wait_for_idle,
2739         .soft_reset = dce_v6_0_soft_reset,
2740         .set_clockgating_state = dce_v6_0_set_clockgating_state,
2741         .set_powergating_state = dce_v6_0_set_powergating_state,
2742 };
2743
2744 static void
2745 dce_v6_0_encoder_mode_set(struct drm_encoder *encoder,
2746                           struct drm_display_mode *mode,
2747                           struct drm_display_mode *adjusted_mode)
2748 {
2749
2750         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2751
2752         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
2753
2754         /* need to call this here rather than in prepare() since we need some crtc info */
2755         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2756
2757         /* set scaler clears this on some chips */
2758         dce_v6_0_set_interleave(encoder->crtc, mode);
2759
2760         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2761                 dce_v6_0_afmt_enable(encoder, true);
2762                 dce_v6_0_afmt_setmode(encoder, adjusted_mode);
2763         }
2764 }
2765
2766 static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder)
2767 {
2768
2769         struct amdgpu_device *adev = encoder->dev->dev_private;
2770         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2771         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
2772
2773         if ((amdgpu_encoder->active_device &
2774              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2775             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
2776              ENCODER_OBJECT_ID_NONE)) {
2777                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2778                 if (dig) {
2779                         dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder);
2780                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
2781                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
2782                 }
2783         }
2784
2785         amdgpu_atombios_scratch_regs_lock(adev, true);
2786
2787         if (connector) {
2788                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
2789
2790                 /* select the clock/data port if it uses a router */
2791                 if (amdgpu_connector->router.cd_valid)
2792                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
2793
2794                 /* turn eDP panel on for mode set */
2795                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2796                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
2797                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
2798         }
2799
2800         /* this is needed for the pll/ss setup to work correctly in some cases */
2801         amdgpu_atombios_encoder_set_crtc_source(encoder);
2802         /* set up the FMT blocks */
2803         dce_v6_0_program_fmt(encoder);
2804 }
2805
2806 static void dce_v6_0_encoder_commit(struct drm_encoder *encoder)
2807 {
2808
2809         struct drm_device *dev = encoder->dev;
2810         struct amdgpu_device *adev = dev->dev_private;
2811
2812         /* need to call this here as we need the crtc set up */
2813         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2814         amdgpu_atombios_scratch_regs_lock(adev, false);
2815 }
2816
2817 static void dce_v6_0_encoder_disable(struct drm_encoder *encoder)
2818 {
2819
2820         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2821         struct amdgpu_encoder_atom_dig *dig;
2822
2823         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2824
2825         if (amdgpu_atombios_encoder_is_digital(encoder)) {
2826                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2827                         dce_v6_0_afmt_enable(encoder, false);
2828                 dig = amdgpu_encoder->enc_priv;
2829                 dig->dig_encoder = -1;
2830         }
2831         amdgpu_encoder->active_device = 0;
2832 }
2833
2834 /* these are handled by the primary encoders */
2835 static void dce_v6_0_ext_prepare(struct drm_encoder *encoder)
2836 {
2837
2838 }
2839
2840 static void dce_v6_0_ext_commit(struct drm_encoder *encoder)
2841 {
2842
2843 }
2844
2845 static void
2846 dce_v6_0_ext_mode_set(struct drm_encoder *encoder,
2847                       struct drm_display_mode *mode,
2848                       struct drm_display_mode *adjusted_mode)
2849 {
2850
2851 }
2852
2853 static void dce_v6_0_ext_disable(struct drm_encoder *encoder)
2854 {
2855
2856 }
2857
2858 static void
2859 dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode)
2860 {
2861
2862 }
2863
2864 static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder,
2865                                     const struct drm_display_mode *mode,
2866                                     struct drm_display_mode *adjusted_mode)
2867 {
2868         return true;
2869 }
2870
2871 static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = {
2872         .dpms = dce_v6_0_ext_dpms,
2873         .mode_fixup = dce_v6_0_ext_mode_fixup,
2874         .prepare = dce_v6_0_ext_prepare,
2875         .mode_set = dce_v6_0_ext_mode_set,
2876         .commit = dce_v6_0_ext_commit,
2877         .disable = dce_v6_0_ext_disable,
2878         /* no detect for TMDS/LVDS yet */
2879 };
2880
2881 static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = {
2882         .dpms = amdgpu_atombios_encoder_dpms,
2883         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
2884         .prepare = dce_v6_0_encoder_prepare,
2885         .mode_set = dce_v6_0_encoder_mode_set,
2886         .commit = dce_v6_0_encoder_commit,
2887         .disable = dce_v6_0_encoder_disable,
2888         .detect = amdgpu_atombios_encoder_dig_detect,
2889 };
2890
2891 static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = {
2892         .dpms = amdgpu_atombios_encoder_dpms,
2893         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
2894         .prepare = dce_v6_0_encoder_prepare,
2895         .mode_set = dce_v6_0_encoder_mode_set,
2896         .commit = dce_v6_0_encoder_commit,
2897         .detect = amdgpu_atombios_encoder_dac_detect,
2898 };
2899
2900 static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder)
2901 {
2902         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2903         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2904                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
2905         kfree(amdgpu_encoder->enc_priv);
2906         drm_encoder_cleanup(encoder);
2907         kfree(amdgpu_encoder);
2908 }
2909
2910 static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = {
2911         .destroy = dce_v6_0_encoder_destroy,
2912 };
2913
2914 static void dce_v6_0_encoder_add(struct amdgpu_device *adev,
2915                                  uint32_t encoder_enum,
2916                                  uint32_t supported_device,
2917                                  u16 caps)
2918 {
2919         struct drm_device *dev = adev->ddev;
2920         struct drm_encoder *encoder;
2921         struct amdgpu_encoder *amdgpu_encoder;
2922
2923         /* see if we already added it */
2924         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2925                 amdgpu_encoder = to_amdgpu_encoder(encoder);
2926                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
2927                         amdgpu_encoder->devices |= supported_device;
2928                         return;
2929                 }
2930
2931         }
2932
2933         /* add a new one */
2934         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
2935         if (!amdgpu_encoder)
2936                 return;
2937
2938         encoder = &amdgpu_encoder->base;
2939         switch (adev->mode_info.num_crtc) {
2940         case 1:
2941                 encoder->possible_crtcs = 0x1;
2942                 break;
2943         case 2:
2944         default:
2945                 encoder->possible_crtcs = 0x3;
2946                 break;
2947         case 4:
2948                 encoder->possible_crtcs = 0xf;
2949                 break;
2950         case 6:
2951                 encoder->possible_crtcs = 0x3f;
2952                 break;
2953         }
2954
2955         amdgpu_encoder->enc_priv = NULL;
2956         amdgpu_encoder->encoder_enum = encoder_enum;
2957         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2958         amdgpu_encoder->devices = supported_device;
2959         amdgpu_encoder->rmx_type = RMX_OFF;
2960         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
2961         amdgpu_encoder->is_ext_encoder = false;
2962         amdgpu_encoder->caps = caps;
2963
2964         switch (amdgpu_encoder->encoder_id) {
2965         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2966         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2967                 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
2968                                  DRM_MODE_ENCODER_DAC, NULL);
2969                 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs);
2970                 break;
2971         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2972         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2973         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2974         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2975         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2976                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2977                         amdgpu_encoder->rmx_type = RMX_FULL;
2978                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
2979                                          DRM_MODE_ENCODER_LVDS, NULL);
2980                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
2981                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2982                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
2983                                          DRM_MODE_ENCODER_DAC, NULL);
2984                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
2985                 } else {
2986                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
2987                                          DRM_MODE_ENCODER_TMDS, NULL);
2988                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
2989                 }
2990                 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs);
2991                 break;
2992         case ENCODER_OBJECT_ID_SI170B:
2993         case ENCODER_OBJECT_ID_CH7303:
2994         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2995         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2996         case ENCODER_OBJECT_ID_TITFP513:
2997         case ENCODER_OBJECT_ID_VT1623:
2998         case ENCODER_OBJECT_ID_HDMI_SI1930:
2999         case ENCODER_OBJECT_ID_TRAVIS:
3000         case ENCODER_OBJECT_ID_NUTMEG:
3001                 /* these are handled by the primary encoders */
3002                 amdgpu_encoder->is_ext_encoder = true;
3003                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3004                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3005                                          DRM_MODE_ENCODER_LVDS, NULL);
3006                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3007                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3008                                          DRM_MODE_ENCODER_DAC, NULL);
3009                 else
3010                         drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3011                                          DRM_MODE_ENCODER_TMDS, NULL);
3012                 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs);
3013                 break;
3014         }
3015 }
3016
3017 static const struct amdgpu_display_funcs dce_v6_0_display_funcs = {
3018         .set_vga_render_state = &dce_v6_0_set_vga_render_state,
3019         .bandwidth_update = &dce_v6_0_bandwidth_update,
3020         .vblank_get_counter = &dce_v6_0_vblank_get_counter,
3021         .vblank_wait = &dce_v6_0_vblank_wait,
3022         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3023         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3024         .hpd_sense = &dce_v6_0_hpd_sense,
3025         .hpd_set_polarity = &dce_v6_0_hpd_set_polarity,
3026         .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg,
3027         .page_flip = &dce_v6_0_page_flip,
3028         .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos,
3029         .add_encoder = &dce_v6_0_encoder_add,
3030         .add_connector = &amdgpu_connector_add,
3031         .stop_mc_access = &dce_v6_0_stop_mc_access,
3032         .resume_mc_access = &dce_v6_0_resume_mc_access,
3033 };
3034
3035 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev)
3036 {
3037         if (adev->mode_info.funcs == NULL)
3038                 adev->mode_info.funcs = &dce_v6_0_display_funcs;
3039 }
3040
3041 static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = {
3042         .set = dce_v6_0_set_crtc_interrupt_state,
3043         .process = dce_v6_0_crtc_irq,
3044 };
3045
3046 static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = {
3047         .set = dce_v6_0_set_pageflip_interrupt_state,
3048         .process = dce_v6_0_pageflip_irq,
3049 };
3050
3051 static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = {
3052         .set = dce_v6_0_set_hpd_interrupt_state,
3053         .process = dce_v6_0_hpd_irq,
3054 };
3055
3056 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3057 {
3058         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3059         adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs;
3060
3061         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3062         adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs;
3063
3064         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3065         adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs;
3066 }
3067
3068 const struct amdgpu_ip_block_version dce_v6_0_ip_block =
3069 {
3070         .type = AMD_IP_BLOCK_TYPE_DCE,
3071         .major = 6,
3072         .minor = 0,
3073         .rev = 0,
3074         .funcs = &dce_v6_0_ip_funcs,
3075 };
3076
3077 const struct amdgpu_ip_block_version dce_v6_4_ip_block =
3078 {
3079         .type = AMD_IP_BLOCK_TYPE_DCE,
3080         .major = 6,
3081         .minor = 4,
3082         .rev = 0,
3083         .funcs = &dce_v6_0_ip_funcs,
3084 };