2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "fiji_ppsmc.h"
28 #include "fiji_smumgr.h"
29 #include "smu_ucode_xfer_vi.h"
30 #include "amdgpu_ucode.h"
32 #include "smu/smu_7_1_3_d.h"
33 #include "smu/smu_7_1_3_sh_mask.h"
35 #define FIJI_SMC_SIZE 0x20000
37 static int fiji_set_smc_sram_address(struct amdgpu_device *adev, uint32_t smc_address, uint32_t limit)
44 if ((smc_address + 3) > limit)
47 WREG32(mmSMC_IND_INDEX_0, smc_address);
49 val = RREG32(mmSMC_IND_ACCESS_CNTL);
50 val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
51 WREG32(mmSMC_IND_ACCESS_CNTL, val);
56 static int fiji_copy_bytes_to_smc(struct amdgpu_device *adev, uint32_t smc_start_address, const uint8_t *src, uint32_t byte_count, uint32_t limit)
59 uint32_t data, orig_data;
64 if (smc_start_address & 3)
67 if ((smc_start_address + byte_count) > limit)
70 addr = smc_start_address;
72 spin_lock_irqsave(&adev->smc_idx_lock, flags);
73 while (byte_count >= 4) {
74 /* Bytes are written into the SMC addres space with the MSB first */
75 data = (src[0] << 24) + (src[1] << 16) + (src[2] << 8) + src[3];
77 result = fiji_set_smc_sram_address(adev, addr, limit);
82 WREG32(mmSMC_IND_DATA_0, data);
89 if (0 != byte_count) {
90 /* Now write odd bytes left, do a read modify write cycle */
93 result = fiji_set_smc_sram_address(adev, addr, limit);
97 orig_data = RREG32(mmSMC_IND_DATA_0);
98 extra_shift = 8 * (4 - byte_count);
100 while (byte_count > 0) {
101 data = (data << 8) + *src++;
105 data <<= extra_shift;
106 data |= (orig_data & ~((~0UL) << extra_shift));
108 result = fiji_set_smc_sram_address(adev, addr, limit);
112 WREG32(mmSMC_IND_DATA_0, data);
116 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
120 static int fiji_program_jump_on_start(struct amdgpu_device *adev)
122 static unsigned char data[] = {0xE0, 0x00, 0x80, 0x40};
123 fiji_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1);
128 static bool fiji_is_smc_ram_running(struct amdgpu_device *adev)
130 uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
131 val = REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable);
133 return ((0 == val) && (0x20100 <= RREG32_SMC(ixSMC_PC_C)));
136 static int wait_smu_response(struct amdgpu_device *adev)
141 for (i = 0; i < adev->usec_timeout; i++) {
142 val = RREG32(mmSMC_RESP_0);
143 if (REG_GET_FIELD(val, SMC_RESP_0, SMC_RESP))
148 if (i == adev->usec_timeout)
154 static int fiji_send_msg_to_smc_offset(struct amdgpu_device *adev)
156 if (wait_smu_response(adev)) {
157 DRM_ERROR("Failed to send previous message\n");
161 WREG32(mmSMC_MSG_ARG_0, 0x20000);
162 WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_Test);
164 if (wait_smu_response(adev)) {
165 DRM_ERROR("Failed to send message\n");
172 static int fiji_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg)
174 if (!fiji_is_smc_ram_running(adev))
179 if (wait_smu_response(adev)) {
180 DRM_ERROR("Failed to send previous message\n");
184 WREG32(mmSMC_MESSAGE_0, msg);
186 if (wait_smu_response(adev)) {
187 DRM_ERROR("Failed to send message\n");
194 static int fiji_send_msg_to_smc_without_waiting(struct amdgpu_device *adev,
197 if (wait_smu_response(adev)) {
198 DRM_ERROR("Failed to send previous message\n");
202 WREG32(mmSMC_MESSAGE_0, msg);
207 static int fiji_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
211 if (!fiji_is_smc_ram_running(adev))
214 if (wait_smu_response(adev)) {
215 DRM_ERROR("Failed to send previous message\n");
219 WREG32(mmSMC_MSG_ARG_0, parameter);
221 return fiji_send_msg_to_smc(adev, msg);
224 static int fiji_send_msg_to_smc_with_parameter_without_waiting(
225 struct amdgpu_device *adev,
226 PPSMC_Msg msg, uint32_t parameter)
228 if (wait_smu_response(adev)) {
229 DRM_ERROR("Failed to send previous message\n");
233 WREG32(mmSMC_MSG_ARG_0, parameter);
235 return fiji_send_msg_to_smc_without_waiting(adev, msg);
238 #if 0 /* not used yet */
239 static int fiji_wait_for_smc_inactive(struct amdgpu_device *adev)
244 if (!fiji_is_smc_ram_running(adev))
247 for (i = 0; i < adev->usec_timeout; i++) {
248 val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
249 if (REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, cken) == 0)
254 if (i == adev->usec_timeout)
261 static int fiji_smu_upload_firmware_image(struct amdgpu_device *adev)
263 const struct smc_firmware_header_v1_0 *hdr;
265 uint32_t ucode_start_address;
275 hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
276 amdgpu_ucode_print_smc_hdr(&hdr->header);
278 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
279 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
280 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
281 src = (const uint8_t *)
282 (adev->pm.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
284 if (ucode_size & 3) {
285 DRM_ERROR("SMC ucode is not 4 bytes aligned\n");
289 if (ucode_size > FIJI_SMC_SIZE) {
290 DRM_ERROR("SMC address is beyond the SMC RAM area\n");
294 spin_lock_irqsave(&adev->smc_idx_lock, flags);
295 WREG32(mmSMC_IND_INDEX_0, ucode_start_address);
297 val = RREG32(mmSMC_IND_ACCESS_CNTL);
298 val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
299 WREG32(mmSMC_IND_ACCESS_CNTL, val);
301 byte_count = ucode_size;
302 data = (uint32_t *)src;
303 for (; byte_count >= 4; data++, byte_count -= 4)
304 WREG32(mmSMC_IND_DATA_0, data[0]);
306 val = RREG32(mmSMC_IND_ACCESS_CNTL);
307 val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
308 WREG32(mmSMC_IND_ACCESS_CNTL, val);
309 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
314 #if 0 /* not used yet */
315 static int fiji_read_smc_sram_dword(struct amdgpu_device *adev,
316 uint32_t smc_address,
323 spin_lock_irqsave(&adev->smc_idx_lock, flags);
324 result = fiji_set_smc_sram_address(adev, smc_address, limit);
326 *value = RREG32(mmSMC_IND_DATA_0);
327 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
331 static int fiji_write_smc_sram_dword(struct amdgpu_device *adev,
332 uint32_t smc_address,
339 spin_lock_irqsave(&adev->smc_idx_lock, flags);
340 result = fiji_set_smc_sram_address(adev, smc_address, limit);
342 WREG32(mmSMC_IND_DATA_0, value);
343 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
347 static int fiji_smu_stop_smc(struct amdgpu_device *adev)
349 uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
350 val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
351 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
353 val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
354 val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1);
355 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);
361 static enum AMDGPU_UCODE_ID fiji_convert_fw_type(uint32_t fw_type)
365 return AMDGPU_UCODE_ID_SDMA0;
367 return AMDGPU_UCODE_ID_SDMA1;
369 return AMDGPU_UCODE_ID_CP_CE;
370 case UCODE_ID_CP_PFP:
371 return AMDGPU_UCODE_ID_CP_PFP;
373 return AMDGPU_UCODE_ID_CP_ME;
374 case UCODE_ID_CP_MEC:
375 case UCODE_ID_CP_MEC_JT1:
376 case UCODE_ID_CP_MEC_JT2:
377 return AMDGPU_UCODE_ID_CP_MEC1;
379 return AMDGPU_UCODE_ID_RLC_G;
381 DRM_ERROR("ucode type is out of range!\n");
382 return AMDGPU_UCODE_ID_MAXIMUM;
386 static int fiji_smu_populate_single_firmware_entry(struct amdgpu_device *adev,
388 struct SMU_Entry *entry)
390 enum AMDGPU_UCODE_ID id = fiji_convert_fw_type(fw_type);
391 struct amdgpu_firmware_info *ucode = &adev->firmware.ucode[id];
392 const struct gfx_firmware_header_v1_0 *header = NULL;
396 if (ucode->fw == NULL)
398 gpu_addr = ucode->mc_addr;
399 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
400 data_size = le32_to_cpu(header->header.ucode_size_bytes);
402 if ((fw_type == UCODE_ID_CP_MEC_JT1) ||
403 (fw_type == UCODE_ID_CP_MEC_JT2)) {
404 gpu_addr += le32_to_cpu(header->jt_offset) << 2;
405 data_size = le32_to_cpu(header->jt_size) << 2;
408 entry->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
409 entry->id = (uint16_t)fw_type;
410 entry->image_addr_high = upper_32_bits(gpu_addr);
411 entry->image_addr_low = lower_32_bits(gpu_addr);
412 entry->meta_data_addr_high = 0;
413 entry->meta_data_addr_low = 0;
414 entry->data_size_byte = data_size;
415 entry->num_register_entries = 0;
417 if (fw_type == UCODE_ID_RLC_G)
425 static int fiji_smu_request_load_fw(struct amdgpu_device *adev)
427 struct fiji_smu_private_data *private = (struct fiji_smu_private_data *)adev->smu.priv;
428 struct SMU_DRAMData_TOC *toc;
431 WREG32_SMC(ixSOFT_REGISTERS_TABLE_28, 0);
433 fiji_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SMU_DRAM_ADDR_HI, private->smu_buffer_addr_high);
434 fiji_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SMU_DRAM_ADDR_LO, private->smu_buffer_addr_low);
436 toc = (struct SMU_DRAMData_TOC *)private->header;
437 toc->num_entries = 0;
438 toc->structure_version = 1;
440 if (!adev->firmware.smu_load)
443 if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_RLC_G,
444 &toc->entry[toc->num_entries++])) {
445 DRM_ERROR("Failed to get firmware entry for RLC\n");
449 if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_CE,
450 &toc->entry[toc->num_entries++])) {
451 DRM_ERROR("Failed to get firmware entry for CE\n");
455 if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_PFP,
456 &toc->entry[toc->num_entries++])) {
457 DRM_ERROR("Failed to get firmware entry for PFP\n");
461 if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_ME,
462 &toc->entry[toc->num_entries++])) {
463 DRM_ERROR("Failed to get firmware entry for ME\n");
467 if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC,
468 &toc->entry[toc->num_entries++])) {
469 DRM_ERROR("Failed to get firmware entry for MEC\n");
473 if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT1,
474 &toc->entry[toc->num_entries++])) {
475 DRM_ERROR("Failed to get firmware entry for MEC_JT1\n");
479 if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT2,
480 &toc->entry[toc->num_entries++])) {
481 DRM_ERROR("Failed to get firmware entry for MEC_JT2\n");
485 if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA0,
486 &toc->entry[toc->num_entries++])) {
487 DRM_ERROR("Failed to get firmware entry for SDMA0\n");
491 if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA1,
492 &toc->entry[toc->num_entries++])) {
493 DRM_ERROR("Failed to get firmware entry for SDMA1\n");
497 fiji_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DRV_DRAM_ADDR_HI, private->header_addr_high);
498 fiji_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DRV_DRAM_ADDR_LO, private->header_addr_low);
500 fw_to_load = UCODE_ID_RLC_G_MASK |
501 UCODE_ID_SDMA0_MASK |
502 UCODE_ID_SDMA1_MASK |
503 UCODE_ID_CP_CE_MASK |
504 UCODE_ID_CP_ME_MASK |
505 UCODE_ID_CP_PFP_MASK |
506 UCODE_ID_CP_MEC_MASK;
508 if (fiji_send_msg_to_smc_with_parameter_without_waiting(adev, PPSMC_MSG_LoadUcodes, fw_to_load)) {
509 DRM_ERROR("Fail to request SMU load ucode\n");
516 static uint32_t fiji_smu_get_mask_for_fw_type(uint32_t fw_type)
519 case AMDGPU_UCODE_ID_SDMA0:
520 return UCODE_ID_SDMA0_MASK;
521 case AMDGPU_UCODE_ID_SDMA1:
522 return UCODE_ID_SDMA1_MASK;
523 case AMDGPU_UCODE_ID_CP_CE:
524 return UCODE_ID_CP_CE_MASK;
525 case AMDGPU_UCODE_ID_CP_PFP:
526 return UCODE_ID_CP_PFP_MASK;
527 case AMDGPU_UCODE_ID_CP_ME:
528 return UCODE_ID_CP_ME_MASK;
529 case AMDGPU_UCODE_ID_CP_MEC1:
530 return UCODE_ID_CP_MEC_MASK;
531 case AMDGPU_UCODE_ID_CP_MEC2:
532 return UCODE_ID_CP_MEC_MASK;
533 case AMDGPU_UCODE_ID_RLC_G:
534 return UCODE_ID_RLC_G_MASK;
536 DRM_ERROR("ucode type is out of range!\n");
541 static int fiji_smu_check_fw_load_finish(struct amdgpu_device *adev,
544 uint32_t fw_mask = fiji_smu_get_mask_for_fw_type(fw_type);
547 for (i = 0; i < adev->usec_timeout; i++) {
548 if (fw_mask == (RREG32_SMC(ixSOFT_REGISTERS_TABLE_28) & fw_mask))
553 if (i == adev->usec_timeout) {
554 DRM_ERROR("check firmware loading failed\n");
561 static int fiji_smu_start_in_protection_mode(struct amdgpu_device *adev)
568 val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
569 val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
570 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
572 result = fiji_smu_upload_firmware_image(adev);
577 WREG32_SMC(ixSMU_STATUS, 0);
580 val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
581 val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
582 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);
584 /* De-assert reset */
585 val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
586 val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
587 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
589 /* Set SMU Auto Start */
590 val = RREG32_SMC(ixSMU_INPUT_DATA);
591 val = REG_SET_FIELD(val, SMU_INPUT_DATA, AUTO_START, 1);
592 WREG32_SMC(ixSMU_INPUT_DATA, val);
594 /* Clear firmware interrupt enable flag */
595 WREG32_SMC(ixFIRMWARE_FLAGS, 0);
597 for (i = 0; i < adev->usec_timeout; i++) {
598 val = RREG32_SMC(ixRCU_UC_EVENTS);
599 if (REG_GET_FIELD(val, RCU_UC_EVENTS, INTERRUPTS_ENABLED))
604 if (i == adev->usec_timeout) {
605 DRM_ERROR("Interrupt is not enabled by firmware\n");
609 /* Call Test SMU message with 0x20000 offset
610 * to trigger SMU start
612 fiji_send_msg_to_smc_offset(adev);
613 DRM_INFO("[FM]try triger smu start\n");
614 /* Wait for done bit to be set */
615 for (i = 0; i < adev->usec_timeout; i++) {
616 val = RREG32_SMC(ixSMU_STATUS);
617 if (REG_GET_FIELD(val, SMU_STATUS, SMU_DONE))
622 if (i == adev->usec_timeout) {
623 DRM_ERROR("Timeout for SMU start\n");
627 /* Check pass/failed indicator */
628 val = RREG32_SMC(ixSMU_STATUS);
629 if (!REG_GET_FIELD(val, SMU_STATUS, SMU_PASS)) {
630 DRM_ERROR("SMU Firmware start failed\n");
633 DRM_INFO("[FM]smu started\n");
634 /* Wait for firmware to initialize */
635 for (i = 0; i < adev->usec_timeout; i++) {
636 val = RREG32_SMC(ixFIRMWARE_FLAGS);
637 if(REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED))
642 if (i == adev->usec_timeout) {
643 DRM_ERROR("SMU firmware initialization failed\n");
646 DRM_INFO("[FM]smu initialized\n");
651 static int fiji_smu_start_in_non_protection_mode(struct amdgpu_device *adev)
656 /* wait for smc boot up */
657 for (i = 0; i < adev->usec_timeout; i++) {
658 val = RREG32_SMC(ixRCU_UC_EVENTS);
659 val = REG_GET_FIELD(val, RCU_UC_EVENTS, boot_seq_done);
665 if (i == adev->usec_timeout) {
666 DRM_ERROR("SMC boot sequence is not completed\n");
670 /* Clear firmware interrupt enable flag */
671 WREG32_SMC(ixFIRMWARE_FLAGS, 0);
674 val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
675 val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
676 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
678 result = fiji_smu_upload_firmware_image(adev);
682 /* Set smc instruct start point at 0x0 */
683 fiji_program_jump_on_start(adev);
686 val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
687 val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
688 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);
690 /* De-assert reset */
691 val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
692 val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
693 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
695 /* Wait for firmware to initialize */
696 for (i = 0; i < adev->usec_timeout; i++) {
697 val = RREG32_SMC(ixFIRMWARE_FLAGS);
698 if (REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED))
703 if (i == adev->usec_timeout) {
704 DRM_ERROR("Timeout for SMC firmware initialization\n");
711 int fiji_smu_start(struct amdgpu_device *adev)
716 if (!fiji_is_smc_ram_running(adev)) {
717 val = RREG32_SMC(ixSMU_FIRMWARE);
718 if (!REG_GET_FIELD(val, SMU_FIRMWARE, SMU_MODE)) {
719 DRM_INFO("[FM]start smu in nonprotection mode\n");
720 result = fiji_smu_start_in_non_protection_mode(adev);
724 DRM_INFO("[FM]start smu in protection mode\n");
725 result = fiji_smu_start_in_protection_mode(adev);
731 return fiji_smu_request_load_fw(adev);
734 static const struct amdgpu_smumgr_funcs fiji_smumgr_funcs = {
735 .check_fw_load_finish = fiji_smu_check_fw_load_finish,
736 .request_smu_load_fw = NULL,
737 .request_smu_specific_fw = NULL,
740 int fiji_smu_init(struct amdgpu_device *adev)
742 struct fiji_smu_private_data *private;
743 uint32_t image_size = ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
744 uint32_t smu_internal_buffer_size = 200*4096;
745 struct amdgpu_bo **toc_buf = &adev->smu.toc_buf;
746 struct amdgpu_bo **smu_buf = &adev->smu.smu_buf;
752 private = kzalloc(sizeof(struct fiji_smu_private_data), GFP_KERNEL);
756 /* allocate firmware buffers */
757 if (adev->firmware.smu_load)
758 amdgpu_ucode_init_bo(adev);
760 adev->smu.priv = private;
761 adev->smu.fw_flags = 0;
763 /* Allocate FW image data structure and header buffer */
764 ret = amdgpu_bo_create(adev, image_size, PAGE_SIZE,
765 true, AMDGPU_GEM_DOMAIN_VRAM,
766 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
767 NULL, NULL, toc_buf);
769 DRM_ERROR("Failed to allocate memory for TOC buffer\n");
773 /* Allocate buffer for SMU internal buffer */
774 ret = amdgpu_bo_create(adev, smu_internal_buffer_size, PAGE_SIZE,
775 true, AMDGPU_GEM_DOMAIN_VRAM,
776 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
777 NULL, NULL, smu_buf);
779 DRM_ERROR("Failed to allocate memory for SMU internal buffer\n");
783 /* Retrieve GPU address for header buffer and internal buffer */
784 ret = amdgpu_bo_reserve(adev->smu.toc_buf, false);
786 amdgpu_bo_unref(&adev->smu.toc_buf);
787 DRM_ERROR("Failed to reserve the TOC buffer\n");
791 ret = amdgpu_bo_pin(adev->smu.toc_buf, AMDGPU_GEM_DOMAIN_VRAM, &mc_addr);
793 amdgpu_bo_unreserve(adev->smu.toc_buf);
794 amdgpu_bo_unref(&adev->smu.toc_buf);
795 DRM_ERROR("Failed to pin the TOC buffer\n");
799 ret = amdgpu_bo_kmap(*toc_buf, &toc_buf_ptr);
801 amdgpu_bo_unreserve(adev->smu.toc_buf);
802 amdgpu_bo_unref(&adev->smu.toc_buf);
803 DRM_ERROR("Failed to map the TOC buffer\n");
807 amdgpu_bo_unreserve(adev->smu.toc_buf);
808 private->header_addr_low = lower_32_bits(mc_addr);
809 private->header_addr_high = upper_32_bits(mc_addr);
810 private->header = toc_buf_ptr;
812 ret = amdgpu_bo_reserve(adev->smu.smu_buf, false);
814 amdgpu_bo_unref(&adev->smu.smu_buf);
815 amdgpu_bo_unref(&adev->smu.toc_buf);
816 DRM_ERROR("Failed to reserve the SMU internal buffer\n");
820 ret = amdgpu_bo_pin(adev->smu.smu_buf, AMDGPU_GEM_DOMAIN_VRAM, &mc_addr);
822 amdgpu_bo_unreserve(adev->smu.smu_buf);
823 amdgpu_bo_unref(&adev->smu.smu_buf);
824 amdgpu_bo_unref(&adev->smu.toc_buf);
825 DRM_ERROR("Failed to pin the SMU internal buffer\n");
829 ret = amdgpu_bo_kmap(*smu_buf, &smu_buf_ptr);
831 amdgpu_bo_unreserve(adev->smu.smu_buf);
832 amdgpu_bo_unref(&adev->smu.smu_buf);
833 amdgpu_bo_unref(&adev->smu.toc_buf);
834 DRM_ERROR("Failed to map the SMU internal buffer\n");
838 amdgpu_bo_unreserve(adev->smu.smu_buf);
839 private->smu_buffer_addr_low = lower_32_bits(mc_addr);
840 private->smu_buffer_addr_high = upper_32_bits(mc_addr);
842 adev->smu.smumgr_funcs = &fiji_smumgr_funcs;
847 int fiji_smu_fini(struct amdgpu_device *adev)
849 amdgpu_bo_unref(&adev->smu.toc_buf);
850 amdgpu_bo_unref(&adev->smu.smu_buf);
851 kfree(adev->smu.priv);
852 adev->smu.priv = NULL;
853 if (adev->firmware.fw_buf)
854 amdgpu_ucode_fini_bo(adev);