drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "gmc_v6_0.h"
  27 #include "amdgpu_ucode.h"
  28
  29 #include "bif/bif_3_0_d.h"
  30 #include "bif/bif_3_0_sh_mask.h"
  31 #include "oss/oss_1_0_d.h"
  32 #include "oss/oss_1_0_sh_mask.h"
  33 #include "gmc/gmc_6_0_d.h"
  34 #include "gmc/gmc_6_0_sh_mask.h"
  35 #include "dce/dce_6_0_d.h"
  36 #include "dce/dce_6_0_sh_mask.h"
  37 #include "si_enums.h"
  38
  39 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev);
  40 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  41 static int gmc_v6_0_wait_for_idle(void *handle);
  42
  43 MODULE_FIRMWARE("radeon/tahiti_mc.bin");
  44 MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
  45 MODULE_FIRMWARE("radeon/verde_mc.bin");
  46 MODULE_FIRMWARE("radeon/oland_mc.bin");
  47 MODULE_FIRMWARE("radeon/si58_mc.bin");
  48
  49 #define MC_SEQ_MISC0__MT__MASK   0xf0000000
  50 #define MC_SEQ_MISC0__MT__GDDR1  0x10000000
  51 #define MC_SEQ_MISC0__MT__DDR2   0x20000000
  52 #define MC_SEQ_MISC0__MT__GDDR3  0x30000000
  53 #define MC_SEQ_MISC0__MT__GDDR4  0x40000000
  54 #define MC_SEQ_MISC0__MT__GDDR5  0x50000000
  55 #define MC_SEQ_MISC0__MT__HBM    0x60000000
  56 #define MC_SEQ_MISC0__MT__DDR3   0xB0000000
  57
  58
  59 static const u32 crtc_offsets[6] =
  60 {
  61         SI_CRTC0_REGISTER_OFFSET,
  62         SI_CRTC1_REGISTER_OFFSET,
  63         SI_CRTC2_REGISTER_OFFSET,
  64         SI_CRTC3_REGISTER_OFFSET,
  65         SI_CRTC4_REGISTER_OFFSET,
  66         SI_CRTC5_REGISTER_OFFSET
  67 };
  68
  69 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev,
  70                              struct amdgpu_mode_mc_save *save)
  71 {
  72         u32 blackout;
  73
  74         if (adev->mode_info.num_crtc)
  75                 amdgpu_display_stop_mc_access(adev, save);
  76
  77         gmc_v6_0_wait_for_idle((void *)adev);
  78
  79         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  80         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  81                 /* Block CPU access */
  82                 WREG32(mmBIF_FB_EN, 0);
  83                 /* blackout the MC */
  84                 blackout = REG_SET_FIELD(blackout,
  85                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  86                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  87         }
  88         /* wait for the MC to settle */
  89         udelay(100);
  90
  91 }
  92
  93 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev,
  94                                struct amdgpu_mode_mc_save *save)
  95 {
  96         u32 tmp;
  97
  98         /* unblackout the MC */
  99         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 100         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 101         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 102         /* allow CPU access */
 103         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 104         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 105         WREG32(mmBIF_FB_EN, tmp);
 106
 107         if (adev->mode_info.num_crtc)
 108                 amdgpu_display_resume_mc_access(adev, save);
 109
 110 }
 111
 112 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
 113 {
 114         const char *chip_name;
 115         char fw_name[30];
 116         int err;
 117         bool is_58_fw = false;
 118
 119         DRM_DEBUG("\n");
 120
 121         switch (adev->asic_type) {
 122         case CHIP_TAHITI:
 123                 chip_name = "tahiti";
 124                 break;
 125         case CHIP_PITCAIRN:
 126                 chip_name = "pitcairn";
 127                 break;
 128         case CHIP_VERDE:
 129                 chip_name = "verde";
 130                 break;
 131         case CHIP_OLAND:
 132                 chip_name = "oland";
 133                 break;
 134         case CHIP_HAINAN:
 135                 chip_name = "hainan";
 136                 break;
 137         default: BUG();
 138         }
 139
 140         /* this memory configuration requires special firmware */
 141         if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
 142                 is_58_fw = true;
 143
 144         if (is_58_fw)
 145                 snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin");
 146         else
 147                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 148         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 149         if (err)
 150                 goto out;
 151
 152         err = amdgpu_ucode_validate(adev->mc.fw);
 153
 154 out:
 155         if (err) {
 156                 dev_err(adev->dev,
 157                        "si_mc: Failed to load firmware \"%s\"\n",
 158                        fw_name);
 159                 release_firmware(adev->mc.fw);
 160                 adev->mc.fw = NULL;
 161         }
 162         return err;
 163 }
 164
 165 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
 166 {
 167         const __le32 *new_fw_data = NULL;
 168         u32 running;
 169         const __le32 *new_io_mc_regs = NULL;
 170         int i, regs_size, ucode_size;
 171         const struct mc_firmware_header_v1_0 *hdr;
 172
 173         if (!adev->mc.fw)
 174                 return -EINVAL;
 175
 176         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 177
 178         amdgpu_ucode_print_mc_hdr(&hdr->header);
 179
 180         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 181         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 182         new_io_mc_regs = (const __le32 *)
 183                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 184         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 185         new_fw_data = (const __le32 *)
 186                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 187
 188         running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
 189
 190         if (running == 0) {
 191
 192                 /* reset the engine and set to writable */
 193                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 194                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 195
 196                 /* load mc io regs */
 197                 for (i = 0; i < regs_size; i++) {
 198                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
 199                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
 200                 }
 201                 /* load the MC ucode */
 202                 for (i = 0; i < ucode_size; i++) {
 203                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
 204                 }
 205
 206                 /* put the engine back into the active state */
 207                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 208                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 209                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 210
 211                 /* wait for training to complete */
 212                 for (i = 0; i < adev->usec_timeout; i++) {
 213                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
 214                                 break;
 215                         udelay(1);
 216                 }
 217                 for (i = 0; i < adev->usec_timeout; i++) {
 218                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
 219                                 break;
 220                         udelay(1);
 221                 }
 222
 223         }
 224
 225         return 0;
 226 }
 227
 228 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
 229                                        struct amdgpu_mc *mc)
 230 {
 231         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 232                 dev_warn(adev->dev, "limiting VRAM\n");
 233                 mc->real_vram_size = 0xFFC0000000ULL;
 234                 mc->mc_vram_size = 0xFFC0000000ULL;
 235         }
 236         amdgpu_vram_location(adev, &adev->mc, 0);
 237         adev->mc.gtt_base_align = 0;
 238         amdgpu_gtt_location(adev, mc);
 239 }
 240
 241 static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
 242 {
 243         struct amdgpu_mode_mc_save save;
 244         u32 tmp;
 245         int i, j;
 246
 247         /* Initialize HDP */
 248         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 249                 WREG32((0xb05 + j), 0x00000000);
 250                 WREG32((0xb06 + j), 0x00000000);
 251                 WREG32((0xb07 + j), 0x00000000);
 252                 WREG32((0xb08 + j), 0x00000000);
 253                 WREG32((0xb09 + j), 0x00000000);
 254         }
 255         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 256
 257         if (adev->mode_info.num_crtc)
 258                 amdgpu_display_set_vga_render_state(adev, false);
 259
 260         gmc_v6_0_mc_stop(adev, &save);
 261
 262         if (gmc_v6_0_wait_for_idle((void *)adev)) {
 263                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 264         }
 265
 266         WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK);
 267         /* Update configuration */
 268         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 269                adev->mc.vram_start >> 12);
 270         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 271                adev->mc.vram_end >> 12);
 272         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 273                adev->vram_scratch.gpu_addr >> 12);
 274         tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 275         tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 276         WREG32(mmMC_VM_FB_LOCATION, tmp);
 277         /* XXX double check these! */
 278         WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 279         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 280         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 281         WREG32(mmMC_VM_AGP_BASE, 0);
 282         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 283         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 284
 285         if (gmc_v6_0_wait_for_idle((void *)adev)) {
 286                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 287         }
 288         gmc_v6_0_mc_resume(adev, &save);
 289 }
 290
 291 static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
 292 {
 293
 294         u32 tmp;
 295         int chansize, numchan;
 296
 297         tmp = RREG32(mmMC_ARB_RAMCFG);
 298         if (tmp & (1 << 11)) {
 299                 chansize = 16;
 300         } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
 301                 chansize = 64;
 302         } else {
 303                 chansize = 32;
 304         }
 305         tmp = RREG32(mmMC_SHARED_CHMAP);
 306         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 307         case 0:
 308         default:
 309                 numchan = 1;
 310                 break;
 311         case 1:
 312                 numchan = 2;
 313                 break;
 314         case 2:
 315                 numchan = 4;
 316                 break;
 317         case 3:
 318                 numchan = 8;
 319                 break;
 320         case 4:
 321                 numchan = 3;
 322                 break;
 323         case 5:
 324                 numchan = 6;
 325                 break;
 326         case 6:
 327                 numchan = 10;
 328                 break;
 329         case 7:
 330                 numchan = 12;
 331                 break;
 332         case 8:
 333                 numchan = 16;
 334                 break;
 335         }
 336         adev->mc.vram_width = numchan * chansize;
 337         /* Could aper size report 0 ? */
 338         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 339         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 340         /* size in MB on si */
 341         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 342         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 343         adev->mc.visible_vram_size = adev->mc.aper_size;
 344
 345         /* unless the user had overridden it, set the gart
 346          * size equal to the 1024 or vram, whichever is larger.
 347          */
 348         if (amdgpu_gart_size == -1)
 349                 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
 350         else
 351                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 352
 353         gmc_v6_0_vram_gtt_location(adev, &adev->mc);
 354
 355         return 0;
 356 }
 357
 358 static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 359                                         uint32_t vmid)
 360 {
 361         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 362
 363         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 364 }
 365
 366 static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
 367                                      void *cpu_pt_addr,
 368                                      uint32_t gpu_page_idx,
 369                                      uint64_t addr,
 370                                      uint32_t flags)
 371 {
 372         void __iomem *ptr = (void *)cpu_pt_addr;
 373         uint64_t value;
 374
 375         value = addr & 0xFFFFFFFFFFFFF000ULL;
 376         value |= flags;
 377         writeq(value, ptr + (gpu_page_idx * 8));
 378
 379         return 0;
 380 }
 381
 382 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
 383                                               bool value)
 384 {
 385         u32 tmp;
 386
 387         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 388         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 389                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 390         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 391                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 392         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 393                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 394         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 395                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 396         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 397                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 398         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 399                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 400         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 401 }
 402
 403  /**
 404    + * gmc_v8_0_set_prt - set PRT VM fault
 405    + *
 406    + * @adev: amdgpu_device pointer
 407    + * @enable: enable/disable VM fault handling for PRT
 408    +*/
 409 static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
 410 {
 411         u32 tmp;
 412
 413         if (enable && !adev->mc.prt_warning) {
 414                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 415                 adev->mc.prt_warning = true;
 416         }
 417
 418         tmp = RREG32(mmVM_PRT_CNTL);
 419         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 420                             CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
 421                             enable);
 422         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 423                             TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
 424                             enable);
 425         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 426                             L2_CACHE_STORE_INVALID_ENTRIES,
 427                             enable);
 428         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 429                             L1_TLB_STORE_INVALID_ENTRIES,
 430                             enable);
 431         WREG32(mmVM_PRT_CNTL, tmp);
 432
 433         if (enable) {
 434                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 435                 uint32_t high = adev->vm_manager.max_pfn;
 436
 437                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 438                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 439                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 440                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 441                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 442                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 443                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 444                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 445         } else {
 446                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 447                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 448                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 449                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 450                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 451                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 452                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 453                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 454         }
 455 }
 456
 457 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 458 {
 459         int r, i;
 460
 461         if (adev->gart.robj == NULL) {
 462                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 463                 return -EINVAL;
 464         }
 465         r = amdgpu_gart_table_vram_pin(adev);
 466         if (r)
 467                 return r;
 468         /* Setup TLB control */
 469         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 470                (0xA << 7) |
 471                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
 472                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
 473                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 474                MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
 475                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 476         /* Setup L2 cache */
 477         WREG32(mmVM_L2_CNTL,
 478                VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
 479                VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
 480                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 481                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 482                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 483                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 484         WREG32(mmVM_L2_CNTL2,
 485                VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
 486                VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
 487         WREG32(mmVM_L2_CNTL3,
 488                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 489                (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
 490                (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 491         /* setup context0 */
 492         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 493         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
 494         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 495         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 496                         (u32)(adev->dummy_page.addr >> 12));
 497         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 498         WREG32(mmVM_CONTEXT0_CNTL,
 499                VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
 500                (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 501                VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
 502
 503         WREG32(0x575, 0);
 504         WREG32(0x576, 0);
 505         WREG32(0x577, 0);
 506
 507         /* empty context1-15 */
 508         /* set vm size, must be a multiple of 4 */
 509         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 510         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 511         /* Assign the pt base to something valid for now; the pts used for
 512          * the VMs are determined by the application and setup and assigned
 513          * on the fly in the vm part of radeon_gart.c
 514          */
 515         for (i = 1; i < 16; i++) {
 516                 if (i < 8)
 517                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 518                                adev->gart.table_addr >> 12);
 519                 else
 520                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 521                                adev->gart.table_addr >> 12);
 522         }
 523
 524         /* enable context1-15 */
 525         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 526                (u32)(adev->dummy_page.addr >> 12));
 527         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 528         WREG32(mmVM_CONTEXT1_CNTL,
 529                VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
 530                (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 531                ((amdgpu_vm_block_size - 9) << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
 532         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 533                 gmc_v6_0_set_fault_enable_default(adev, false);
 534         else
 535                 gmc_v6_0_set_fault_enable_default(adev, true);
 536
 537         gmc_v6_0_gart_flush_gpu_tlb(adev, 0);
 538         dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
 539                  (unsigned)(adev->mc.gtt_size >> 20),
 540                  (unsigned long long)adev->gart.table_addr);
 541         adev->gart.ready = true;
 542         return 0;
 543 }
 544
 545 static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
 546 {
 547         int r;
 548
 549         if (adev->gart.robj) {
 550                 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
 551                 return 0;
 552         }
 553         r = amdgpu_gart_init(adev);
 554         if (r)
 555                 return r;
 556         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 557         return amdgpu_gart_table_vram_alloc(adev);
 558 }
 559
 560 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
 561 {
 562         /*unsigned i;
 563
 564         for (i = 1; i < 16; ++i) {
 565                 uint32_t reg;
 566                 if (i < 8)
 567                         reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
 568                 else
 569                         reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
 570                 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
 571         }*/
 572
 573         /* Disable all tables */
 574         WREG32(mmVM_CONTEXT0_CNTL, 0);
 575         WREG32(mmVM_CONTEXT1_CNTL, 0);
 576         /* Setup TLB control */
 577         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 578                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 579                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 580         /* Setup L2 cache */
 581         WREG32(mmVM_L2_CNTL,
 582                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 583                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 584                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 585                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 586         WREG32(mmVM_L2_CNTL2, 0);
 587         WREG32(mmVM_L2_CNTL3,
 588                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 589                (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 590         amdgpu_gart_table_vram_unpin(adev);
 591 }
 592
 593 static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
 594 {
 595         amdgpu_gart_table_vram_free(adev);
 596         amdgpu_gart_fini(adev);
 597 }
 598
 599 static int gmc_v6_0_vm_init(struct amdgpu_device *adev)
 600 {
 601         /*
 602          * number of VMs
 603          * VMID 0 is reserved for System
 604          * amdgpu graphics/compute will use VMIDs 1-7
 605          * amdkfd will use VMIDs 8-15
 606          */
 607         adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
 608         amdgpu_vm_manager_init(adev);
 609
 610         /* base offset of vram pages */
 611         if (adev->flags & AMD_IS_APU) {
 612                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 613                 tmp <<= 22;
 614                 adev->vm_manager.vram_base_offset = tmp;
 615         } else
 616                 adev->vm_manager.vram_base_offset = 0;
 617
 618         return 0;
 619 }
 620
 621 static void gmc_v6_0_vm_fini(struct amdgpu_device *adev)
 622 {
 623 }
 624
 625 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
 626                                      u32 status, u32 addr, u32 mc_client)
 627 {
 628         u32 mc_id;
 629         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 630         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 631                                         PROTECTIONS);
 632         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 633                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 634
 635         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 636                               MEMORY_CLIENT_ID);
 637
 638         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 639                protections, vmid, addr,
 640                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 641                              MEMORY_CLIENT_RW) ?
 642                "write" : "read", block, mc_client, mc_id);
 643 }
 644
 645 /*
 646 static const u32 mc_cg_registers[] = {
 647         MC_HUB_MISC_HUB_CG,
 648         MC_HUB_MISC_SIP_CG,
 649         MC_HUB_MISC_VM_CG,
 650         MC_XPB_CLK_GAT,
 651         ATC_MISC_CG,
 652         MC_CITF_MISC_WR_CG,
 653         MC_CITF_MISC_RD_CG,
 654         MC_CITF_MISC_VM_CG,
 655         VM_L2_CG,
 656 };
 657
 658 static const u32 mc_cg_ls_en[] = {
 659         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 660         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 661         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 662         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 663         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 664         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 665         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 666         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 667         VM_L2_CG__MEM_LS_ENABLE_MASK,
 668 };
 669
 670 static const u32 mc_cg_en[] = {
 671         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 672         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 673         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 674         MC_XPB_CLK_GAT__ENABLE_MASK,
 675         ATC_MISC_CG__ENABLE_MASK,
 676         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 677         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 678         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 679         VM_L2_CG__ENABLE_MASK,
 680 };
 681
 682 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
 683                                   bool enable)
 684 {
 685         int i;
 686         u32 orig, data;
 687
 688         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 689                 orig = data = RREG32(mc_cg_registers[i]);
 690                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
 691                         data |= mc_cg_ls_en[i];
 692                 else
 693                         data &= ~mc_cg_ls_en[i];
 694                 if (data != orig)
 695                         WREG32(mc_cg_registers[i], data);
 696         }
 697 }
 698
 699 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
 700                                     bool enable)
 701 {
 702         int i;
 703         u32 orig, data;
 704
 705         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 706                 orig = data = RREG32(mc_cg_registers[i]);
 707                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
 708                         data |= mc_cg_en[i];
 709                 else
 710                         data &= ~mc_cg_en[i];
 711                 if (data != orig)
 712                         WREG32(mc_cg_registers[i], data);
 713         }
 714 }
 715
 716 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
 717                                      bool enable)
 718 {
 719         u32 orig, data;
 720
 721         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 722
 723         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
 724                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 725                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 726                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 727                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 728         } else {
 729                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 730                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 731                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 732                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 733         }
 734
 735         if (orig != data)
 736                 WREG32_PCIE(ixPCIE_CNTL2, data);
 737 }
 738
 739 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 740                                      bool enable)
 741 {
 742         u32 orig, data;
 743
 744         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 745
 746         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
 747                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 748         else
 749                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 750
 751         if (orig != data)
 752                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 753 }
 754
 755 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
 756                                    bool enable)
 757 {
 758         u32 orig, data;
 759
 760         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 761
 762         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
 763                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 764         else
 765                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 766
 767         if (orig != data)
 768                 WREG32(mmHDP_MEM_POWER_LS, data);
 769 }
 770 */
 771
 772 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
 773 {
 774         switch (mc_seq_vram_type) {
 775         case MC_SEQ_MISC0__MT__GDDR1:
 776                 return AMDGPU_VRAM_TYPE_GDDR1;
 777         case MC_SEQ_MISC0__MT__DDR2:
 778                 return AMDGPU_VRAM_TYPE_DDR2;
 779         case MC_SEQ_MISC0__MT__GDDR3:
 780                 return AMDGPU_VRAM_TYPE_GDDR3;
 781         case MC_SEQ_MISC0__MT__GDDR4:
 782                 return AMDGPU_VRAM_TYPE_GDDR4;
 783         case MC_SEQ_MISC0__MT__GDDR5:
 784                 return AMDGPU_VRAM_TYPE_GDDR5;
 785         case MC_SEQ_MISC0__MT__DDR3:
 786                 return AMDGPU_VRAM_TYPE_DDR3;
 787         default:
 788                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 789         }
 790 }
 791
 792 static int gmc_v6_0_early_init(void *handle)
 793 {
 794         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 795
 796         gmc_v6_0_set_gart_funcs(adev);
 797         gmc_v6_0_set_irq_funcs(adev);
 798
 799         if (adev->flags & AMD_IS_APU) {
 800                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 801         } else {
 802                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 803                 tmp &= MC_SEQ_MISC0__MT__MASK;
 804                 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp);
 805         }
 806
 807         return 0;
 808 }
 809
 810 static int gmc_v6_0_late_init(void *handle)
 811 {
 812         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 813
 814         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 815                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 816         else
 817                 return 0;
 818 }
 819
 820 static int gmc_v6_0_sw_init(void *handle)
 821 {
 822         int r;
 823         int dma_bits;
 824         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 825
 826         r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
 827         if (r)
 828                 return r;
 829
 830         r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
 831         if (r)
 832                 return r;
 833
 834         adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
 835
 836         adev->mc.mc_mask = 0xffffffffffULL;
 837
 838         adev->need_dma32 = false;
 839         dma_bits = adev->need_dma32 ? 32 : 40;
 840         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 841         if (r) {
 842                 adev->need_dma32 = true;
 843                 dma_bits = 32;
 844                 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
 845         }
 846         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 847         if (r) {
 848                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 849                 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
 850         }
 851
 852         r = gmc_v6_0_init_microcode(adev);
 853         if (r) {
 854                 dev_err(adev->dev, "Failed to load mc firmware!\n");
 855                 return r;
 856         }
 857
 858         r = gmc_v6_0_mc_init(adev);
 859         if (r)
 860                 return r;
 861
 862         r = amdgpu_bo_init(adev);
 863         if (r)
 864                 return r;
 865
 866         r = gmc_v6_0_gart_init(adev);
 867         if (r)
 868                 return r;
 869
 870         if (!adev->vm_manager.enabled) {
 871                 r = gmc_v6_0_vm_init(adev);
 872                 if (r) {
 873                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
 874                         return r;
 875                 }
 876                 adev->vm_manager.enabled = true;
 877         }
 878
 879         return r;
 880 }
 881
 882 static int gmc_v6_0_sw_fini(void *handle)
 883 {
 884         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 885
 886         if (adev->vm_manager.enabled) {
 887                 gmc_v6_0_vm_fini(adev);
 888                 adev->vm_manager.enabled = false;
 889         }
 890         gmc_v6_0_gart_fini(adev);
 891         amdgpu_gem_force_release(adev);
 892         amdgpu_bo_fini(adev);
 893
 894         return 0;
 895 }
 896
 897 static int gmc_v6_0_hw_init(void *handle)
 898 {
 899         int r;
 900         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 901
 902         gmc_v6_0_mc_program(adev);
 903
 904         if (!(adev->flags & AMD_IS_APU)) {
 905                 r = gmc_v6_0_mc_load_microcode(adev);
 906                 if (r) {
 907                         dev_err(adev->dev, "Failed to load MC firmware!\n");
 908                         return r;
 909                 }
 910         }
 911
 912         r = gmc_v6_0_gart_enable(adev);
 913         if (r)
 914                 return r;
 915
 916         return r;
 917 }
 918
 919 static int gmc_v6_0_hw_fini(void *handle)
 920 {
 921         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 922
 923         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
 924         gmc_v6_0_gart_disable(adev);
 925
 926         return 0;
 927 }
 928
 929 static int gmc_v6_0_suspend(void *handle)
 930 {
 931         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 932
 933         if (adev->vm_manager.enabled) {
 934                 gmc_v6_0_vm_fini(adev);
 935                 adev->vm_manager.enabled = false;
 936         }
 937         gmc_v6_0_hw_fini(adev);
 938
 939         return 0;
 940 }
 941
 942 static int gmc_v6_0_resume(void *handle)
 943 {
 944         int r;
 945         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 946
 947         r = gmc_v6_0_hw_init(adev);
 948         if (r)
 949                 return r;
 950
 951         if (!adev->vm_manager.enabled) {
 952                 r = gmc_v6_0_vm_init(adev);
 953                 if (r) {
 954                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
 955                         return r;
 956                 }
 957                 adev->vm_manager.enabled = true;
 958         }
 959
 960         return r;
 961 }
 962
 963 static bool gmc_v6_0_is_idle(void *handle)
 964 {
 965         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 966         u32 tmp = RREG32(mmSRBM_STATUS);
 967
 968         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 969                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
 970                 return false;
 971
 972         return true;
 973 }
 974
 975 static int gmc_v6_0_wait_for_idle(void *handle)
 976 {
 977         unsigned i;
 978         u32 tmp;
 979         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 980
 981         for (i = 0; i < adev->usec_timeout; i++) {
 982                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
 983                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 984                                                SRBM_STATUS__MCC_BUSY_MASK |
 985                                                SRBM_STATUS__MCD_BUSY_MASK |
 986                                                SRBM_STATUS__VMC_BUSY_MASK);
 987                 if (!tmp)
 988                         return 0;
 989                 udelay(1);
 990         }
 991         return -ETIMEDOUT;
 992
 993 }
 994
 995 static int gmc_v6_0_soft_reset(void *handle)
 996 {
 997         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 998         struct amdgpu_mode_mc_save save;
 999         u32 srbm_soft_reset = 0;
1000         u32 tmp = RREG32(mmSRBM_STATUS);
1001
1002         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1003                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1004                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1005
1006         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1007                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1008                 if (!(adev->flags & AMD_IS_APU))
1009                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1010                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1011         }
1012
1013         if (srbm_soft_reset) {
1014                 gmc_v6_0_mc_stop(adev, &save);
1015                 if (gmc_v6_0_wait_for_idle(adev)) {
1016                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1017                 }
1018
1019
1020                 tmp = RREG32(mmSRBM_SOFT_RESET);
1021                 tmp |= srbm_soft_reset;
1022                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1023                 WREG32(mmSRBM_SOFT_RESET, tmp);
1024                 tmp = RREG32(mmSRBM_SOFT_RESET);
1025
1026                 udelay(50);
1027
1028                 tmp &= ~srbm_soft_reset;
1029                 WREG32(mmSRBM_SOFT_RESET, tmp);
1030                 tmp = RREG32(mmSRBM_SOFT_RESET);
1031
1032                 udelay(50);
1033
1034                 gmc_v6_0_mc_resume(adev, &save);
1035                 udelay(50);
1036         }
1037
1038         return 0;
1039 }
1040
1041 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1042                                              struct amdgpu_irq_src *src,
1043                                              unsigned type,
1044                                              enum amdgpu_interrupt_state state)
1045 {
1046         u32 tmp;
1047         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1048                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1049                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1050                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1051                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1052                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1053
1054         switch (state) {
1055         case AMDGPU_IRQ_STATE_DISABLE:
1056                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1057                 tmp &= ~bits;
1058                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1059                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1060                 tmp &= ~bits;
1061                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1062                 break;
1063         case AMDGPU_IRQ_STATE_ENABLE:
1064                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1065                 tmp |= bits;
1066                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1067                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1068                 tmp |= bits;
1069                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1070                 break;
1071         default:
1072                 break;
1073         }
1074
1075         return 0;
1076 }
1077
1078 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1079                                       struct amdgpu_irq_src *source,
1080                                       struct amdgpu_iv_entry *entry)
1081 {
1082         u32 addr, status;
1083
1084         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1085         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1086         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1087
1088         if (!addr && !status)
1089                 return 0;
1090
1091         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1092                 gmc_v6_0_set_fault_enable_default(adev, false);
1093
1094         if (printk_ratelimit()) {
1095                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1096                         entry->src_id, entry->src_data);
1097                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1098                         addr);
1099                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1100                         status);
1101                 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1102         }
1103
1104         return 0;
1105 }
1106
1107 static int gmc_v6_0_set_clockgating_state(void *handle,
1108                                           enum amd_clockgating_state state)
1109 {
1110         return 0;
1111 }
1112
1113 static int gmc_v6_0_set_powergating_state(void *handle,
1114                                           enum amd_powergating_state state)
1115 {
1116         return 0;
1117 }
1118
1119 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1120         .name = "gmc_v6_0",
1121         .early_init = gmc_v6_0_early_init,
1122         .late_init = gmc_v6_0_late_init,
1123         .sw_init = gmc_v6_0_sw_init,
1124         .sw_fini = gmc_v6_0_sw_fini,
1125         .hw_init = gmc_v6_0_hw_init,
1126         .hw_fini = gmc_v6_0_hw_fini,
1127         .suspend = gmc_v6_0_suspend,
1128         .resume = gmc_v6_0_resume,
1129         .is_idle = gmc_v6_0_is_idle,
1130         .wait_for_idle = gmc_v6_0_wait_for_idle,
1131         .soft_reset = gmc_v6_0_soft_reset,
1132         .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1133         .set_powergating_state = gmc_v6_0_set_powergating_state,
1134 };
1135
1136 static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
1137         .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
1138         .set_pte_pde = gmc_v6_0_gart_set_pte_pde,
1139         .set_prt = gmc_v6_0_set_prt,
1140 };
1141
1142 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1143         .set = gmc_v6_0_vm_fault_interrupt_state,
1144         .process = gmc_v6_0_process_interrupt,
1145 };
1146
1147 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev)
1148 {
1149         if (adev->gart.gart_funcs == NULL)
1150                 adev->gart.gart_funcs = &gmc_v6_0_gart_funcs;
1151 }
1152
1153 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1154 {
1155         adev->mc.vm_fault.num_types = 1;
1156         adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1157 }
1158
1159 const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1160 {
1161         .type = AMD_IP_BLOCK_TYPE_GMC,
1162         .major = 6,
1163         .minor = 0,
1164         .rev = 0,
1165         .funcs = &gmc_v6_0_ip_funcs,
1166 };