drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "gmc_v8_0.h"
  27 #include "amdgpu_ucode.h"
  28
  29 #include "gmc/gmc_8_1_d.h"
  30 #include "gmc/gmc_8_1_sh_mask.h"
  31
  32 #include "bif/bif_5_0_d.h"
  33 #include "bif/bif_5_0_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "vid.h"
  39 #include "vi.h"
  40
  41
  42 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
  43 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  44 static int gmc_v8_0_wait_for_idle(void *handle);
  45
  46 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
  47 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
  48 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
  49 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
  50
  51 static const u32 golden_settings_tonga_a11[] =
  52 {
  53         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  54         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  55         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  56         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  57         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  58         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  59         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  60 };
  61
  62 static const u32 tonga_mgcg_cgcg_init[] =
  63 {
  64         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  65 };
  66
  67 static const u32 golden_settings_fiji_a10[] =
  68 {
  69         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  70         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  71         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  72         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  73 };
  74
  75 static const u32 fiji_mgcg_cgcg_init[] =
  76 {
  77         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  78 };
  79
  80 static const u32 golden_settings_polaris11_a11[] =
  81 {
  82         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  83         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  84         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  85         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  86 };
  87
  88 static const u32 golden_settings_polaris10_a11[] =
  89 {
  90         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  91         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  92         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  93         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  94         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  95 };
  96
  97 static const u32 cz_mgcg_cgcg_init[] =
  98 {
  99         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 100 };
 101
 102 static const u32 stoney_mgcg_cgcg_init[] =
 103 {
 104         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 105         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 106 };
 107
 108 static const u32 golden_settings_stoney_common[] =
 109 {
 110         mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
 111         mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
 112 };
 113
 114 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 115 {
 116         switch (adev->asic_type) {
 117         case CHIP_FIJI:
 118                 amdgpu_program_register_sequence(adev,
 119                                                  fiji_mgcg_cgcg_init,
 120                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 121                 amdgpu_program_register_sequence(adev,
 122                                                  golden_settings_fiji_a10,
 123                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 124                 break;
 125         case CHIP_TONGA:
 126                 amdgpu_program_register_sequence(adev,
 127                                                  tonga_mgcg_cgcg_init,
 128                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 129                 amdgpu_program_register_sequence(adev,
 130                                                  golden_settings_tonga_a11,
 131                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 132                 break;
 133         case CHIP_POLARIS11:
 134         case CHIP_POLARIS12:
 135                 amdgpu_program_register_sequence(adev,
 136                                                  golden_settings_polaris11_a11,
 137                                                  (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
 138                 break;
 139         case CHIP_POLARIS10:
 140                 amdgpu_program_register_sequence(adev,
 141                                                  golden_settings_polaris10_a11,
 142                                                  (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
 143                 break;
 144         case CHIP_CARRIZO:
 145                 amdgpu_program_register_sequence(adev,
 146                                                  cz_mgcg_cgcg_init,
 147                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 148                 break;
 149         case CHIP_STONEY:
 150                 amdgpu_program_register_sequence(adev,
 151                                                  stoney_mgcg_cgcg_init,
 152                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 153                 amdgpu_program_register_sequence(adev,
 154                                                  golden_settings_stoney_common,
 155                                                  (const u32)ARRAY_SIZE(golden_settings_stoney_common));
 156                 break;
 157         default:
 158                 break;
 159         }
 160 }
 161
 162 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
 163                              struct amdgpu_mode_mc_save *save)
 164 {
 165         u32 blackout;
 166
 167         if (adev->mode_info.num_crtc)
 168                 amdgpu_display_stop_mc_access(adev, save);
 169
 170         gmc_v8_0_wait_for_idle(adev);
 171
 172         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 173         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 174                 /* Block CPU access */
 175                 WREG32(mmBIF_FB_EN, 0);
 176                 /* blackout the MC */
 177                 blackout = REG_SET_FIELD(blackout,
 178                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 179                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 180         }
 181         /* wait for the MC to settle */
 182         udelay(100);
 183 }
 184
 185 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
 186                                struct amdgpu_mode_mc_save *save)
 187 {
 188         u32 tmp;
 189
 190         /* unblackout the MC */
 191         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 192         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 193         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 194         /* allow CPU access */
 195         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 196         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 197         WREG32(mmBIF_FB_EN, tmp);
 198
 199         if (adev->mode_info.num_crtc)
 200                 amdgpu_display_resume_mc_access(adev, save);
 201 }
 202
 203 /**
 204  * gmc_v8_0_init_microcode - load ucode images from disk
 205  *
 206  * @adev: amdgpu_device pointer
 207  *
 208  * Use the firmware interface to load the ucode images into
 209  * the driver (not loaded into hw).
 210  * Returns 0 on success, error on failure.
 211  */
 212 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 213 {
 214         const char *chip_name;
 215         char fw_name[30];
 216         int err;
 217
 218         DRM_DEBUG("\n");
 219
 220         switch (adev->asic_type) {
 221         case CHIP_TONGA:
 222                 chip_name = "tonga";
 223                 break;
 224         case CHIP_POLARIS11:
 225                 chip_name = "polaris11";
 226                 break;
 227         case CHIP_POLARIS10:
 228                 chip_name = "polaris10";
 229                 break;
 230         case CHIP_POLARIS12:
 231                 chip_name = "polaris12";
 232                 break;
 233         case CHIP_FIJI:
 234         case CHIP_CARRIZO:
 235         case CHIP_STONEY:
 236                 return 0;
 237         default: BUG();
 238         }
 239
 240         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 241         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 242         if (err)
 243                 goto out;
 244         err = amdgpu_ucode_validate(adev->mc.fw);
 245
 246 out:
 247         if (err) {
 248                 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
 249                 release_firmware(adev->mc.fw);
 250                 adev->mc.fw = NULL;
 251         }
 252         return err;
 253 }
 254
 255 /**
 256  * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
 257  *
 258  * @adev: amdgpu_device pointer
 259  *
 260  * Load the GDDR MC ucode into the hw (CIK).
 261  * Returns 0 on success, error on failure.
 262  */
 263 static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev)
 264 {
 265         const struct mc_firmware_header_v1_0 *hdr;
 266         const __le32 *fw_data = NULL;
 267         const __le32 *io_mc_regs = NULL;
 268         u32 running;
 269         int i, ucode_size, regs_size;
 270
 271         if (!adev->mc.fw)
 272                 return -EINVAL;
 273
 274         /* Skip MC ucode loading on SR-IOV capable boards.
 275          * vbios does this for us in asic_init in that case.
 276          * Skip MC ucode loading on VF, because hypervisor will do that
 277          * for this adaptor.
 278          */
 279         if (amdgpu_sriov_bios(adev))
 280                 return 0;
 281
 282         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 283         amdgpu_ucode_print_mc_hdr(&hdr->header);
 284
 285         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 286         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 287         io_mc_regs = (const __le32 *)
 288                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 289         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 290         fw_data = (const __le32 *)
 291                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 292
 293         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 294
 295         if (running == 0) {
 296                 /* reset the engine and set to writable */
 297                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 298                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 299
 300                 /* load mc io regs */
 301                 for (i = 0; i < regs_size; i++) {
 302                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 303                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 304                 }
 305                 /* load the MC ucode */
 306                 for (i = 0; i < ucode_size; i++)
 307                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 308
 309                 /* put the engine back into the active state */
 310                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 311                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 312                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 313
 314                 /* wait for training to complete */
 315                 for (i = 0; i < adev->usec_timeout; i++) {
 316                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 317                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 318                                 break;
 319                         udelay(1);
 320                 }
 321                 for (i = 0; i < adev->usec_timeout; i++) {
 322                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 323                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 324                                 break;
 325                         udelay(1);
 326                 }
 327         }
 328
 329         return 0;
 330 }
 331
 332 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 333                                        struct amdgpu_mc *mc)
 334 {
 335         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 336                 /* leave room for at least 1024M GTT */
 337                 dev_warn(adev->dev, "limiting VRAM\n");
 338                 mc->real_vram_size = 0xFFC0000000ULL;
 339                 mc->mc_vram_size = 0xFFC0000000ULL;
 340         }
 341         amdgpu_vram_location(adev, &adev->mc, 0);
 342         adev->mc.gtt_base_align = 0;
 343         amdgpu_gtt_location(adev, mc);
 344 }
 345
 346 /**
 347  * gmc_v8_0_mc_program - program the GPU memory controller
 348  *
 349  * @adev: amdgpu_device pointer
 350  *
 351  * Set the location of vram, gart, and AGP in the GPU's
 352  * physical address space (CIK).
 353  */
 354 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 355 {
 356         struct amdgpu_mode_mc_save save;
 357         u32 tmp;
 358         int i, j;
 359
 360         /* Initialize HDP */
 361         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 362                 WREG32((0xb05 + j), 0x00000000);
 363                 WREG32((0xb06 + j), 0x00000000);
 364                 WREG32((0xb07 + j), 0x00000000);
 365                 WREG32((0xb08 + j), 0x00000000);
 366                 WREG32((0xb09 + j), 0x00000000);
 367         }
 368         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 369
 370         if (adev->mode_info.num_crtc)
 371                 amdgpu_display_set_vga_render_state(adev, false);
 372
 373         gmc_v8_0_mc_stop(adev, &save);
 374         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 375                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 376         }
 377         /* Update configuration */
 378         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 379                adev->mc.vram_start >> 12);
 380         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 381                adev->mc.vram_end >> 12);
 382         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 383                adev->vram_scratch.gpu_addr >> 12);
 384         tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 385         tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 386         WREG32(mmMC_VM_FB_LOCATION, tmp);
 387         /* XXX double check these! */
 388         WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 389         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 390         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 391         WREG32(mmMC_VM_AGP_BASE, 0);
 392         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 393         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 394         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 395                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 396         }
 397         gmc_v8_0_mc_resume(adev, &save);
 398
 399         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 400
 401         tmp = RREG32(mmHDP_MISC_CNTL);
 402         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 403         WREG32(mmHDP_MISC_CNTL, tmp);
 404
 405         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 406         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 407 }
 408
 409 /**
 410  * gmc_v8_0_mc_init - initialize the memory controller driver params
 411  *
 412  * @adev: amdgpu_device pointer
 413  *
 414  * Look up the amount of vram, vram width, and decide how to place
 415  * vram and gart within the GPU's physical address space (CIK).
 416  * Returns 0 for success.
 417  */
 418 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 419 {
 420         u32 tmp;
 421         int chansize, numchan;
 422
 423         /* Get VRAM informations */
 424         tmp = RREG32(mmMC_ARB_RAMCFG);
 425         if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 426                 chansize = 64;
 427         } else {
 428                 chansize = 32;
 429         }
 430         tmp = RREG32(mmMC_SHARED_CHMAP);
 431         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 432         case 0:
 433         default:
 434                 numchan = 1;
 435                 break;
 436         case 1:
 437                 numchan = 2;
 438                 break;
 439         case 2:
 440                 numchan = 4;
 441                 break;
 442         case 3:
 443                 numchan = 8;
 444                 break;
 445         case 4:
 446                 numchan = 3;
 447                 break;
 448         case 5:
 449                 numchan = 6;
 450                 break;
 451         case 6:
 452                 numchan = 10;
 453                 break;
 454         case 7:
 455                 numchan = 12;
 456                 break;
 457         case 8:
 458                 numchan = 16;
 459                 break;
 460         }
 461         adev->mc.vram_width = numchan * chansize;
 462         /* Could aper size report 0 ? */
 463         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 464         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 465         /* size in MB on si */
 466         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 467         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 468
 469 #ifdef CONFIG_X86_64
 470         if (adev->flags & AMD_IS_APU) {
 471                 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 472                 adev->mc.aper_size = adev->mc.real_vram_size;
 473         }
 474 #endif
 475
 476         /* In case the PCI BAR is larger than the actual amount of vram */
 477         adev->mc.visible_vram_size = adev->mc.aper_size;
 478         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 479                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 480
 481         /* unless the user had overridden it, set the gart
 482          * size equal to the 1024 or vram, whichever is larger.
 483          */
 484         if (amdgpu_gart_size == -1)
 485                 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
 486         else
 487                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 488
 489         gmc_v8_0_vram_gtt_location(adev, &adev->mc);
 490
 491         return 0;
 492 }
 493
 494 /*
 495  * GART
 496  * VMID 0 is the physical GPU addresses as used by the kernel.
 497  * VMIDs 1-15 are used for userspace clients and are handled
 498  * by the amdgpu vm/hsa code.
 499  */
 500
 501 /**
 502  * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
 503  *
 504  * @adev: amdgpu_device pointer
 505  * @vmid: vm instance to flush
 506  *
 507  * Flush the TLB for the requested page table (CIK).
 508  */
 509 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 510                                         uint32_t vmid)
 511 {
 512         /* flush hdp cache */
 513         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 514
 515         /* bits 0-15 are the VM contexts0-15 */
 516         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 517 }
 518
 519 /**
 520  * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
 521  *
 522  * @adev: amdgpu_device pointer
 523  * @cpu_pt_addr: cpu address of the page table
 524  * @gpu_page_idx: entry in the page table to update
 525  * @addr: dst addr to write into pte/pde
 526  * @flags: access flags
 527  *
 528  * Update the page tables using the CPU.
 529  */
 530 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
 531                                      void *cpu_pt_addr,
 532                                      uint32_t gpu_page_idx,
 533                                      uint64_t addr,
 534                                      uint32_t flags)
 535 {
 536         void __iomem *ptr = (void *)cpu_pt_addr;
 537         uint64_t value;
 538
 539         /*
 540          * PTE format on VI:
 541          * 63:40 reserved
 542          * 39:12 4k physical page base address
 543          * 11:7 fragment
 544          * 6 write
 545          * 5 read
 546          * 4 exe
 547          * 3 reserved
 548          * 2 snooped
 549          * 1 system
 550          * 0 valid
 551          *
 552          * PDE format on VI:
 553          * 63:59 block fragment size
 554          * 58:40 reserved
 555          * 39:1 physical base address of PTE
 556          * bits 5:1 must be 0.
 557          * 0 valid
 558          */
 559         value = addr & 0x000000FFFFFFF000ULL;
 560         value |= flags;
 561         writeq(value, ptr + (gpu_page_idx * 8));
 562
 563         return 0;
 564 }
 565
 566 /**
 567  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 568  *
 569  * @adev: amdgpu_device pointer
 570  * @value: true redirects VM faults to the default page
 571  */
 572 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 573                                               bool value)
 574 {
 575         u32 tmp;
 576
 577         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 578         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 579                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 580         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 581                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 582         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 583                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 584         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 585                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 586         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 587                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 588         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 589                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 590         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 591                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 592         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 593 }
 594
 595 /**
 596  * gmc_v8_0_set_prt - set PRT VM fault
 597  *
 598  * @adev: amdgpu_device pointer
 599  * @enable: enable/disable VM fault handling for PRT
 600 */
 601 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
 602 {
 603         u32 tmp;
 604
 605         if (enable && !adev->mc.prt_warning) {
 606                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 607                 adev->mc.prt_warning = true;
 608         }
 609
 610         tmp = RREG32(mmVM_PRT_CNTL);
 611         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 612                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 613         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 614                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 615         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 616                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 617         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 618                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 619         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 620                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 621         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 622                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 623         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 624                             MASK_PDE0_FAULT, enable);
 625         WREG32(mmVM_PRT_CNTL, tmp);
 626
 627         if (enable) {
 628                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 629                 uint32_t high = adev->vm_manager.max_pfn;
 630
 631                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 632                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 633                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 634                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 635                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 636                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 637                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 638                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 639         } else {
 640                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 641                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 642                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 643                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 644                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 645                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 646                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 647                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 648         }
 649 }
 650
 651 /**
 652  * gmc_v8_0_gart_enable - gart enable
 653  *
 654  * @adev: amdgpu_device pointer
 655  *
 656  * This sets up the TLBs, programs the page tables for VMID0,
 657  * sets up the hw for VMIDs 1-15 which are allocated on
 658  * demand, and sets up the global locations for the LDS, GDS,
 659  * and GPUVM for FSA64 clients (CIK).
 660  * Returns 0 for success, errors for failure.
 661  */
 662 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 663 {
 664         int r, i;
 665         u32 tmp;
 666
 667         if (adev->gart.robj == NULL) {
 668                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 669                 return -EINVAL;
 670         }
 671         r = amdgpu_gart_table_vram_pin(adev);
 672         if (r)
 673                 return r;
 674         /* Setup TLB control */
 675         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 676         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 677         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 678         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 679         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 680         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 681         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 682         /* Setup L2 cache */
 683         tmp = RREG32(mmVM_L2_CNTL);
 684         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 685         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 686         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 687         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 688         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 689         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 690         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 691         WREG32(mmVM_L2_CNTL, tmp);
 692         tmp = RREG32(mmVM_L2_CNTL2);
 693         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 694         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 695         WREG32(mmVM_L2_CNTL2, tmp);
 696         tmp = RREG32(mmVM_L2_CNTL3);
 697         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 698         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
 699         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
 700         WREG32(mmVM_L2_CNTL3, tmp);
 701         /* XXX: set to enable PTE/PDE in system memory */
 702         tmp = RREG32(mmVM_L2_CNTL4);
 703         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 704         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 705         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 706         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 707         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 708         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 709         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 710         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 711         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 712         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 713         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 714         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 715         WREG32(mmVM_L2_CNTL4, tmp);
 716         /* setup context0 */
 717         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 718         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
 719         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 720         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 721                         (u32)(adev->dummy_page.addr >> 12));
 722         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 723         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 724         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 725         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 726         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 727         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 728
 729         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 730         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 731         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 732
 733         /* empty context1-15 */
 734         /* FIXME start with 4G, once using 2 level pt switch to full
 735          * vm size space
 736          */
 737         /* set vm size, must be a multiple of 4 */
 738         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 739         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 740         for (i = 1; i < 16; i++) {
 741                 if (i < 8)
 742                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 743                                adev->gart.table_addr >> 12);
 744                 else
 745                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 746                                adev->gart.table_addr >> 12);
 747         }
 748
 749         /* enable context1-15 */
 750         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 751                (u32)(adev->dummy_page.addr >> 12));
 752         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 753         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 754         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 755         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 756         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 757         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 758         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 759         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 760         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 761         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 762         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 763         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 764                             amdgpu_vm_block_size - 9);
 765         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 766         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 767                 gmc_v8_0_set_fault_enable_default(adev, false);
 768         else
 769                 gmc_v8_0_set_fault_enable_default(adev, true);
 770
 771         gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
 772         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 773                  (unsigned)(adev->mc.gtt_size >> 20),
 774                  (unsigned long long)adev->gart.table_addr);
 775         adev->gart.ready = true;
 776         return 0;
 777 }
 778
 779 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 780 {
 781         int r;
 782
 783         if (adev->gart.robj) {
 784                 WARN(1, "R600 PCIE GART already initialized\n");
 785                 return 0;
 786         }
 787         /* Initialize common gart structure */
 788         r = amdgpu_gart_init(adev);
 789         if (r)
 790                 return r;
 791         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 792         return amdgpu_gart_table_vram_alloc(adev);
 793 }
 794
 795 /**
 796  * gmc_v8_0_gart_disable - gart disable
 797  *
 798  * @adev: amdgpu_device pointer
 799  *
 800  * This disables all VM page table (CIK).
 801  */
 802 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 803 {
 804         u32 tmp;
 805
 806         /* Disable all tables */
 807         WREG32(mmVM_CONTEXT0_CNTL, 0);
 808         WREG32(mmVM_CONTEXT1_CNTL, 0);
 809         /* Setup TLB control */
 810         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 811         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 812         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 813         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 814         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 815         /* Setup L2 cache */
 816         tmp = RREG32(mmVM_L2_CNTL);
 817         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 818         WREG32(mmVM_L2_CNTL, tmp);
 819         WREG32(mmVM_L2_CNTL2, 0);
 820         amdgpu_gart_table_vram_unpin(adev);
 821 }
 822
 823 /**
 824  * gmc_v8_0_gart_fini - vm fini callback
 825  *
 826  * @adev: amdgpu_device pointer
 827  *
 828  * Tears down the driver GART/VM setup (CIK).
 829  */
 830 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
 831 {
 832         amdgpu_gart_table_vram_free(adev);
 833         amdgpu_gart_fini(adev);
 834 }
 835
 836 /*
 837  * vm
 838  * VMID 0 is the physical GPU addresses as used by the kernel.
 839  * VMIDs 1-15 are used for userspace clients and are handled
 840  * by the amdgpu vm/hsa code.
 841  */
 842 /**
 843  * gmc_v8_0_vm_init - cik vm init callback
 844  *
 845  * @adev: amdgpu_device pointer
 846  *
 847  * Inits cik specific vm parameters (number of VMs, base of vram for
 848  * VMIDs 1-15) (CIK).
 849  * Returns 0 for success.
 850  */
 851 static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
 852 {
 853         /*
 854          * number of VMs
 855          * VMID 0 is reserved for System
 856          * amdgpu graphics/compute will use VMIDs 1-7
 857          * amdkfd will use VMIDs 8-15
 858          */
 859         adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
 860         amdgpu_vm_manager_init(adev);
 861
 862         /* base offset of vram pages */
 863         if (adev->flags & AMD_IS_APU) {
 864                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 865                 tmp <<= 22;
 866                 adev->vm_manager.vram_base_offset = tmp;
 867         } else
 868                 adev->vm_manager.vram_base_offset = 0;
 869
 870         return 0;
 871 }
 872
 873 /**
 874  * gmc_v8_0_vm_fini - cik vm fini callback
 875  *
 876  * @adev: amdgpu_device pointer
 877  *
 878  * Tear down any asic specific VM setup (CIK).
 879  */
 880 static void gmc_v8_0_vm_fini(struct amdgpu_device *adev)
 881 {
 882 }
 883
 884 /**
 885  * gmc_v8_0_vm_decode_fault - print human readable fault info
 886  *
 887  * @adev: amdgpu_device pointer
 888  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 889  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 890  *
 891  * Print human readable fault information (CIK).
 892  */
 893 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
 894                                      u32 status, u32 addr, u32 mc_client)
 895 {
 896         u32 mc_id;
 897         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 898         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 899                                         PROTECTIONS);
 900         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 901                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 902
 903         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 904                               MEMORY_CLIENT_ID);
 905
 906         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 907                protections, vmid, addr,
 908                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 909                              MEMORY_CLIENT_RW) ?
 910                "write" : "read", block, mc_client, mc_id);
 911 }
 912
 913 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
 914 {
 915         switch (mc_seq_vram_type) {
 916         case MC_SEQ_MISC0__MT__GDDR1:
 917                 return AMDGPU_VRAM_TYPE_GDDR1;
 918         case MC_SEQ_MISC0__MT__DDR2:
 919                 return AMDGPU_VRAM_TYPE_DDR2;
 920         case MC_SEQ_MISC0__MT__GDDR3:
 921                 return AMDGPU_VRAM_TYPE_GDDR3;
 922         case MC_SEQ_MISC0__MT__GDDR4:
 923                 return AMDGPU_VRAM_TYPE_GDDR4;
 924         case MC_SEQ_MISC0__MT__GDDR5:
 925                 return AMDGPU_VRAM_TYPE_GDDR5;
 926         case MC_SEQ_MISC0__MT__HBM:
 927                 return AMDGPU_VRAM_TYPE_HBM;
 928         case MC_SEQ_MISC0__MT__DDR3:
 929                 return AMDGPU_VRAM_TYPE_DDR3;
 930         default:
 931                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 932         }
 933 }
 934
 935 static int gmc_v8_0_early_init(void *handle)
 936 {
 937         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 938
 939         gmc_v8_0_set_gart_funcs(adev);
 940         gmc_v8_0_set_irq_funcs(adev);
 941
 942         adev->mc.shared_aperture_start = 0x2000000000000000ULL;
 943         adev->mc.shared_aperture_end =
 944                 adev->mc.shared_aperture_start + (4ULL << 30) - 1;
 945         adev->mc.private_aperture_start =
 946                 adev->mc.shared_aperture_end + 1;
 947         adev->mc.private_aperture_end =
 948                 adev->mc.private_aperture_start + (4ULL << 30) - 1;
 949
 950         return 0;
 951 }
 952
 953 static int gmc_v8_0_late_init(void *handle)
 954 {
 955         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 956
 957         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 958                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 959         else
 960                 return 0;
 961 }
 962
 963 #define mmMC_SEQ_MISC0_FIJI 0xA71
 964
 965 static int gmc_v8_0_sw_init(void *handle)
 966 {
 967         int r;
 968         int dma_bits;
 969         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 970
 971         if (adev->flags & AMD_IS_APU) {
 972                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 973         } else {
 974                 u32 tmp;
 975
 976                 if (adev->asic_type == CHIP_FIJI)
 977                         tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
 978                 else
 979                         tmp = RREG32(mmMC_SEQ_MISC0);
 980                 tmp &= MC_SEQ_MISC0__MT__MASK;
 981                 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
 982         }
 983
 984         r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
 985         if (r)
 986                 return r;
 987
 988         r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
 989         if (r)
 990                 return r;
 991
 992         /* Adjust VM size here.
 993          * Currently set to 4GB ((1 << 20) 4k pages).
 994          * Max GPUVM size for cayman and SI is 40 bits.
 995          */
 996         adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
 997
 998         /* Set the internal MC address mask
 999          * This is the max address of the GPU's
1000          * internal address space.
1001          */
1002         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1003
1004         /* set DMA mask + need_dma32 flags.
1005          * PCIE - can handle 40-bits.
1006          * IGP - can handle 40-bits
1007          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1008          */
1009         adev->need_dma32 = false;
1010         dma_bits = adev->need_dma32 ? 32 : 40;
1011         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1012         if (r) {
1013                 adev->need_dma32 = true;
1014                 dma_bits = 32;
1015                 pr_warn("amdgpu: No suitable DMA available\n");
1016         }
1017         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1018         if (r) {
1019                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1020                 pr_warn("amdgpu: No coherent DMA available\n");
1021         }
1022
1023         r = gmc_v8_0_init_microcode(adev);
1024         if (r) {
1025                 DRM_ERROR("Failed to load mc firmware!\n");
1026                 return r;
1027         }
1028
1029         r = gmc_v8_0_mc_init(adev);
1030         if (r)
1031                 return r;
1032
1033         /* Memory manager */
1034         r = amdgpu_bo_init(adev);
1035         if (r)
1036                 return r;
1037
1038         r = gmc_v8_0_gart_init(adev);
1039         if (r)
1040                 return r;
1041
1042         if (!adev->vm_manager.enabled) {
1043                 r = gmc_v8_0_vm_init(adev);
1044                 if (r) {
1045                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1046                         return r;
1047                 }
1048                 adev->vm_manager.enabled = true;
1049         }
1050
1051         return r;
1052 }
1053
1054 static int gmc_v8_0_sw_fini(void *handle)
1055 {
1056         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1057
1058         if (adev->vm_manager.enabled) {
1059                 amdgpu_vm_manager_fini(adev);
1060                 gmc_v8_0_vm_fini(adev);
1061                 adev->vm_manager.enabled = false;
1062         }
1063         gmc_v8_0_gart_fini(adev);
1064         amdgpu_gem_force_release(adev);
1065         amdgpu_bo_fini(adev);
1066
1067         return 0;
1068 }
1069
1070 static int gmc_v8_0_hw_init(void *handle)
1071 {
1072         int r;
1073         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1074
1075         gmc_v8_0_init_golden_registers(adev);
1076
1077         gmc_v8_0_mc_program(adev);
1078
1079         if (adev->asic_type == CHIP_TONGA) {
1080                 r = gmc_v8_0_mc_load_microcode(adev);
1081                 if (r) {
1082                         DRM_ERROR("Failed to load MC firmware!\n");
1083                         return r;
1084                 }
1085         }
1086
1087         r = gmc_v8_0_gart_enable(adev);
1088         if (r)
1089                 return r;
1090
1091         return r;
1092 }
1093
1094 static int gmc_v8_0_hw_fini(void *handle)
1095 {
1096         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1097
1098         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1099         gmc_v8_0_gart_disable(adev);
1100
1101         return 0;
1102 }
1103
1104 static int gmc_v8_0_suspend(void *handle)
1105 {
1106         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1107
1108         if (adev->vm_manager.enabled) {
1109                 gmc_v8_0_vm_fini(adev);
1110                 adev->vm_manager.enabled = false;
1111         }
1112         gmc_v8_0_hw_fini(adev);
1113
1114         return 0;
1115 }
1116
1117 static int gmc_v8_0_resume(void *handle)
1118 {
1119         int r;
1120         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1121
1122         r = gmc_v8_0_hw_init(adev);
1123         if (r)
1124                 return r;
1125
1126         if (!adev->vm_manager.enabled) {
1127                 r = gmc_v8_0_vm_init(adev);
1128                 if (r) {
1129                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1130                         return r;
1131                 }
1132                 adev->vm_manager.enabled = true;
1133         }
1134
1135         return r;
1136 }
1137
1138 static bool gmc_v8_0_is_idle(void *handle)
1139 {
1140         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1141         u32 tmp = RREG32(mmSRBM_STATUS);
1142
1143         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1144                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1145                 return false;
1146
1147         return true;
1148 }
1149
1150 static int gmc_v8_0_wait_for_idle(void *handle)
1151 {
1152         unsigned i;
1153         u32 tmp;
1154         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1155
1156         for (i = 0; i < adev->usec_timeout; i++) {
1157                 /* read MC_STATUS */
1158                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1159                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1160                                                SRBM_STATUS__MCC_BUSY_MASK |
1161                                                SRBM_STATUS__MCD_BUSY_MASK |
1162                                                SRBM_STATUS__VMC_BUSY_MASK |
1163                                                SRBM_STATUS__VMC1_BUSY_MASK);
1164                 if (!tmp)
1165                         return 0;
1166                 udelay(1);
1167         }
1168         return -ETIMEDOUT;
1169
1170 }
1171
1172 static bool gmc_v8_0_check_soft_reset(void *handle)
1173 {
1174         u32 srbm_soft_reset = 0;
1175         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1176         u32 tmp = RREG32(mmSRBM_STATUS);
1177
1178         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1179                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1180                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1181
1182         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1183                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1184                 if (!(adev->flags & AMD_IS_APU))
1185                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1186                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1187         }
1188         if (srbm_soft_reset) {
1189                 adev->mc.srbm_soft_reset = srbm_soft_reset;
1190                 return true;
1191         } else {
1192                 adev->mc.srbm_soft_reset = 0;
1193                 return false;
1194         }
1195 }
1196
1197 static int gmc_v8_0_pre_soft_reset(void *handle)
1198 {
1199         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1200
1201         if (!adev->mc.srbm_soft_reset)
1202                 return 0;
1203
1204         gmc_v8_0_mc_stop(adev, &adev->mc.save);
1205         if (gmc_v8_0_wait_for_idle(adev)) {
1206                 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1207         }
1208
1209         return 0;
1210 }
1211
1212 static int gmc_v8_0_soft_reset(void *handle)
1213 {
1214         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1215         u32 srbm_soft_reset;
1216
1217         if (!adev->mc.srbm_soft_reset)
1218                 return 0;
1219         srbm_soft_reset = adev->mc.srbm_soft_reset;
1220
1221         if (srbm_soft_reset) {
1222                 u32 tmp;
1223
1224                 tmp = RREG32(mmSRBM_SOFT_RESET);
1225                 tmp |= srbm_soft_reset;
1226                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1227                 WREG32(mmSRBM_SOFT_RESET, tmp);
1228                 tmp = RREG32(mmSRBM_SOFT_RESET);
1229
1230                 udelay(50);
1231
1232                 tmp &= ~srbm_soft_reset;
1233                 WREG32(mmSRBM_SOFT_RESET, tmp);
1234                 tmp = RREG32(mmSRBM_SOFT_RESET);
1235
1236                 /* Wait a little for things to settle down */
1237                 udelay(50);
1238         }
1239
1240         return 0;
1241 }
1242
1243 static int gmc_v8_0_post_soft_reset(void *handle)
1244 {
1245         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1246
1247         if (!adev->mc.srbm_soft_reset)
1248                 return 0;
1249
1250         gmc_v8_0_mc_resume(adev, &adev->mc.save);
1251         return 0;
1252 }
1253
1254 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1255                                              struct amdgpu_irq_src *src,
1256                                              unsigned type,
1257                                              enum amdgpu_interrupt_state state)
1258 {
1259         u32 tmp;
1260         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1261                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1262                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1263                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1264                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1265                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1266                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1267
1268         switch (state) {
1269         case AMDGPU_IRQ_STATE_DISABLE:
1270                 /* system context */
1271                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1272                 tmp &= ~bits;
1273                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1274                 /* VMs */
1275                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1276                 tmp &= ~bits;
1277                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1278                 break;
1279         case AMDGPU_IRQ_STATE_ENABLE:
1280                 /* system context */
1281                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1282                 tmp |= bits;
1283                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1284                 /* VMs */
1285                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1286                 tmp |= bits;
1287                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1288                 break;
1289         default:
1290                 break;
1291         }
1292
1293         return 0;
1294 }
1295
1296 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1297                                       struct amdgpu_irq_src *source,
1298                                       struct amdgpu_iv_entry *entry)
1299 {
1300         u32 addr, status, mc_client;
1301
1302         if (amdgpu_sriov_vf(adev)) {
1303                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1304                         entry->src_id, entry->src_data);
1305                 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1306                 return 0;
1307         }
1308
1309         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1310         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1311         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1312         /* reset addr and status */
1313         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1314
1315         if (!addr && !status)
1316                 return 0;
1317
1318         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1319                 gmc_v8_0_set_fault_enable_default(adev, false);
1320
1321         if (printk_ratelimit()) {
1322                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1323                         entry->src_id, entry->src_data);
1324                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1325                         addr);
1326                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1327                         status);
1328                 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
1329         }
1330
1331         return 0;
1332 }
1333
1334 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1335                                                      bool enable)
1336 {
1337         uint32_t data;
1338
1339         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1340                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1341                 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1342                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1343
1344                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1345                 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1346                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1347
1348                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1349                 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1350                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1351
1352                 data = RREG32(mmMC_XPB_CLK_GAT);
1353                 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1354                 WREG32(mmMC_XPB_CLK_GAT, data);
1355
1356                 data = RREG32(mmATC_MISC_CG);
1357                 data |= ATC_MISC_CG__ENABLE_MASK;
1358                 WREG32(mmATC_MISC_CG, data);
1359
1360                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1361                 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1362                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1363
1364                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1365                 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1366                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1367
1368                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1369                 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1370                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1371
1372                 data = RREG32(mmVM_L2_CG);
1373                 data |= VM_L2_CG__ENABLE_MASK;
1374                 WREG32(mmVM_L2_CG, data);
1375         } else {
1376                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1377                 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1378                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1379
1380                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1381                 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1382                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1383
1384                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1385                 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1386                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1387
1388                 data = RREG32(mmMC_XPB_CLK_GAT);
1389                 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1390                 WREG32(mmMC_XPB_CLK_GAT, data);
1391
1392                 data = RREG32(mmATC_MISC_CG);
1393                 data &= ~ATC_MISC_CG__ENABLE_MASK;
1394                 WREG32(mmATC_MISC_CG, data);
1395
1396                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1397                 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1398                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1399
1400                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1401                 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1402                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1403
1404                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1405                 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1406                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1407
1408                 data = RREG32(mmVM_L2_CG);
1409                 data &= ~VM_L2_CG__ENABLE_MASK;
1410                 WREG32(mmVM_L2_CG, data);
1411         }
1412 }
1413
1414 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1415                                        bool enable)
1416 {
1417         uint32_t data;
1418
1419         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1420                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1421                 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1422                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1423
1424                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1425                 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1426                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1427
1428                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1429                 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1430                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1431
1432                 data = RREG32(mmMC_XPB_CLK_GAT);
1433                 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1434                 WREG32(mmMC_XPB_CLK_GAT, data);
1435
1436                 data = RREG32(mmATC_MISC_CG);
1437                 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1438                 WREG32(mmATC_MISC_CG, data);
1439
1440                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1441                 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1442                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1443
1444                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1445                 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1446                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1447
1448                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1449                 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1450                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1451
1452                 data = RREG32(mmVM_L2_CG);
1453                 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1454                 WREG32(mmVM_L2_CG, data);
1455         } else {
1456                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1457                 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1458                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1459
1460                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1461                 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1462                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1463
1464                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1465                 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1466                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1467
1468                 data = RREG32(mmMC_XPB_CLK_GAT);
1469                 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1470                 WREG32(mmMC_XPB_CLK_GAT, data);
1471
1472                 data = RREG32(mmATC_MISC_CG);
1473                 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1474                 WREG32(mmATC_MISC_CG, data);
1475
1476                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1477                 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1478                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1479
1480                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1481                 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1482                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1483
1484                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1485                 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1486                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1487
1488                 data = RREG32(mmVM_L2_CG);
1489                 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1490                 WREG32(mmVM_L2_CG, data);
1491         }
1492 }
1493
1494 static int gmc_v8_0_set_clockgating_state(void *handle,
1495                                           enum amd_clockgating_state state)
1496 {
1497         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1498
1499         if (amdgpu_sriov_vf(adev))
1500                 return 0;
1501
1502         switch (adev->asic_type) {
1503         case CHIP_FIJI:
1504                 fiji_update_mc_medium_grain_clock_gating(adev,
1505                                 state == AMD_CG_STATE_GATE ? true : false);
1506                 fiji_update_mc_light_sleep(adev,
1507                                 state == AMD_CG_STATE_GATE ? true : false);
1508                 break;
1509         default:
1510                 break;
1511         }
1512         return 0;
1513 }
1514
1515 static int gmc_v8_0_set_powergating_state(void *handle,
1516                                           enum amd_powergating_state state)
1517 {
1518         return 0;
1519 }
1520
1521 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags)
1522 {
1523         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1524         int data;
1525
1526         if (amdgpu_sriov_vf(adev))
1527                 *flags = 0;
1528
1529         /* AMD_CG_SUPPORT_MC_MGCG */
1530         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1531         if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1532                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1533
1534         /* AMD_CG_SUPPORT_MC_LS */
1535         if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1536                 *flags |= AMD_CG_SUPPORT_MC_LS;
1537 }
1538
1539 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1540         .name = "gmc_v8_0",
1541         .early_init = gmc_v8_0_early_init,
1542         .late_init = gmc_v8_0_late_init,
1543         .sw_init = gmc_v8_0_sw_init,
1544         .sw_fini = gmc_v8_0_sw_fini,
1545         .hw_init = gmc_v8_0_hw_init,
1546         .hw_fini = gmc_v8_0_hw_fini,
1547         .suspend = gmc_v8_0_suspend,
1548         .resume = gmc_v8_0_resume,
1549         .is_idle = gmc_v8_0_is_idle,
1550         .wait_for_idle = gmc_v8_0_wait_for_idle,
1551         .check_soft_reset = gmc_v8_0_check_soft_reset,
1552         .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1553         .soft_reset = gmc_v8_0_soft_reset,
1554         .post_soft_reset = gmc_v8_0_post_soft_reset,
1555         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1556         .set_powergating_state = gmc_v8_0_set_powergating_state,
1557         .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1558 };
1559
1560 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1561         .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1562         .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1563         .set_prt = gmc_v8_0_set_prt,
1564 };
1565
1566 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1567         .set = gmc_v8_0_vm_fault_interrupt_state,
1568         .process = gmc_v8_0_process_interrupt,
1569 };
1570
1571 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1572 {
1573         if (adev->gart.gart_funcs == NULL)
1574                 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1575 }
1576
1577 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1578 {
1579         adev->mc.vm_fault.num_types = 1;
1580         adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1581 }
1582
1583 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1584 {
1585         .type = AMD_IP_BLOCK_TYPE_GMC,
1586         .major = 8,
1587         .minor = 0,
1588         .rev = 0,
1589         .funcs = &gmc_v8_0_ip_funcs,
1590 };
1591
1592 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1593 {
1594         .type = AMD_IP_BLOCK_TYPE_GMC,
1595         .major = 8,
1596         .minor = 1,
1597         .rev = 0,
1598         .funcs = &gmc_v8_0_ip_funcs,
1599 };
1600
1601 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1602 {
1603         .type = AMD_IP_BLOCK_TYPE_GMC,
1604         .major = 8,
1605         .minor = 5,
1606         .rev = 0,
1607         .funcs = &gmc_v8_0_ip_funcs,
1608 };