drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29
  30 #include "vega10/soc15ip.h"
  31 #include "vega10/SDMA0/sdma0_4_0_offset.h"
  32 #include "vega10/SDMA0/sdma0_4_0_sh_mask.h"
  33 #include "vega10/SDMA1/sdma1_4_0_offset.h"
  34 #include "vega10/SDMA1/sdma1_4_0_sh_mask.h"
  35 #include "vega10/MMHUB/mmhub_1_0_offset.h"
  36 #include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
  37 #include "vega10/HDP/hdp_4_0_offset.h"
  38
  39 #include "soc15_common.h"
  40 #include "soc15.h"
  41 #include "vega10_sdma_pkt_open.h"
  42
  43 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
  44 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
  45
  46 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
  47 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
  48 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  49 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  50
  51 static const u32 golden_settings_sdma_4[] = {
  52         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07,
  53         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100,
  54         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x00000100,
  55         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
  56         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL), 0x800f0100, 0x00000100,
  57         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  58         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0x003ff006, 0x0003c000,
  59         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0100, 0x00000100,
  60         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  61         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0100, 0x00000100,
  62         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  63         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0,
  64         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CHICKEN_BITS), 0xfe931f07, 0x02831f07,
  65         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), 0xffffffff, 0x3f000100,
  66         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_IB_CNTL), 0x800f0100, 0x00000100,
  67         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  68         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL), 0x800f0100, 0x00000100,
  69         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  70         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), 0x003ff000, 0x0003c000,
  71         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL), 0x800f0100, 0x00000100,
  72         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  73         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL), 0x800f0100, 0x00000100,
  74         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  75         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_UTCL1_PAGE), 0x000003ff, 0x000003c0
  76 };
  77
  78 static const u32 golden_settings_sdma_vg10[] = {
  79         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00104002,
  80         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002,
  81         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG), 0x0018773f, 0x00104002,
  82         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002
  83 };
  84
  85 static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset)
  86 {
  87         u32 base = 0;
  88
  89         switch (instance) {
  90         case 0:
  91                 base = SDMA0_BASE.instance[0].segment[0];
  92                 break;
  93         case 1:
  94                 base = SDMA1_BASE.instance[0].segment[0];
  95                 break;
  96         default:
  97                 BUG();
  98                 break;
  99         }
 100
 101         return base + internal_offset;
 102 }
 103
 104 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
 105 {
 106         switch (adev->asic_type) {
 107         case CHIP_VEGA10:
 108                 amdgpu_program_register_sequence(adev,
 109                                                  golden_settings_sdma_4,
 110                                                  (const u32)ARRAY_SIZE(golden_settings_sdma_4));
 111                 amdgpu_program_register_sequence(adev,
 112                                                  golden_settings_sdma_vg10,
 113                                                  (const u32)ARRAY_SIZE(golden_settings_sdma_vg10));
 114                 break;
 115         default:
 116                 break;
 117         }
 118 }
 119
 120 static void sdma_v4_0_print_ucode_regs(void *handle)
 121 {
 122         int i;
 123         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 124
 125         dev_info(adev->dev, "VEGA10 SDMA ucode registers\n");
 126         for (i = 0; i < adev->sdma.num_instances; i++) {
 127                 dev_info(adev->dev, "  SDMA%d_UCODE_ADDR=0x%08X\n",
 128                          i, RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR)));
 129                 dev_info(adev->dev, "  SDMA%d_UCODE_CHECKSUM=0x%08X\n",
 130                          i, RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_CHECKSUM)));
 131         }
 132 }
 133
 134 /**
 135  * sdma_v4_0_init_microcode - load ucode images from disk
 136  *
 137  * @adev: amdgpu_device pointer
 138  *
 139  * Use the firmware interface to load the ucode images into
 140  * the driver (not loaded into hw).
 141  * Returns 0 on success, error on failure.
 142  */
 143
 144 // emulation only, won't work on real chip
 145 // vega10 real chip need to use PSP to load firmware
 146 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
 147 {
 148         const char *chip_name;
 149         char fw_name[30];
 150         int err = 0, i;
 151         struct amdgpu_firmware_info *info = NULL;
 152         const struct common_firmware_header *header = NULL;
 153         const struct sdma_firmware_header_v1_0 *hdr;
 154
 155         DRM_DEBUG("\n");
 156
 157         switch (adev->asic_type) {
 158         case CHIP_VEGA10:
 159                 chip_name = "vega10";
 160                 break;
 161         default:
 162                 BUG();
 163         }
 164
 165         for (i = 0; i < adev->sdma.num_instances; i++) {
 166                 if (i == 0)
 167                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 168                 else
 169                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 170                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 171                 if (err)
 172                         goto out;
 173                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 174                 if (err)
 175                         goto out;
 176                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 177                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 178                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 179                 if (adev->sdma.instance[i].feature_version >= 20)
 180                         adev->sdma.instance[i].burst_nop = true;
 181                 DRM_DEBUG("psp_load == '%s'\n",
 182                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 183
 184                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 185                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 186                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 187                         info->fw = adev->sdma.instance[i].fw;
 188                         header = (const struct common_firmware_header *)info->fw->data;
 189                         adev->firmware.fw_size +=
 190                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 191                 }
 192         }
 193 out:
 194         if (err) {
 195                 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
 196                 for (i = 0; i < adev->sdma.num_instances; i++) {
 197                         release_firmware(adev->sdma.instance[i].fw);
 198                         adev->sdma.instance[i].fw = NULL;
 199                 }
 200         }
 201         return err;
 202 }
 203
 204 /**
 205  * sdma_v4_0_ring_get_rptr - get the current read pointer
 206  *
 207  * @ring: amdgpu ring pointer
 208  *
 209  * Get the current rptr from the hardware (VEGA10+).
 210  */
 211 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
 212 {
 213         u64 *rptr;
 214
 215         /* XXX check if swapping is necessary on BE */
 216         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 217
 218         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 219         return ((*rptr) >> 2);
 220 }
 221
 222 /**
 223  * sdma_v4_0_ring_get_wptr - get the current write pointer
 224  *
 225  * @ring: amdgpu ring pointer
 226  *
 227  * Get the current wptr from the hardware (VEGA10+).
 228  */
 229 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
 230 {
 231         struct amdgpu_device *adev = ring->adev;
 232         u64 *wptr = NULL;
 233         uint64_t local_wptr = 0;
 234
 235         if (ring->use_doorbell) {
 236                 /* XXX check if swapping is necessary on BE */
 237                 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]);
 238                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr);
 239                 *wptr = (*wptr) >> 2;
 240                 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr);
 241         } else {
 242                 u32 lowbit, highbit;
 243                 int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 244
 245                 wptr = &local_wptr;
 246                 lowbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR)) >> 2;
 247                 highbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
 248
 249                 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
 250                                 me, highbit, lowbit);
 251                 *wptr = highbit;
 252                 *wptr = (*wptr) << 32;
 253                 *wptr |= lowbit;
 254         }
 255
 256         return *wptr;
 257 }
 258
 259 /**
 260  * sdma_v4_0_ring_set_wptr - commit the write pointer
 261  *
 262  * @ring: amdgpu ring pointer
 263  *
 264  * Write the wptr back to the hardware (VEGA10+).
 265  */
 266 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 267 {
 268         struct amdgpu_device *adev = ring->adev;
 269
 270         DRM_DEBUG("Setting write pointer\n");
 271         if (ring->use_doorbell) {
 272                 DRM_DEBUG("Using doorbell -- "
 273                                 "wptr_offs == 0x%08x "
 274                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 275                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 276                                 ring->wptr_offs,
 277                                 lower_32_bits(ring->wptr << 2),
 278                                 upper_32_bits(ring->wptr << 2));
 279                 /* XXX check if swapping is necessary on BE */
 280                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 281                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 282                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 283                                 ring->doorbell_index, ring->wptr << 2);
 284                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 285         } else {
 286                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 287
 288                 DRM_DEBUG("Not using doorbell -- "
 289                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 290                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 291                                 me,
 292                                 lower_32_bits(ring->wptr << 2),
 293                                 me,
 294                                 upper_32_bits(ring->wptr << 2));
 295                 WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
 296                 WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
 297         }
 298 }
 299
 300 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 301 {
 302         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 303         int i;
 304
 305         for (i = 0; i < count; i++)
 306                 if (sdma && sdma->burst_nop && (i == 0))
 307                         amdgpu_ring_write(ring, ring->funcs->nop |
 308                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 309                 else
 310                         amdgpu_ring_write(ring, ring->funcs->nop);
 311 }
 312
 313 /**
 314  * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
 315  *
 316  * @ring: amdgpu ring pointer
 317  * @ib: IB object to schedule
 318  *
 319  * Schedule an IB in the DMA ring (VEGA10).
 320  */
 321 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
 322                                         struct amdgpu_ib *ib,
 323                                         unsigned vm_id, bool ctx_switch)
 324 {
 325         u32 vmid = vm_id & 0xf;
 326
 327         /* IB packet must end on a 8 DW boundary */
 328         sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 329
 330         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 331                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 332         /* base must be 32 byte aligned */
 333         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 334         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 335         amdgpu_ring_write(ring, ib->length_dw);
 336         amdgpu_ring_write(ring, 0);
 337         amdgpu_ring_write(ring, 0);
 338
 339 }
 340
 341 /**
 342  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 343  *
 344  * @ring: amdgpu ring pointer
 345  *
 346  * Emit an hdp flush packet on the requested DMA ring.
 347  */
 348 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 349 {
 350         u32 ref_and_mask = 0;
 351         struct nbio_hdp_flush_reg *nbio_hf_reg;
 352
 353         if (ring->adev->asic_type == CHIP_VEGA10)
 354                 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
 355
 356         if (ring == &ring->adev->sdma.instance[0].ring)
 357                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 358         else
 359                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 360
 361         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 362                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 363                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 364         amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_done_offset << 2);
 365         amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_req_offset << 2);
 366         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 367         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 368         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 369                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 370 }
 371
 372 static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 373 {
 374         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 375                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 376         amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0));
 377         amdgpu_ring_write(ring, 1);
 378 }
 379
 380 /**
 381  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
 382  *
 383  * @ring: amdgpu ring pointer
 384  * @fence: amdgpu fence object
 385  *
 386  * Add a DMA fence packet to the ring to write
 387  * the fence seq number and DMA trap packet to generate
 388  * an interrupt if needed (VEGA10).
 389  */
 390 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 391                                       unsigned flags)
 392 {
 393         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 394         /* write the fence */
 395         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 396         /* zero in first two bits */
 397         BUG_ON(addr & 0x3);
 398         amdgpu_ring_write(ring, lower_32_bits(addr));
 399         amdgpu_ring_write(ring, upper_32_bits(addr));
 400         amdgpu_ring_write(ring, lower_32_bits(seq));
 401
 402         /* optionally write high bits as well */
 403         if (write64bit) {
 404                 addr += 4;
 405                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 406                 /* zero in first two bits */
 407                 BUG_ON(addr & 0x3);
 408                 amdgpu_ring_write(ring, lower_32_bits(addr));
 409                 amdgpu_ring_write(ring, upper_32_bits(addr));
 410                 amdgpu_ring_write(ring, upper_32_bits(seq));
 411         }
 412
 413         /* generate an interrupt */
 414         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 415         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 416 }
 417
 418
 419 /**
 420  * sdma_v4_0_gfx_stop - stop the gfx async dma engines
 421  *
 422  * @adev: amdgpu_device pointer
 423  *
 424  * Stop the gfx async dma ring buffers (VEGA10).
 425  */
 426 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
 427 {
 428         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 429         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 430         u32 rb_cntl, ib_cntl;
 431         int i;
 432
 433         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 434             (adev->mman.buffer_funcs_ring == sdma1))
 435                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 436
 437         for (i = 0; i < adev->sdma.num_instances; i++) {
 438                 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL));
 439                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 440                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 441                 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL));
 442                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 443                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 444         }
 445
 446         sdma0->ready = false;
 447         sdma1->ready = false;
 448 }
 449
 450 /**
 451  * sdma_v4_0_rlc_stop - stop the compute async dma engines
 452  *
 453  * @adev: amdgpu_device pointer
 454  *
 455  * Stop the compute async dma queues (VEGA10).
 456  */
 457 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
 458 {
 459         /* XXX todo */
 460 }
 461
 462 /**
 463  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 464  *
 465  * @adev: amdgpu_device pointer
 466  * @enable: enable/disable the DMA MEs context switch.
 467  *
 468  * Halt or unhalt the async dma engines context switch (VEGA10).
 469  */
 470 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 471 {
 472         u32 f32_cntl;
 473         int i;
 474
 475         for (i = 0; i < adev->sdma.num_instances; i++) {
 476                 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL));
 477                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 478                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 479                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), f32_cntl);
 480         }
 481
 482 }
 483
 484 /**
 485  * sdma_v4_0_enable - stop the async dma engines
 486  *
 487  * @adev: amdgpu_device pointer
 488  * @enable: enable/disable the DMA MEs.
 489  *
 490  * Halt or unhalt the async dma engines (VEGA10).
 491  */
 492 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
 493 {
 494         u32 f32_cntl;
 495         int i;
 496
 497         if (enable == false) {
 498                 sdma_v4_0_gfx_stop(adev);
 499                 sdma_v4_0_rlc_stop(adev);
 500         }
 501
 502         for (i = 0; i < adev->sdma.num_instances; i++) {
 503                 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL));
 504                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 505                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), f32_cntl);
 506         }
 507 }
 508
 509 /**
 510  * sdma_v4_0_gfx_resume - setup and start the async dma engines
 511  *
 512  * @adev: amdgpu_device pointer
 513  *
 514  * Set up the gfx DMA ring buffers and enable them (VEGA10).
 515  * Returns 0 for success, error for failure.
 516  */
 517 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
 518 {
 519         struct amdgpu_ring *ring;
 520         u32 rb_cntl, ib_cntl;
 521         u32 rb_bufsz;
 522         u32 wb_offset;
 523         u32 doorbell;
 524         u32 doorbell_offset;
 525         u32 temp;
 526         int i, r;
 527
 528         for (i = 0; i < adev->sdma.num_instances; i++) {
 529                 ring = &adev->sdma.instance[i].ring;
 530                 wb_offset = (ring->rptr_offs * 4);
 531
 532                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 533
 534                 /* Set ring buffer size in dwords */
 535                 rb_bufsz = order_base_2(ring->ring_size / 4);
 536                 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL));
 537                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 538 #ifdef __BIG_ENDIAN
 539                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 540                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 541                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 542 #endif
 543                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 544
 545                 /* Initialize the ring buffer's read and write pointers */
 546                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR), 0);
 547                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 548                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), 0);
 549                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 550
 551                 /* set the wb address whether it's enabled or not */
 552                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 553                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 554                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 555                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 556
 557                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 558
 559                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 560                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 561
 562                 ring->wptr = 0;
 563
 564                 /* before programing wptr to a less value, need set minor_ptr_update first */
 565                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 566
 567                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 568                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 569                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 570                 }
 571
 572                 doorbell = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL));
 573                 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET));
 574
 575                 if (ring->use_doorbell) {
 576                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 577                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 578                                         OFFSET, ring->doorbell_index);
 579                 } else {
 580                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 581                 }
 582                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL), doorbell);
 583                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 584                 nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index);
 585
 586                 if (amdgpu_sriov_vf(adev))
 587                         sdma_v4_0_ring_set_wptr(ring);
 588
 589                 /* set minor_ptr_update to 0 after wptr programed */
 590                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 591
 592                 /* set utc l1 enable flag always to 1 */
 593                 temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL));
 594                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 595                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), temp);
 596
 597                 if (!amdgpu_sriov_vf(adev)) {
 598                         /* unhalt engine */
 599                         temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL));
 600                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 601                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), temp);
 602                 }
 603
 604                 /* enable DMA RB */
 605                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 606                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 607
 608                 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL));
 609                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 610 #ifdef __BIG_ENDIAN
 611                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 612 #endif
 613                 /* enable DMA IBs */
 614                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 615
 616                 ring->ready = true;
 617
 618                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 619                         sdma_v4_0_ctx_switch_enable(adev, true);
 620                         sdma_v4_0_enable(adev, true);
 621                 }
 622
 623                 r = amdgpu_ring_test_ring(ring);
 624                 if (r) {
 625                         ring->ready = false;
 626                         return r;
 627                 }
 628
 629                 if (adev->mman.buffer_funcs_ring == ring)
 630                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 631         }
 632
 633         return 0;
 634 }
 635
 636 /**
 637  * sdma_v4_0_rlc_resume - setup and start the async dma engines
 638  *
 639  * @adev: amdgpu_device pointer
 640  *
 641  * Set up the compute DMA queues and enable them (VEGA10).
 642  * Returns 0 for success, error for failure.
 643  */
 644 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
 645 {
 646         /* XXX todo */
 647         return 0;
 648 }
 649
 650 /**
 651  * sdma_v4_0_load_microcode - load the sDMA ME ucode
 652  *
 653  * @adev: amdgpu_device pointer
 654  *
 655  * Loads the sDMA0/1 ucode.
 656  * Returns 0 for success, -EINVAL if the ucode is not available.
 657  */
 658 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
 659 {
 660         const struct sdma_firmware_header_v1_0 *hdr;
 661         const __le32 *fw_data;
 662         u32 fw_size;
 663         u32 digest_size = 0;
 664         int i, j;
 665
 666         /* halt the MEs */
 667         sdma_v4_0_enable(adev, false);
 668
 669         for (i = 0; i < adev->sdma.num_instances; i++) {
 670                 uint16_t version_major;
 671                 uint16_t version_minor;
 672                 if (!adev->sdma.instance[i].fw)
 673                         return -EINVAL;
 674
 675                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 676                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 677                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 678
 679                 version_major = le16_to_cpu(hdr->header.header_version_major);
 680                 version_minor = le16_to_cpu(hdr->header.header_version_minor);
 681
 682                 if (version_major == 1 && version_minor >= 1) {
 683                         const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = (const struct sdma_firmware_header_v1_1 *) hdr;
 684                         digest_size = le32_to_cpu(sdma_v1_1_hdr->digest_size);
 685                 }
 686
 687                 fw_size -= digest_size;
 688
 689                 fw_data = (const __le32 *)
 690                         (adev->sdma.instance[i].fw->data +
 691                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 692
 693                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), 0);
 694
 695
 696                 for (j = 0; j < fw_size; j++)
 697                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 698
 699                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 700         }
 701
 702         sdma_v4_0_print_ucode_regs(adev);
 703
 704         return 0;
 705 }
 706
 707 /**
 708  * sdma_v4_0_start - setup and start the async dma engines
 709  *
 710  * @adev: amdgpu_device pointer
 711  *
 712  * Set up the DMA engines and enable them (VEGA10).
 713  * Returns 0 for success, error for failure.
 714  */
 715 static int sdma_v4_0_start(struct amdgpu_device *adev)
 716 {
 717         int r = 0;
 718
 719         if (amdgpu_sriov_vf(adev)) {
 720                 sdma_v4_0_ctx_switch_enable(adev, false);
 721                 sdma_v4_0_enable(adev, false);
 722
 723                 /* set RB registers */
 724                 r = sdma_v4_0_gfx_resume(adev);
 725                 return r;
 726         }
 727
 728         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 729                 DRM_INFO("Loading via direct write\n");
 730                 r = sdma_v4_0_load_microcode(adev);
 731                 if (r)
 732                         return r;
 733         }
 734
 735         /* unhalt the MEs */
 736         sdma_v4_0_enable(adev, true);
 737         /* enable sdma ring preemption */
 738         sdma_v4_0_ctx_switch_enable(adev, true);
 739
 740         /* start the gfx rings and rlc compute queues */
 741         r = sdma_v4_0_gfx_resume(adev);
 742         if (r)
 743                 return r;
 744         r = sdma_v4_0_rlc_resume(adev);
 745
 746         return r;
 747 }
 748
 749 /**
 750  * sdma_v4_0_ring_test_ring - simple async dma engine test
 751  *
 752  * @ring: amdgpu_ring structure holding ring information
 753  *
 754  * Test the DMA engine by writing using it to write an
 755  * value to memory. (VEGA10).
 756  * Returns 0 for success, error for failure.
 757  */
 758 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
 759 {
 760         struct amdgpu_device *adev = ring->adev;
 761         unsigned i;
 762         unsigned index;
 763         int r;
 764         u32 tmp;
 765         u64 gpu_addr;
 766
 767         DRM_INFO("In Ring test func\n");
 768
 769         r = amdgpu_wb_get(adev, &index);
 770         if (r) {
 771                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 772                 return r;
 773         }
 774
 775         gpu_addr = adev->wb.gpu_addr + (index * 4);
 776         tmp = 0xCAFEDEAD;
 777         adev->wb.wb[index] = cpu_to_le32(tmp);
 778
 779         r = amdgpu_ring_alloc(ring, 5);
 780         if (r) {
 781                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 782                 amdgpu_wb_free(adev, index);
 783                 return r;
 784         }
 785
 786         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 787                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 788         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 789         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 790         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 791         amdgpu_ring_write(ring, 0xDEADBEEF);
 792         amdgpu_ring_commit(ring);
 793
 794         for (i = 0; i < adev->usec_timeout; i++) {
 795                 tmp = le32_to_cpu(adev->wb.wb[index]);
 796                 if (tmp == 0xDEADBEEF)
 797                         break;
 798                 DRM_UDELAY(1);
 799         }
 800
 801         if (i < adev->usec_timeout) {
 802                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 803         } else {
 804                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 805                           ring->idx, tmp);
 806                 r = -EINVAL;
 807         }
 808         amdgpu_wb_free(adev, index);
 809
 810         return r;
 811 }
 812
 813 /**
 814  * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
 815  *
 816  * @ring: amdgpu_ring structure holding ring information
 817  *
 818  * Test a simple IB in the DMA ring (VEGA10).
 819  * Returns 0 on success, error on failure.
 820  */
 821 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 822 {
 823         struct amdgpu_device *adev = ring->adev;
 824         struct amdgpu_ib ib;
 825         struct dma_fence *f = NULL;
 826         unsigned index;
 827         long r;
 828         u32 tmp = 0;
 829         u64 gpu_addr;
 830
 831         r = amdgpu_wb_get(adev, &index);
 832         if (r) {
 833                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 834                 return r;
 835         }
 836
 837         gpu_addr = adev->wb.gpu_addr + (index * 4);
 838         tmp = 0xCAFEDEAD;
 839         adev->wb.wb[index] = cpu_to_le32(tmp);
 840         memset(&ib, 0, sizeof(ib));
 841         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 842         if (r) {
 843                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 844                 goto err0;
 845         }
 846
 847         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 848                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 849         ib.ptr[1] = lower_32_bits(gpu_addr);
 850         ib.ptr[2] = upper_32_bits(gpu_addr);
 851         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 852         ib.ptr[4] = 0xDEADBEEF;
 853         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 854         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 855         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 856         ib.length_dw = 8;
 857
 858         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 859         if (r)
 860                 goto err1;
 861
 862         r = dma_fence_wait_timeout(f, false, timeout);
 863         if (r == 0) {
 864                 DRM_ERROR("amdgpu: IB test timed out\n");
 865                 r = -ETIMEDOUT;
 866                 goto err1;
 867         } else if (r < 0) {
 868                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 869                 goto err1;
 870         }
 871         tmp = le32_to_cpu(adev->wb.wb[index]);
 872         if (tmp == 0xDEADBEEF) {
 873                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 874                 r = 0;
 875         } else {
 876                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 877                 r = -EINVAL;
 878         }
 879 err1:
 880         amdgpu_ib_free(adev, &ib, NULL);
 881         dma_fence_put(f);
 882 err0:
 883         amdgpu_wb_free(adev, index);
 884         return r;
 885 }
 886
 887
 888 /**
 889  * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
 890  *
 891  * @ib: indirect buffer to fill with commands
 892  * @pe: addr of the page entry
 893  * @src: src addr to copy from
 894  * @count: number of page entries to update
 895  *
 896  * Update PTEs by copying them from the GART using sDMA (VEGA10).
 897  */
 898 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
 899                                   uint64_t pe, uint64_t src,
 900                                   unsigned count)
 901 {
 902         unsigned bytes = count * 8;
 903
 904         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 905                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 906         ib->ptr[ib->length_dw++] = bytes - 1;
 907         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 908         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 909         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 910         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 911         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 912
 913 }
 914
 915 /**
 916  * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
 917  *
 918  * @ib: indirect buffer to fill with commands
 919  * @pe: addr of the page entry
 920  * @addr: dst addr to write into pe
 921  * @count: number of page entries to update
 922  * @incr: increase next addr by incr bytes
 923  * @flags: access flags
 924  *
 925  * Update PTEs by writing them manually using sDMA (VEGA10).
 926  */
 927 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 928                                    uint64_t value, unsigned count,
 929                                    uint32_t incr)
 930 {
 931         unsigned ndw = count * 2;
 932
 933         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 934                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 935         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 936         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 937         ib->ptr[ib->length_dw++] = ndw - 1;
 938         for (; ndw > 0; ndw -= 2) {
 939                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 940                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 941                 value += incr;
 942         }
 943 }
 944
 945 /**
 946  * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
 947  *
 948  * @ib: indirect buffer to fill with commands
 949  * @pe: addr of the page entry
 950  * @addr: dst addr to write into pe
 951  * @count: number of page entries to update
 952  * @incr: increase next addr by incr bytes
 953  * @flags: access flags
 954  *
 955  * Update the page tables using sDMA (VEGA10).
 956  */
 957 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
 958                                      uint64_t pe,
 959                                      uint64_t addr, unsigned count,
 960                                      uint32_t incr, uint64_t flags)
 961 {
 962         /* for physically contiguous pages (vram) */
 963         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
 964         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 965         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 966         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
 967         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
 968         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 969         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 970         ib->ptr[ib->length_dw++] = incr; /* increment size */
 971         ib->ptr[ib->length_dw++] = 0;
 972         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
 973 }
 974
 975 /**
 976  * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
 977  *
 978  * @ib: indirect buffer to fill with padding
 979  *
 980  */
 981 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 982 {
 983         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 984         u32 pad_count;
 985         int i;
 986
 987         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 988         for (i = 0; i < pad_count; i++)
 989                 if (sdma && sdma->burst_nop && (i == 0))
 990                         ib->ptr[ib->length_dw++] =
 991                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
 992                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
 993                 else
 994                         ib->ptr[ib->length_dw++] =
 995                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 996 }
 997
 998
 999 /**
1000  * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1001  *
1002  * @ring: amdgpu_ring pointer
1003  *
1004  * Make sure all previous operations are completed (CIK).
1005  */
1006 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1007 {
1008         uint32_t seq = ring->fence_drv.sync_seq;
1009         uint64_t addr = ring->fence_drv.gpu_addr;
1010
1011         /* wait for idle */
1012         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1013                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1014                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1015                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1016         amdgpu_ring_write(ring, addr & 0xfffffffc);
1017         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1018         amdgpu_ring_write(ring, seq); /* reference */
1019         amdgpu_ring_write(ring, 0xfffffff); /* mask */
1020         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1021                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1022 }
1023
1024
1025 /**
1026  * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1027  *
1028  * @ring: amdgpu_ring pointer
1029  * @vm: amdgpu_vm pointer
1030  *
1031  * Update the page table base and flush the VM TLB
1032  * using sDMA (VEGA10).
1033  */
1034 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1035                                          unsigned vm_id, uint64_t pd_addr)
1036 {
1037         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1038         uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
1039         unsigned eng = ring->vm_inv_eng;
1040
1041         pd_addr = pd_addr | 0x1; /* valid bit */
1042         /* now only use physical base address of PDE and valid */
1043         BUG_ON(pd_addr & 0xFFFF00000000003EULL);
1044
1045         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1046                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1047         amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vm_id * 2);
1048         amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1049
1050         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1051                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1052         amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vm_id * 2);
1053         amdgpu_ring_write(ring, upper_32_bits(pd_addr));
1054
1055         /* flush TLB */
1056         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1057                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1058         amdgpu_ring_write(ring, hub->vm_inv_eng0_req + eng);
1059         amdgpu_ring_write(ring, req);
1060
1061         /* wait for flush */
1062         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1063                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1064                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1065         amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
1066         amdgpu_ring_write(ring, 0);
1067         amdgpu_ring_write(ring, 1 << vm_id); /* reference */
1068         amdgpu_ring_write(ring, 1 << vm_id); /* mask */
1069         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1070                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1071 }
1072
1073 static int sdma_v4_0_early_init(void *handle)
1074 {
1075         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1076
1077         adev->sdma.num_instances = 2;
1078
1079         sdma_v4_0_set_ring_funcs(adev);
1080         sdma_v4_0_set_buffer_funcs(adev);
1081         sdma_v4_0_set_vm_pte_funcs(adev);
1082         sdma_v4_0_set_irq_funcs(adev);
1083
1084         return 0;
1085 }
1086
1087
1088 static int sdma_v4_0_sw_init(void *handle)
1089 {
1090         struct amdgpu_ring *ring;
1091         int r, i;
1092         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1093
1094         /* SDMA trap event */
1095         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA0, 224,
1096                               &adev->sdma.trap_irq);
1097         if (r)
1098                 return r;
1099
1100         /* SDMA trap event */
1101         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA1, 224,
1102                               &adev->sdma.trap_irq);
1103         if (r)
1104                 return r;
1105
1106         r = sdma_v4_0_init_microcode(adev);
1107         if (r) {
1108                 DRM_ERROR("Failed to load sdma firmware!\n");
1109                 return r;
1110         }
1111
1112         for (i = 0; i < adev->sdma.num_instances; i++) {
1113                 ring = &adev->sdma.instance[i].ring;
1114                 ring->ring_obj = NULL;
1115                 ring->use_doorbell = true;
1116
1117                 DRM_INFO("use_doorbell being set to: [%s]\n",
1118                                 ring->use_doorbell?"true":"false");
1119
1120                 ring->doorbell_index = (i == 0) ?
1121                         (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
1122                         : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
1123
1124                 sprintf(ring->name, "sdma%d", i);
1125                 r = amdgpu_ring_init(adev, ring, 1024,
1126                                      &adev->sdma.trap_irq,
1127                                      (i == 0) ?
1128                                      AMDGPU_SDMA_IRQ_TRAP0 :
1129                                      AMDGPU_SDMA_IRQ_TRAP1);
1130                 if (r)
1131                         return r;
1132         }
1133
1134         return r;
1135 }
1136
1137 static int sdma_v4_0_sw_fini(void *handle)
1138 {
1139         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1140         int i;
1141
1142         for (i = 0; i < adev->sdma.num_instances; i++)
1143                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1144
1145         return 0;
1146 }
1147
1148 static int sdma_v4_0_hw_init(void *handle)
1149 {
1150         int r;
1151         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1152
1153         sdma_v4_0_init_golden_registers(adev);
1154
1155         r = sdma_v4_0_start(adev);
1156
1157         return r;
1158 }
1159
1160 static int sdma_v4_0_hw_fini(void *handle)
1161 {
1162         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1163
1164         if (amdgpu_sriov_vf(adev))
1165                 return 0;
1166
1167         sdma_v4_0_ctx_switch_enable(adev, false);
1168         sdma_v4_0_enable(adev, false);
1169
1170         return 0;
1171 }
1172
1173 static int sdma_v4_0_suspend(void *handle)
1174 {
1175         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1176
1177         return sdma_v4_0_hw_fini(adev);
1178 }
1179
1180 static int sdma_v4_0_resume(void *handle)
1181 {
1182         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1183
1184         return sdma_v4_0_hw_init(adev);
1185 }
1186
1187 static bool sdma_v4_0_is_idle(void *handle)
1188 {
1189         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1190         u32 i;
1191
1192         for (i = 0; i < adev->sdma.num_instances; i++) {
1193                 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_STATUS_REG));
1194
1195                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1196                         return false;
1197         }
1198
1199         return true;
1200 }
1201
1202 static int sdma_v4_0_wait_for_idle(void *handle)
1203 {
1204         unsigned i;
1205         u32 sdma0, sdma1;
1206         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1207
1208         for (i = 0; i < adev->usec_timeout; i++) {
1209                 sdma0 = RREG32(sdma_v4_0_get_reg_offset(0, mmSDMA0_STATUS_REG));
1210                 sdma1 = RREG32(sdma_v4_0_get_reg_offset(1, mmSDMA0_STATUS_REG));
1211
1212                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1213                         return 0;
1214                 udelay(1);
1215         }
1216         return -ETIMEDOUT;
1217 }
1218
1219 static int sdma_v4_0_soft_reset(void *handle)
1220 {
1221         /* todo */
1222
1223         return 0;
1224 }
1225
1226 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
1227                                         struct amdgpu_irq_src *source,
1228                                         unsigned type,
1229                                         enum amdgpu_interrupt_state state)
1230 {
1231         u32 sdma_cntl;
1232
1233         u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ?
1234                 sdma_v4_0_get_reg_offset(0, mmSDMA0_CNTL) :
1235                 sdma_v4_0_get_reg_offset(1, mmSDMA0_CNTL);
1236
1237         sdma_cntl = RREG32(reg_offset);
1238         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1239                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1240         WREG32(reg_offset, sdma_cntl);
1241
1242         return 0;
1243 }
1244
1245 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
1246                                       struct amdgpu_irq_src *source,
1247                                       struct amdgpu_iv_entry *entry)
1248 {
1249         DRM_DEBUG("IH: SDMA trap\n");
1250         switch (entry->client_id) {
1251         case AMDGPU_IH_CLIENTID_SDMA0:
1252                 switch (entry->ring_id) {
1253                 case 0:
1254                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1255                         break;
1256                 case 1:
1257                         /* XXX compute */
1258                         break;
1259                 case 2:
1260                         /* XXX compute */
1261                         break;
1262                 case 3:
1263                         /* XXX page queue*/
1264                         break;
1265                 }
1266                 break;
1267         case AMDGPU_IH_CLIENTID_SDMA1:
1268                 switch (entry->ring_id) {
1269                 case 0:
1270                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1271                         break;
1272                 case 1:
1273                         /* XXX compute */
1274                         break;
1275                 case 2:
1276                         /* XXX compute */
1277                         break;
1278                 case 3:
1279                         /* XXX page queue*/
1280                         break;
1281                 }
1282                 break;
1283         }
1284         return 0;
1285 }
1286
1287 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1288                                               struct amdgpu_irq_src *source,
1289                                               struct amdgpu_iv_entry *entry)
1290 {
1291         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1292         schedule_work(&adev->reset_work);
1293         return 0;
1294 }
1295
1296
1297 static void sdma_v4_0_update_medium_grain_clock_gating(
1298                 struct amdgpu_device *adev,
1299                 bool enable)
1300 {
1301         uint32_t data, def;
1302
1303         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1304                 /* enable sdma0 clock gating */
1305                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1306                 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1307                           SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1308                           SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1309                           SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1310                           SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1311                           SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1312                           SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1313                           SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1314                 if (def != data)
1315                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1316
1317                 if (adev->asic_type == CHIP_VEGA10) {
1318                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1319                         data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1320                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1321                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1322                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1323                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1324                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1325                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1326                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1327                         if (def != data)
1328                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1329                 }
1330         } else {
1331                 /* disable sdma0 clock gating */
1332                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1333                 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1334                          SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1335                          SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1336                          SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1337                          SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1338                          SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1339                          SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1340                          SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1341
1342                 if (def != data)
1343                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1344
1345                 if (adev->asic_type == CHIP_VEGA10) {
1346                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1347                         data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1348                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1349                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1350                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1351                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1352                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1353                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1354                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1355                         if (def != data)
1356                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1357                 }
1358         }
1359 }
1360
1361
1362 static void sdma_v4_0_update_medium_grain_light_sleep(
1363                 struct amdgpu_device *adev,
1364                 bool enable)
1365 {
1366         uint32_t data, def;
1367
1368         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1369                 /* 1-not override: enable sdma0 mem light sleep */
1370                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1371                 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1372                 if (def != data)
1373                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1374
1375                 /* 1-not override: enable sdma1 mem light sleep */
1376                 if (adev->asic_type == CHIP_VEGA10) {
1377                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1378                         data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1379                         if (def != data)
1380                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1381                 }
1382         } else {
1383                 /* 0-override:disable sdma0 mem light sleep */
1384                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1385                 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1386                 if (def != data)
1387                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1388
1389                 /* 0-override:disable sdma1 mem light sleep */
1390                 if (adev->asic_type == CHIP_VEGA10) {
1391                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1392                         data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1393                         if (def != data)
1394                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1395                 }
1396         }
1397 }
1398
1399 static int sdma_v4_0_set_clockgating_state(void *handle,
1400                                           enum amd_clockgating_state state)
1401 {
1402         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1403
1404         if (amdgpu_sriov_vf(adev))
1405                 return 0;
1406
1407         switch (adev->asic_type) {
1408         case CHIP_VEGA10:
1409                 sdma_v4_0_update_medium_grain_clock_gating(adev,
1410                                 state == AMD_CG_STATE_GATE ? true : false);
1411                 sdma_v4_0_update_medium_grain_light_sleep(adev,
1412                                 state == AMD_CG_STATE_GATE ? true : false);
1413                 break;
1414         default:
1415                 break;
1416         }
1417         return 0;
1418 }
1419
1420 static int sdma_v4_0_set_powergating_state(void *handle,
1421                                           enum amd_powergating_state state)
1422 {
1423         return 0;
1424 }
1425
1426 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
1427 {
1428         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1429         int data;
1430
1431         if (amdgpu_sriov_vf(adev))
1432                 *flags = 0;
1433
1434         /* AMD_CG_SUPPORT_SDMA_MGCG */
1435         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1436         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1437                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1438
1439         /* AMD_CG_SUPPORT_SDMA_LS */
1440         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1441         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1442                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1443 }
1444
1445 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
1446         .name = "sdma_v4_0",
1447         .early_init = sdma_v4_0_early_init,
1448         .late_init = NULL,
1449         .sw_init = sdma_v4_0_sw_init,
1450         .sw_fini = sdma_v4_0_sw_fini,
1451         .hw_init = sdma_v4_0_hw_init,
1452         .hw_fini = sdma_v4_0_hw_fini,
1453         .suspend = sdma_v4_0_suspend,
1454         .resume = sdma_v4_0_resume,
1455         .is_idle = sdma_v4_0_is_idle,
1456         .wait_for_idle = sdma_v4_0_wait_for_idle,
1457         .soft_reset = sdma_v4_0_soft_reset,
1458         .set_clockgating_state = sdma_v4_0_set_clockgating_state,
1459         .set_powergating_state = sdma_v4_0_set_powergating_state,
1460         .get_clockgating_state = sdma_v4_0_get_clockgating_state,
1461 };
1462
1463 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
1464         .type = AMDGPU_RING_TYPE_SDMA,
1465         .align_mask = 0xf,
1466         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1467         .support_64bit_ptrs = true,
1468         .vmhub = AMDGPU_MMHUB,
1469         .get_rptr = sdma_v4_0_ring_get_rptr,
1470         .get_wptr = sdma_v4_0_ring_get_wptr,
1471         .set_wptr = sdma_v4_0_ring_set_wptr,
1472         .emit_frame_size =
1473                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
1474                 3 + /* sdma_v4_0_ring_emit_hdp_invalidate */
1475                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
1476                 18 + /* sdma_v4_0_ring_emit_vm_flush */
1477                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
1478         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
1479         .emit_ib = sdma_v4_0_ring_emit_ib,
1480         .emit_fence = sdma_v4_0_ring_emit_fence,
1481         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
1482         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
1483         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
1484         .emit_hdp_invalidate = sdma_v4_0_ring_emit_hdp_invalidate,
1485         .test_ring = sdma_v4_0_ring_test_ring,
1486         .test_ib = sdma_v4_0_ring_test_ib,
1487         .insert_nop = sdma_v4_0_ring_insert_nop,
1488         .pad_ib = sdma_v4_0_ring_pad_ib,
1489 };
1490
1491 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
1492 {
1493         int i;
1494
1495         for (i = 0; i < adev->sdma.num_instances; i++)
1496                 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
1497 }
1498
1499 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
1500         .set = sdma_v4_0_set_trap_irq_state,
1501         .process = sdma_v4_0_process_trap_irq,
1502 };
1503
1504 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
1505         .process = sdma_v4_0_process_illegal_inst_irq,
1506 };
1507
1508 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
1509 {
1510         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1511         adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
1512         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
1513 }
1514
1515 /**
1516  * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
1517  *
1518  * @ring: amdgpu_ring structure holding ring information
1519  * @src_offset: src GPU address
1520  * @dst_offset: dst GPU address
1521  * @byte_count: number of bytes to xfer
1522  *
1523  * Copy GPU buffers using the DMA engine (VEGA10).
1524  * Used by the amdgpu ttm implementation to move pages if
1525  * registered as the asic copy callback.
1526  */
1527 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
1528                                        uint64_t src_offset,
1529                                        uint64_t dst_offset,
1530                                        uint32_t byte_count)
1531 {
1532         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1533                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1534         ib->ptr[ib->length_dw++] = byte_count - 1;
1535         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1536         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1537         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1538         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1539         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1540 }
1541
1542 /**
1543  * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
1544  *
1545  * @ring: amdgpu_ring structure holding ring information
1546  * @src_data: value to write to buffer
1547  * @dst_offset: dst GPU address
1548  * @byte_count: number of bytes to xfer
1549  *
1550  * Fill GPU buffers using the DMA engine (VEGA10).
1551  */
1552 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
1553                                        uint32_t src_data,
1554                                        uint64_t dst_offset,
1555                                        uint32_t byte_count)
1556 {
1557         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1558         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1559         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1560         ib->ptr[ib->length_dw++] = src_data;
1561         ib->ptr[ib->length_dw++] = byte_count - 1;
1562 }
1563
1564 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
1565         .copy_max_bytes = 0x400000,
1566         .copy_num_dw = 7,
1567         .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
1568
1569         .fill_max_bytes = 0x400000,
1570         .fill_num_dw = 5,
1571         .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
1572 };
1573
1574 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
1575 {
1576         if (adev->mman.buffer_funcs == NULL) {
1577                 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
1578                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1579         }
1580 }
1581
1582 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
1583         .copy_pte = sdma_v4_0_vm_copy_pte,
1584         .write_pte = sdma_v4_0_vm_write_pte,
1585         .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
1586 };
1587
1588 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1589 {
1590         unsigned i;
1591
1592         if (adev->vm_manager.vm_pte_funcs == NULL) {
1593                 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
1594                 for (i = 0; i < adev->sdma.num_instances; i++)
1595                         adev->vm_manager.vm_pte_rings[i] =
1596                                 &adev->sdma.instance[i].ring;
1597
1598                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1599         }
1600 }
1601
1602 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
1603         .type = AMD_IP_BLOCK_TYPE_SDMA,
1604         .major = 4,
1605         .minor = 0,
1606         .rev = 0,
1607         .funcs = &sdma_v4_0_ip_funcs,
1608 };