drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include "drmP.h"
  27 #include "amdgpu.h"
  28 #include "amdgpu_atomfirmware.h"
  29 #include "amdgpu_ih.h"
  30 #include "amdgpu_uvd.h"
  31 #include "amdgpu_vce.h"
  32 #include "amdgpu_ucode.h"
  33 #include "amdgpu_psp.h"
  34 #include "atom.h"
  35 #include "amd_pcie.h"
  36
  37 #include "vega10/soc15ip.h"
  38 #include "vega10/UVD/uvd_7_0_offset.h"
  39 #include "vega10/GC/gc_9_0_offset.h"
  40 #include "vega10/GC/gc_9_0_sh_mask.h"
  41 #include "vega10/SDMA0/sdma0_4_0_offset.h"
  42 #include "vega10/SDMA1/sdma1_4_0_offset.h"
  43 #include "vega10/HDP/hdp_4_0_offset.h"
  44 #include "vega10/HDP/hdp_4_0_sh_mask.h"
  45 #include "vega10/MP/mp_9_0_offset.h"
  46 #include "vega10/MP/mp_9_0_sh_mask.h"
  47 #include "vega10/SMUIO/smuio_9_0_offset.h"
  48 #include "vega10/SMUIO/smuio_9_0_sh_mask.h"
  49
  50 #include "soc15.h"
  51 #include "soc15_common.h"
  52 #include "gfx_v9_0.h"
  53 #include "gmc_v9_0.h"
  54 #include "gfxhub_v1_0.h"
  55 #include "mmhub_v1_0.h"
  56 #include "vega10_ih.h"
  57 #include "sdma_v4_0.h"
  58 #include "uvd_v7_0.h"
  59 #include "vce_v4_0.h"
  60 #include "amdgpu_powerplay.h"
  61 #include "dce_virtual.h"
  62 #include "mxgpu_ai.h"
  63
  64 MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
  65
  66 #define mmFabricConfigAccessControl                                                                    0x0410
  67 #define mmFabricConfigAccessControl_BASE_IDX                                                           0
  68 #define mmFabricConfigAccessControl_DEFAULT                                      0x00000000
  69 //FabricConfigAccessControl
  70 #define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT                                                     0x0
  71 #define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT                                                0x1
  72 #define FabricConfigAccessControl__CfgRegInstID__SHIFT                                                        0x10
  73 #define FabricConfigAccessControl__CfgRegInstAccEn_MASK                                                       0x00000001L
  74 #define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK                                                  0x00000002L
  75 #define FabricConfigAccessControl__CfgRegInstID_MASK                                                          0x00FF0000L
  76
  77
  78 #define mmDF_PIE_AON0_DfGlobalClkGater                                                                 0x00fc
  79 #define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX                                                        0
  80 //DF_PIE_AON0_DfGlobalClkGater
  81 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT                                                         0x0
  82 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK                                                           0x0000000FL
  83
  84 enum {
  85         DF_MGCG_DISABLE = 0,
  86         DF_MGCG_ENABLE_00_CYCLE_DELAY =1,
  87         DF_MGCG_ENABLE_01_CYCLE_DELAY =2,
  88         DF_MGCG_ENABLE_15_CYCLE_DELAY =13,
  89         DF_MGCG_ENABLE_31_CYCLE_DELAY =14,
  90         DF_MGCG_ENABLE_63_CYCLE_DELAY =15
  91 };
  92
  93 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  94 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  95 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  96 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  97
  98 /*
  99  * Indirect registers accessor
 100  */
 101 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 102 {
 103         unsigned long flags, address, data;
 104         u32 r;
 105         struct nbio_pcie_index_data *nbio_pcie_id;
 106
 107         if (adev->asic_type == CHIP_VEGA10)
 108                 nbio_pcie_id = &nbio_v6_1_pcie_index_data;
 109         else
 110                 BUG();
 111
 112         address = nbio_pcie_id->index_offset;
 113         data = nbio_pcie_id->data_offset;
 114
 115         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 116         WREG32(address, reg);
 117         (void)RREG32(address);
 118         r = RREG32(data);
 119         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 120         return r;
 121 }
 122
 123 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 124 {
 125         unsigned long flags, address, data;
 126         struct nbio_pcie_index_data *nbio_pcie_id;
 127
 128         if (adev->asic_type == CHIP_VEGA10)
 129                 nbio_pcie_id = &nbio_v6_1_pcie_index_data;
 130         else
 131                 BUG();
 132
 133         address = nbio_pcie_id->index_offset;
 134         data = nbio_pcie_id->data_offset;
 135
 136         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 137         WREG32(address, reg);
 138         (void)RREG32(address);
 139         WREG32(data, v);
 140         (void)RREG32(data);
 141         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 142 }
 143
 144 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 145 {
 146         unsigned long flags, address, data;
 147         u32 r;
 148
 149         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 150         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 151
 152         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 153         WREG32(address, ((reg) & 0x1ff));
 154         r = RREG32(data);
 155         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 156         return r;
 157 }
 158
 159 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 160 {
 161         unsigned long flags, address, data;
 162
 163         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 164         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 165
 166         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 167         WREG32(address, ((reg) & 0x1ff));
 168         WREG32(data, (v));
 169         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 170 }
 171
 172 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 173 {
 174         unsigned long flags, address, data;
 175         u32 r;
 176
 177         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 178         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 179
 180         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 181         WREG32(address, (reg));
 182         r = RREG32(data);
 183         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 184         return r;
 185 }
 186
 187 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 188 {
 189         unsigned long flags, address, data;
 190
 191         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 192         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 193
 194         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 195         WREG32(address, (reg));
 196         WREG32(data, (v));
 197         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 198 }
 199
 200 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 201 {
 202         return nbio_v6_1_get_memsize(adev);
 203 }
 204
 205 static const u32 vega10_golden_init[] =
 206 {
 207 };
 208
 209 static void soc15_init_golden_registers(struct amdgpu_device *adev)
 210 {
 211         /* Some of the registers might be dependent on GRBM_GFX_INDEX */
 212         mutex_lock(&adev->grbm_idx_mutex);
 213
 214         switch (adev->asic_type) {
 215         case CHIP_VEGA10:
 216                 amdgpu_program_register_sequence(adev,
 217                                                  vega10_golden_init,
 218                                                  (const u32)ARRAY_SIZE(vega10_golden_init));
 219                 break;
 220         default:
 221                 break;
 222         }
 223         mutex_unlock(&adev->grbm_idx_mutex);
 224 }
 225 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 226 {
 227         if (adev->asic_type == CHIP_VEGA10)
 228                 return adev->clock.spll.reference_freq/4;
 229         else
 230                 return adev->clock.spll.reference_freq;
 231 }
 232
 233
 234 void soc15_grbm_select(struct amdgpu_device *adev,
 235                      u32 me, u32 pipe, u32 queue, u32 vmid)
 236 {
 237         u32 grbm_gfx_cntl = 0;
 238         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 239         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 240         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 241         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 242
 243         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 244 }
 245
 246 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 247 {
 248         /* todo */
 249 }
 250
 251 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 252 {
 253         /* todo */
 254         return false;
 255 }
 256
 257 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 258                                      u8 *bios, u32 length_bytes)
 259 {
 260         u32 *dw_ptr;
 261         u32 i, length_dw;
 262
 263         if (bios == NULL)
 264                 return false;
 265         if (length_bytes == 0)
 266                 return false;
 267         /* APU vbios image is part of sbios image */
 268         if (adev->flags & AMD_IS_APU)
 269                 return false;
 270
 271         dw_ptr = (u32 *)bios;
 272         length_dw = ALIGN(length_bytes, 4) / 4;
 273
 274         /* set rom index to 0 */
 275         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 276         /* read out the rom data */
 277         for (i = 0; i < length_dw; i++)
 278                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 279
 280         return true;
 281 }
 282
 283 static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = {
 284         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)},
 285         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2)},
 286         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0)},
 287         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1)},
 288         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2)},
 289         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3)},
 290         { SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_STATUS_REG)},
 291         { SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_STATUS_REG)},
 292         { SOC15_REG_OFFSET(GC, 0, mmCP_STAT)},
 293         { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1)},
 294         { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2)},
 295         { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3)},
 296         { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT)},
 297         { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1)},
 298         { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS)},
 299         { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1)},
 300         { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS)},
 301         { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)},
 302 };
 303
 304 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 305                                          u32 sh_num, u32 reg_offset)
 306 {
 307         uint32_t val;
 308
 309         mutex_lock(&adev->grbm_idx_mutex);
 310         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 311                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 312
 313         val = RREG32(reg_offset);
 314
 315         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 316                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 317         mutex_unlock(&adev->grbm_idx_mutex);
 318         return val;
 319 }
 320
 321 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 322                                          bool indexed, u32 se_num,
 323                                          u32 sh_num, u32 reg_offset)
 324 {
 325         if (indexed) {
 326                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 327         } else {
 328                 switch (reg_offset) {
 329                 case SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG):
 330                         return adev->gfx.config.gb_addr_config;
 331                 default:
 332                         return RREG32(reg_offset);
 333                 }
 334         }
 335 }
 336
 337 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 338                             u32 sh_num, u32 reg_offset, u32 *value)
 339 {
 340         uint32_t i;
 341
 342         *value = 0;
 343         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 344                 if (reg_offset != soc15_allowed_read_registers[i].reg_offset)
 345                         continue;
 346
 347                 *value = soc15_get_register_value(adev,
 348                                                   soc15_allowed_read_registers[i].grbm_indexed,
 349                                                   se_num, sh_num, reg_offset);
 350                 return 0;
 351         }
 352         return -EINVAL;
 353 }
 354
 355 static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev)
 356 {
 357         u32 i;
 358
 359         dev_info(adev->dev, "GPU pci config reset\n");
 360
 361         /* disable BM */
 362         pci_clear_master(adev->pdev);
 363         /* reset */
 364         amdgpu_pci_config_reset(adev);
 365
 366         udelay(100);
 367
 368         /* wait for asic to come out of reset */
 369         for (i = 0; i < adev->usec_timeout; i++) {
 370                 if (nbio_v6_1_get_memsize(adev) != 0xffffffff)
 371                         break;
 372                 udelay(1);
 373         }
 374
 375 }
 376
 377 static int soc15_asic_reset(struct amdgpu_device *adev)
 378 {
 379         amdgpu_atomfirmware_scratch_regs_engine_hung(adev, true);
 380
 381         soc15_gpu_pci_config_reset(adev);
 382
 383         amdgpu_atomfirmware_scratch_regs_engine_hung(adev, false);
 384
 385         return 0;
 386 }
 387
 388 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 389                         u32 cntl_reg, u32 status_reg)
 390 {
 391         return 0;
 392 }*/
 393
 394 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 395 {
 396         /*int r;
 397
 398         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 399         if (r)
 400                 return r;
 401
 402         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 403         */
 404         return 0;
 405 }
 406
 407 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 408 {
 409         /* todo */
 410
 411         return 0;
 412 }
 413
 414 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 415 {
 416         if (pci_is_root_bus(adev->pdev->bus))
 417                 return;
 418
 419         if (amdgpu_pcie_gen2 == 0)
 420                 return;
 421
 422         if (adev->flags & AMD_IS_APU)
 423                 return;
 424
 425         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 426                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 427                 return;
 428
 429         /* todo */
 430 }
 431
 432 static void soc15_program_aspm(struct amdgpu_device *adev)
 433 {
 434
 435         if (amdgpu_aspm == 0)
 436                 return;
 437
 438         /* todo */
 439 }
 440
 441 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 442                                         bool enable)
 443 {
 444         nbio_v6_1_enable_doorbell_aperture(adev, enable);
 445         nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable);
 446 }
 447
 448 static const struct amdgpu_ip_block_version vega10_common_ip_block =
 449 {
 450         .type = AMD_IP_BLOCK_TYPE_COMMON,
 451         .major = 2,
 452         .minor = 0,
 453         .rev = 0,
 454         .funcs = &soc15_common_ip_funcs,
 455 };
 456
 457 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 458 {
 459         nbio_v6_1_detect_hw_virt(adev);
 460
 461         if (amdgpu_sriov_vf(adev))
 462                 adev->virt.ops = &xgpu_ai_virt_ops;
 463
 464         switch (adev->asic_type) {
 465         case CHIP_VEGA10:
 466                 amdgpu_ip_block_add(adev, &vega10_common_ip_block);
 467                 amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block);
 468                 amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
 469                 amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
 470                 amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
 471                 if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1)
 472                         amdgpu_ip_block_add(adev, &psp_v3_1_ip_block);
 473                 if (!amdgpu_sriov_vf(adev))
 474                         amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
 475                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 476                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
 477                 amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
 478                 amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
 479                 amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block);
 480                 amdgpu_ip_block_add(adev, &vce_v4_0_ip_block);
 481                 break;
 482         default:
 483                 return -EINVAL;
 484         }
 485
 486         return 0;
 487 }
 488
 489 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 490 {
 491         return nbio_v6_1_get_rev_id(adev);
 492 }
 493
 494
 495 int gmc_v9_0_mc_wait_for_idle(struct amdgpu_device *adev)
 496 {
 497         /* to be implemented in MC IP*/
 498         return 0;
 499 }
 500
 501 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 502 {
 503         .read_disabled_bios = &soc15_read_disabled_bios,
 504         .read_bios_from_rom = &soc15_read_bios_from_rom,
 505         .read_register = &soc15_read_register,
 506         .reset = &soc15_asic_reset,
 507         .set_vga_state = &soc15_vga_set_state,
 508         .get_xclk = &soc15_get_xclk,
 509         .set_uvd_clocks = &soc15_set_uvd_clocks,
 510         .set_vce_clocks = &soc15_set_vce_clocks,
 511         .get_config_memsize = &soc15_get_config_memsize,
 512 };
 513
 514 static int soc15_common_early_init(void *handle)
 515 {
 516         bool psp_enabled = false;
 517         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 518
 519         adev->smc_rreg = NULL;
 520         adev->smc_wreg = NULL;
 521         adev->pcie_rreg = &soc15_pcie_rreg;
 522         adev->pcie_wreg = &soc15_pcie_wreg;
 523         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
 524         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
 525         adev->didt_rreg = &soc15_didt_rreg;
 526         adev->didt_wreg = &soc15_didt_wreg;
 527
 528         adev->asic_funcs = &soc15_asic_funcs;
 529
 530         if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) &&
 531                 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
 532                 psp_enabled = true;
 533
 534         /*
 535          * nbio need be used for both sdma and gfx9, but only
 536          * initializes once
 537          */
 538         switch(adev->asic_type) {
 539         case CHIP_VEGA10:
 540                 nbio_v6_1_init(adev);
 541                 break;
 542         default:
 543                 return -EINVAL;
 544         }
 545
 546         adev->rev_id = soc15_get_rev_id(adev);
 547         adev->external_rev_id = 0xFF;
 548         switch (adev->asic_type) {
 549         case CHIP_VEGA10:
 550                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 551                         AMD_CG_SUPPORT_GFX_MGLS |
 552                         AMD_CG_SUPPORT_GFX_RLC_LS |
 553                         AMD_CG_SUPPORT_GFX_CP_LS |
 554                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 555                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 556                         AMD_CG_SUPPORT_GFX_CGCG |
 557                         AMD_CG_SUPPORT_GFX_CGLS |
 558                         AMD_CG_SUPPORT_BIF_MGCG |
 559                         AMD_CG_SUPPORT_BIF_LS |
 560                         AMD_CG_SUPPORT_HDP_LS |
 561                         AMD_CG_SUPPORT_DRM_MGCG |
 562                         AMD_CG_SUPPORT_DRM_LS |
 563                         AMD_CG_SUPPORT_ROM_MGCG |
 564                         AMD_CG_SUPPORT_DF_MGCG |
 565                         AMD_CG_SUPPORT_SDMA_MGCG |
 566                         AMD_CG_SUPPORT_SDMA_LS |
 567                         AMD_CG_SUPPORT_MC_MGCG |
 568                         AMD_CG_SUPPORT_MC_LS;
 569                 adev->pg_flags = 0;
 570                 adev->external_rev_id = 0x1;
 571                 break;
 572         default:
 573                 /* FIXME: not supported yet */
 574                 return -EINVAL;
 575         }
 576
 577         if (amdgpu_sriov_vf(adev)) {
 578                 amdgpu_virt_init_setting(adev);
 579                 xgpu_ai_mailbox_set_irq_funcs(adev);
 580         }
 581
 582         adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
 583
 584         amdgpu_get_pcie_info(adev);
 585
 586         return 0;
 587 }
 588
 589 static int soc15_common_late_init(void *handle)
 590 {
 591         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 592
 593         if (amdgpu_sriov_vf(adev))
 594                 xgpu_ai_mailbox_get_irq(adev);
 595
 596         return 0;
 597 }
 598
 599 static int soc15_common_sw_init(void *handle)
 600 {
 601         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 602
 603         if (amdgpu_sriov_vf(adev))
 604                 xgpu_ai_mailbox_add_irq_id(adev);
 605
 606         return 0;
 607 }
 608
 609 static int soc15_common_sw_fini(void *handle)
 610 {
 611         return 0;
 612 }
 613
 614 static int soc15_common_hw_init(void *handle)
 615 {
 616         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 617
 618         /* move the golden regs per IP block */
 619         soc15_init_golden_registers(adev);
 620         /* enable pcie gen2/3 link */
 621         soc15_pcie_gen3_enable(adev);
 622         /* enable aspm */
 623         soc15_program_aspm(adev);
 624         /* enable the doorbell aperture */
 625         soc15_enable_doorbell_aperture(adev, true);
 626
 627         return 0;
 628 }
 629
 630 static int soc15_common_hw_fini(void *handle)
 631 {
 632         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 633
 634         /* disable the doorbell aperture */
 635         soc15_enable_doorbell_aperture(adev, false);
 636         if (amdgpu_sriov_vf(adev))
 637                 xgpu_ai_mailbox_put_irq(adev);
 638
 639         return 0;
 640 }
 641
 642 static int soc15_common_suspend(void *handle)
 643 {
 644         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 645
 646         return soc15_common_hw_fini(adev);
 647 }
 648
 649 static int soc15_common_resume(void *handle)
 650 {
 651         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 652
 653         return soc15_common_hw_init(adev);
 654 }
 655
 656 static bool soc15_common_is_idle(void *handle)
 657 {
 658         return true;
 659 }
 660
 661 static int soc15_common_wait_for_idle(void *handle)
 662 {
 663         return 0;
 664 }
 665
 666 static int soc15_common_soft_reset(void *handle)
 667 {
 668         return 0;
 669 }
 670
 671 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
 672 {
 673         uint32_t def, data;
 674
 675         def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 676
 677         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 678                 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 679         else
 680                 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 681
 682         if (def != data)
 683                 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
 684 }
 685
 686 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
 687 {
 688         uint32_t def, data;
 689
 690         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
 691
 692         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
 693                 data &= ~(0x01000000 |
 694                           0x02000000 |
 695                           0x04000000 |
 696                           0x08000000 |
 697                           0x10000000 |
 698                           0x20000000 |
 699                           0x40000000 |
 700                           0x80000000);
 701         else
 702                 data |= (0x01000000 |
 703                          0x02000000 |
 704                          0x04000000 |
 705                          0x08000000 |
 706                          0x10000000 |
 707                          0x20000000 |
 708                          0x40000000 |
 709                          0x80000000);
 710
 711         if (def != data)
 712                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
 713 }
 714
 715 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
 716 {
 717         uint32_t def, data;
 718
 719         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
 720
 721         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
 722                 data |= 1;
 723         else
 724                 data &= ~1;
 725
 726         if (def != data)
 727                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
 728 }
 729
 730 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
 731                                                        bool enable)
 732 {
 733         uint32_t def, data;
 734
 735         def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
 736
 737         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
 738                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
 739                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
 740         else
 741                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
 742                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
 743
 744         if (def != data)
 745                 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
 746 }
 747
 748 static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device *adev,
 749                                                        bool enable)
 750 {
 751         uint32_t data;
 752
 753         /* Put DF on broadcast mode */
 754         data = RREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl));
 755         data &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
 756         WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), data);
 757
 758         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
 759                 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 760                 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
 761                 data |= DF_MGCG_ENABLE_15_CYCLE_DELAY;
 762                 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
 763         } else {
 764                 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 765                 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
 766                 data |= DF_MGCG_DISABLE;
 767                 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
 768         }
 769
 770         WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl),
 771                mmFabricConfigAccessControl_DEFAULT);
 772 }
 773
 774 static int soc15_common_set_clockgating_state(void *handle,
 775                                             enum amd_clockgating_state state)
 776 {
 777         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 778
 779         if (amdgpu_sriov_vf(adev))
 780                 return 0;
 781
 782         switch (adev->asic_type) {
 783         case CHIP_VEGA10:
 784                 nbio_v6_1_update_medium_grain_clock_gating(adev,
 785                                 state == AMD_CG_STATE_GATE ? true : false);
 786                 nbio_v6_1_update_medium_grain_light_sleep(adev,
 787                                 state == AMD_CG_STATE_GATE ? true : false);
 788                 soc15_update_hdp_light_sleep(adev,
 789                                 state == AMD_CG_STATE_GATE ? true : false);
 790                 soc15_update_drm_clock_gating(adev,
 791                                 state == AMD_CG_STATE_GATE ? true : false);
 792                 soc15_update_drm_light_sleep(adev,
 793                                 state == AMD_CG_STATE_GATE ? true : false);
 794                 soc15_update_rom_medium_grain_clock_gating(adev,
 795                                 state == AMD_CG_STATE_GATE ? true : false);
 796                 soc15_update_df_medium_grain_clock_gating(adev,
 797                                 state == AMD_CG_STATE_GATE ? true : false);
 798                 break;
 799         default:
 800                 break;
 801         }
 802         return 0;
 803 }
 804
 805 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
 806 {
 807         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 808         int data;
 809
 810         if (amdgpu_sriov_vf(adev))
 811                 *flags = 0;
 812
 813         nbio_v6_1_get_clockgating_state(adev, flags);
 814
 815         /* AMD_CG_SUPPORT_HDP_LS */
 816         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 817         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
 818                 *flags |= AMD_CG_SUPPORT_HDP_LS;
 819
 820         /* AMD_CG_SUPPORT_DRM_MGCG */
 821         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
 822         if (!(data & 0x01000000))
 823                 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
 824
 825         /* AMD_CG_SUPPORT_DRM_LS */
 826         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
 827         if (data & 0x1)
 828                 *flags |= AMD_CG_SUPPORT_DRM_LS;
 829
 830         /* AMD_CG_SUPPORT_ROM_MGCG */
 831         data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
 832         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
 833                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
 834
 835         /* AMD_CG_SUPPORT_DF_MGCG */
 836         data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 837         if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY)
 838                 *flags |= AMD_CG_SUPPORT_DF_MGCG;
 839 }
 840
 841 static int soc15_common_set_powergating_state(void *handle,
 842                                             enum amd_powergating_state state)
 843 {
 844         /* todo */
 845         return 0;
 846 }
 847
 848 const struct amd_ip_funcs soc15_common_ip_funcs = {
 849         .name = "soc15_common",
 850         .early_init = soc15_common_early_init,
 851         .late_init = soc15_common_late_init,
 852         .sw_init = soc15_common_sw_init,
 853         .sw_fini = soc15_common_sw_fini,
 854         .hw_init = soc15_common_hw_init,
 855         .hw_fini = soc15_common_hw_fini,
 856         .suspend = soc15_common_suspend,
 857         .resume = soc15_common_resume,
 858         .is_idle = soc15_common_is_idle,
 859         .wait_for_idle = soc15_common_wait_for_idle,
 860         .soft_reset = soc15_common_soft_reset,
 861         .set_clockgating_state = soc15_common_set_clockgating_state,
 862         .set_powergating_state = soc15_common_set_powergating_state,
 863         .get_clockgating_state= soc15_common_get_clockgating_state,
 864 };