drivers/gpu/drm/amd/amdgpu/vi.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include "drmP.h"
  27 #include "amdgpu.h"
  28 #include "amdgpu_atombios.h"
  29 #include "amdgpu_ih.h"
  30 #include "amdgpu_uvd.h"
  31 #include "amdgpu_vce.h"
  32 #include "amdgpu_ucode.h"
  33 #include "atom.h"
  34 #include "amd_pcie.h"
  35
  36 #include "gmc/gmc_8_1_d.h"
  37 #include "gmc/gmc_8_1_sh_mask.h"
  38
  39 #include "oss/oss_3_0_d.h"
  40 #include "oss/oss_3_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "gca/gfx_8_0_d.h"
  46 #include "gca/gfx_8_0_sh_mask.h"
  47
  48 #include "smu/smu_7_1_1_d.h"
  49 #include "smu/smu_7_1_1_sh_mask.h"
  50
  51 #include "uvd/uvd_5_0_d.h"
  52 #include "uvd/uvd_5_0_sh_mask.h"
  53
  54 #include "vce/vce_3_0_d.h"
  55 #include "vce/vce_3_0_sh_mask.h"
  56
  57 #include "dce/dce_10_0_d.h"
  58 #include "dce/dce_10_0_sh_mask.h"
  59
  60 #include "vid.h"
  61 #include "vi.h"
  62 #include "vi_dpm.h"
  63 #include "gmc_v8_0.h"
  64 #include "gmc_v7_0.h"
  65 #include "gfx_v8_0.h"
  66 #include "sdma_v2_4.h"
  67 #include "sdma_v3_0.h"
  68 #include "dce_v10_0.h"
  69 #include "dce_v11_0.h"
  70 #include "iceland_ih.h"
  71 #include "tonga_ih.h"
  72 #include "cz_ih.h"
  73 #include "uvd_v5_0.h"
  74 #include "uvd_v6_0.h"
  75 #include "vce_v3_0.h"
  76 #include "amdgpu_powerplay.h"
  77
  78 /*
  79  * Indirect registers accessor
  80  */
  81 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  82 {
  83         unsigned long flags;
  84         u32 r;
  85
  86         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  87         WREG32(mmPCIE_INDEX, reg);
  88         (void)RREG32(mmPCIE_INDEX);
  89         r = RREG32(mmPCIE_DATA);
  90         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  91         return r;
  92 }
  93
  94 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  95 {
  96         unsigned long flags;
  97
  98         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  99         WREG32(mmPCIE_INDEX, reg);
 100         (void)RREG32(mmPCIE_INDEX);
 101         WREG32(mmPCIE_DATA, v);
 102         (void)RREG32(mmPCIE_DATA);
 103         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 104 }
 105
 106 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
 107 {
 108         unsigned long flags;
 109         u32 r;
 110
 111         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 112         WREG32(mmSMC_IND_INDEX_0, (reg));
 113         r = RREG32(mmSMC_IND_DATA_0);
 114         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 115         return r;
 116 }
 117
 118 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 119 {
 120         unsigned long flags;
 121
 122         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 123         WREG32(mmSMC_IND_INDEX_0, (reg));
 124         WREG32(mmSMC_IND_DATA_0, (v));
 125         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 126 }
 127
 128 /* smu_8_0_d.h */
 129 #define mmMP0PUB_IND_INDEX                                                      0x180
 130 #define mmMP0PUB_IND_DATA                                                       0x181
 131
 132 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
 133 {
 134         unsigned long flags;
 135         u32 r;
 136
 137         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 138         WREG32(mmMP0PUB_IND_INDEX, (reg));
 139         r = RREG32(mmMP0PUB_IND_DATA);
 140         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 141         return r;
 142 }
 143
 144 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 145 {
 146         unsigned long flags;
 147
 148         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 149         WREG32(mmMP0PUB_IND_INDEX, (reg));
 150         WREG32(mmMP0PUB_IND_DATA, (v));
 151         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 152 }
 153
 154 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 155 {
 156         unsigned long flags;
 157         u32 r;
 158
 159         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 160         WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
 161         r = RREG32(mmUVD_CTX_DATA);
 162         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 163         return r;
 164 }
 165
 166 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 167 {
 168         unsigned long flags;
 169
 170         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 171         WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
 172         WREG32(mmUVD_CTX_DATA, (v));
 173         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 174 }
 175
 176 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
 177 {
 178         unsigned long flags;
 179         u32 r;
 180
 181         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 182         WREG32(mmDIDT_IND_INDEX, (reg));
 183         r = RREG32(mmDIDT_IND_DATA);
 184         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 185         return r;
 186 }
 187
 188 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 189 {
 190         unsigned long flags;
 191
 192         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 193         WREG32(mmDIDT_IND_INDEX, (reg));
 194         WREG32(mmDIDT_IND_DATA, (v));
 195         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 196 }
 197
 198 static const u32 tonga_mgcg_cgcg_init[] =
 199 {
 200         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 201         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 202         mmPCIE_DATA, 0x000f0000, 0x00000000,
 203         mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
 204         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 205         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 206         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 207 };
 208
 209 static const u32 fiji_mgcg_cgcg_init[] =
 210 {
 211         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 212         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 213         mmPCIE_DATA, 0x000f0000, 0x00000000,
 214         mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
 215         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 216         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 217         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 218 };
 219
 220 static const u32 iceland_mgcg_cgcg_init[] =
 221 {
 222         mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
 223         mmPCIE_DATA, 0x000f0000, 0x00000000,
 224         mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
 225         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 226         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 227 };
 228
 229 static const u32 cz_mgcg_cgcg_init[] =
 230 {
 231         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 232         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 233         mmPCIE_DATA, 0x000f0000, 0x00000000,
 234         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 235         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 236 };
 237
 238 static const u32 stoney_mgcg_cgcg_init[] =
 239 {
 240         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
 241         mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
 242         mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
 243 };
 244
 245 static void vi_init_golden_registers(struct amdgpu_device *adev)
 246 {
 247         /* Some of the registers might be dependent on GRBM_GFX_INDEX */
 248         mutex_lock(&adev->grbm_idx_mutex);
 249
 250         switch (adev->asic_type) {
 251         case CHIP_TOPAZ:
 252                 amdgpu_program_register_sequence(adev,
 253                                                  iceland_mgcg_cgcg_init,
 254                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
 255                 break;
 256         case CHIP_FIJI:
 257                 amdgpu_program_register_sequence(adev,
 258                                                  fiji_mgcg_cgcg_init,
 259                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 260                 break;
 261         case CHIP_TONGA:
 262                 amdgpu_program_register_sequence(adev,
 263                                                  tonga_mgcg_cgcg_init,
 264                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 265                 break;
 266         case CHIP_CARRIZO:
 267                 amdgpu_program_register_sequence(adev,
 268                                                  cz_mgcg_cgcg_init,
 269                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 270                 break;
 271         case CHIP_STONEY:
 272                 amdgpu_program_register_sequence(adev,
 273                                                  stoney_mgcg_cgcg_init,
 274                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 275                 break;
 276         default:
 277                 break;
 278         }
 279         mutex_unlock(&adev->grbm_idx_mutex);
 280 }
 281
 282 /**
 283  * vi_get_xclk - get the xclk
 284  *
 285  * @adev: amdgpu_device pointer
 286  *
 287  * Returns the reference clock used by the gfx engine
 288  * (VI).
 289  */
 290 static u32 vi_get_xclk(struct amdgpu_device *adev)
 291 {
 292         u32 reference_clock = adev->clock.spll.reference_freq;
 293         u32 tmp;
 294
 295         if (adev->flags & AMD_IS_APU)
 296                 return reference_clock;
 297
 298         tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
 299         if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
 300                 return 1000;
 301
 302         tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
 303         if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
 304                 return reference_clock / 4;
 305
 306         return reference_clock;
 307 }
 308
 309 /**
 310  * vi_srbm_select - select specific register instances
 311  *
 312  * @adev: amdgpu_device pointer
 313  * @me: selected ME (micro engine)
 314  * @pipe: pipe
 315  * @queue: queue
 316  * @vmid: VMID
 317  *
 318  * Switches the currently active registers instances.  Some
 319  * registers are instanced per VMID, others are instanced per
 320  * me/pipe/queue combination.
 321  */
 322 void vi_srbm_select(struct amdgpu_device *adev,
 323                      u32 me, u32 pipe, u32 queue, u32 vmid)
 324 {
 325         u32 srbm_gfx_cntl = 0;
 326         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
 327         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
 328         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
 329         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
 330         WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
 331 }
 332
 333 static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
 334 {
 335         /* todo */
 336 }
 337
 338 static bool vi_read_disabled_bios(struct amdgpu_device *adev)
 339 {
 340         u32 bus_cntl;
 341         u32 d1vga_control = 0;
 342         u32 d2vga_control = 0;
 343         u32 vga_render_control = 0;
 344         u32 rom_cntl;
 345         bool r;
 346
 347         bus_cntl = RREG32(mmBUS_CNTL);
 348         if (adev->mode_info.num_crtc) {
 349                 d1vga_control = RREG32(mmD1VGA_CONTROL);
 350                 d2vga_control = RREG32(mmD2VGA_CONTROL);
 351                 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 352         }
 353         rom_cntl = RREG32_SMC(ixROM_CNTL);
 354
 355         /* enable the rom */
 356         WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
 357         if (adev->mode_info.num_crtc) {
 358                 /* Disable VGA mode */
 359                 WREG32(mmD1VGA_CONTROL,
 360                        (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
 361                                           D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
 362                 WREG32(mmD2VGA_CONTROL,
 363                        (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
 364                                           D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
 365                 WREG32(mmVGA_RENDER_CONTROL,
 366                        (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
 367         }
 368         WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
 369
 370         r = amdgpu_read_bios(adev);
 371
 372         /* restore regs */
 373         WREG32(mmBUS_CNTL, bus_cntl);
 374         if (adev->mode_info.num_crtc) {
 375                 WREG32(mmD1VGA_CONTROL, d1vga_control);
 376                 WREG32(mmD2VGA_CONTROL, d2vga_control);
 377                 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
 378         }
 379         WREG32_SMC(ixROM_CNTL, rom_cntl);
 380         return r;
 381 }
 382
 383 static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
 384                                   u8 *bios, u32 length_bytes)
 385 {
 386         u32 *dw_ptr;
 387         unsigned long flags;
 388         u32 i, length_dw;
 389
 390         if (bios == NULL)
 391                 return false;
 392         if (length_bytes == 0)
 393                 return false;
 394         /* APU vbios image is part of sbios image */
 395         if (adev->flags & AMD_IS_APU)
 396                 return false;
 397
 398         dw_ptr = (u32 *)bios;
 399         length_dw = ALIGN(length_bytes, 4) / 4;
 400         /* take the smc lock since we are using the smc index */
 401         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 402         /* set rom index to 0 */
 403         WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
 404         WREG32(mmSMC_IND_DATA_0, 0);
 405         /* set index to data for continous read */
 406         WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
 407         for (i = 0; i < length_dw; i++)
 408                 dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
 409         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 410
 411         return true;
 412 }
 413
 414 static struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
 415         {mmGB_MACROTILE_MODE7, true},
 416 };
 417
 418 static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
 419         {mmGB_TILE_MODE7, true},
 420         {mmGB_TILE_MODE12, true},
 421         {mmGB_TILE_MODE17, true},
 422         {mmGB_TILE_MODE23, true},
 423         {mmGB_MACROTILE_MODE7, true},
 424 };
 425
 426 static struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
 427         {mmGRBM_STATUS, false},
 428         {mmGRBM_STATUS2, false},
 429         {mmGRBM_STATUS_SE0, false},
 430         {mmGRBM_STATUS_SE1, false},
 431         {mmGRBM_STATUS_SE2, false},
 432         {mmGRBM_STATUS_SE3, false},
 433         {mmSRBM_STATUS, false},
 434         {mmSRBM_STATUS2, false},
 435         {mmSRBM_STATUS3, false},
 436         {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET, false},
 437         {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET, false},
 438         {mmCP_STAT, false},
 439         {mmCP_STALLED_STAT1, false},
 440         {mmCP_STALLED_STAT2, false},
 441         {mmCP_STALLED_STAT3, false},
 442         {mmCP_CPF_BUSY_STAT, false},
 443         {mmCP_CPF_STALLED_STAT1, false},
 444         {mmCP_CPF_STATUS, false},
 445         {mmCP_CPC_BUSY_STAT, false},
 446         {mmCP_CPC_STALLED_STAT1, false},
 447         {mmCP_CPC_STATUS, false},
 448         {mmGB_ADDR_CONFIG, false},
 449         {mmMC_ARB_RAMCFG, false},
 450         {mmGB_TILE_MODE0, false},
 451         {mmGB_TILE_MODE1, false},
 452         {mmGB_TILE_MODE2, false},
 453         {mmGB_TILE_MODE3, false},
 454         {mmGB_TILE_MODE4, false},
 455         {mmGB_TILE_MODE5, false},
 456         {mmGB_TILE_MODE6, false},
 457         {mmGB_TILE_MODE7, false},
 458         {mmGB_TILE_MODE8, false},
 459         {mmGB_TILE_MODE9, false},
 460         {mmGB_TILE_MODE10, false},
 461         {mmGB_TILE_MODE11, false},
 462         {mmGB_TILE_MODE12, false},
 463         {mmGB_TILE_MODE13, false},
 464         {mmGB_TILE_MODE14, false},
 465         {mmGB_TILE_MODE15, false},
 466         {mmGB_TILE_MODE16, false},
 467         {mmGB_TILE_MODE17, false},
 468         {mmGB_TILE_MODE18, false},
 469         {mmGB_TILE_MODE19, false},
 470         {mmGB_TILE_MODE20, false},
 471         {mmGB_TILE_MODE21, false},
 472         {mmGB_TILE_MODE22, false},
 473         {mmGB_TILE_MODE23, false},
 474         {mmGB_TILE_MODE24, false},
 475         {mmGB_TILE_MODE25, false},
 476         {mmGB_TILE_MODE26, false},
 477         {mmGB_TILE_MODE27, false},
 478         {mmGB_TILE_MODE28, false},
 479         {mmGB_TILE_MODE29, false},
 480         {mmGB_TILE_MODE30, false},
 481         {mmGB_TILE_MODE31, false},
 482         {mmGB_MACROTILE_MODE0, false},
 483         {mmGB_MACROTILE_MODE1, false},
 484         {mmGB_MACROTILE_MODE2, false},
 485         {mmGB_MACROTILE_MODE3, false},
 486         {mmGB_MACROTILE_MODE4, false},
 487         {mmGB_MACROTILE_MODE5, false},
 488         {mmGB_MACROTILE_MODE6, false},
 489         {mmGB_MACROTILE_MODE7, false},
 490         {mmGB_MACROTILE_MODE8, false},
 491         {mmGB_MACROTILE_MODE9, false},
 492         {mmGB_MACROTILE_MODE10, false},
 493         {mmGB_MACROTILE_MODE11, false},
 494         {mmGB_MACROTILE_MODE12, false},
 495         {mmGB_MACROTILE_MODE13, false},
 496         {mmGB_MACROTILE_MODE14, false},
 497         {mmGB_MACROTILE_MODE15, false},
 498         {mmCC_RB_BACKEND_DISABLE, false, true},
 499         {mmGC_USER_RB_BACKEND_DISABLE, false, true},
 500         {mmGB_BACKEND_MAP, false, false},
 501         {mmPA_SC_RASTER_CONFIG, false, true},
 502         {mmPA_SC_RASTER_CONFIG_1, false, true},
 503 };
 504
 505 static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 506                                          u32 sh_num, u32 reg_offset)
 507 {
 508         uint32_t val;
 509
 510         mutex_lock(&adev->grbm_idx_mutex);
 511         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 512                 gfx_v8_0_select_se_sh(adev, se_num, sh_num);
 513
 514         val = RREG32(reg_offset);
 515
 516         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 517                 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
 518         mutex_unlock(&adev->grbm_idx_mutex);
 519         return val;
 520 }
 521
 522 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
 523                             u32 sh_num, u32 reg_offset, u32 *value)
 524 {
 525         struct amdgpu_allowed_register_entry *asic_register_table = NULL;
 526         struct amdgpu_allowed_register_entry *asic_register_entry;
 527         uint32_t size, i;
 528
 529         *value = 0;
 530         switch (adev->asic_type) {
 531         case CHIP_TOPAZ:
 532                 asic_register_table = tonga_allowed_read_registers;
 533                 size = ARRAY_SIZE(tonga_allowed_read_registers);
 534                 break;
 535         case CHIP_FIJI:
 536         case CHIP_TONGA:
 537         case CHIP_CARRIZO:
 538         case CHIP_STONEY:
 539                 asic_register_table = cz_allowed_read_registers;
 540                 size = ARRAY_SIZE(cz_allowed_read_registers);
 541                 break;
 542         default:
 543                 return -EINVAL;
 544         }
 545
 546         if (asic_register_table) {
 547                 for (i = 0; i < size; i++) {
 548                         asic_register_entry = asic_register_table + i;
 549                         if (reg_offset != asic_register_entry->reg_offset)
 550                                 continue;
 551                         if (!asic_register_entry->untouched)
 552                                 *value = asic_register_entry->grbm_indexed ?
 553                                         vi_read_indexed_register(adev, se_num,
 554                                                                  sh_num, reg_offset) :
 555                                         RREG32(reg_offset);
 556                         return 0;
 557                 }
 558         }
 559
 560         for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
 561                 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
 562                         continue;
 563
 564                 if (!vi_allowed_read_registers[i].untouched)
 565                         *value = vi_allowed_read_registers[i].grbm_indexed ?
 566                                 vi_read_indexed_register(adev, se_num,
 567                                                          sh_num, reg_offset) :
 568                                 RREG32(reg_offset);
 569                 return 0;
 570         }
 571         return -EINVAL;
 572 }
 573
 574 static void vi_print_gpu_status_regs(struct amdgpu_device *adev)
 575 {
 576         dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
 577                 RREG32(mmGRBM_STATUS));
 578         dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
 579                 RREG32(mmGRBM_STATUS2));
 580         dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
 581                 RREG32(mmGRBM_STATUS_SE0));
 582         dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
 583                 RREG32(mmGRBM_STATUS_SE1));
 584         dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
 585                 RREG32(mmGRBM_STATUS_SE2));
 586         dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
 587                 RREG32(mmGRBM_STATUS_SE3));
 588         dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
 589                 RREG32(mmSRBM_STATUS));
 590         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
 591                 RREG32(mmSRBM_STATUS2));
 592         dev_info(adev->dev, "  SDMA0_STATUS_REG   = 0x%08X\n",
 593                 RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
 594         if (adev->sdma.num_instances > 1) {
 595                 dev_info(adev->dev, "  SDMA1_STATUS_REG   = 0x%08X\n",
 596                         RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
 597         }
 598         dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
 599         dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
 600                  RREG32(mmCP_STALLED_STAT1));
 601         dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
 602                  RREG32(mmCP_STALLED_STAT2));
 603         dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
 604                  RREG32(mmCP_STALLED_STAT3));
 605         dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
 606                  RREG32(mmCP_CPF_BUSY_STAT));
 607         dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
 608                  RREG32(mmCP_CPF_STALLED_STAT1));
 609         dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
 610         dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
 611         dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
 612                  RREG32(mmCP_CPC_STALLED_STAT1));
 613         dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
 614 }
 615
 616 /**
 617  * vi_gpu_check_soft_reset - check which blocks are busy
 618  *
 619  * @adev: amdgpu_device pointer
 620  *
 621  * Check which blocks are busy and return the relevant reset
 622  * mask to be used by vi_gpu_soft_reset().
 623  * Returns a mask of the blocks to be reset.
 624  */
 625 u32 vi_gpu_check_soft_reset(struct amdgpu_device *adev)
 626 {
 627         u32 reset_mask = 0;
 628         u32 tmp;
 629
 630         /* GRBM_STATUS */
 631         tmp = RREG32(mmGRBM_STATUS);
 632         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
 633                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
 634                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
 635                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
 636                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
 637                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
 638                 reset_mask |= AMDGPU_RESET_GFX;
 639
 640         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK))
 641                 reset_mask |= AMDGPU_RESET_CP;
 642
 643         /* GRBM_STATUS2 */
 644         tmp = RREG32(mmGRBM_STATUS2);
 645         if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
 646                 reset_mask |= AMDGPU_RESET_RLC;
 647
 648         if (tmp & (GRBM_STATUS2__CPF_BUSY_MASK |
 649                    GRBM_STATUS2__CPC_BUSY_MASK |
 650                    GRBM_STATUS2__CPG_BUSY_MASK))
 651                 reset_mask |= AMDGPU_RESET_CP;
 652
 653         /* SRBM_STATUS2 */
 654         tmp = RREG32(mmSRBM_STATUS2);
 655         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK)
 656                 reset_mask |= AMDGPU_RESET_DMA;
 657
 658         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)
 659                 reset_mask |= AMDGPU_RESET_DMA1;
 660
 661         /* SRBM_STATUS */
 662         tmp = RREG32(mmSRBM_STATUS);
 663
 664         if (tmp & SRBM_STATUS__IH_BUSY_MASK)
 665                 reset_mask |= AMDGPU_RESET_IH;
 666
 667         if (tmp & SRBM_STATUS__SEM_BUSY_MASK)
 668                 reset_mask |= AMDGPU_RESET_SEM;
 669
 670         if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
 671                 reset_mask |= AMDGPU_RESET_GRBM;
 672
 673         if (adev->asic_type != CHIP_TOPAZ) {
 674                 if (tmp & (SRBM_STATUS__UVD_RQ_PENDING_MASK |
 675                            SRBM_STATUS__UVD_BUSY_MASK))
 676                         reset_mask |= AMDGPU_RESET_UVD;
 677         }
 678
 679         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
 680                 reset_mask |= AMDGPU_RESET_VMC;
 681
 682         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 683                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK))
 684                 reset_mask |= AMDGPU_RESET_MC;
 685
 686         /* SDMA0_STATUS_REG */
 687         tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
 688         if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
 689                 reset_mask |= AMDGPU_RESET_DMA;
 690
 691         /* SDMA1_STATUS_REG */
 692         if (adev->sdma.num_instances > 1) {
 693                 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
 694                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
 695                         reset_mask |= AMDGPU_RESET_DMA1;
 696         }
 697 #if 0
 698         /* VCE_STATUS */
 699         if (adev->asic_type != CHIP_TOPAZ) {
 700                 tmp = RREG32(mmVCE_STATUS);
 701                 if (tmp & VCE_STATUS__VCPU_REPORT_RB0_BUSY_MASK)
 702                         reset_mask |= AMDGPU_RESET_VCE;
 703                 if (tmp & VCE_STATUS__VCPU_REPORT_RB1_BUSY_MASK)
 704                         reset_mask |= AMDGPU_RESET_VCE1;
 705
 706         }
 707
 708         if (adev->asic_type != CHIP_TOPAZ) {
 709                 if (amdgpu_display_is_display_hung(adev))
 710                         reset_mask |= AMDGPU_RESET_DISPLAY;
 711         }
 712 #endif
 713
 714         /* Skip MC reset as it's mostly likely not hung, just busy */
 715         if (reset_mask & AMDGPU_RESET_MC) {
 716                 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
 717                 reset_mask &= ~AMDGPU_RESET_MC;
 718         }
 719
 720         return reset_mask;
 721 }
 722
 723 /**
 724  * vi_gpu_soft_reset - soft reset GPU
 725  *
 726  * @adev: amdgpu_device pointer
 727  * @reset_mask: mask of which blocks to reset
 728  *
 729  * Soft reset the blocks specified in @reset_mask.
 730  */
 731 static void vi_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
 732 {
 733         struct amdgpu_mode_mc_save save;
 734         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
 735         u32 tmp;
 736
 737         if (reset_mask == 0)
 738                 return;
 739
 740         dev_info(adev->dev, "GPU softreset: 0x%08X\n", reset_mask);
 741
 742         vi_print_gpu_status_regs(adev);
 743         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
 744                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
 745         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
 746                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
 747
 748         /* disable CG/PG */
 749
 750         /* stop the rlc */
 751         //XXX
 752         //gfx_v8_0_rlc_stop(adev);
 753
 754         /* Disable GFX parsing/prefetching */
 755         tmp = RREG32(mmCP_ME_CNTL);
 756         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
 757         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
 758         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
 759         WREG32(mmCP_ME_CNTL, tmp);
 760
 761         /* Disable MEC parsing/prefetching */
 762         tmp = RREG32(mmCP_MEC_CNTL);
 763         tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
 764         tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
 765         WREG32(mmCP_MEC_CNTL, tmp);
 766
 767         if (reset_mask & AMDGPU_RESET_DMA) {
 768                 /* sdma0 */
 769                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
 770                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
 771                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
 772         }
 773         if (reset_mask & AMDGPU_RESET_DMA1) {
 774                 /* sdma1 */
 775                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
 776                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
 777                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
 778         }
 779
 780         gmc_v8_0_mc_stop(adev, &save);
 781         if (amdgpu_asic_wait_for_mc_idle(adev)) {
 782                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 783         }
 784
 785         if (reset_mask & (AMDGPU_RESET_GFX | AMDGPU_RESET_COMPUTE | AMDGPU_RESET_CP)) {
 786                 grbm_soft_reset =
 787                         REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
 788                 grbm_soft_reset =
 789                         REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
 790         }
 791
 792         if (reset_mask & AMDGPU_RESET_CP) {
 793                 grbm_soft_reset =
 794                         REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
 795                 srbm_soft_reset =
 796                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
 797         }
 798
 799         if (reset_mask & AMDGPU_RESET_DMA)
 800                 srbm_soft_reset =
 801                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA, 1);
 802
 803         if (reset_mask & AMDGPU_RESET_DMA1)
 804                 srbm_soft_reset =
 805                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1, 1);
 806
 807         if (reset_mask & AMDGPU_RESET_DISPLAY)
 808                 srbm_soft_reset =
 809                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_DC, 1);
 810
 811         if (reset_mask & AMDGPU_RESET_RLC)
 812                 grbm_soft_reset =
 813                         REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
 814
 815         if (reset_mask & AMDGPU_RESET_SEM)
 816                 srbm_soft_reset =
 817                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
 818
 819         if (reset_mask & AMDGPU_RESET_IH)
 820                 srbm_soft_reset =
 821                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_IH, 1);
 822
 823         if (reset_mask & AMDGPU_RESET_GRBM)
 824                 srbm_soft_reset =
 825                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
 826
 827         if (reset_mask & AMDGPU_RESET_VMC)
 828                 srbm_soft_reset =
 829                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
 830
 831         if (reset_mask & AMDGPU_RESET_UVD)
 832                 srbm_soft_reset =
 833                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
 834
 835         if (reset_mask & AMDGPU_RESET_VCE)
 836                 srbm_soft_reset =
 837                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
 838
 839         if (reset_mask & AMDGPU_RESET_VCE)
 840                 srbm_soft_reset =
 841                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
 842
 843         if (!(adev->flags & AMD_IS_APU)) {
 844                 if (reset_mask & AMDGPU_RESET_MC)
 845                 srbm_soft_reset =
 846                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
 847         }
 848
 849         if (grbm_soft_reset) {
 850                 tmp = RREG32(mmGRBM_SOFT_RESET);
 851                 tmp |= grbm_soft_reset;
 852                 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
 853                 WREG32(mmGRBM_SOFT_RESET, tmp);
 854                 tmp = RREG32(mmGRBM_SOFT_RESET);
 855
 856                 udelay(50);
 857
 858                 tmp &= ~grbm_soft_reset;
 859                 WREG32(mmGRBM_SOFT_RESET, tmp);
 860                 tmp = RREG32(mmGRBM_SOFT_RESET);
 861         }
 862
 863         if (srbm_soft_reset) {
 864                 tmp = RREG32(mmSRBM_SOFT_RESET);
 865                 tmp |= srbm_soft_reset;
 866                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 867                 WREG32(mmSRBM_SOFT_RESET, tmp);
 868                 tmp = RREG32(mmSRBM_SOFT_RESET);
 869
 870                 udelay(50);
 871
 872                 tmp &= ~srbm_soft_reset;
 873                 WREG32(mmSRBM_SOFT_RESET, tmp);
 874                 tmp = RREG32(mmSRBM_SOFT_RESET);
 875         }
 876
 877         /* Wait a little for things to settle down */
 878         udelay(50);
 879
 880         gmc_v8_0_mc_resume(adev, &save);
 881         udelay(50);
 882
 883         vi_print_gpu_status_regs(adev);
 884 }
 885
 886 static void vi_gpu_pci_config_reset(struct amdgpu_device *adev)
 887 {
 888         struct amdgpu_mode_mc_save save;
 889         u32 tmp, i;
 890
 891         dev_info(adev->dev, "GPU pci config reset\n");
 892
 893         /* disable dpm? */
 894
 895         /* disable cg/pg */
 896
 897         /* Disable GFX parsing/prefetching */
 898         tmp = RREG32(mmCP_ME_CNTL);
 899         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
 900         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
 901         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
 902         WREG32(mmCP_ME_CNTL, tmp);
 903
 904         /* Disable MEC parsing/prefetching */
 905         tmp = RREG32(mmCP_MEC_CNTL);
 906         tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
 907         tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
 908         WREG32(mmCP_MEC_CNTL, tmp);
 909
 910         /* Disable GFX parsing/prefetching */
 911         WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK |
 912                 CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
 913
 914         /* Disable MEC parsing/prefetching */
 915         WREG32(mmCP_MEC_CNTL,
 916                         CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
 917
 918         /* sdma0 */
 919         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
 920         tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
 921         WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
 922
 923         /* sdma1 */
 924         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
 925         tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
 926         WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
 927
 928         /* XXX other engines? */
 929
 930         /* halt the rlc, disable cp internal ints */
 931         //XXX
 932         //gfx_v8_0_rlc_stop(adev);
 933
 934         udelay(50);
 935
 936         /* disable mem access */
 937         gmc_v8_0_mc_stop(adev, &save);
 938         if (amdgpu_asic_wait_for_mc_idle(adev)) {
 939                 dev_warn(adev->dev, "Wait for MC idle timed out !\n");
 940         }
 941
 942         /* disable BM */
 943         pci_clear_master(adev->pdev);
 944         /* reset */
 945         amdgpu_pci_config_reset(adev);
 946
 947         udelay(100);
 948
 949         /* wait for asic to come out of reset */
 950         for (i = 0; i < adev->usec_timeout; i++) {
 951                 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff)
 952                         break;
 953                 udelay(1);
 954         }
 955
 956 }
 957
 958 static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
 959 {
 960         u32 tmp = RREG32(mmBIOS_SCRATCH_3);
 961
 962         if (hung)
 963                 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
 964         else
 965                 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
 966
 967         WREG32(mmBIOS_SCRATCH_3, tmp);
 968 }
 969
 970 /**
 971  * vi_asic_reset - soft reset GPU
 972  *
 973  * @adev: amdgpu_device pointer
 974  *
 975  * Look up which blocks are hung and attempt
 976  * to reset them.
 977  * Returns 0 for success.
 978  */
 979 static int vi_asic_reset(struct amdgpu_device *adev)
 980 {
 981         u32 reset_mask;
 982
 983         reset_mask = vi_gpu_check_soft_reset(adev);
 984
 985         if (reset_mask)
 986                 vi_set_bios_scratch_engine_hung(adev, true);
 987
 988         /* try soft reset */
 989         vi_gpu_soft_reset(adev, reset_mask);
 990
 991         reset_mask = vi_gpu_check_soft_reset(adev);
 992
 993         /* try pci config reset */
 994         if (reset_mask && amdgpu_hard_reset)
 995                 vi_gpu_pci_config_reset(adev);
 996
 997         reset_mask = vi_gpu_check_soft_reset(adev);
 998
 999         if (!reset_mask)
1000                 vi_set_bios_scratch_engine_hung(adev, false);
1001
1002         return 0;
1003 }
1004
1005 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
1006                         u32 cntl_reg, u32 status_reg)
1007 {
1008         int r, i;
1009         struct atom_clock_dividers dividers;
1010         uint32_t tmp;
1011
1012         r = amdgpu_atombios_get_clock_dividers(adev,
1013                                                COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1014                                                clock, false, &dividers);
1015         if (r)
1016                 return r;
1017
1018         tmp = RREG32_SMC(cntl_reg);
1019         tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
1020                 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
1021         tmp |= dividers.post_divider;
1022         WREG32_SMC(cntl_reg, tmp);
1023
1024         for (i = 0; i < 100; i++) {
1025                 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
1026                         break;
1027                 mdelay(10);
1028         }
1029         if (i == 100)
1030                 return -ETIMEDOUT;
1031
1032         return 0;
1033 }
1034
1035 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1036 {
1037         int r;
1038
1039         r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
1040         if (r)
1041                 return r;
1042
1043         r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
1044
1045         return 0;
1046 }
1047
1048 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
1049 {
1050         /* todo */
1051
1052         return 0;
1053 }
1054
1055 static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
1056 {
1057         if (pci_is_root_bus(adev->pdev->bus))
1058                 return;
1059
1060         if (amdgpu_pcie_gen2 == 0)
1061                 return;
1062
1063         if (adev->flags & AMD_IS_APU)
1064                 return;
1065
1066         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1067                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
1068                 return;
1069
1070         /* todo */
1071 }
1072
1073 static void vi_program_aspm(struct amdgpu_device *adev)
1074 {
1075
1076         if (amdgpu_aspm == 0)
1077                 return;
1078
1079         /* todo */
1080 }
1081
1082 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
1083                                         bool enable)
1084 {
1085         u32 tmp;
1086
1087         /* not necessary on CZ */
1088         if (adev->flags & AMD_IS_APU)
1089                 return;
1090
1091         tmp = RREG32(mmBIF_DOORBELL_APER_EN);
1092         if (enable)
1093                 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
1094         else
1095                 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
1096
1097         WREG32(mmBIF_DOORBELL_APER_EN, tmp);
1098 }
1099
1100 /* topaz has no DCE, UVD, VCE */
1101 static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
1102 {
1103         /* ORDER MATTERS! */
1104         {
1105                 .type = AMD_IP_BLOCK_TYPE_COMMON,
1106                 .major = 2,
1107                 .minor = 0,
1108                 .rev = 0,
1109                 .funcs = &vi_common_ip_funcs,
1110         },
1111         {
1112                 .type = AMD_IP_BLOCK_TYPE_GMC,
1113                 .major = 7,
1114                 .minor = 4,
1115                 .rev = 0,
1116                 .funcs = &gmc_v7_0_ip_funcs,
1117         },
1118         {
1119                 .type = AMD_IP_BLOCK_TYPE_IH,
1120                 .major = 2,
1121                 .minor = 4,
1122                 .rev = 0,
1123                 .funcs = &iceland_ih_ip_funcs,
1124         },
1125         {
1126                 .type = AMD_IP_BLOCK_TYPE_SMC,
1127                 .major = 7,
1128                 .minor = 1,
1129                 .rev = 0,
1130                 .funcs = &amdgpu_pp_ip_funcs,
1131         },
1132         {
1133                 .type = AMD_IP_BLOCK_TYPE_GFX,
1134                 .major = 8,
1135                 .minor = 0,
1136                 .rev = 0,
1137                 .funcs = &gfx_v8_0_ip_funcs,
1138         },
1139         {
1140                 .type = AMD_IP_BLOCK_TYPE_SDMA,
1141                 .major = 2,
1142                 .minor = 4,
1143                 .rev = 0,
1144                 .funcs = &sdma_v2_4_ip_funcs,
1145         },
1146 };
1147
1148 static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
1149 {
1150         /* ORDER MATTERS! */
1151         {
1152                 .type = AMD_IP_BLOCK_TYPE_COMMON,
1153                 .major = 2,
1154                 .minor = 0,
1155                 .rev = 0,
1156                 .funcs = &vi_common_ip_funcs,
1157         },
1158         {
1159                 .type = AMD_IP_BLOCK_TYPE_GMC,
1160                 .major = 8,
1161                 .minor = 0,
1162                 .rev = 0,
1163                 .funcs = &gmc_v8_0_ip_funcs,
1164         },
1165         {
1166                 .type = AMD_IP_BLOCK_TYPE_IH,
1167                 .major = 3,
1168                 .minor = 0,
1169                 .rev = 0,
1170                 .funcs = &tonga_ih_ip_funcs,
1171         },
1172         {
1173                 .type = AMD_IP_BLOCK_TYPE_SMC,
1174                 .major = 7,
1175                 .minor = 1,
1176                 .rev = 0,
1177                 .funcs = &amdgpu_pp_ip_funcs,
1178         },
1179         {
1180                 .type = AMD_IP_BLOCK_TYPE_DCE,
1181                 .major = 10,
1182                 .minor = 0,
1183                 .rev = 0,
1184                 .funcs = &dce_v10_0_ip_funcs,
1185         },
1186         {
1187                 .type = AMD_IP_BLOCK_TYPE_GFX,
1188                 .major = 8,
1189                 .minor = 0,
1190                 .rev = 0,
1191                 .funcs = &gfx_v8_0_ip_funcs,
1192         },
1193         {
1194                 .type = AMD_IP_BLOCK_TYPE_SDMA,
1195                 .major = 3,
1196                 .minor = 0,
1197                 .rev = 0,
1198                 .funcs = &sdma_v3_0_ip_funcs,
1199         },
1200         {
1201                 .type = AMD_IP_BLOCK_TYPE_UVD,
1202                 .major = 5,
1203                 .minor = 0,
1204                 .rev = 0,
1205                 .funcs = &uvd_v5_0_ip_funcs,
1206         },
1207         {
1208                 .type = AMD_IP_BLOCK_TYPE_VCE,
1209                 .major = 3,
1210                 .minor = 0,
1211                 .rev = 0,
1212                 .funcs = &vce_v3_0_ip_funcs,
1213         },
1214 };
1215
1216 static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
1217 {
1218         /* ORDER MATTERS! */
1219         {
1220                 .type = AMD_IP_BLOCK_TYPE_COMMON,
1221                 .major = 2,
1222                 .minor = 0,
1223                 .rev = 0,
1224                 .funcs = &vi_common_ip_funcs,
1225         },
1226         {
1227                 .type = AMD_IP_BLOCK_TYPE_GMC,
1228                 .major = 8,
1229                 .minor = 5,
1230                 .rev = 0,
1231                 .funcs = &gmc_v8_0_ip_funcs,
1232         },
1233         {
1234                 .type = AMD_IP_BLOCK_TYPE_IH,
1235                 .major = 3,
1236                 .minor = 0,
1237                 .rev = 0,
1238                 .funcs = &tonga_ih_ip_funcs,
1239         },
1240         {
1241                 .type = AMD_IP_BLOCK_TYPE_SMC,
1242                 .major = 7,
1243                 .minor = 1,
1244                 .rev = 0,
1245                 .funcs = &amdgpu_pp_ip_funcs,
1246         },
1247         {
1248                 .type = AMD_IP_BLOCK_TYPE_DCE,
1249                 .major = 10,
1250                 .minor = 1,
1251                 .rev = 0,
1252                 .funcs = &dce_v10_0_ip_funcs,
1253         },
1254         {
1255                 .type = AMD_IP_BLOCK_TYPE_GFX,
1256                 .major = 8,
1257                 .minor = 0,
1258                 .rev = 0,
1259                 .funcs = &gfx_v8_0_ip_funcs,
1260         },
1261         {
1262                 .type = AMD_IP_BLOCK_TYPE_SDMA,
1263                 .major = 3,
1264                 .minor = 0,
1265                 .rev = 0,
1266                 .funcs = &sdma_v3_0_ip_funcs,
1267         },
1268         {
1269                 .type = AMD_IP_BLOCK_TYPE_UVD,
1270                 .major = 6,
1271                 .minor = 0,
1272                 .rev = 0,
1273                 .funcs = &uvd_v6_0_ip_funcs,
1274         },
1275         {
1276                 .type = AMD_IP_BLOCK_TYPE_VCE,
1277                 .major = 3,
1278                 .minor = 0,
1279                 .rev = 0,
1280                 .funcs = &vce_v3_0_ip_funcs,
1281         },
1282 };
1283
1284 static const struct amdgpu_ip_block_version cz_ip_blocks[] =
1285 {
1286         /* ORDER MATTERS! */
1287         {
1288                 .type = AMD_IP_BLOCK_TYPE_COMMON,
1289                 .major = 2,
1290                 .minor = 0,
1291                 .rev = 0,
1292                 .funcs = &vi_common_ip_funcs,
1293         },
1294         {
1295                 .type = AMD_IP_BLOCK_TYPE_GMC,
1296                 .major = 8,
1297                 .minor = 0,
1298                 .rev = 0,
1299                 .funcs = &gmc_v8_0_ip_funcs,
1300         },
1301         {
1302                 .type = AMD_IP_BLOCK_TYPE_IH,
1303                 .major = 3,
1304                 .minor = 0,
1305                 .rev = 0,
1306                 .funcs = &cz_ih_ip_funcs,
1307         },
1308         {
1309                 .type = AMD_IP_BLOCK_TYPE_SMC,
1310                 .major = 8,
1311                 .minor = 0,
1312                 .rev = 0,
1313                 .funcs = &amdgpu_pp_ip_funcs
1314         },
1315         {
1316                 .type = AMD_IP_BLOCK_TYPE_DCE,
1317                 .major = 11,
1318                 .minor = 0,
1319                 .rev = 0,
1320                 .funcs = &dce_v11_0_ip_funcs,
1321         },
1322         {
1323                 .type = AMD_IP_BLOCK_TYPE_GFX,
1324                 .major = 8,
1325                 .minor = 0,
1326                 .rev = 0,
1327                 .funcs = &gfx_v8_0_ip_funcs,
1328         },
1329         {
1330                 .type = AMD_IP_BLOCK_TYPE_SDMA,
1331                 .major = 3,
1332                 .minor = 0,
1333                 .rev = 0,
1334                 .funcs = &sdma_v3_0_ip_funcs,
1335         },
1336         {
1337                 .type = AMD_IP_BLOCK_TYPE_UVD,
1338                 .major = 6,
1339                 .minor = 0,
1340                 .rev = 0,
1341                 .funcs = &uvd_v6_0_ip_funcs,
1342         },
1343         {
1344                 .type = AMD_IP_BLOCK_TYPE_VCE,
1345                 .major = 3,
1346                 .minor = 0,
1347                 .rev = 0,
1348                 .funcs = &vce_v3_0_ip_funcs,
1349         },
1350 };
1351
1352 int vi_set_ip_blocks(struct amdgpu_device *adev)
1353 {
1354         switch (adev->asic_type) {
1355         case CHIP_TOPAZ:
1356                 adev->ip_blocks = topaz_ip_blocks;
1357                 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
1358                 break;
1359         case CHIP_FIJI:
1360                 adev->ip_blocks = fiji_ip_blocks;
1361                 adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
1362                 break;
1363         case CHIP_TONGA:
1364                 adev->ip_blocks = tonga_ip_blocks;
1365                 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
1366                 break;
1367         case CHIP_CARRIZO:
1368         case CHIP_STONEY:
1369                 adev->ip_blocks = cz_ip_blocks;
1370                 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
1371                 break;
1372         default:
1373                 /* FIXME: not supported yet */
1374                 return -EINVAL;
1375         }
1376
1377         return 0;
1378 }
1379
1380 #define ATI_REV_ID_FUSE_MACRO__ADDRESS      0xC0014044
1381 #define ATI_REV_ID_FUSE_MACRO__SHIFT        9
1382 #define ATI_REV_ID_FUSE_MACRO__MASK         0x00001E00
1383
1384 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
1385 {
1386         if (adev->flags & AMD_IS_APU)
1387                 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
1388                         >> ATI_REV_ID_FUSE_MACRO__SHIFT;
1389         else
1390                 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
1391                         >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
1392 }
1393
1394 static const struct amdgpu_asic_funcs vi_asic_funcs =
1395 {
1396         .read_disabled_bios = &vi_read_disabled_bios,
1397         .read_bios_from_rom = &vi_read_bios_from_rom,
1398         .read_register = &vi_read_register,
1399         .reset = &vi_asic_reset,
1400         .set_vga_state = &vi_vga_set_state,
1401         .get_xclk = &vi_get_xclk,
1402         .set_uvd_clocks = &vi_set_uvd_clocks,
1403         .set_vce_clocks = &vi_set_vce_clocks,
1404         .get_cu_info = &gfx_v8_0_get_cu_info,
1405         /* these should be moved to their own ip modules */
1406         .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
1407         .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle,
1408 };
1409
1410 static int vi_common_early_init(void *handle)
1411 {
1412         bool smc_enabled = false;
1413         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1414
1415         if (adev->flags & AMD_IS_APU) {
1416                 adev->smc_rreg = &cz_smc_rreg;
1417                 adev->smc_wreg = &cz_smc_wreg;
1418         } else {
1419                 adev->smc_rreg = &vi_smc_rreg;
1420                 adev->smc_wreg = &vi_smc_wreg;
1421         }
1422         adev->pcie_rreg = &vi_pcie_rreg;
1423         adev->pcie_wreg = &vi_pcie_wreg;
1424         adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1425         adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1426         adev->didt_rreg = &vi_didt_rreg;
1427         adev->didt_wreg = &vi_didt_wreg;
1428
1429         adev->asic_funcs = &vi_asic_funcs;
1430
1431         if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
1432                 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
1433                 smc_enabled = true;
1434
1435         adev->rev_id = vi_get_rev_id(adev);
1436         adev->external_rev_id = 0xFF;
1437         switch (adev->asic_type) {
1438         case CHIP_TOPAZ:
1439                 adev->has_uvd = false;
1440                 adev->cg_flags = 0;
1441                 adev->pg_flags = 0;
1442                 adev->external_rev_id = 0x1;
1443                 break;
1444         case CHIP_FIJI:
1445                 adev->has_uvd = true;
1446                 adev->cg_flags = 0;
1447                 adev->pg_flags = 0;
1448                 adev->external_rev_id = adev->rev_id + 0x3c;
1449                 break;
1450         case CHIP_TONGA:
1451                 adev->has_uvd = true;
1452                 adev->cg_flags = 0;
1453                 adev->pg_flags = 0;
1454                 adev->external_rev_id = adev->rev_id + 0x14;
1455                 break;
1456         case CHIP_CARRIZO:
1457         case CHIP_STONEY:
1458                 adev->has_uvd = true;
1459                 adev->cg_flags = 0;
1460                 /* Disable UVD pg */
1461                 adev->pg_flags = /* AMDGPU_PG_SUPPORT_UVD | */AMDGPU_PG_SUPPORT_VCE;
1462                 adev->external_rev_id = adev->rev_id + 0x1;
1463                 break;
1464         default:
1465                 /* FIXME: not supported yet */
1466                 return -EINVAL;
1467         }
1468
1469         if (amdgpu_smc_load_fw && smc_enabled)
1470                 adev->firmware.smu_load = true;
1471
1472         amdgpu_get_pcie_info(adev);
1473
1474         return 0;
1475 }
1476
1477 static int vi_common_sw_init(void *handle)
1478 {
1479         return 0;
1480 }
1481
1482 static int vi_common_sw_fini(void *handle)
1483 {
1484         return 0;
1485 }
1486
1487 static int vi_common_hw_init(void *handle)
1488 {
1489         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1490
1491         /* move the golden regs per IP block */
1492         vi_init_golden_registers(adev);
1493         /* enable pcie gen2/3 link */
1494         vi_pcie_gen3_enable(adev);
1495         /* enable aspm */
1496         vi_program_aspm(adev);
1497         /* enable the doorbell aperture */
1498         vi_enable_doorbell_aperture(adev, true);
1499
1500         return 0;
1501 }
1502
1503 static int vi_common_hw_fini(void *handle)
1504 {
1505         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1506
1507         /* enable the doorbell aperture */
1508         vi_enable_doorbell_aperture(adev, false);
1509
1510         return 0;
1511 }
1512
1513 static int vi_common_suspend(void *handle)
1514 {
1515         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1516
1517         return vi_common_hw_fini(adev);
1518 }
1519
1520 static int vi_common_resume(void *handle)
1521 {
1522         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1523
1524         return vi_common_hw_init(adev);
1525 }
1526
1527 static bool vi_common_is_idle(void *handle)
1528 {
1529         return true;
1530 }
1531
1532 static int vi_common_wait_for_idle(void *handle)
1533 {
1534         return 0;
1535 }
1536
1537 static void vi_common_print_status(void *handle)
1538 {
1539         return;
1540 }
1541
1542 static int vi_common_soft_reset(void *handle)
1543 {
1544         return 0;
1545 }
1546
1547 static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1548                 bool enable)
1549 {
1550         uint32_t temp, data;
1551
1552         temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1553
1554         if (enable)
1555                 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1556                                 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1557                                 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1558         else
1559                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1560                                 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1561                                 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1562
1563         if (temp != data)
1564                 WREG32_PCIE(ixPCIE_CNTL2, data);
1565 }
1566
1567 static void fiji_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1568                 bool enable)
1569 {
1570         uint32_t temp, data;
1571
1572         temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1573
1574         if (enable)
1575                 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1576         else
1577                 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1578
1579         if (temp != data)
1580                 WREG32(mmHDP_HOST_PATH_CNTL, data);
1581 }
1582
1583 static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev,
1584                 bool enable)
1585 {
1586         uint32_t temp, data;
1587
1588         temp = data = RREG32(mmHDP_MEM_POWER_LS);
1589
1590         if (enable)
1591                 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1592         else
1593                 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1594
1595         if (temp != data)
1596                 WREG32(mmHDP_MEM_POWER_LS, data);
1597 }
1598
1599 static void fiji_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1600                 bool enable)
1601 {
1602         uint32_t temp, data;
1603
1604         temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1605
1606         if (enable)
1607                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1608                                 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1609         else
1610                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1611                                 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1612
1613         if (temp != data)
1614                 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1615 }
1616
1617 static int vi_common_set_clockgating_state(void *handle,
1618                                             enum amd_clockgating_state state)
1619 {
1620         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1621
1622         switch (adev->asic_type) {
1623         case CHIP_FIJI:
1624                 fiji_update_bif_medium_grain_light_sleep(adev,
1625                                 state == AMD_CG_STATE_GATE ? true : false);
1626                 fiji_update_hdp_medium_grain_clock_gating(adev,
1627                                 state == AMD_CG_STATE_GATE ? true : false);
1628                 fiji_update_hdp_light_sleep(adev,
1629                                 state == AMD_CG_STATE_GATE ? true : false);
1630                 fiji_update_rom_medium_grain_clock_gating(adev,
1631                                 state == AMD_CG_STATE_GATE ? true : false);
1632                 break;
1633         default:
1634                 break;
1635         }
1636         return 0;
1637 }
1638
1639 static int vi_common_set_powergating_state(void *handle,
1640                                             enum amd_powergating_state state)
1641 {
1642         return 0;
1643 }
1644
1645 const struct amd_ip_funcs vi_common_ip_funcs = {
1646         .early_init = vi_common_early_init,
1647         .late_init = NULL,
1648         .sw_init = vi_common_sw_init,
1649         .sw_fini = vi_common_sw_fini,
1650         .hw_init = vi_common_hw_init,
1651         .hw_fini = vi_common_hw_fini,
1652         .suspend = vi_common_suspend,
1653         .resume = vi_common_resume,
1654         .is_idle = vi_common_is_idle,
1655         .wait_for_idle = vi_common_wait_for_idle,
1656         .soft_reset = vi_common_soft_reset,
1657         .print_status = vi_common_print_status,
1658         .set_clockgating_state = vi_common_set_clockgating_state,
1659         .set_powergating_state = vi_common_set_powergating_state,
1660 };
1661