2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef __AMD_SHARED_H__
24 #define __AMD_SHARED_H__
26 #define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */
29 * Supported ASIC types
58 AMD_ASIC_MASK = 0x0000ffffUL,
59 AMD_FLAGS_MASK = 0xffff0000UL,
60 AMD_IS_MOBILITY = 0x00010000UL,
61 AMD_IS_APU = 0x00020000UL,
62 AMD_IS_PX = 0x00040000UL,
63 AMD_EXP_HW_SUPPORT = 0x00080000UL,
66 enum amd_ip_block_type {
67 AMD_IP_BLOCK_TYPE_COMMON,
68 AMD_IP_BLOCK_TYPE_GMC,
70 AMD_IP_BLOCK_TYPE_SMC,
71 AMD_IP_BLOCK_TYPE_PSP,
72 AMD_IP_BLOCK_TYPE_DCE,
73 AMD_IP_BLOCK_TYPE_GFX,
74 AMD_IP_BLOCK_TYPE_SDMA,
75 AMD_IP_BLOCK_TYPE_UVD,
76 AMD_IP_BLOCK_TYPE_VCE,
77 AMD_IP_BLOCK_TYPE_ACP,
78 AMD_IP_BLOCK_TYPE_GFXHUB,
79 AMD_IP_BLOCK_TYPE_MMHUB
82 enum amd_clockgating_state {
83 AMD_CG_STATE_GATE = 0,
87 enum amd_dpm_forced_level {
88 AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
89 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
90 AMD_DPM_FORCED_LEVEL_LOW = 0x4,
91 AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
92 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
93 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
94 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
95 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
96 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
99 enum amd_powergating_state {
100 AMD_PG_STATE_GATE = 0,
104 struct amd_vce_state {
116 #define AMD_MAX_VCE_LEVELS 6
119 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
120 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
121 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
122 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
123 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
124 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
127 enum amd_pp_profile_type {
129 AMD_PP_COMPUTE_PROFILE,
132 struct amd_pp_profile {
133 enum amd_pp_profile_type type;
136 uint16_t activity_threshold;
142 #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
143 #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1)
144 #define AMD_CG_SUPPORT_GFX_CGCG (1 << 2)
145 #define AMD_CG_SUPPORT_GFX_CGLS (1 << 3)
146 #define AMD_CG_SUPPORT_GFX_CGTS (1 << 4)
147 #define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
148 #define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6)
149 #define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7)
150 #define AMD_CG_SUPPORT_MC_LS (1 << 8)
151 #define AMD_CG_SUPPORT_MC_MGCG (1 << 9)
152 #define AMD_CG_SUPPORT_SDMA_LS (1 << 10)
153 #define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11)
154 #define AMD_CG_SUPPORT_BIF_LS (1 << 12)
155 #define AMD_CG_SUPPORT_UVD_MGCG (1 << 13)
156 #define AMD_CG_SUPPORT_VCE_MGCG (1 << 14)
157 #define AMD_CG_SUPPORT_HDP_LS (1 << 15)
158 #define AMD_CG_SUPPORT_HDP_MGCG (1 << 16)
159 #define AMD_CG_SUPPORT_ROM_MGCG (1 << 17)
160 #define AMD_CG_SUPPORT_DRM_LS (1 << 18)
161 #define AMD_CG_SUPPORT_BIF_MGCG (1 << 19)
162 #define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20)
163 #define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21)
164 #define AMD_CG_SUPPORT_DRM_MGCG (1 << 22)
165 #define AMD_CG_SUPPORT_DF_MGCG (1 << 23)
168 #define AMD_PG_SUPPORT_GFX_PG (1 << 0)
169 #define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
170 #define AMD_PG_SUPPORT_GFX_DMG (1 << 2)
171 #define AMD_PG_SUPPORT_UVD (1 << 3)
172 #define AMD_PG_SUPPORT_VCE (1 << 4)
173 #define AMD_PG_SUPPORT_CP (1 << 5)
174 #define AMD_PG_SUPPORT_GDS (1 << 6)
175 #define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)
176 #define AMD_PG_SUPPORT_SDMA (1 << 8)
177 #define AMD_PG_SUPPORT_ACP (1 << 9)
178 #define AMD_PG_SUPPORT_SAMU (1 << 10)
179 #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11)
180 #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
182 enum amd_pm_state_type {
183 /* not used for dpm */
184 POWER_STATE_TYPE_DEFAULT,
185 POWER_STATE_TYPE_POWERSAVE,
186 /* user selectable states */
187 POWER_STATE_TYPE_BATTERY,
188 POWER_STATE_TYPE_BALANCED,
189 POWER_STATE_TYPE_PERFORMANCE,
190 /* internal states */
191 POWER_STATE_TYPE_INTERNAL_UVD,
192 POWER_STATE_TYPE_INTERNAL_UVD_SD,
193 POWER_STATE_TYPE_INTERNAL_UVD_HD,
194 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
195 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
196 POWER_STATE_TYPE_INTERNAL_BOOT,
197 POWER_STATE_TYPE_INTERNAL_THERMAL,
198 POWER_STATE_TYPE_INTERNAL_ACPI,
199 POWER_STATE_TYPE_INTERNAL_ULV,
200 POWER_STATE_TYPE_INTERNAL_3DPERF,
203 struct amd_ip_funcs {
204 /* Name of IP block */
206 /* sets up early driver state (pre sw_init), does not configure hw - Optional */
207 int (*early_init)(void *handle);
208 /* sets up late driver/hw state (post hw_init) - Optional */
209 int (*late_init)(void *handle);
210 /* sets up driver state, does not configure hw */
211 int (*sw_init)(void *handle);
212 /* tears down driver state, does not configure hw */
213 int (*sw_fini)(void *handle);
214 /* sets up the hw state */
215 int (*hw_init)(void *handle);
216 /* tears down the hw state */
217 int (*hw_fini)(void *handle);
218 void (*late_fini)(void *handle);
219 /* handles IP specific hw/sw changes for suspend */
220 int (*suspend)(void *handle);
221 /* handles IP specific hw/sw changes for resume */
222 int (*resume)(void *handle);
223 /* returns current IP block idle status */
224 bool (*is_idle)(void *handle);
226 int (*wait_for_idle)(void *handle);
227 /* check soft reset the IP block */
228 bool (*check_soft_reset)(void *handle);
229 /* pre soft reset the IP block */
230 int (*pre_soft_reset)(void *handle);
231 /* soft reset the IP block */
232 int (*soft_reset)(void *handle);
233 /* post soft reset the IP block */
234 int (*post_soft_reset)(void *handle);
235 /* enable/disable cg for the IP block */
236 int (*set_clockgating_state)(void *handle,
237 enum amd_clockgating_state state);
238 /* enable/disable pg for the IP block */
239 int (*set_powergating_state)(void *handle,
240 enum amd_powergating_state state);
241 /* get current clockgating status */
242 void (*get_clockgating_state)(void *handle, u32 *flags);
245 #endif /* __AMD_SHARED_H__ */