2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef __AMD_SHARED_H__
24 #define __AMD_SHARED_H__
26 #define AMD_MAX_USEC_TIMEOUT 100000 /* 100 ms */
29 * Supported GPU families (aligned with amdgpu_drm.h)
31 #define AMD_FAMILY_UNKNOWN 0
32 #define AMD_FAMILY_CI 120 /* Bonaire, Hawaii */
33 #define AMD_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
34 #define AMD_FAMILY_VI 130 /* Iceland, Tonga */
35 #define AMD_FAMILY_CZ 135 /* Carrizo */
38 * Supported ASIC types
57 AMD_ASIC_MASK = 0x0000ffffUL,
58 AMD_FLAGS_MASK = 0xffff0000UL,
59 AMD_IS_MOBILITY = 0x00010000UL,
60 AMD_IS_APU = 0x00020000UL,
61 AMD_IS_PX = 0x00040000UL,
62 AMD_EXP_HW_SUPPORT = 0x00080000UL,
65 enum amd_ip_block_type {
66 AMD_IP_BLOCK_TYPE_COMMON,
67 AMD_IP_BLOCK_TYPE_GMC,
69 AMD_IP_BLOCK_TYPE_SMC,
70 AMD_IP_BLOCK_TYPE_DCE,
71 AMD_IP_BLOCK_TYPE_GFX,
72 AMD_IP_BLOCK_TYPE_SDMA,
73 AMD_IP_BLOCK_TYPE_UVD,
74 AMD_IP_BLOCK_TYPE_VCE,
77 enum amd_clockgating_state {
78 AMD_CG_STATE_GATE = 0,
82 enum amd_powergating_state {
83 AMD_PG_STATE_GATE = 0,
88 /* sets up early driver state (pre sw_init), does not configure hw - Optional */
89 int (*early_init)(void *handle);
90 /* sets up late driver/hw state (post hw_init) - Optional */
91 int (*late_init)(void *handle);
92 /* sets up driver state, does not configure hw */
93 int (*sw_init)(void *handle);
94 /* tears down driver state, does not configure hw */
95 int (*sw_fini)(void *handle);
96 /* sets up the hw state */
97 int (*hw_init)(void *handle);
98 /* tears down the hw state */
99 int (*hw_fini)(void *handle);
100 /* handles IP specific hw/sw changes for suspend */
101 int (*suspend)(void *handle);
102 /* handles IP specific hw/sw changes for resume */
103 int (*resume)(void *handle);
104 /* returns current IP block idle status */
105 bool (*is_idle)(void *handle);
107 int (*wait_for_idle)(void *handle);
108 /* soft reset the IP block */
109 int (*soft_reset)(void *handle);
110 /* dump the IP block status registers */
111 void (*print_status)(void *handle);
112 /* enable/disable cg for the IP block */
113 int (*set_clockgating_state)(void *handle,
114 enum amd_clockgating_state state);
115 /* enable/disable pg for the IP block */
116 int (*set_powergating_state)(void *handle,
117 enum amd_powergating_state state);
120 #endif /* __AMD_SHARED_H__ */