2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "amd_shared.h"
30 * enum cgs_gpu_mem_type - GPU memory types
32 enum cgs_gpu_mem_type {
33 CGS_GPU_MEM_TYPE__VISIBLE_FB,
34 CGS_GPU_MEM_TYPE__INVISIBLE_FB,
35 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
36 CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB,
37 CGS_GPU_MEM_TYPE__GART_CACHEABLE,
38 CGS_GPU_MEM_TYPE__GART_WRITECOMBINE
42 * enum cgs_ind_reg - Indirect register spaces
50 CGS_IND_REG__AUDIO_ENDPT
54 * enum cgs_clock - Clocks controlled by the SMU
68 * enum cgs_engine - Engines that can be statically power-gated
82 * enum cgs_voltage_planes - Voltage planes for external camera HW
84 enum cgs_voltage_planes {
85 CGS_VOLTAGE_PLANE__SENSOR0,
86 CGS_VOLTAGE_PLANE__SENSOR1,
91 * enum cgs_ucode_id - Firmware types for different IPs
101 CGS_UCODE_ID_CP_MEC_JT1,
102 CGS_UCODE_ID_CP_MEC_JT2,
103 CGS_UCODE_ID_GMCON_RENG,
105 CGS_UCODE_ID_MAXIMUM,
108 enum cgs_system_info_id {
109 CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1,
110 CGS_SYSTEM_INFO_ID_MAXIMUM,
113 struct cgs_system_info {
120 uint64_t padding[13];
124 * struct cgs_clock_limits - Clock limits
126 * Clocks are specified in 10KHz units.
128 struct cgs_clock_limits {
129 unsigned min; /**< Minimum supported frequency */
130 unsigned max; /**< Maxumim supported frequency */
131 unsigned sustainable; /**< Thermally sustainable frequency */
135 * struct cgs_firmware_info - Firmware information
137 struct cgs_firmware_info {
139 uint16_t feature_version;
145 struct cgs_mode_info {
146 uint32_t refresh_rate;
148 uint32_t vblank_time_us;
151 struct cgs_display_info {
152 uint32_t display_count;
153 uint32_t active_display_mask;
154 struct cgs_mode_info *mode_info;
157 typedef unsigned long cgs_handle_t;
159 #define CGS_ACPI_METHOD_ATCS 0x53435441
160 #define CGS_ACPI_METHOD_ATIF 0x46495441
161 #define CGS_ACPI_METHOD_ATPX 0x58505441
162 #define CGS_ACPI_FIELD_METHOD_NAME 0x00000001
163 #define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT 0x00000002
164 #define CGS_ACPI_MAX_BUFFER_SIZE 256
165 #define CGS_ACPI_TYPE_ANY 0x00
166 #define CGS_ACPI_TYPE_INTEGER 0x01
167 #define CGS_ACPI_TYPE_STRING 0x02
168 #define CGS_ACPI_TYPE_BUFFER 0x03
169 #define CGS_ACPI_TYPE_PACKAGE 0x04
171 struct cgs_acpi_method_argument {
173 uint32_t method_length;
174 uint32_t data_length;
181 struct cgs_acpi_method_info {
184 uint32_t input_count;
186 struct cgs_acpi_method_argument *pinput_argument;
187 uint32_t output_count;
188 struct cgs_acpi_method_argument *poutput_argument;
193 * cgs_gpu_mem_info() - Return information about memory heaps
194 * @cgs_device: opaque device handle
196 * @mc_start: Start MC address of the heap (output)
197 * @mc_size: MC address space size (output)
198 * @mem_size: maximum amount of memory available for allocation (output)
200 * This function returns information about memory heaps. The type
201 * parameter is used to select the memory heap. The mc_start and
202 * mc_size for GART heaps may be bigger than the memory available for
205 * mc_start and mc_size are undefined for non-contiguous FB memory
206 * types, since buffers allocated with these types may or may not be
209 * Return: 0 on success, -errno otherwise
211 typedef int (*cgs_gpu_mem_info_t)(void *cgs_device, enum cgs_gpu_mem_type type,
212 uint64_t *mc_start, uint64_t *mc_size,
216 * cgs_gmap_kmem() - map kernel memory to GART aperture
217 * @cgs_device: opaque device handle
218 * @kmem: pointer to kernel memory
220 * @min_offset: minimum offset from start of GART aperture
221 * @max_offset: maximum offset from start of GART aperture
222 * @kmem_handle: kernel memory handle (output)
223 * @mcaddr: MC address (output)
225 * Return: 0 on success, -errno otherwise
227 typedef int (*cgs_gmap_kmem_t)(void *cgs_device, void *kmem, uint64_t size,
228 uint64_t min_offset, uint64_t max_offset,
229 cgs_handle_t *kmem_handle, uint64_t *mcaddr);
232 * cgs_gunmap_kmem() - unmap kernel memory
233 * @cgs_device: opaque device handle
234 * @kmem_handle: kernel memory handle returned by gmap_kmem
236 * Return: 0 on success, -errno otherwise
238 typedef int (*cgs_gunmap_kmem_t)(void *cgs_device, cgs_handle_t kmem_handle);
241 * cgs_alloc_gpu_mem() - Allocate GPU memory
242 * @cgs_device: opaque device handle
244 * @size: size in bytes
245 * @align: alignment in bytes
246 * @min_offset: minimum offset from start of heap
247 * @max_offset: maximum offset from start of heap
248 * @handle: memory handle (output)
250 * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous
251 * memory allocation. This guarantees that the MC address returned by
252 * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous
253 * FB memory types may be GART mapped depending on memory
254 * fragmentation and memory allocator policies.
256 * If min/max_offset are non-0, the allocation will be forced to
257 * reside between these offsets in its respective memory heap. The
258 * base address that the offset relates to, depends on the memory
261 * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address
262 * - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address
263 * - others: undefined, don't use with max_offset
265 * Return: 0 on success, -errno otherwise
267 typedef int (*cgs_alloc_gpu_mem_t)(void *cgs_device, enum cgs_gpu_mem_type type,
268 uint64_t size, uint64_t align,
269 uint64_t min_offset, uint64_t max_offset,
270 cgs_handle_t *handle);
273 * cgs_free_gpu_mem() - Free GPU memory
274 * @cgs_device: opaque device handle
275 * @handle: memory handle returned by alloc or import
277 * Return: 0 on success, -errno otherwise
279 typedef int (*cgs_free_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
282 * cgs_gmap_gpu_mem() - GPU-map GPU memory
283 * @cgs_device: opaque device handle
284 * @handle: memory handle returned by alloc or import
285 * @mcaddr: MC address (output)
287 * Ensures that a buffer is GPU accessible and returns its MC address.
289 * Return: 0 on success, -errno otherwise
291 typedef int (*cgs_gmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle,
295 * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory
296 * @cgs_device: opaque device handle
297 * @handle: memory handle returned by alloc or import
299 * Allows the buffer to be migrated while it's not used by the GPU.
301 * Return: 0 on success, -errno otherwise
303 typedef int (*cgs_gunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
306 * cgs_kmap_gpu_mem() - Kernel-map GPU memory
308 * @cgs_device: opaque device handle
309 * @handle: memory handle returned by alloc or import
310 * @map: Kernel virtual address the memory was mapped to (output)
312 * Return: 0 on success, -errno otherwise
314 typedef int (*cgs_kmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle,
318 * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory
319 * @cgs_device: opaque device handle
320 * @handle: memory handle returned by alloc or import
322 * Return: 0 on success, -errno otherwise
324 typedef int (*cgs_kunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
327 * cgs_read_register() - Read an MMIO register
328 * @cgs_device: opaque device handle
329 * @offset: register offset
331 * Return: register value
333 typedef uint32_t (*cgs_read_register_t)(void *cgs_device, unsigned offset);
336 * cgs_write_register() - Write an MMIO register
337 * @cgs_device: opaque device handle
338 * @offset: register offset
339 * @value: register value
341 typedef void (*cgs_write_register_t)(void *cgs_device, unsigned offset,
345 * cgs_read_ind_register() - Read an indirect register
346 * @cgs_device: opaque device handle
347 * @offset: register offset
349 * Return: register value
351 typedef uint32_t (*cgs_read_ind_register_t)(void *cgs_device, enum cgs_ind_reg space,
355 * cgs_write_ind_register() - Write an indirect register
356 * @cgs_device: opaque device handle
357 * @offset: register offset
358 * @value: register value
360 typedef void (*cgs_write_ind_register_t)(void *cgs_device, enum cgs_ind_reg space,
361 unsigned index, uint32_t value);
364 * cgs_read_pci_config_byte() - Read byte from PCI configuration space
365 * @cgs_device: opaque device handle
370 typedef uint8_t (*cgs_read_pci_config_byte_t)(void *cgs_device, unsigned addr);
373 * cgs_read_pci_config_word() - Read word from PCI configuration space
374 * @cgs_device: opaque device handle
375 * @addr: address, must be word-aligned
379 typedef uint16_t (*cgs_read_pci_config_word_t)(void *cgs_device, unsigned addr);
382 * cgs_read_pci_config_dword() - Read dword from PCI configuration space
383 * @cgs_device: opaque device handle
384 * @addr: address, must be dword-aligned
388 typedef uint32_t (*cgs_read_pci_config_dword_t)(void *cgs_device,
392 * cgs_write_pci_config_byte() - Write byte to PCI configuration space
393 * @cgs_device: opaque device handle
395 * @value: value to write
397 typedef void (*cgs_write_pci_config_byte_t)(void *cgs_device, unsigned addr,
401 * cgs_write_pci_config_word() - Write byte to PCI configuration space
402 * @cgs_device: opaque device handle
403 * @addr: address, must be word-aligned
404 * @value: value to write
406 typedef void (*cgs_write_pci_config_word_t)(void *cgs_device, unsigned addr,
410 * cgs_write_pci_config_dword() - Write byte to PCI configuration space
411 * @cgs_device: opaque device handle
412 * @addr: address, must be dword-aligned
413 * @value: value to write
415 typedef void (*cgs_write_pci_config_dword_t)(void *cgs_device, unsigned addr,
419 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
420 * @cgs_device: opaque device handle
421 * @table: data table index
422 * @size: size of the table (output, may be NULL)
423 * @frev: table format revision (output, may be NULL)
424 * @crev: table content revision (output, may be NULL)
426 * Return: Pointer to start of the table, or NULL on failure
428 typedef const void *(*cgs_atom_get_data_table_t)(
429 void *cgs_device, unsigned table,
430 uint16_t *size, uint8_t *frev, uint8_t *crev);
433 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
434 * @cgs_device: opaque device handle
435 * @table: data table index
436 * @frev: table format revision (output, may be NULL)
437 * @crev: table content revision (output, may be NULL)
439 * Return: 0 on success, -errno otherwise
441 typedef int (*cgs_atom_get_cmd_table_revs_t)(void *cgs_device, unsigned table,
442 uint8_t *frev, uint8_t *crev);
445 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
446 * @cgs_device: opaque device handle
447 * @table: command table index
450 * Return: 0 on success, -errno otherwise
452 typedef int (*cgs_atom_exec_cmd_table_t)(void *cgs_device,
453 unsigned table, void *args);
456 * cgs_create_pm_request() - Create a power management request
457 * @cgs_device: opaque device handle
458 * @request: handle of created PM request (output)
460 * Return: 0 on success, -errno otherwise
462 typedef int (*cgs_create_pm_request_t)(void *cgs_device, cgs_handle_t *request);
465 * cgs_destroy_pm_request() - Destroy a power management request
466 * @cgs_device: opaque device handle
467 * @request: handle of created PM request
469 * Return: 0 on success, -errno otherwise
471 typedef int (*cgs_destroy_pm_request_t)(void *cgs_device, cgs_handle_t request);
474 * cgs_set_pm_request() - Activate or deactiveate a PM request
475 * @cgs_device: opaque device handle
476 * @request: PM request handle
477 * @active: 0 = deactivate, non-0 = activate
479 * While a PM request is active, its minimum clock requests are taken
480 * into account as the requested engines are powered up. When the
481 * request is inactive, the engines may be powered down and clocks may
482 * be lower, depending on other PM requests by other driver
485 * Return: 0 on success, -errno otherwise
487 typedef int (*cgs_set_pm_request_t)(void *cgs_device, cgs_handle_t request,
491 * cgs_pm_request_clock() - Request a minimum frequency for a specific clock
492 * @cgs_device: opaque device handle
493 * @request: PM request handle
494 * @clock: which clock?
495 * @freq: requested min. frequency in 10KHz units (0 to clear request)
497 * Return: 0 on success, -errno otherwise
499 typedef int (*cgs_pm_request_clock_t)(void *cgs_device, cgs_handle_t request,
500 enum cgs_clock clock, unsigned freq);
503 * cgs_pm_request_engine() - Request an engine to be powered up
504 * @cgs_device: opaque device handle
505 * @request: PM request handle
506 * @engine: which engine?
507 * @powered: 0 = powered down, non-0 = powered up
509 * Return: 0 on success, -errno otherwise
511 typedef int (*cgs_pm_request_engine_t)(void *cgs_device, cgs_handle_t request,
512 enum cgs_engine engine, int powered);
515 * cgs_pm_query_clock_limits() - Query clock frequency limits
516 * @cgs_device: opaque device handle
517 * @clock: which clock?
518 * @limits: clock limits
520 * Return: 0 on success, -errno otherwise
522 typedef int (*cgs_pm_query_clock_limits_t)(void *cgs_device,
523 enum cgs_clock clock,
524 struct cgs_clock_limits *limits);
527 * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes
528 * @cgs_device: opaque device handle
529 * @mask: bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...)
530 * @voltages: pointer to array of voltage values in 1mV units
532 * Return: 0 on success, -errno otherwise
534 typedef int (*cgs_set_camera_voltages_t)(void *cgs_device, uint32_t mask,
535 const uint32_t *voltages);
537 * cgs_get_firmware_info - Get the firmware information from core driver
538 * @cgs_device: opaque device handle
539 * @type: the firmware type
540 * @info: returend firmware information
542 * Return: 0 on success, -errno otherwise
544 typedef int (*cgs_get_firmware_info)(void *cgs_device,
545 enum cgs_ucode_id type,
546 struct cgs_firmware_info *info);
548 typedef int(*cgs_set_powergating_state)(void *cgs_device,
549 enum amd_ip_block_type block_type,
550 enum amd_powergating_state state);
552 typedef int(*cgs_set_clockgating_state)(void *cgs_device,
553 enum amd_ip_block_type block_type,
554 enum amd_clockgating_state state);
556 typedef int(*cgs_get_active_displays_info)(
558 struct cgs_display_info *info);
560 typedef int (*cgs_call_acpi_method)(void *cgs_device,
561 uint32_t acpi_method,
562 uint32_t acpi_function,
563 void *pinput, void *poutput,
564 uint32_t output_count,
566 uint32_t output_size);
568 typedef int (*cgs_query_system_info)(void *cgs_device,
569 struct cgs_system_info *sys_info);
572 /* memory management calls (similar to KFD interface) */
573 cgs_gpu_mem_info_t gpu_mem_info;
574 cgs_gmap_kmem_t gmap_kmem;
575 cgs_gunmap_kmem_t gunmap_kmem;
576 cgs_alloc_gpu_mem_t alloc_gpu_mem;
577 cgs_free_gpu_mem_t free_gpu_mem;
578 cgs_gmap_gpu_mem_t gmap_gpu_mem;
579 cgs_gunmap_gpu_mem_t gunmap_gpu_mem;
580 cgs_kmap_gpu_mem_t kmap_gpu_mem;
581 cgs_kunmap_gpu_mem_t kunmap_gpu_mem;
583 cgs_read_register_t read_register;
584 cgs_write_register_t write_register;
585 cgs_read_ind_register_t read_ind_register;
586 cgs_write_ind_register_t write_ind_register;
587 /* PCI configuration space access */
588 cgs_read_pci_config_byte_t read_pci_config_byte;
589 cgs_read_pci_config_word_t read_pci_config_word;
590 cgs_read_pci_config_dword_t read_pci_config_dword;
591 cgs_write_pci_config_byte_t write_pci_config_byte;
592 cgs_write_pci_config_word_t write_pci_config_word;
593 cgs_write_pci_config_dword_t write_pci_config_dword;
595 cgs_atom_get_data_table_t atom_get_data_table;
596 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
597 cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
598 /* Power management */
599 cgs_create_pm_request_t create_pm_request;
600 cgs_destroy_pm_request_t destroy_pm_request;
601 cgs_set_pm_request_t set_pm_request;
602 cgs_pm_request_clock_t pm_request_clock;
603 cgs_pm_request_engine_t pm_request_engine;
604 cgs_pm_query_clock_limits_t pm_query_clock_limits;
605 cgs_set_camera_voltages_t set_camera_voltages;
607 cgs_get_firmware_info get_firmware_info;
609 cgs_set_powergating_state set_powergating_state;
610 cgs_set_clockgating_state set_clockgating_state;
611 /* display manager */
612 cgs_get_active_displays_info get_active_displays_info;
614 cgs_call_acpi_method call_acpi_method;
615 /* get system info */
616 cgs_query_system_info query_system_info;
619 struct cgs_os_ops; /* To be define in OS-specific CGS header */
623 const struct cgs_ops *ops;
624 const struct cgs_os_ops *os_ops;
625 /* to be embedded at the start of driver private structure */
628 /* Convenience macros that make CGS indirect function calls look like
629 * normal function calls */
630 #define CGS_CALL(func,dev,...) \
631 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
632 #define CGS_OS_CALL(func,dev,...) \
633 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
635 #define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size) \
636 CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size)
637 #define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \
638 CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr)
639 #define cgs_gunmap_kmem(dev,kmem_handle) \
640 CGS_CALL(gunmap_kmem,dev,keme_handle)
641 #define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \
642 CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle)
643 #define cgs_free_gpu_mem(dev,handle) \
644 CGS_CALL(free_gpu_mem,dev,handle)
645 #define cgs_gmap_gpu_mem(dev,handle,mcaddr) \
646 CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr)
647 #define cgs_gunmap_gpu_mem(dev,handle) \
648 CGS_CALL(gunmap_gpu_mem,dev,handle)
649 #define cgs_kmap_gpu_mem(dev,handle,map) \
650 CGS_CALL(kmap_gpu_mem,dev,handle,map)
651 #define cgs_kunmap_gpu_mem(dev,handle) \
652 CGS_CALL(kunmap_gpu_mem,dev,handle)
654 #define cgs_read_register(dev,offset) \
655 CGS_CALL(read_register,dev,offset)
656 #define cgs_write_register(dev,offset,value) \
657 CGS_CALL(write_register,dev,offset,value)
658 #define cgs_read_ind_register(dev,space,index) \
659 CGS_CALL(read_ind_register,dev,space,index)
660 #define cgs_write_ind_register(dev,space,index,value) \
661 CGS_CALL(write_ind_register,dev,space,index,value)
663 #define cgs_read_pci_config_byte(dev,addr) \
664 CGS_CALL(read_pci_config_byte,dev,addr)
665 #define cgs_read_pci_config_word(dev,addr) \
666 CGS_CALL(read_pci_config_word,dev,addr)
667 #define cgs_read_pci_config_dword(dev,addr) \
668 CGS_CALL(read_pci_config_dword,dev,addr)
669 #define cgs_write_pci_config_byte(dev,addr,value) \
670 CGS_CALL(write_pci_config_byte,dev,addr,value)
671 #define cgs_write_pci_config_word(dev,addr,value) \
672 CGS_CALL(write_pci_config_word,dev,addr,value)
673 #define cgs_write_pci_config_dword(dev,addr,value) \
674 CGS_CALL(write_pci_config_dword,dev,addr,value)
676 #define cgs_atom_get_data_table(dev,table,size,frev,crev) \
677 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
678 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \
679 CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
680 #define cgs_atom_exec_cmd_table(dev,table,args) \
681 CGS_CALL(atom_exec_cmd_table,dev,table,args)
683 #define cgs_create_pm_request(dev,request) \
684 CGS_CALL(create_pm_request,dev,request)
685 #define cgs_destroy_pm_request(dev,request) \
686 CGS_CALL(destroy_pm_request,dev,request)
687 #define cgs_set_pm_request(dev,request,active) \
688 CGS_CALL(set_pm_request,dev,request,active)
689 #define cgs_pm_request_clock(dev,request,clock,freq) \
690 CGS_CALL(pm_request_clock,dev,request,clock,freq)
691 #define cgs_pm_request_engine(dev,request,engine,powered) \
692 CGS_CALL(pm_request_engine,dev,request,engine,powered)
693 #define cgs_pm_query_clock_limits(dev,clock,limits) \
694 CGS_CALL(pm_query_clock_limits,dev,clock,limits)
695 #define cgs_set_camera_voltages(dev,mask,voltages) \
696 CGS_CALL(set_camera_voltages,dev,mask,voltages)
697 #define cgs_get_firmware_info(dev, type, info) \
698 CGS_CALL(get_firmware_info, dev, type, info)
699 #define cgs_set_powergating_state(dev, block_type, state) \
700 CGS_CALL(set_powergating_state, dev, block_type, state)
701 #define cgs_set_clockgating_state(dev, block_type, state) \
702 CGS_CALL(set_clockgating_state, dev, block_type, state)
703 #define cgs_get_active_displays_info(dev, info) \
704 CGS_CALL(get_active_displays_info, dev, info)
705 #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \
706 CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
707 #define cgs_query_system_info(dev, sys_info) \
708 CGS_CALL(query_system_info, dev, sys_info)
710 #endif /* _CGS_COMMON_H */