drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "pp_debug.h"
  24 #include <linux/errno.h>
  25 #include "hwmgr.h"
  26 #include "hardwaremanager.h"
  27 #include "power_state.h"
  28
  29 #define PHM_FUNC_CHECK(hw) \
  30         do {                                                    \
  31                 if ((hw) == NULL || (hw)->hwmgr_func == NULL)   \
  32                         return -EINVAL;                         \
  33         } while (0)
  34
  35 bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
  36 {
  37         return hwmgr->block_hw_access;
  38 }
  39
  40 int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
  41 {
  42         hwmgr->block_hw_access = block;
  43         return 0;
  44 }
  45
  46 int phm_setup_asic(struct pp_hwmgr *hwmgr)
  47 {
  48         PHM_FUNC_CHECK(hwmgr);
  49
  50         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
  51                 PHM_PlatformCaps_TablelessHardwareInterface)) {
  52                 if (NULL != hwmgr->hwmgr_func->asic_setup)
  53                         return hwmgr->hwmgr_func->asic_setup(hwmgr);
  54         } else {
  55                 return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
  56                                           NULL, NULL);
  57         }
  58
  59         return 0;
  60 }
  61
  62 int phm_power_down_asic(struct pp_hwmgr *hwmgr)
  63 {
  64         PHM_FUNC_CHECK(hwmgr);
  65
  66         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
  67                 PHM_PlatformCaps_TablelessHardwareInterface)) {
  68                 if (NULL != hwmgr->hwmgr_func->power_off_asic)
  69                         return hwmgr->hwmgr_func->power_off_asic(hwmgr);
  70         } else {
  71                 return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic),
  72                                           NULL, NULL);
  73         }
  74
  75         return 0;
  76 }
  77
  78 int phm_set_power_state(struct pp_hwmgr *hwmgr,
  79                     const struct pp_hw_power_state *pcurrent_state,
  80                     const struct pp_hw_power_state *pnew_power_state)
  81 {
  82         struct phm_set_power_state_input states;
  83
  84         PHM_FUNC_CHECK(hwmgr);
  85
  86         states.pcurrent_state = pcurrent_state;
  87         states.pnew_state = pnew_power_state;
  88
  89         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
  90                 PHM_PlatformCaps_TablelessHardwareInterface)) {
  91                 if (NULL != hwmgr->hwmgr_func->power_state_set)
  92                         return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
  93         } else {
  94                 return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
  95         }
  96
  97         return 0;
  98 }
  99
 100 int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
 101 {
 102         int ret = 1;
 103         bool enabled;
 104         PHM_FUNC_CHECK(hwmgr);
 105
 106         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 107                 PHM_PlatformCaps_TablelessHardwareInterface)) {
 108                 if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
 109                         ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
 110         } else {
 111                 ret = phm_dispatch_table(hwmgr,
 112                                 &(hwmgr->enable_dynamic_state_management),
 113                                 NULL, NULL);
 114         }
 115
 116         enabled = ret == 0;
 117
 118         cgs_notify_dpm_enabled(hwmgr->device, enabled);
 119
 120         return ret;
 121 }
 122
 123 int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
 124 {
 125         int ret = -1;
 126         bool enabled;
 127
 128         PHM_FUNC_CHECK(hwmgr);
 129
 130         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 131                 PHM_PlatformCaps_TablelessHardwareInterface)) {
 132                 if (hwmgr->hwmgr_func->dynamic_state_management_disable)
 133                         ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
 134         } else {
 135                 ret = phm_dispatch_table(hwmgr,
 136                                 &(hwmgr->disable_dynamic_state_management),
 137                                 NULL, NULL);
 138         }
 139
 140         enabled = ret == 0 ? false : true;
 141
 142         cgs_notify_dpm_enabled(hwmgr->device, enabled);
 143
 144         return ret;
 145 }
 146
 147 int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
 148 {
 149         int ret = 0;
 150
 151         PHM_FUNC_CHECK(hwmgr);
 152
 153         if (hwmgr->hwmgr_func->force_dpm_level != NULL) {
 154                 ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
 155                 if (ret)
 156                         return ret;
 157
 158                 if (hwmgr->hwmgr_func->set_power_profile_state) {
 159                         if (hwmgr->current_power_profile == AMD_PP_GFX_PROFILE)
 160                                 ret = hwmgr->hwmgr_func->set_power_profile_state(
 161                                                 hwmgr,
 162                                                 &hwmgr->gfx_power_profile);
 163                         else if (hwmgr->current_power_profile == AMD_PP_COMPUTE_PROFILE)
 164                                 ret = hwmgr->hwmgr_func->set_power_profile_state(
 165                                                 hwmgr,
 166                                                 &hwmgr->compute_power_profile);
 167                 }
 168         }
 169
 170         return ret;
 171 }
 172
 173 int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 174                                    struct pp_power_state *adjusted_ps,
 175                              const struct pp_power_state *current_ps)
 176 {
 177         PHM_FUNC_CHECK(hwmgr);
 178
 179         if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
 180                 return hwmgr->hwmgr_func->apply_state_adjust_rules(
 181                                                                         hwmgr,
 182                                                                  adjusted_ps,
 183                                                                  current_ps);
 184         return 0;
 185 }
 186
 187 int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
 188 {
 189         PHM_FUNC_CHECK(hwmgr);
 190
 191         if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
 192                 return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
 193         return 0;
 194 }
 195
 196 int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
 197 {
 198         PHM_FUNC_CHECK(hwmgr);
 199
 200         if (hwmgr->hwmgr_func->powergate_uvd != NULL)
 201                 return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
 202         return 0;
 203 }
 204
 205 int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
 206 {
 207         PHM_FUNC_CHECK(hwmgr);
 208
 209         if (hwmgr->hwmgr_func->powergate_vce != NULL)
 210                 return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
 211         return 0;
 212 }
 213
 214 int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
 215 {
 216         PHM_FUNC_CHECK(hwmgr);
 217
 218         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 219                 PHM_PlatformCaps_TablelessHardwareInterface)) {
 220                 if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
 221                         return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
 222         } else {
 223                 return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
 224         }
 225         return 0;
 226 }
 227
 228 int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr)
 229 {
 230         PHM_FUNC_CHECK(hwmgr);
 231
 232         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 233                 PHM_PlatformCaps_TablelessHardwareInterface)) {
 234                 if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
 235                         return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
 236         }
 237         return 0;
 238 }
 239
 240
 241 int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
 242 {
 243         PHM_FUNC_CHECK(hwmgr);
 244
 245         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 246                                  PHM_PlatformCaps_TablelessHardwareInterface)) {
 247                 if (NULL != hwmgr->hwmgr_func->display_config_changed)
 248                         hwmgr->hwmgr_func->display_config_changed(hwmgr);
 249         } else
 250                 return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
 251         return 0;
 252 }
 253
 254 int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
 255 {
 256         PHM_FUNC_CHECK(hwmgr);
 257
 258         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 259                                  PHM_PlatformCaps_TablelessHardwareInterface))
 260                 if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
 261                         hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
 262
 263         return 0;
 264 }
 265
 266 int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
 267 {
 268         PHM_FUNC_CHECK(hwmgr);
 269
 270         if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
 271                 return -EINVAL;
 272
 273         return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
 274 }
 275
 276 int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
 277 {
 278         PHM_FUNC_CHECK(hwmgr);
 279
 280         if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
 281                 return -EINVAL;
 282
 283         return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
 284 }
 285
 286 /**
 287 * Initializes the thermal controller subsystem.
 288 *
 289 * @param    pHwMgr  the address of the powerplay hardware manager.
 290 * @param    pTemperatureRange the address of the structure holding the temperature range.
 291 * @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
 292 */
 293 int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range)
 294 {
 295         return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
 296 }
 297
 298
 299 bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
 300 {
 301         PHM_FUNC_CHECK(hwmgr);
 302
 303         if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
 304                 return false;
 305
 306         return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
 307 }
 308
 309
 310 int phm_check_states_equal(struct pp_hwmgr *hwmgr,
 311                                  const struct pp_hw_power_state *pstate1,
 312                                  const struct pp_hw_power_state *pstate2,
 313                                  bool *equal)
 314 {
 315         PHM_FUNC_CHECK(hwmgr);
 316
 317         if (hwmgr->hwmgr_func->check_states_equal == NULL)
 318                 return -EINVAL;
 319
 320         return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
 321 }
 322
 323 int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
 324                     const struct amd_pp_display_configuration *display_config)
 325 {
 326         PHM_FUNC_CHECK(hwmgr);
 327
 328         if (display_config == NULL)
 329                 return -EINVAL;
 330
 331         hwmgr->display_config = *display_config;
 332
 333         if (hwmgr->hwmgr_func->store_cc6_data == NULL)
 334                 return -EINVAL;
 335
 336         /* TODO: pass other display configuration in the future */
 337
 338         if (hwmgr->hwmgr_func->store_cc6_data)
 339                 hwmgr->hwmgr_func->store_cc6_data(hwmgr,
 340                                 display_config->cpu_pstate_separation_time,
 341                                 display_config->cpu_cc6_disable,
 342                                 display_config->cpu_pstate_disable,
 343                                 display_config->nb_pstate_switch_disable);
 344
 345         return 0;
 346 }
 347
 348 int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
 349                 struct amd_pp_simple_clock_info *info)
 350 {
 351         PHM_FUNC_CHECK(hwmgr);
 352
 353         if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
 354                 return -EINVAL;
 355         return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
 356 }
 357
 358 int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
 359 {
 360         PHM_FUNC_CHECK(hwmgr);
 361
 362         if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
 363                 return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
 364
 365         return 0;
 366 }
 367
 368
 369 int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
 370                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
 371                                 PHM_PerformanceLevel *level)
 372 {
 373         PHM_FUNC_CHECK(hwmgr);
 374         if (hwmgr->hwmgr_func->get_performance_level == NULL)
 375                 return -EINVAL;
 376
 377         return hwmgr->hwmgr_func->get_performance_level(hwmgr, state, designation, index, level);
 378
 379
 380 }
 381
 382
 383 /**
 384 * Gets Clock Info.
 385 *
 386 * @param    pHwMgr  the address of the powerplay hardware manager.
 387 * @param    pPowerState the address of the Power State structure.
 388 * @param    pClockInfo the address of PP_ClockInfo structure where the result will be returned.
 389 * @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the back-end.
 390 */
 391 int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *pclock_info,
 392                         PHM_PerformanceLevelDesignation designation)
 393 {
 394         int result;
 395         PHM_PerformanceLevel performance_level;
 396
 397         PHM_FUNC_CHECK(hwmgr);
 398
 399         PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL);
 400         PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL);
 401
 402         result = phm_get_performance_level(hwmgr, state, PHM_PerformanceLevelDesignation_Activity, 0, &performance_level);
 403
 404         PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result);
 405
 406
 407         pclock_info->min_mem_clk = performance_level.memory_clock;
 408         pclock_info->min_eng_clk = performance_level.coreClock;
 409         pclock_info->min_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
 410
 411
 412         result = phm_get_performance_level(hwmgr, state, designation,
 413                                         (hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1), &performance_level);
 414
 415         PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result);
 416
 417         pclock_info->max_mem_clk = performance_level.memory_clock;
 418         pclock_info->max_eng_clk = performance_level.coreClock;
 419         pclock_info->max_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
 420
 421         return 0;
 422 }
 423
 424 int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
 425 {
 426         PHM_FUNC_CHECK(hwmgr);
 427
 428         if (hwmgr->hwmgr_func->get_current_shallow_sleep_clocks == NULL)
 429                 return -EINVAL;
 430
 431         return hwmgr->hwmgr_func->get_current_shallow_sleep_clocks(hwmgr, state, clock_info);
 432
 433 }
 434
 435 int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
 436 {
 437         PHM_FUNC_CHECK(hwmgr);
 438
 439         if (hwmgr->hwmgr_func->get_clock_by_type == NULL)
 440                 return -EINVAL;
 441
 442         return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks);
 443
 444 }
 445
 446 int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
 447                 enum amd_pp_clock_type type,
 448                 struct pp_clock_levels_with_latency *clocks)
 449 {
 450         PHM_FUNC_CHECK(hwmgr);
 451
 452         if (hwmgr->hwmgr_func->get_clock_by_type_with_latency == NULL)
 453                 return -EINVAL;
 454
 455         return hwmgr->hwmgr_func->get_clock_by_type_with_latency(hwmgr, type, clocks);
 456
 457 }
 458
 459 int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
 460                 enum amd_pp_clock_type type,
 461                 struct pp_clock_levels_with_voltage *clocks)
 462 {
 463         PHM_FUNC_CHECK(hwmgr);
 464
 465         if (hwmgr->hwmgr_func->get_clock_by_type_with_voltage == NULL)
 466                 return -EINVAL;
 467
 468         return hwmgr->hwmgr_func->get_clock_by_type_with_voltage(hwmgr, type, clocks);
 469
 470 }
 471
 472 int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
 473                 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
 474 {
 475         PHM_FUNC_CHECK(hwmgr);
 476
 477         if (!hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges)
 478                 return -EINVAL;
 479
 480         return hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges(hwmgr,
 481                         wm_with_clock_ranges);
 482 }
 483
 484 int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
 485                 struct pp_display_clock_request *clock)
 486 {
 487         PHM_FUNC_CHECK(hwmgr);
 488
 489         if (!hwmgr->hwmgr_func->display_clock_voltage_request)
 490                 return -EINVAL;
 491
 492         return hwmgr->hwmgr_func->display_clock_voltage_request(hwmgr, clock);
 493 }
 494
 495 int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
 496 {
 497         PHM_FUNC_CHECK(hwmgr);
 498
 499         if (hwmgr->hwmgr_func->get_max_high_clocks == NULL)
 500                 return -EINVAL;
 501
 502         return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks);
 503 }