2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/errno.h>
26 #include "hardwaremanager.h"
27 #include "power_state.h"
29 #define PHM_FUNC_CHECK(hw) \
31 if ((hw) == NULL || (hw)->hwmgr_func == NULL) \
35 bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
37 return hwmgr->block_hw_access;
40 int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
42 hwmgr->block_hw_access = block;
46 int phm_setup_asic(struct pp_hwmgr *hwmgr)
48 PHM_FUNC_CHECK(hwmgr);
50 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
51 PHM_PlatformCaps_TablelessHardwareInterface)) {
52 if (NULL != hwmgr->hwmgr_func->asic_setup)
53 return hwmgr->hwmgr_func->asic_setup(hwmgr);
55 return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
62 int phm_power_down_asic(struct pp_hwmgr *hwmgr)
64 PHM_FUNC_CHECK(hwmgr);
66 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
67 PHM_PlatformCaps_TablelessHardwareInterface)) {
68 if (NULL != hwmgr->hwmgr_func->power_off_asic)
69 return hwmgr->hwmgr_func->power_off_asic(hwmgr);
71 return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic),
78 int phm_set_power_state(struct pp_hwmgr *hwmgr,
79 const struct pp_hw_power_state *pcurrent_state,
80 const struct pp_hw_power_state *pnew_power_state)
82 struct phm_set_power_state_input states;
84 PHM_FUNC_CHECK(hwmgr);
86 states.pcurrent_state = pcurrent_state;
87 states.pnew_state = pnew_power_state;
89 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
90 PHM_PlatformCaps_TablelessHardwareInterface)) {
91 if (NULL != hwmgr->hwmgr_func->power_state_set)
92 return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
94 return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
100 int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
104 PHM_FUNC_CHECK(hwmgr);
106 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
107 PHM_PlatformCaps_TablelessHardwareInterface)) {
108 if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
109 ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
111 ret = phm_dispatch_table(hwmgr,
112 &(hwmgr->enable_dynamic_state_management),
118 cgs_notify_dpm_enabled(hwmgr->device, enabled);
123 int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
128 PHM_FUNC_CHECK(hwmgr);
130 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
131 PHM_PlatformCaps_TablelessHardwareInterface)) {
132 if (hwmgr->hwmgr_func->dynamic_state_management_disable)
133 ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
135 ret = phm_dispatch_table(hwmgr,
136 &(hwmgr->disable_dynamic_state_management),
140 enabled = ret == 0 ? false : true;
142 cgs_notify_dpm_enabled(hwmgr->device, enabled);
147 int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
151 PHM_FUNC_CHECK(hwmgr);
153 if (hwmgr->hwmgr_func->force_dpm_level != NULL) {
154 ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
158 if (hwmgr->hwmgr_func->set_power_profile_state) {
159 if (hwmgr->current_power_profile == AMD_PP_GFX_PROFILE)
160 ret = hwmgr->hwmgr_func->set_power_profile_state(
162 &hwmgr->gfx_power_profile);
163 else if (hwmgr->current_power_profile == AMD_PP_COMPUTE_PROFILE)
164 ret = hwmgr->hwmgr_func->set_power_profile_state(
166 &hwmgr->compute_power_profile);
173 int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
174 struct pp_power_state *adjusted_ps,
175 const struct pp_power_state *current_ps)
177 PHM_FUNC_CHECK(hwmgr);
179 if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
180 return hwmgr->hwmgr_func->apply_state_adjust_rules(
187 int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
189 PHM_FUNC_CHECK(hwmgr);
191 if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
192 return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
196 int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
198 PHM_FUNC_CHECK(hwmgr);
200 if (hwmgr->hwmgr_func->powergate_uvd != NULL)
201 return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
205 int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
207 PHM_FUNC_CHECK(hwmgr);
209 if (hwmgr->hwmgr_func->powergate_vce != NULL)
210 return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
214 int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
216 PHM_FUNC_CHECK(hwmgr);
218 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
219 PHM_PlatformCaps_TablelessHardwareInterface)) {
220 if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
221 return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
223 return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
228 int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr)
230 PHM_FUNC_CHECK(hwmgr);
232 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
233 PHM_PlatformCaps_TablelessHardwareInterface)) {
234 if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
235 return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
241 int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
243 PHM_FUNC_CHECK(hwmgr);
245 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
246 PHM_PlatformCaps_TablelessHardwareInterface)) {
247 if (NULL != hwmgr->hwmgr_func->display_config_changed)
248 hwmgr->hwmgr_func->display_config_changed(hwmgr);
250 return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
254 int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
256 PHM_FUNC_CHECK(hwmgr);
258 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
259 PHM_PlatformCaps_TablelessHardwareInterface))
260 if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
261 hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
266 int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
268 PHM_FUNC_CHECK(hwmgr);
270 if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
273 return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
276 int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
278 PHM_FUNC_CHECK(hwmgr);
280 if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
283 return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
287 * Initializes the thermal controller subsystem.
289 * @param pHwMgr the address of the powerplay hardware manager.
290 * @param pTemperatureRange the address of the structure holding the temperature range.
291 * @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
293 int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range)
295 return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
299 bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
301 PHM_FUNC_CHECK(hwmgr);
303 if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
306 return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
310 int phm_check_states_equal(struct pp_hwmgr *hwmgr,
311 const struct pp_hw_power_state *pstate1,
312 const struct pp_hw_power_state *pstate2,
315 PHM_FUNC_CHECK(hwmgr);
317 if (hwmgr->hwmgr_func->check_states_equal == NULL)
320 return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
323 int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
324 const struct amd_pp_display_configuration *display_config)
326 PHM_FUNC_CHECK(hwmgr);
328 if (display_config == NULL)
331 hwmgr->display_config = *display_config;
333 if (hwmgr->hwmgr_func->store_cc6_data == NULL)
336 /* TODO: pass other display configuration in the future */
338 if (hwmgr->hwmgr_func->store_cc6_data)
339 hwmgr->hwmgr_func->store_cc6_data(hwmgr,
340 display_config->cpu_pstate_separation_time,
341 display_config->cpu_cc6_disable,
342 display_config->cpu_pstate_disable,
343 display_config->nb_pstate_switch_disable);
348 int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
349 struct amd_pp_simple_clock_info *info)
351 PHM_FUNC_CHECK(hwmgr);
353 if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
355 return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
358 int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
360 PHM_FUNC_CHECK(hwmgr);
362 if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
363 return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
369 int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
370 PHM_PerformanceLevelDesignation designation, uint32_t index,
371 PHM_PerformanceLevel *level)
373 PHM_FUNC_CHECK(hwmgr);
374 if (hwmgr->hwmgr_func->get_performance_level == NULL)
377 return hwmgr->hwmgr_func->get_performance_level(hwmgr, state, designation, index, level);
386 * @param pHwMgr the address of the powerplay hardware manager.
387 * @param pPowerState the address of the Power State structure.
388 * @param pClockInfo the address of PP_ClockInfo structure where the result will be returned.
389 * @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the back-end.
391 int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *pclock_info,
392 PHM_PerformanceLevelDesignation designation)
395 PHM_PerformanceLevel performance_level;
397 PHM_FUNC_CHECK(hwmgr);
399 PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL);
400 PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL);
402 result = phm_get_performance_level(hwmgr, state, PHM_PerformanceLevelDesignation_Activity, 0, &performance_level);
404 PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result);
407 pclock_info->min_mem_clk = performance_level.memory_clock;
408 pclock_info->min_eng_clk = performance_level.coreClock;
409 pclock_info->min_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
412 result = phm_get_performance_level(hwmgr, state, designation,
413 (hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1), &performance_level);
415 PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result);
417 pclock_info->max_mem_clk = performance_level.memory_clock;
418 pclock_info->max_eng_clk = performance_level.coreClock;
419 pclock_info->max_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
424 int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
426 PHM_FUNC_CHECK(hwmgr);
428 if (hwmgr->hwmgr_func->get_current_shallow_sleep_clocks == NULL)
431 return hwmgr->hwmgr_func->get_current_shallow_sleep_clocks(hwmgr, state, clock_info);
435 int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
437 PHM_FUNC_CHECK(hwmgr);
439 if (hwmgr->hwmgr_func->get_clock_by_type == NULL)
442 return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks);
446 int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
447 enum amd_pp_clock_type type,
448 struct pp_clock_levels_with_latency *clocks)
450 PHM_FUNC_CHECK(hwmgr);
452 if (hwmgr->hwmgr_func->get_clock_by_type_with_latency == NULL)
455 return hwmgr->hwmgr_func->get_clock_by_type_with_latency(hwmgr, type, clocks);
459 int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
460 enum amd_pp_clock_type type,
461 struct pp_clock_levels_with_voltage *clocks)
463 PHM_FUNC_CHECK(hwmgr);
465 if (hwmgr->hwmgr_func->get_clock_by_type_with_voltage == NULL)
468 return hwmgr->hwmgr_func->get_clock_by_type_with_voltage(hwmgr, type, clocks);
472 int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
473 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
475 PHM_FUNC_CHECK(hwmgr);
477 if (!hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges)
480 return hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges(hwmgr,
481 wm_with_clock_ranges);
484 int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
485 struct pp_display_clock_request *clock)
487 PHM_FUNC_CHECK(hwmgr);
489 if (!hwmgr->hwmgr_func->display_clock_voltage_request)
492 return hwmgr->hwmgr_func->display_clock_voltage_request(hwmgr, clock);
495 int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
497 PHM_FUNC_CHECK(hwmgr);
499 if (hwmgr->hwmgr_func->get_max_high_clocks == NULL)
502 return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks);
505 int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr)
507 PHM_FUNC_CHECK(hwmgr);
509 if (hwmgr->hwmgr_func->disable_smc_firmware_ctf == NULL)
512 return hwmgr->hwmgr_func->disable_smc_firmware_ctf(hwmgr);