drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/fb.h>
  26 #include <asm/div64.h>
  27 #include "linux/delay.h"
  28 #include "pp_acpi.h"
  29 #include "hwmgr.h"
  30 #include "polaris10_hwmgr.h"
  31 #include "polaris10_powertune.h"
  32 #include "polaris10_dyn_defaults.h"
  33 #include "polaris10_smumgr.h"
  34 #include "pp_debug.h"
  35 #include "ppatomctrl.h"
  36 #include "atombios.h"
  37 #include "tonga_pptable.h"
  38 #include "pppcielanes.h"
  39 #include "amd_pcie_helpers.h"
  40 #include "hardwaremanager.h"
  41 #include "tonga_processpptables.h"
  42 #include "cgs_common.h"
  43 #include "smu74.h"
  44 #include "smu_ucode_xfer_vi.h"
  45 #include "smu74_discrete.h"
  46 #include "smu/smu_7_1_3_d.h"
  47 #include "smu/smu_7_1_3_sh_mask.h"
  48 #include "gmc/gmc_8_1_d.h"
  49 #include "gmc/gmc_8_1_sh_mask.h"
  50 #include "oss/oss_3_0_d.h"
  51 #include "gca/gfx_8_0_d.h"
  52 #include "bif/bif_5_0_d.h"
  53 #include "bif/bif_5_0_sh_mask.h"
  54 #include "gmc/gmc_8_1_d.h"
  55 #include "gmc/gmc_8_1_sh_mask.h"
  56 #include "bif/bif_5_0_d.h"
  57 #include "bif/bif_5_0_sh_mask.h"
  58 #include "dce/dce_10_0_d.h"
  59 #include "dce/dce_10_0_sh_mask.h"
  60
  61 #include "polaris10_thermal.h"
  62 #include "polaris10_clockpowergating.h"
  63
  64 #define MC_CG_ARB_FREQ_F0           0x0a
  65 #define MC_CG_ARB_FREQ_F1           0x0b
  66 #define MC_CG_ARB_FREQ_F2           0x0c
  67 #define MC_CG_ARB_FREQ_F3           0x0d
  68
  69 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  70 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  71 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  72 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  73
  74
  75 #define SMC_RAM_END 0x40000
  76
  77 #define SMC_CG_IND_START            0xc0030000
  78 #define SMC_CG_IND_END              0xc0040000
  79
  80 #define VOLTAGE_SCALE               4
  81 #define VOLTAGE_VID_OFFSET_SCALE1   625
  82 #define VOLTAGE_VID_OFFSET_SCALE2   100
  83
  84 #define VDDC_VDDCI_DELTA            200
  85
  86 #define MEM_FREQ_LOW_LATENCY        25000
  87 #define MEM_FREQ_HIGH_LATENCY       80000
  88
  89 #define MEM_LATENCY_HIGH            45
  90 #define MEM_LATENCY_LOW             35
  91 #define MEM_LATENCY_ERR             0xFFFF
  92
  93 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  94 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  95 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  96
  97
  98 #define PCIE_BUS_CLK                10000
  99 #define TCLK                        (PCIE_BUS_CLK / 10)
 100
 101
 102 static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
 103 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
 104
 105 /*  [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
 106 static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
 107 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
 108   { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
 109
 110 /*  [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
 111 static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
 112 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
 113
 114 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 115 enum DPM_EVENT_SRC {
 116         DPM_EVENT_SRC_ANALOG = 0,
 117         DPM_EVENT_SRC_EXTERNAL = 1,
 118         DPM_EVENT_SRC_DIGITAL = 2,
 119         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
 120         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 121 };
 122
 123 static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
 124
 125 struct polaris10_power_state *cast_phw_polaris10_power_state(
 126                                   struct pp_hw_power_state *hw_ps)
 127 {
 128         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 129                                 "Invalid Powerstate Type!",
 130                                  return NULL);
 131
 132         return (struct polaris10_power_state *)hw_ps;
 133 }
 134
 135 const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
 136                                  const struct pp_hw_power_state *hw_ps)
 137 {
 138         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 139                                 "Invalid Powerstate Type!",
 140                                  return NULL);
 141
 142         return (const struct polaris10_power_state *)hw_ps;
 143 }
 144
 145 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
 146 {
 147         return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
 148                         CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
 149                         ? true : false;
 150 }
 151
 152 /**
 153  * Find the MC microcode version and store it in the HwMgr struct
 154  *
 155  * @param    hwmgr  the address of the powerplay hardware manager.
 156  * @return   always 0
 157  */
 158 int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
 159 {
 160         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 161
 162         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
 163
 164         return 0;
 165 }
 166
 167 uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 168 {
 169         uint32_t speedCntl = 0;
 170
 171         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 172         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 173                         ixPCIE_LC_SPEED_CNTL);
 174         return((uint16_t)PHM_GET_FIELD(speedCntl,
 175                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 176 }
 177
 178 int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 179 {
 180         uint32_t link_width;
 181
 182         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 183         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 184                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 185
 186         PP_ASSERT_WITH_CODE((7 >= link_width),
 187                         "Invalid PCIe lane width!", return 0);
 188
 189         return decode_pcie_lane_width(link_width);
 190 }
 191
 192 /**
 193 * Enable voltage control
 194 *
 195 * @param    pHwMgr  the address of the powerplay hardware manager.
 196 * @return   always PP_Result_OK
 197 */
 198 int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
 199 {
 200         PP_ASSERT_WITH_CODE(
 201                 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
 202                 "Failed to enable voltage DPM during DPM Start Function!",
 203                 return 1;
 204         );
 205
 206         return 0;
 207 }
 208
 209 /**
 210 * Checks if we want to support voltage control
 211 *
 212 * @param    hwmgr  the address of the powerplay hardware manager.
 213 */
 214 static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
 215 {
 216         const struct polaris10_hwmgr *data =
 217                         (const struct polaris10_hwmgr *)(hwmgr->backend);
 218
 219         return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
 220 }
 221
 222 /**
 223 * Enable voltage control
 224 *
 225 * @param    hwmgr  the address of the powerplay hardware manager.
 226 * @return   always 0
 227 */
 228 static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
 229 {
 230         /* enable voltage control */
 231         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 232                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 233
 234         return 0;
 235 }
 236
 237 /**
 238 * Create Voltage Tables.
 239 *
 240 * @param    hwmgr  the address of the powerplay hardware manager.
 241 * @return   always 0
 242 */
 243 static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
 244 {
 245         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 246         struct phm_ppt_v1_information *table_info =
 247                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 248         int result;
 249
 250         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 251                 result = atomctrl_get_voltage_table_v3(hwmgr,
 252                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
 253                                 &(data->mvdd_voltage_table));
 254                 PP_ASSERT_WITH_CODE((0 == result),
 255                                 "Failed to retrieve MVDD table.",
 256                                 return result);
 257         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
 258                 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
 259                                 table_info->vdd_dep_on_mclk);
 260                 PP_ASSERT_WITH_CODE((0 == result),
 261                                 "Failed to retrieve SVI2 MVDD table from dependancy table.",
 262                                 return result;);
 263         }
 264
 265         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 266                 result = atomctrl_get_voltage_table_v3(hwmgr,
 267                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
 268                                 &(data->vddci_voltage_table));
 269                 PP_ASSERT_WITH_CODE((0 == result),
 270                                 "Failed to retrieve VDDCI table.",
 271                                 return result);
 272         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
 273                 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
 274                                 table_info->vdd_dep_on_mclk);
 275                 PP_ASSERT_WITH_CODE((0 == result),
 276                                 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
 277                                 return result);
 278         }
 279
 280         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 281                 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
 282                                 table_info->vddc_lookup_table);
 283                 PP_ASSERT_WITH_CODE((0 == result),
 284                                 "Failed to retrieve SVI2 VDDC table from lookup table.",
 285                                 return result);
 286         }
 287
 288         PP_ASSERT_WITH_CODE(
 289                         (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
 290                         "Too many voltage values for VDDC. Trimming to fit state table.",
 291                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
 292                                                                 &(data->vddc_voltage_table)));
 293
 294         PP_ASSERT_WITH_CODE(
 295                         (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
 296                         "Too many voltage values for VDDCI. Trimming to fit state table.",
 297                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
 298                                         &(data->vddci_voltage_table)));
 299
 300         PP_ASSERT_WITH_CODE(
 301                         (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
 302                         "Too many voltage values for MVDD. Trimming to fit state table.",
 303                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
 304                                                            &(data->mvdd_voltage_table)));
 305
 306         return 0;
 307 }
 308
 309 /**
 310 * Programs static screed detection parameters
 311 *
 312 * @param    hwmgr  the address of the powerplay hardware manager.
 313 * @return   always 0
 314 */
 315 static int polaris10_program_static_screen_threshold_parameters(
 316                                                         struct pp_hwmgr *hwmgr)
 317 {
 318         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 319
 320         /* Set static screen threshold unit */
 321         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 322                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
 323                         data->static_screen_threshold_unit);
 324         /* Set static screen threshold */
 325         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 326                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
 327                         data->static_screen_threshold);
 328
 329         return 0;
 330 }
 331
 332 /**
 333 * Setup display gap for glitch free memory clock switching.
 334 *
 335 * @param    hwmgr  the address of the powerplay hardware manager.
 336 * @return   always  0
 337 */
 338 static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
 339 {
 340         uint32_t display_gap =
 341                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 342                                         ixCG_DISPLAY_GAP_CNTL);
 343
 344         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 345                         DISP_GAP, DISPLAY_GAP_IGNORE);
 346
 347         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 348                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
 349
 350         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 351                         ixCG_DISPLAY_GAP_CNTL, display_gap);
 352
 353         return 0;
 354 }
 355
 356 /**
 357 * Programs activity state transition voting clients
 358 *
 359 * @param    hwmgr  the address of the powerplay hardware manager.
 360 * @return   always  0
 361 */
 362 static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
 363 {
 364         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 365
 366         /* Clear reset for voting clients before enabling DPM */
 367         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 368                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
 369         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 370                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
 371
 372         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 373                         ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
 374         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 375                         ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
 376         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 377                         ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
 378         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 379                         ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
 380         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 381                         ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
 382         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 383                         ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
 384         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 385                         ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
 386         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 387                         ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
 388
 389         return 0;
 390 }
 391
 392 /**
 393 * Get the location of various tables inside the FW image.
 394 *
 395 * @param    hwmgr  the address of the powerplay hardware manager.
 396 * @return   always  0
 397 */
 398 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
 399 {
 400         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 401         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
 402         uint32_t tmp;
 403         int result;
 404         bool error = false;
 405
 406         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 407                         SMU7_FIRMWARE_HEADER_LOCATION +
 408                         offsetof(SMU74_Firmware_Header, DpmTable),
 409                         &tmp, data->sram_end);
 410
 411         if (0 == result)
 412                 data->dpm_table_start = tmp;
 413
 414         error |= (0 != result);
 415
 416         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 417                         SMU7_FIRMWARE_HEADER_LOCATION +
 418                         offsetof(SMU74_Firmware_Header, SoftRegisters),
 419                         &tmp, data->sram_end);
 420
 421         if (!result) {
 422                 data->soft_regs_start = tmp;
 423                 smu_data->soft_regs_start = tmp;
 424         }
 425
 426         error |= (0 != result);
 427
 428         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 429                         SMU7_FIRMWARE_HEADER_LOCATION +
 430                         offsetof(SMU74_Firmware_Header, mcRegisterTable),
 431                         &tmp, data->sram_end);
 432
 433         if (!result)
 434                 data->mc_reg_table_start = tmp;
 435
 436         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 437                         SMU7_FIRMWARE_HEADER_LOCATION +
 438                         offsetof(SMU74_Firmware_Header, FanTable),
 439                         &tmp, data->sram_end);
 440
 441         if (!result)
 442                 data->fan_table_start = tmp;
 443
 444         error |= (0 != result);
 445
 446         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 447                         SMU7_FIRMWARE_HEADER_LOCATION +
 448                         offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
 449                         &tmp, data->sram_end);
 450
 451         if (!result)
 452                 data->arb_table_start = tmp;
 453
 454         error |= (0 != result);
 455
 456         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 457                         SMU7_FIRMWARE_HEADER_LOCATION +
 458                         offsetof(SMU74_Firmware_Header, Version),
 459                         &tmp, data->sram_end);
 460
 461         if (!result)
 462                 hwmgr->microcode_version_info.SMC = tmp;
 463
 464         error |= (0 != result);
 465
 466         return error ? -1 : 0;
 467 }
 468
 469 /* Copy one arb setting to another and then switch the active set.
 470  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
 471  */
 472 static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
 473                 uint32_t arb_src, uint32_t arb_dest)
 474 {
 475         uint32_t mc_arb_dram_timing;
 476         uint32_t mc_arb_dram_timing2;
 477         uint32_t burst_time;
 478         uint32_t mc_cg_config;
 479
 480         switch (arb_src) {
 481         case MC_CG_ARB_FREQ_F0:
 482                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
 483                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
 484                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
 485                 break;
 486         case MC_CG_ARB_FREQ_F1:
 487                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
 488                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
 489                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
 490                 break;
 491         default:
 492                 return -EINVAL;
 493         }
 494
 495         switch (arb_dest) {
 496         case MC_CG_ARB_FREQ_F0:
 497                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 498                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 499                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
 500                 break;
 501         case MC_CG_ARB_FREQ_F1:
 502                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 503                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 504                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
 505                 break;
 506         default:
 507                 return -EINVAL;
 508         }
 509
 510         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
 511         mc_cg_config |= 0x0000000F;
 512         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
 513         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
 514
 515         return 0;
 516 }
 517
 518 /**
 519 * Initial switch from ARB F0->F1
 520 *
 521 * @param    hwmgr  the address of the powerplay hardware manager.
 522 * @return   always 0
 523 * This function is to be called from the SetPowerState table.
 524 */
 525 static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
 526 {
 527         return polaris10_copy_and_switch_arb_sets(hwmgr,
 528                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
 529 }
 530
 531 static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 532 {
 533         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 534         struct phm_ppt_v1_information *table_info =
 535                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 536         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
 537         uint32_t i, max_entry;
 538
 539         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
 540                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
 541                         return -EINVAL);
 542
 543         if (data->use_pcie_performance_levels &&
 544                         !data->use_pcie_power_saving_levels) {
 545                 data->pcie_gen_power_saving = data->pcie_gen_performance;
 546                 data->pcie_lane_power_saving = data->pcie_lane_performance;
 547         } else if (!data->use_pcie_performance_levels &&
 548                         data->use_pcie_power_saving_levels) {
 549                 data->pcie_gen_performance = data->pcie_gen_power_saving;
 550                 data->pcie_lane_performance = data->pcie_lane_power_saving;
 551         }
 552
 553         phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
 554                                         SMU74_MAX_LEVELS_LINK,
 555                                         MAX_REGULAR_DPM_NUMBER);
 556
 557         if (pcie_table != NULL) {
 558                 /* max_entry is used to make sure we reserve one PCIE level
 559                  * for boot level (fix for A+A PSPP issue).
 560                  * If PCIE table from PPTable have ULV entry + 8 entries,
 561                  * then ignore the last entry.*/
 562                 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
 563                                 SMU74_MAX_LEVELS_LINK : pcie_table->count;
 564                 for (i = 1; i < max_entry; i++) {
 565                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
 566                                         get_pcie_gen_support(data->pcie_gen_cap,
 567                                                         pcie_table->entries[i].gen_speed),
 568                                         get_pcie_lane_support(data->pcie_lane_cap,
 569                                                         pcie_table->entries[i].lane_width));
 570                 }
 571                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
 572
 573                 /* Setup BIF_SCLK levels */
 574                 for (i = 0; i < max_entry; i++)
 575                         data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
 576         } else {
 577                 /* Hardcode Pcie Table */
 578                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
 579                                 get_pcie_gen_support(data->pcie_gen_cap,
 580                                                 PP_Min_PCIEGen),
 581                                 get_pcie_lane_support(data->pcie_lane_cap,
 582                                                 PP_Max_PCIELane));
 583                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
 584                                 get_pcie_gen_support(data->pcie_gen_cap,
 585                                                 PP_Min_PCIEGen),
 586                                 get_pcie_lane_support(data->pcie_lane_cap,
 587                                                 PP_Max_PCIELane));
 588                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
 589                                 get_pcie_gen_support(data->pcie_gen_cap,
 590                                                 PP_Max_PCIEGen),
 591                                 get_pcie_lane_support(data->pcie_lane_cap,
 592                                                 PP_Max_PCIELane));
 593                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
 594                                 get_pcie_gen_support(data->pcie_gen_cap,
 595                                                 PP_Max_PCIEGen),
 596                                 get_pcie_lane_support(data->pcie_lane_cap,
 597                                                 PP_Max_PCIELane));
 598                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
 599                                 get_pcie_gen_support(data->pcie_gen_cap,
 600                                                 PP_Max_PCIEGen),
 601                                 get_pcie_lane_support(data->pcie_lane_cap,
 602                                                 PP_Max_PCIELane));
 603                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
 604                                 get_pcie_gen_support(data->pcie_gen_cap,
 605                                                 PP_Max_PCIEGen),
 606                                 get_pcie_lane_support(data->pcie_lane_cap,
 607                                                 PP_Max_PCIELane));
 608
 609                 data->dpm_table.pcie_speed_table.count = 6;
 610         }
 611         /* Populate last level for boot PCIE level, but do not increment count. */
 612         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
 613                         data->dpm_table.pcie_speed_table.count,
 614                         get_pcie_gen_support(data->pcie_gen_cap,
 615                                         PP_Min_PCIEGen),
 616                         get_pcie_lane_support(data->pcie_lane_cap,
 617                                         PP_Max_PCIELane));
 618
 619         return 0;
 620 }
 621
 622 /*
 623  * This function is to initalize all DPM state tables
 624  * for SMU7 based on the dependency table.
 625  * Dynamic state patching function will then trim these
 626  * state tables to the allowed range based
 627  * on the power policy or external client requests,
 628  * such as UVD request, etc.
 629  */
 630 int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 631 {
 632         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 633         struct phm_ppt_v1_information *table_info =
 634                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 635         uint32_t i;
 636
 637         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
 638                         table_info->vdd_dep_on_sclk;
 639         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
 640                         table_info->vdd_dep_on_mclk;
 641
 642         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
 643                         "SCLK dependency table is missing. This table is mandatory",
 644                         return -EINVAL);
 645         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
 646                         "SCLK dependency table has to have is missing."
 647                         "This table is mandatory",
 648                         return -EINVAL);
 649
 650         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
 651                         "MCLK dependency table is missing. This table is mandatory",
 652                         return -EINVAL);
 653         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
 654                         "MCLK dependency table has to have is missing."
 655                         "This table is mandatory",
 656                         return -EINVAL);
 657
 658         /* clear the state table to reset everything to default */
 659         phm_reset_single_dpm_table(
 660                         &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
 661         phm_reset_single_dpm_table(
 662                         &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
 663
 664
 665         /* Initialize Sclk DPM table based on allow Sclk values */
 666         data->dpm_table.sclk_table.count = 0;
 667         for (i = 0; i < dep_sclk_table->count; i++) {
 668                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
 669                                                 dep_sclk_table->entries[i].clk) {
 670
 671                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 672                                         dep_sclk_table->entries[i].clk;
 673
 674                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
 675                                         (i == 0) ? true : false;
 676                         data->dpm_table.sclk_table.count++;
 677                 }
 678         }
 679
 680         /* Initialize Mclk DPM table based on allow Mclk values */
 681         data->dpm_table.mclk_table.count = 0;
 682         for (i = 0; i < dep_mclk_table->count; i++) {
 683                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
 684                                 [data->dpm_table.mclk_table.count - 1].value !=
 685                                                 dep_mclk_table->entries[i].clk) {
 686                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 687                                                         dep_mclk_table->entries[i].clk;
 688                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
 689                                                         (i == 0) ? true : false;
 690                         data->dpm_table.mclk_table.count++;
 691                 }
 692         }
 693
 694         /* setup PCIE gen speed levels */
 695         polaris10_setup_default_pcie_table(hwmgr);
 696
 697         /* save a copy of the default DPM table */
 698         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 699                         sizeof(struct polaris10_dpm_table));
 700
 701         return 0;
 702 }
 703
 704 uint8_t convert_to_vid(uint16_t vddc)
 705 {
 706         return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
 707 }
 708
 709 /**
 710  * Mvdd table preparation for SMC.
 711  *
 712  * @param    *hwmgr The address of the hardware manager.
 713  * @param    *table The SMC DPM table structure to be populated.
 714  * @return   0
 715  */
 716 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
 717                         SMU74_Discrete_DpmTable *table)
 718 {
 719         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 720         uint32_t count, level;
 721
 722         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 723                 count = data->mvdd_voltage_table.count;
 724                 if (count > SMU_MAX_SMIO_LEVELS)
 725                         count = SMU_MAX_SMIO_LEVELS;
 726                 for (level = 0; level < count; level++) {
 727                         table->SmioTable2.Pattern[level].Voltage =
 728                                 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
 729                         /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
 730                         table->SmioTable2.Pattern[level].Smio =
 731                                 (uint8_t) level;
 732                         table->Smio[level] |=
 733                                 data->mvdd_voltage_table.entries[level].smio_low;
 734                 }
 735                 table->SmioMask2 = data->vddci_voltage_table.mask_low;
 736
 737                 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
 738         }
 739
 740         return 0;
 741 }
 742
 743 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
 744                                         struct SMU74_Discrete_DpmTable *table)
 745 {
 746         uint32_t count, level;
 747         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 748
 749         count = data->vddci_voltage_table.count;
 750
 751         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 752                 if (count > SMU_MAX_SMIO_LEVELS)
 753                         count = SMU_MAX_SMIO_LEVELS;
 754                 for (level = 0; level < count; ++level) {
 755                         table->SmioTable1.Pattern[level].Voltage =
 756                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
 757                         table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
 758
 759                         table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
 760                 }
 761         }
 762
 763         table->SmioMask1 = data->vddci_voltage_table.mask_low;
 764
 765         return 0;
 766 }
 767
 768 /**
 769 * Preparation of vddc and vddgfx CAC tables for SMC.
 770 *
 771 * @param    hwmgr  the address of the hardware manager
 772 * @param    table  the SMC DPM table structure to be populated
 773 * @return   always 0
 774 */
 775 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
 776                 struct SMU74_Discrete_DpmTable *table)
 777 {
 778         uint32_t count;
 779         uint8_t index;
 780         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 781         struct phm_ppt_v1_information *table_info =
 782                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 783         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
 784                         table_info->vddc_lookup_table;
 785         /* tables is already swapped, so in order to use the value from it,
 786          * we need to swap it back.
 787          * We are populating vddc CAC data to BapmVddc table
 788          * in split and merged mode
 789          */
 790         for (count = 0; count < lookup_table->count; count++) {
 791                 index = phm_get_voltage_index(lookup_table,
 792                                 data->vddc_voltage_table.entries[count].value);
 793                 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
 794                 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
 795                 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
 796         }
 797
 798         return 0;
 799 }
 800
 801 /**
 802 * Preparation of voltage tables for SMC.
 803 *
 804 * @param    hwmgr   the address of the hardware manager
 805 * @param    table   the SMC DPM table structure to be populated
 806 * @return   always  0
 807 */
 808
 809 int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
 810                 struct SMU74_Discrete_DpmTable *table)
 811 {
 812         polaris10_populate_smc_vddci_table(hwmgr, table);
 813         polaris10_populate_smc_mvdd_table(hwmgr, table);
 814         polaris10_populate_cac_table(hwmgr, table);
 815
 816         return 0;
 817 }
 818
 819 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
 820                 struct SMU74_Discrete_Ulv *state)
 821 {
 822         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 823         struct phm_ppt_v1_information *table_info =
 824                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 825
 826         state->CcPwrDynRm = 0;
 827         state->CcPwrDynRm1 = 0;
 828
 829         state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
 830         state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
 831                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
 832
 833         state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
 834
 835         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
 836         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
 837         CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
 838
 839         return 0;
 840 }
 841
 842 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
 843                 struct SMU74_Discrete_DpmTable *table)
 844 {
 845         return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
 846 }
 847
 848 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
 849                 struct SMU74_Discrete_DpmTable *table)
 850 {
 851         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 852         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
 853         int i;
 854
 855         /* Index (dpm_table->pcie_speed_table.count)
 856          * is reserved for PCIE boot level. */
 857         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
 858                 table->LinkLevel[i].PcieGenSpeed  =
 859                                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
 860                 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
 861                                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
 862                 table->LinkLevel[i].EnabledForActivity = 1;
 863                 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
 864                 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
 865                 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
 866         }
 867
 868         data->smc_state_table.LinkLevelCount =
 869                         (uint8_t)dpm_table->pcie_speed_table.count;
 870         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
 871                         phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
 872
 873         return 0;
 874 }
 875
 876 static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
 877 {
 878         uint32_t reference_clock, tmp;
 879         struct cgs_display_info info = {0};
 880         struct cgs_mode_info mode_info;
 881
 882         info.mode_info = &mode_info;
 883
 884         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
 885
 886         if (tmp)
 887                 return TCLK;
 888
 889         cgs_get_active_displays_info(hwmgr->device, &info);
 890         reference_clock = mode_info.ref_clock;
 891
 892         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
 893
 894         if (0 != tmp)
 895                 return reference_clock / 4;
 896
 897         return reference_clock;
 898 }
 899
 900 /**
 901 * Calculates the SCLK dividers using the provided engine clock
 902 *
 903 * @param    hwmgr  the address of the hardware manager
 904 * @param    clock  the engine clock to use to populate the structure
 905 * @param    sclk   the SMC SCLK structure to be populated
 906 */
 907 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 908                 uint32_t clock, SMU_SclkSetting *sclk_setting)
 909 {
 910         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 911         const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
 912         struct pp_atomctrl_clock_dividers_ai dividers;
 913
 914         uint32_t ref_clock;
 915         uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
 916         uint8_t i;
 917         int result;
 918         uint64_t temp;
 919
 920         sclk_setting->SclkFrequency = clock;
 921         /* get the engine clock dividers for this clock value */
 922         result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
 923         if (result == 0) {
 924                 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
 925                 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
 926                 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
 927                 sclk_setting->PllRange = dividers.ucSclkPllRange;
 928                 sclk_setting->Sclk_slew_rate = 0x400;
 929                 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
 930                 sclk_setting->Pcc_down_slew_rate = 0xffff;
 931                 sclk_setting->SSc_En = dividers.ucSscEnable;
 932                 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
 933                 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
 934                 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
 935                 return result;
 936         }
 937
 938         ref_clock = polaris10_get_xclk(hwmgr);
 939
 940         for (i = 0; i < NUM_SCLK_RANGE; i++) {
 941                 if (clock > data->range_table[i].trans_lower_frequency
 942                 && clock <= data->range_table[i].trans_upper_frequency) {
 943                         sclk_setting->PllRange = i;
 944                         break;
 945                 }
 946         }
 947
 948         sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 949         temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 950         temp <<= 0x10;
 951         do_div(temp, ref_clock);
 952         sclk_setting->Fcw_frac = temp & 0xffff;
 953
 954         pcc_target_percent = 10; /*  Hardcode 10% for now. */
 955         pcc_target_freq = clock - (clock * pcc_target_percent / 100);
 956         sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 957
 958         ss_target_percent = 2; /*  Hardcode 2% for now. */
 959         sclk_setting->SSc_En = 0;
 960         if (ss_target_percent) {
 961                 sclk_setting->SSc_En = 1;
 962                 ss_target_freq = clock - (clock * ss_target_percent / 100);
 963                 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 964                 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 965                 temp <<= 0x10;
 966                 do_div(temp, ref_clock);
 967                 sclk_setting->Fcw1_frac = temp & 0xffff;
 968         }
 969
 970         return 0;
 971 }
 972
 973 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
 974                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
 975                 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
 976 {
 977         uint32_t i;
 978         uint16_t vddci;
 979         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 980
 981         *voltage = *mvdd = 0;
 982
 983         /* clock - voltage dependency table is empty table */
 984         if (dep_table->count == 0)
 985                 return -EINVAL;
 986
 987         for (i = 0; i < dep_table->count; i++) {
 988                 /* find first sclk bigger than request */
 989                 if (dep_table->entries[i].clk >= clock) {
 990                         *voltage |= (dep_table->entries[i].vddc *
 991                                         VOLTAGE_SCALE) << VDDC_SHIFT;
 992                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
 993                                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
 994                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
 995                         else if (dep_table->entries[i].vddci)
 996                                 *voltage |= (dep_table->entries[i].vddci *
 997                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
 998                         else {
 999                                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1000                                                 (dep_table->entries[i].vddc -
1001                                                                 (uint16_t)data->vddc_vddci_delta));
1002                                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1003                         }
1004
1005                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1006                                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1007                                         VOLTAGE_SCALE;
1008                         else if (dep_table->entries[i].mvdd)
1009                                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1010                                         VOLTAGE_SCALE;
1011
1012                         *voltage |= 1 << PHASES_SHIFT;
1013                         return 0;
1014                 }
1015         }
1016
1017         /* sclk is bigger than max sclk in the dependence table */
1018         *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1019
1020         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1021                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1022                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1023         else if (dep_table->entries[i-1].vddci) {
1024                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1025                                 (dep_table->entries[i].vddc -
1026                                                 (uint16_t)data->vddc_vddci_delta));
1027                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1028         }
1029
1030         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1031                 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1032         else if (dep_table->entries[i].mvdd)
1033                 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1034
1035         return 0;
1036 }
1037
1038 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
1039 { {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
1040   {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1041   {VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
1042   {VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
1043   {VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
1044   {VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
1045   {VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
1046   {VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
1047
1048 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
1049 {
1050         uint32_t i, ref_clk;
1051         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1052         SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
1053         struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1054
1055         ref_clk = polaris10_get_xclk(hwmgr);
1056
1057         if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1058                 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1059                         table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1060                         table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1061                         table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1062
1063                         table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1064                         table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1065
1066                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1067                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1068                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1069                 }
1070                 return;
1071         }
1072
1073         for (i = 0; i < NUM_SCLK_RANGE; i++) {
1074
1075                 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1076                 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1077
1078                 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1079                 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1080                 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1081
1082                 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1083                 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1084
1085                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1086                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1087                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1088         }
1089 }
1090
1091 /**
1092 * Populates single SMC SCLK structure using the provided engine clock
1093 *
1094 * @param    hwmgr      the address of the hardware manager
1095 * @param    clock the engine clock to use to populate the structure
1096 * @param    sclk        the SMC SCLK structure to be populated
1097 */
1098
1099 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1100                 uint32_t clock, uint16_t sclk_al_threshold,
1101                 struct SMU74_Discrete_GraphicsLevel *level)
1102 {
1103         int result, i, temp;
1104         /* PP_Clocks minClocks; */
1105         uint32_t mvdd;
1106         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1107         struct phm_ppt_v1_information *table_info =
1108                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1109         SMU_SclkSetting curr_sclk_setting = { 0 };
1110
1111         result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
1112
1113         /* populate graphics levels */
1114         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1115                         table_info->vdd_dep_on_sclk, clock,
1116                         &level->MinVoltage, &mvdd);
1117
1118         PP_ASSERT_WITH_CODE((0 == result),
1119                         "can not find VDDC voltage value for "
1120                         "VDDC engine clock dependency table",
1121                         return result);
1122         level->ActivityLevel = sclk_al_threshold;
1123
1124         level->CcPwrDynRm = 0;
1125         level->CcPwrDynRm1 = 0;
1126         level->EnabledForActivity = 0;
1127         level->EnabledForThrottle = 1;
1128         level->UpHyst = 10;
1129         level->DownHyst = 0;
1130         level->VoltageDownHyst = 0;
1131         level->PowerThrottle = 0;
1132
1133         /*
1134         * TODO: get minimum clocks from dal configaration
1135         * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1136         */
1137         /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1138
1139         /* get level->DeepSleepDivId
1140         if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1141                 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1142         */
1143         PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0);
1144         for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1145                 temp = clock >> i;
1146
1147                 if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0)
1148                         break;
1149         }
1150
1151         level->DeepSleepDivId = i;
1152
1153         /* Default to slow, highest DPM level will be
1154          * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1155          */
1156         if (data->update_up_hyst)
1157                 level->UpHyst = (uint8_t)data->up_hyst;
1158         if (data->update_down_hyst)
1159                 level->DownHyst = (uint8_t)data->down_hyst;
1160
1161         level->SclkSetting = curr_sclk_setting;
1162
1163         CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1164         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1165         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1166         CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1167         CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1168         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1169         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1170         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1171         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1172         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1173         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1174         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1175         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1176         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1177         return 0;
1178 }
1179
1180 /**
1181 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1182 *
1183 * @param    hwmgr      the address of the hardware manager
1184 */
1185 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1186 {
1187         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1188         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1189         struct phm_ppt_v1_information *table_info =
1190                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1191         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1192         uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1193         int result = 0;
1194         uint32_t array = data->dpm_table_start +
1195                         offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1196         uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1197                         SMU74_MAX_LEVELS_GRAPHICS;
1198         struct SMU74_Discrete_GraphicsLevel *levels =
1199                         data->smc_state_table.GraphicsLevel;
1200         uint32_t i, max_entry;
1201         uint8_t hightest_pcie_level_enabled = 0,
1202                 lowest_pcie_level_enabled = 0,
1203                 mid_pcie_level_enabled = 0,
1204                 count = 0;
1205
1206         polaris10_get_sclk_range_table(hwmgr);
1207
1208         for (i = 0; i < dpm_table->sclk_table.count; i++) {
1209
1210                 result = polaris10_populate_single_graphic_level(hwmgr,
1211                                 dpm_table->sclk_table.dpm_levels[i].value,
1212                                 (uint16_t)data->activity_target[i],
1213                                 &(data->smc_state_table.GraphicsLevel[i]));
1214                 if (result)
1215                         return result;
1216
1217                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1218                 if (i > 1)
1219                         levels[i].DeepSleepDivId = 0;
1220         }
1221         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1222                                         PHM_PlatformCaps_SPLLShutdownSupport))
1223                 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1224
1225         data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1226         data->smc_state_table.GraphicsDpmLevelCount =
1227                         (uint8_t)dpm_table->sclk_table.count;
1228         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1229                         phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1230
1231
1232         if (pcie_table != NULL) {
1233                 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1234                                 "There must be 1 or more PCIE levels defined in PPTable.",
1235                                 return -EINVAL);
1236                 max_entry = pcie_entry_cnt - 1;
1237                 for (i = 0; i < dpm_table->sclk_table.count; i++)
1238                         levels[i].pcieDpmLevel =
1239                                         (uint8_t) ((i < max_entry) ? i : max_entry);
1240         } else {
1241                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1242                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1243                                                 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1244                         hightest_pcie_level_enabled++;
1245
1246                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1247                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1248                                                 (1 << lowest_pcie_level_enabled)) == 0))
1249                         lowest_pcie_level_enabled++;
1250
1251                 while ((count < hightest_pcie_level_enabled) &&
1252                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1253                                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1254                         count++;
1255
1256                 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1257                                 hightest_pcie_level_enabled ?
1258                                                 (lowest_pcie_level_enabled + 1 + count) :
1259                                                 hightest_pcie_level_enabled;
1260
1261                 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1262                 for (i = 2; i < dpm_table->sclk_table.count; i++)
1263                         levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1264
1265                 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1266                 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1267
1268                 /* set pcieDpmLevel to mid_pcie_level_enabled */
1269                 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1270         }
1271         /* level count will send to smc once at init smc table and never change */
1272         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1273                         (uint32_t)array_size, data->sram_end);
1274
1275         return result;
1276 }
1277
1278 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1279                 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1280 {
1281         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1282         struct phm_ppt_v1_information *table_info =
1283                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1284         int result = 0;
1285         struct cgs_display_info info = {0, 0, NULL};
1286
1287         cgs_get_active_displays_info(hwmgr->device, &info);
1288
1289         if (table_info->vdd_dep_on_mclk) {
1290                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1291                                 table_info->vdd_dep_on_mclk, clock,
1292                                 &mem_level->MinVoltage, &mem_level->MinMvdd);
1293                 PP_ASSERT_WITH_CODE((0 == result),
1294                                 "can not find MinVddc voltage value from memory "
1295                                 "VDDC voltage dependency table", return result);
1296         }
1297
1298         mem_level->MclkFrequency = clock;
1299         mem_level->EnabledForThrottle = 1;
1300         mem_level->EnabledForActivity = 0;
1301         mem_level->UpHyst = 0;
1302         mem_level->DownHyst = 100;
1303         mem_level->VoltageDownHyst = 0;
1304         mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1305         mem_level->StutterEnable = false;
1306         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1307
1308         data->display_timing.num_existing_displays = info.display_count;
1309
1310         if ((data->mclk_stutter_mode_threshold) &&
1311                 (clock <= data->mclk_stutter_mode_threshold) &&
1312                 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1313                                 STUTTER_ENABLE) & 0x1))
1314                 mem_level->StutterEnable = true;
1315
1316         if (!result) {
1317                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1318                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1319                 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1320                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1321         }
1322         return result;
1323 }
1324
1325 /**
1326 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1327 *
1328 * @param    hwmgr      the address of the hardware manager
1329 */
1330 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1331 {
1332         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1333         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1334         int result;
1335         /* populate MCLK dpm table to SMU7 */
1336         uint32_t array = data->dpm_table_start +
1337                         offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1338         uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1339                         SMU74_MAX_LEVELS_MEMORY;
1340         struct SMU74_Discrete_MemoryLevel *levels =
1341                         data->smc_state_table.MemoryLevel;
1342         uint32_t i;
1343
1344         for (i = 0; i < dpm_table->mclk_table.count; i++) {
1345                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1346                                 "can not populate memory level as memory clock is zero",
1347                                 return -EINVAL);
1348                 result = polaris10_populate_single_memory_level(hwmgr,
1349                                 dpm_table->mclk_table.dpm_levels[i].value,
1350                                 &levels[i]);
1351                 if (i == dpm_table->mclk_table.count - 1) {
1352                         levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1353                         levels[i].EnabledForActivity = 1;
1354                 }
1355                 if (result)
1356                         return result;
1357         }
1358
1359         /* in order to prevent MC activity from stutter mode to push DPM up.
1360          * the UVD change complements this by putting the MCLK in
1361          * a higher state by default such that we are not effected by
1362          * up threshold or and MCLK DPM latency.
1363          */
1364         levels[0].ActivityLevel = 0x1f;
1365         CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1366
1367         data->smc_state_table.MemoryDpmLevelCount =
1368                         (uint8_t)dpm_table->mclk_table.count;
1369         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1370                         phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1371
1372         /* level count will send to smc once at init smc table and never change */
1373         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1374                         (uint32_t)array_size, data->sram_end);
1375
1376         return result;
1377 }
1378
1379 /**
1380 * Populates the SMC MVDD structure using the provided memory clock.
1381 *
1382 * @param    hwmgr      the address of the hardware manager
1383 * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
1384 * @param    voltage     the SMC VOLTAGE structure to be populated
1385 */
1386 int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1387                 uint32_t mclk, SMIO_Pattern *smio_pat)
1388 {
1389         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1390         struct phm_ppt_v1_information *table_info =
1391                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1392         uint32_t i = 0;
1393
1394         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1395                 /* find mvdd value which clock is more than request */
1396                 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1397                         if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1398                                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1399                                 break;
1400                         }
1401                 }
1402                 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1403                                 "MVDD Voltage is outside the supported range.",
1404                                 return -EINVAL);
1405         } else
1406                 return -EINVAL;
1407
1408         return 0;
1409 }
1410
1411 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1412                 SMU74_Discrete_DpmTable *table)
1413 {
1414         int result = 0;
1415         uint32_t sclk_frequency;
1416         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1417         struct phm_ppt_v1_information *table_info =
1418                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1419         SMIO_Pattern vol_level;
1420         uint32_t mvdd;
1421         uint16_t us_mvdd;
1422
1423         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1424
1425         if (!data->sclk_dpm_key_disabled) {
1426                 /* Get MinVoltage and Frequency from DPM0,
1427                  * already converted to SMC_UL */
1428                 sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1429                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1430                                 table_info->vdd_dep_on_sclk,
1431                                 table->ACPILevel.SclkFrequency,
1432                                 &table->ACPILevel.MinVoltage, &mvdd);
1433                 PP_ASSERT_WITH_CODE((0 == result),
1434                                 "Cannot find ACPI VDDC voltage value "
1435                                 "in Clock Dependency Table", );
1436         } else {
1437                 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1438                 table->ACPILevel.MinVoltage =
1439                                 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1440         }
1441
1442         result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
1443         PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1444
1445         table->ACPILevel.DeepSleepDivId = 0;
1446         table->ACPILevel.CcPwrDynRm = 0;
1447         table->ACPILevel.CcPwrDynRm1 = 0;
1448
1449         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1450         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1451         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1452         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1453
1454         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1455         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1456         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1457         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1458         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1459         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1460         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1461         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1462         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1463         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1464
1465         if (!data->mclk_dpm_key_disabled) {
1466                 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1467                 table->MemoryACPILevel.MclkFrequency =
1468                                 data->dpm_table.mclk_table.dpm_levels[0].value;
1469                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1470                                 table_info->vdd_dep_on_mclk,
1471                                 table->MemoryACPILevel.MclkFrequency,
1472                                 &table->MemoryACPILevel.MinVoltage, &mvdd);
1473                 PP_ASSERT_WITH_CODE((0 == result),
1474                                 "Cannot find ACPI VDDCI voltage value "
1475                                 "in Clock Dependency Table",
1476                                 );
1477         } else {
1478                 table->MemoryACPILevel.MclkFrequency =
1479                                 data->vbios_boot_state.mclk_bootup_value;
1480                 table->MemoryACPILevel.MinVoltage =
1481                                 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1482         }
1483
1484         us_mvdd = 0;
1485         if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1486                         (data->mclk_dpm_key_disabled))
1487                 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1488         else {
1489                 if (!polaris10_populate_mvdd_value(hwmgr,
1490                                 data->dpm_table.mclk_table.dpm_levels[0].value,
1491                                 &vol_level))
1492                         us_mvdd = vol_level.Voltage;
1493         }
1494
1495         if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1496                 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1497         else
1498                 table->MemoryACPILevel.MinMvdd = 0;
1499
1500         table->MemoryACPILevel.StutterEnable = false;
1501
1502         table->MemoryACPILevel.EnabledForThrottle = 0;
1503         table->MemoryACPILevel.EnabledForActivity = 0;
1504         table->MemoryACPILevel.UpHyst = 0;
1505         table->MemoryACPILevel.DownHyst = 100;
1506         table->MemoryACPILevel.VoltageDownHyst = 0;
1507         table->MemoryACPILevel.ActivityLevel =
1508                         PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1509
1510         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1511         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1512
1513         return result;
1514 }
1515
1516 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1517                 SMU74_Discrete_DpmTable *table)
1518 {
1519         int result = -EINVAL;
1520         uint8_t count;
1521         struct pp_atomctrl_clock_dividers_vi dividers;
1522         struct phm_ppt_v1_information *table_info =
1523                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1524         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1525                         table_info->mm_dep_table;
1526         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1527
1528         table->VceLevelCount = (uint8_t)(mm_table->count);
1529         table->VceBootLevel = 0;
1530
1531         for (count = 0; count < table->VceLevelCount; count++) {
1532                 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1533                 table->VceLevel[count].MinVoltage = 0;
1534                 table->VceLevel[count].MinVoltage |=
1535                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1536                 table->VceLevel[count].MinVoltage |=
1537                                 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
1538                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1539                 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1540
1541                 /*retrieve divider value for VBIOS */
1542                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1543                                 table->VceLevel[count].Frequency, &dividers);
1544                 PP_ASSERT_WITH_CODE((0 == result),
1545                                 "can not find divide id for VCE engine clock",
1546                                 return result);
1547
1548                 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1549
1550                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1551                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1552         }
1553         return result;
1554 }
1555
1556 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1557                 SMU74_Discrete_DpmTable *table)
1558 {
1559         int result = -EINVAL;
1560         uint8_t count;
1561         struct pp_atomctrl_clock_dividers_vi dividers;
1562         struct phm_ppt_v1_information *table_info =
1563                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1564         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1565                         table_info->mm_dep_table;
1566         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1567
1568         table->SamuBootLevel = 0;
1569         table->SamuLevelCount = (uint8_t)(mm_table->count);
1570
1571         for (count = 0; count < table->SamuLevelCount; count++) {
1572                 /* not sure whether we need evclk or not */
1573                 table->SamuLevel[count].MinVoltage = 0;
1574                 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1575                 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1576                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1577                 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1578                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1579                 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1580
1581                 /* retrieve divider value for VBIOS */
1582                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1583                                 table->SamuLevel[count].Frequency, &dividers);
1584                 PP_ASSERT_WITH_CODE((0 == result),
1585                                 "can not find divide id for samu clock", return result);
1586
1587                 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1588
1589                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1590                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1591         }
1592         return result;
1593 }
1594
1595 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1596                 int32_t eng_clock, int32_t mem_clock,
1597                 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1598 {
1599         uint32_t dram_timing;
1600         uint32_t dram_timing2;
1601         uint32_t burst_time;
1602         int result;
1603
1604         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1605                         eng_clock, mem_clock);
1606         PP_ASSERT_WITH_CODE(result == 0,
1607                         "Error calling VBIOS to set DRAM_TIMING.", return result);
1608
1609         dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1610         dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1611         burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1612
1613
1614         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
1615         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1616         arb_regs->McArbBurstTime   = (uint8_t)burst_time;
1617
1618         return 0;
1619 }
1620
1621 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1622 {
1623         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1624         struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1625         uint32_t i, j;
1626         int result = 0;
1627
1628         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1629                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1630                         result = polaris10_populate_memory_timing_parameters(hwmgr,
1631                                         data->dpm_table.sclk_table.dpm_levels[i].value,
1632                                         data->dpm_table.mclk_table.dpm_levels[j].value,
1633                                         &arb_regs.entries[i][j]);
1634                         if (result == 0)
1635                                 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1636                         if (result != 0)
1637                                 return result;
1638                 }
1639         }
1640
1641         result = polaris10_copy_bytes_to_smc(
1642                         hwmgr->smumgr,
1643                         data->arb_table_start,
1644                         (uint8_t *)&arb_regs,
1645                         sizeof(SMU74_Discrete_MCArbDramTimingTable),
1646                         data->sram_end);
1647         return result;
1648 }
1649
1650 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1651                 struct SMU74_Discrete_DpmTable *table)
1652 {
1653         int result = -EINVAL;
1654         uint8_t count;
1655         struct pp_atomctrl_clock_dividers_vi dividers;
1656         struct phm_ppt_v1_information *table_info =
1657                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1658         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1659                         table_info->mm_dep_table;
1660         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1661
1662         table->UvdLevelCount = (uint8_t)(mm_table->count);
1663         table->UvdBootLevel = 0;
1664
1665         for (count = 0; count < table->UvdLevelCount; count++) {
1666                 table->UvdLevel[count].MinVoltage = 0;
1667                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1668                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1669                 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1670                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1671                 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1672                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1673                 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1674
1675                 /* retrieve divider value for VBIOS */
1676                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1677                                 table->UvdLevel[count].VclkFrequency, &dividers);
1678                 PP_ASSERT_WITH_CODE((0 == result),
1679                                 "can not find divide id for Vclk clock", return result);
1680
1681                 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1682
1683                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1684                                 table->UvdLevel[count].DclkFrequency, &dividers);
1685                 PP_ASSERT_WITH_CODE((0 == result),
1686                                 "can not find divide id for Dclk clock", return result);
1687
1688                 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1689
1690                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1691                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1692                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1693
1694         }
1695         return result;
1696 }
1697
1698 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1699                 struct SMU74_Discrete_DpmTable *table)
1700 {
1701         int result = 0;
1702         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1703
1704         table->GraphicsBootLevel = 0;
1705         table->MemoryBootLevel = 0;
1706
1707         /* find boot level from dpm table */
1708         result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1709                         data->vbios_boot_state.sclk_bootup_value,
1710                         (uint32_t *)&(table->GraphicsBootLevel));
1711
1712         result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1713                         data->vbios_boot_state.mclk_bootup_value,
1714                         (uint32_t *)&(table->MemoryBootLevel));
1715
1716         table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
1717                         VOLTAGE_SCALE;
1718         table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1719                         VOLTAGE_SCALE;
1720         table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
1721                         VOLTAGE_SCALE;
1722
1723         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1724         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1725         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1726
1727         return 0;
1728 }
1729
1730
1731 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1732 {
1733         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1734         struct phm_ppt_v1_information *table_info =
1735                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1736         uint8_t count, level;
1737
1738         count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1739
1740         for (level = 0; level < count; level++) {
1741                 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1742                                 data->vbios_boot_state.sclk_bootup_value) {
1743                         data->smc_state_table.GraphicsBootLevel = level;
1744                         break;
1745                 }
1746         }
1747
1748         count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1749         for (level = 0; level < count; level++) {
1750                 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1751                                 data->vbios_boot_state.mclk_bootup_value) {
1752                         data->smc_state_table.MemoryBootLevel = level;
1753                         break;
1754                 }
1755         }
1756
1757         return 0;
1758 }
1759
1760 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1761 {
1762         uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1763         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1764         uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
1765         struct phm_ppt_v1_information *table_info =
1766                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1767         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1768                         table_info->vdd_dep_on_sclk;
1769
1770         stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1771
1772         /* Read SMU_Eefuse to read and calculate RO and determine
1773          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1774          */
1775         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1776                         ixSMU_EFUSE_0 + (67 * 4));
1777         efuse &= 0xFF000000;
1778         efuse = efuse >> 24;
1779
1780         if (hwmgr->chip_id == CHIP_POLARIS10) {
1781                 min = 1000;
1782                 max = 2300;
1783         } else {
1784                 min = 1100;
1785                 max = 2100;
1786         }
1787
1788         ro = efuse * (max -min)/255 + min;
1789
1790         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1791         for (i = 0; i < sclk_table->count; i++) {
1792                 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1793                                 sclk_table->entries[i].cks_enable << i;
1794
1795                 volt_without_cks =  (uint32_t)(((ro - 40) * 1000 - 2753594 - sclk_table->entries[i].clk/100 * 136418 /1000) / \
1796                                         (sclk_table->entries[i].clk/100 * 1132925 /10000 - 242418)/100);
1797
1798                 volt_with_cks = (uint32_t)((ro * 1000 -2396351 - sclk_table->entries[i].clk/100 * 329021/1000) / \
1799                                 (sclk_table->entries[i].clk/10000 * 649434 /1000  - 18005)/10);
1800
1801                 if (volt_without_cks >= volt_with_cks)
1802                         volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1803                                         sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1804
1805                 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1806         }
1807
1808         data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
1809         /* Populate CKS Lookup Table */
1810         if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1811                 stretch_amount2 = 0;
1812         else if (stretch_amount == 3 || stretch_amount == 4)
1813                 stretch_amount2 = 1;
1814         else {
1815                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1816                                 PHM_PlatformCaps_ClockStretcher);
1817                 PP_ASSERT_WITH_CODE(false,
1818                                 "Stretch Amount in PPTable not supported\n",
1819                                 return -EINVAL);
1820         }
1821
1822         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1823         value &= 0xFFFFFFFE;
1824         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1825
1826         return 0;
1827 }
1828
1829 /**
1830 * Populates the SMC VRConfig field in DPM table.
1831 *
1832 * @param    hwmgr   the address of the hardware manager
1833 * @param    table   the SMC DPM table structure to be populated
1834 * @return   always 0
1835 */
1836 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1837                 struct SMU74_Discrete_DpmTable *table)
1838 {
1839         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1840         uint16_t config;
1841
1842         config = VR_MERGED_WITH_VDDC;
1843         table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1844
1845         /* Set Vddc Voltage Controller */
1846         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1847                 config = VR_SVI2_PLANE_1;
1848                 table->VRConfig |= config;
1849         } else {
1850                 PP_ASSERT_WITH_CODE(false,
1851                                 "VDDC should be on SVI2 control in merged mode!",
1852                                 );
1853         }
1854         /* Set Vddci Voltage Controller */
1855         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1856                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
1857                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1858         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1859                 config = VR_SMIO_PATTERN_1;
1860                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1861         } else {
1862                 config = VR_STATIC_VOLTAGE;
1863                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1864         }
1865         /* Set Mvdd Voltage Controller */
1866         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1867                 config = VR_SVI2_PLANE_2;
1868                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1869         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1870                 config = VR_SMIO_PATTERN_2;
1871                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1872         } else {
1873                 config = VR_STATIC_VOLTAGE;
1874                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1875         }
1876
1877         return 0;
1878 }
1879
1880
1881 int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1882 {
1883         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1884         SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
1885         int result = 0;
1886         struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1887         AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1888         AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1889         uint32_t tmp, i;
1890         struct pp_smumgr *smumgr = hwmgr->smumgr;
1891         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
1892
1893         struct phm_ppt_v1_information *table_info =
1894                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1895         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1896                         table_info->vdd_dep_on_sclk;
1897
1898
1899         if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
1900                 return result;
1901
1902         result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1903
1904         if (0 == result) {
1905                 table->BTCGB_VDROOP_TABLE[0].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1906                 table->BTCGB_VDROOP_TABLE[0].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1907                 table->BTCGB_VDROOP_TABLE[0].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1908                 table->BTCGB_VDROOP_TABLE[1].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1909                 table->BTCGB_VDROOP_TABLE[1].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1910                 table->BTCGB_VDROOP_TABLE[1].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1911                 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1912                 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1913                 table->AVFSGB_VDROOP_TABLE[0].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1914                 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1915                 table->AVFSGB_VDROOP_TABLE[0].m2_shift  = 12;
1916                 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1917                 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1918                 table->AVFSGB_VDROOP_TABLE[1].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1919                 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1920                 table->AVFSGB_VDROOP_TABLE[1].m2_shift  = 12;
1921                 table->MaxVoltage                = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1922                 AVFS_meanNsigma.Aconstant[0]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1923                 AVFS_meanNsigma.Aconstant[1]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1924                 AVFS_meanNsigma.Aconstant[2]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1925                 AVFS_meanNsigma.DC_tol_sigma      = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1926                 AVFS_meanNsigma.Platform_mean     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1927                 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1928                 AVFS_meanNsigma.Platform_sigma     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1929
1930                 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1931                         AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1932                         AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1933                 }
1934
1935                 result = polaris10_read_smc_sram_dword(smumgr,
1936                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1937                                 &tmp, data->sram_end);
1938
1939                 polaris10_copy_bytes_to_smc(smumgr,
1940                                         tmp,
1941                                         (uint8_t *)&AVFS_meanNsigma,
1942                                         sizeof(AVFS_meanNsigma_t),
1943                                         data->sram_end);
1944
1945                 result = polaris10_read_smc_sram_dword(smumgr,
1946                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1947                                 &tmp, data->sram_end);
1948                 polaris10_copy_bytes_to_smc(smumgr,
1949                                         tmp,
1950                                         (uint8_t *)&AVFS_SclkOffset,
1951                                         sizeof(AVFS_Sclk_Offset_t),
1952                                         data->sram_end);
1953
1954                 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1955                                                 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1956                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1957                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1958                 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1959         }
1960         return result;
1961 }
1962
1963
1964 /**
1965 * Initializes the SMC table and uploads it
1966 *
1967 * @param    hwmgr  the address of the powerplay hardware manager.
1968 * @return   always 0
1969 */
1970 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1971 {
1972         int result;
1973         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1974         struct phm_ppt_v1_information *table_info =
1975                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1976         struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1977         const struct polaris10_ulv_parm *ulv = &(data->ulv);
1978         uint8_t i;
1979         struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1980         pp_atomctrl_clock_dividers_vi dividers;
1981
1982         result = polaris10_setup_default_dpm_tables(hwmgr);
1983         PP_ASSERT_WITH_CODE(0 == result,
1984                         "Failed to setup default DPM tables!", return result);
1985
1986         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
1987                 polaris10_populate_smc_voltage_tables(hwmgr, table);
1988
1989         table->SystemFlags = 0;
1990         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1991                         PHM_PlatformCaps_AutomaticDCTransition))
1992                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1993
1994         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1995                         PHM_PlatformCaps_StepVddc))
1996                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1997
1998         if (data->is_memory_gddr5)
1999                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2000
2001         if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2002                 result = polaris10_populate_ulv_state(hwmgr, table);
2003                 PP_ASSERT_WITH_CODE(0 == result,
2004                                 "Failed to initialize ULV state!", return result);
2005                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2006                                 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
2007         }
2008
2009         result = polaris10_populate_smc_link_level(hwmgr, table);
2010         PP_ASSERT_WITH_CODE(0 == result,
2011                         "Failed to initialize Link Level!", return result);
2012
2013         result = polaris10_populate_all_graphic_levels(hwmgr);
2014         PP_ASSERT_WITH_CODE(0 == result,
2015                         "Failed to initialize Graphics Level!", return result);
2016
2017         result = polaris10_populate_all_memory_levels(hwmgr);
2018         PP_ASSERT_WITH_CODE(0 == result,
2019                         "Failed to initialize Memory Level!", return result);
2020
2021         result = polaris10_populate_smc_acpi_level(hwmgr, table);
2022         PP_ASSERT_WITH_CODE(0 == result,
2023                         "Failed to initialize ACPI Level!", return result);
2024
2025         result = polaris10_populate_smc_vce_level(hwmgr, table);
2026         PP_ASSERT_WITH_CODE(0 == result,
2027                         "Failed to initialize VCE Level!", return result);
2028
2029         result = polaris10_populate_smc_samu_level(hwmgr, table);
2030         PP_ASSERT_WITH_CODE(0 == result,
2031                         "Failed to initialize SAMU Level!", return result);
2032
2033         /* Since only the initial state is completely set up at this point
2034          * (the other states are just copies of the boot state) we only
2035          * need to populate the  ARB settings for the initial state.
2036          */
2037         result = polaris10_program_memory_timing_parameters(hwmgr);
2038         PP_ASSERT_WITH_CODE(0 == result,
2039                         "Failed to Write ARB settings for the initial state.", return result);
2040
2041         result = polaris10_populate_smc_uvd_level(hwmgr, table);
2042         PP_ASSERT_WITH_CODE(0 == result,
2043                         "Failed to initialize UVD Level!", return result);
2044
2045         result = polaris10_populate_smc_boot_level(hwmgr, table);
2046         PP_ASSERT_WITH_CODE(0 == result,
2047                         "Failed to initialize Boot Level!", return result);
2048
2049         result = polaris10_populate_smc_initailial_state(hwmgr);
2050         PP_ASSERT_WITH_CODE(0 == result,
2051                         "Failed to initialize Boot State!", return result);
2052
2053         result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
2054         PP_ASSERT_WITH_CODE(0 == result,
2055                         "Failed to populate BAPM Parameters!", return result);
2056
2057         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2058                         PHM_PlatformCaps_ClockStretcher)) {
2059                 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2060                 PP_ASSERT_WITH_CODE(0 == result,
2061                                 "Failed to populate Clock Stretcher Data Table!",
2062                                 return result);
2063         }
2064
2065         result = polaris10_populate_avfs_parameters(hwmgr);
2066         PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
2067
2068         table->CurrSclkPllRange = 0xff;
2069         table->GraphicsVoltageChangeEnable  = 1;
2070         table->GraphicsThermThrottleEnable  = 1;
2071         table->GraphicsInterval = 1;
2072         table->VoltageInterval  = 1;
2073         table->ThermalInterval  = 1;
2074         table->TemperatureLimitHigh =
2075                         table_info->cac_dtp_table->usTargetOperatingTemp *
2076                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2077         table->TemperatureLimitLow  =
2078                         (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2079                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2080         table->MemoryVoltageChangeEnable = 1;
2081         table->MemoryInterval = 1;
2082         table->VoltageResponseTime = 0;
2083         table->PhaseResponseTime = 0;
2084         table->MemoryThermThrottleEnable = 1;
2085         table->PCIeBootLinkLevel = 0;
2086         table->PCIeGenInterval = 1;
2087         table->VRConfig = 0;
2088
2089         result = polaris10_populate_vr_config(hwmgr, table);
2090         PP_ASSERT_WITH_CODE(0 == result,
2091                         "Failed to populate VRConfig setting!", return result);
2092
2093         table->ThermGpio = 17;
2094         table->SclkStepSize = 0x4000;
2095
2096         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2097                 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2098         } else {
2099                 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
2100                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2101                                 PHM_PlatformCaps_RegulatorHot);
2102         }
2103
2104         if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2105                         &gpio_pin)) {
2106                 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2107                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2108                                 PHM_PlatformCaps_AutomaticDCTransition);
2109         } else {
2110                 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
2111                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2112                                 PHM_PlatformCaps_AutomaticDCTransition);
2113         }
2114
2115         /* Thermal Output GPIO */
2116         if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2117                         &gpio_pin)) {
2118                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2119                                 PHM_PlatformCaps_ThermalOutGPIO);
2120
2121                 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2122
2123                 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2124                  * since VBIOS will program this register to set 'inactive state',
2125                  * driver can then determine 'active state' from this and
2126                  * program SMU with correct polarity
2127                  */
2128                 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2129                                         & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2130                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2131
2132                 /* if required, combine VRHot/PCC with thermal out GPIO */
2133                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2134                 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2135                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2136         } else {
2137                 table->ThermOutGpio = 17;
2138                 table->ThermOutPolarity = 1;
2139                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2140         }
2141
2142         /* Populate BIF_SCLK levels into SMC DPM table */
2143         for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2144                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
2145                 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2146
2147                 if (i == 0)
2148                         table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2149                 else
2150                         table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2151         }
2152
2153         for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2154                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2155
2156         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2157         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2158         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2159         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2160         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2161         CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2162         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2163         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2164         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2165         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2166
2167         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2168         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
2169                         data->dpm_table_start +
2170                         offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2171                         (uint8_t *)&(table->SystemFlags),
2172                         sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2173                         data->sram_end);
2174         PP_ASSERT_WITH_CODE(0 == result,
2175                         "Failed to upload dpm data to SMC memory!", return result);
2176
2177         return 0;
2178 }
2179
2180 /**
2181 * Initialize the ARB DRAM timing table's index field.
2182 *
2183 * @param    hwmgr  the address of the powerplay hardware manager.
2184 * @return   always 0
2185 */
2186 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
2187 {
2188         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2189         uint32_t tmp;
2190         int result;
2191
2192         /* This is a read-modify-write on the first byte of the ARB table.
2193          * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2194          * is the field 'current'.
2195          * This solution is ugly, but we never write the whole table only
2196          * individual fields in it.
2197          * In reality this field should not be in that structure
2198          * but in a soft register.
2199          */
2200         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
2201                         data->arb_table_start, &tmp, data->sram_end);
2202
2203         if (result)
2204                 return result;
2205
2206         tmp &= 0x00FFFFFF;
2207         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2208
2209         return polaris10_write_smc_sram_dword(hwmgr->smumgr,
2210                         data->arb_table_start, tmp, data->sram_end);
2211 }
2212
2213 static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
2214 {
2215         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2216                         PHM_PlatformCaps_RegulatorHot))
2217                 return smum_send_msg_to_smc(hwmgr->smumgr,
2218                                 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2219
2220         return 0;
2221 }
2222
2223 static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
2224 {
2225         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2226                         SCLK_PWRMGT_OFF, 0);
2227         return 0;
2228 }
2229
2230 static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
2231 {
2232         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2233         struct polaris10_ulv_parm *ulv = &(data->ulv);
2234
2235         if (ulv->ulv_supported)
2236                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2237
2238         return 0;
2239 }
2240
2241 static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2242 {
2243         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2244                         PHM_PlatformCaps_SclkDeepSleep)) {
2245                 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2246                         PP_ASSERT_WITH_CODE(false,
2247                                         "Attempt to enable Master Deep Sleep switch failed!",
2248                                         return -1);
2249         } else {
2250                 if (smum_send_msg_to_smc(hwmgr->smumgr,
2251                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2252                         PP_ASSERT_WITH_CODE(false,
2253                                         "Attempt to disable Master Deep Sleep switch failed!",
2254                                         return -1);
2255                 }
2256         }
2257
2258         return 0;
2259 }
2260
2261 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2262 {
2263         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2264         uint32_t soft_register_value = 0;
2265         uint32_t handshake_disables_offset = data->soft_regs_start
2266                                 + offsetof(SMU74_SoftRegisters, HandshakeDisables);
2267
2268         /* enable SCLK dpm */
2269         if (!data->sclk_dpm_key_disabled)
2270                 PP_ASSERT_WITH_CODE(
2271                 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2272                 "Failed to enable SCLK DPM during DPM Start Function!",
2273                 return -1);
2274
2275         /* enable MCLK dpm */
2276         if (0 == data->mclk_dpm_key_disabled) {
2277 /* Disable UVD - SMU handshake for MCLK. */
2278                 soft_register_value = cgs_read_ind_register(hwmgr->device,
2279                                         CGS_IND_REG__SMC, handshake_disables_offset);
2280                 soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2281                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2282                                 handshake_disables_offset, soft_register_value);
2283
2284                 PP_ASSERT_WITH_CODE(
2285                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2286                                                 PPSMC_MSG_MCLKDPM_Enable)),
2287                                 "Failed to enable MCLK DPM during DPM Start Function!",
2288                                 return -1);
2289
2290                 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2291
2292                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2293                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2294                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2295                 udelay(10);
2296                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2297                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2298                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2299         }
2300
2301         return 0;
2302 }
2303
2304 static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
2305 {
2306         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2307
2308         /*enable general power management */
2309
2310         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2311                         GLOBAL_PWRMGT_EN, 1);
2312
2313         /* enable sclk deep sleep */
2314
2315         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2316                         DYNAMIC_PM_EN, 1);
2317
2318         /* prepare for PCIE DPM */
2319
2320         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2321                         data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2322                                         VoltageChangeTimeout), 0x1000);
2323         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2324                         SWRST_COMMAND_1, RESETLC, 0x0);
2325 /*
2326         PP_ASSERT_WITH_CODE(
2327                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2328                                         PPSMC_MSG_Voltage_Cntl_Enable)),
2329                         "Failed to enable voltage DPM during DPM Start Function!",
2330                         return -1);
2331 */
2332
2333         if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
2334                 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2335                 return -1;
2336         }
2337
2338         /* enable PCIE dpm */
2339         if (0 == data->pcie_dpm_key_disabled) {
2340                 PP_ASSERT_WITH_CODE(
2341                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2342                                                 PPSMC_MSG_PCIeDPM_Enable)),
2343                                 "Failed to enable pcie DPM during DPM Start Function!",
2344                                 return -1);
2345         }
2346
2347         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2348                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
2349                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2350                                 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2351                                 "Failed to enable AC DC GPIO Interrupt!",
2352                                 );
2353         }
2354
2355         return 0;
2356 }
2357
2358 static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
2359 {
2360         bool protection;
2361         enum DPM_EVENT_SRC src;
2362
2363         switch (sources) {
2364         default:
2365                 printk(KERN_ERR "Unknown throttling event sources.");
2366                 /* fall through */
2367         case 0:
2368                 protection = false;
2369                 /* src is unused */
2370                 break;
2371         case (1 << PHM_AutoThrottleSource_Thermal):
2372                 protection = true;
2373                 src = DPM_EVENT_SRC_DIGITAL;
2374                 break;
2375         case (1 << PHM_AutoThrottleSource_External):
2376                 protection = true;
2377                 src = DPM_EVENT_SRC_EXTERNAL;
2378                 break;
2379         case (1 << PHM_AutoThrottleSource_External) |
2380                         (1 << PHM_AutoThrottleSource_Thermal):
2381                 protection = true;
2382                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2383                 break;
2384         }
2385         /* Order matters - don't enable thermal protection for the wrong source. */
2386         if (protection) {
2387                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2388                                 DPM_EVENT_SRC, src);
2389                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2390                                 THERMAL_PROTECTION_DIS,
2391                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2392                                                 PHM_PlatformCaps_ThermalController));
2393         } else
2394                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2395                                 THERMAL_PROTECTION_DIS, 1);
2396 }
2397
2398 static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2399                 PHM_AutoThrottleSource source)
2400 {
2401         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2402
2403         if (!(data->active_auto_throttle_sources & (1 << source))) {
2404                 data->active_auto_throttle_sources |= 1 << source;
2405                 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2406         }
2407         return 0;
2408 }
2409
2410 static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2411 {
2412         return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2413 }
2414
2415 int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
2416 {
2417         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2418         data->pcie_performance_request = true;
2419
2420         return 0;
2421 }
2422
2423 int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2424 {
2425         int tmp_result, result = 0;
2426         tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2427         PP_ASSERT_WITH_CODE(result == 0,
2428                         "DPM is already running right now, no need to enable DPM!",
2429                         return 0);
2430
2431         if (polaris10_voltage_control(hwmgr)) {
2432                 tmp_result = polaris10_enable_voltage_control(hwmgr);
2433                 PP_ASSERT_WITH_CODE(tmp_result == 0,
2434                                 "Failed to enable voltage control!",
2435                                 result = tmp_result);
2436
2437                 tmp_result = polaris10_construct_voltage_tables(hwmgr);
2438                 PP_ASSERT_WITH_CODE((0 == tmp_result),
2439                                 "Failed to contruct voltage tables!",
2440                                 result = tmp_result);
2441         }
2442
2443         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2444                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2445                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2446                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2447
2448         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2449                         PHM_PlatformCaps_ThermalController))
2450                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2451                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2452
2453         tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
2454         PP_ASSERT_WITH_CODE((0 == tmp_result),
2455                         "Failed to program static screen threshold parameters!",
2456                         result = tmp_result);
2457
2458         tmp_result = polaris10_enable_display_gap(hwmgr);
2459         PP_ASSERT_WITH_CODE((0 == tmp_result),
2460                         "Failed to enable display gap!", result = tmp_result);
2461
2462         tmp_result = polaris10_program_voting_clients(hwmgr);
2463         PP_ASSERT_WITH_CODE((0 == tmp_result),
2464                         "Failed to program voting clients!", result = tmp_result);
2465
2466         tmp_result = polaris10_process_firmware_header(hwmgr);
2467         PP_ASSERT_WITH_CODE((0 == tmp_result),
2468                         "Failed to process firmware header!", result = tmp_result);
2469
2470         tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
2471         PP_ASSERT_WITH_CODE((0 == tmp_result),
2472                         "Failed to initialize switch from ArbF0 to F1!",
2473                         result = tmp_result);
2474
2475         tmp_result = polaris10_init_smc_table(hwmgr);
2476         PP_ASSERT_WITH_CODE((0 == tmp_result),
2477                         "Failed to initialize SMC table!", result = tmp_result);
2478
2479         tmp_result = polaris10_init_arb_table_index(hwmgr);
2480         PP_ASSERT_WITH_CODE((0 == tmp_result),
2481                         "Failed to initialize ARB table index!", result = tmp_result);
2482
2483         tmp_result = polaris10_populate_pm_fuses(hwmgr);
2484         PP_ASSERT_WITH_CODE((0 == tmp_result),
2485                         "Failed to populate PM fuses!", result = tmp_result);
2486
2487         tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
2488         PP_ASSERT_WITH_CODE((0 == tmp_result),
2489                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2490
2491         smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay);
2492
2493         tmp_result = polaris10_enable_sclk_control(hwmgr);
2494         PP_ASSERT_WITH_CODE((0 == tmp_result),
2495                         "Failed to enable SCLK control!", result = tmp_result);
2496
2497         tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
2498         PP_ASSERT_WITH_CODE((0 == tmp_result),
2499                         "Failed to enable voltage control!", result = tmp_result);
2500
2501         tmp_result = polaris10_enable_ulv(hwmgr);
2502         PP_ASSERT_WITH_CODE((0 == tmp_result),
2503                         "Failed to enable ULV!", result = tmp_result);
2504
2505         tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
2506         PP_ASSERT_WITH_CODE((0 == tmp_result),
2507                         "Failed to enable deep sleep master switch!", result = tmp_result);
2508
2509         tmp_result = polaris10_start_dpm(hwmgr);
2510         PP_ASSERT_WITH_CODE((0 == tmp_result),
2511                         "Failed to start DPM!", result = tmp_result);
2512
2513         tmp_result = polaris10_enable_smc_cac(hwmgr);
2514         PP_ASSERT_WITH_CODE((0 == tmp_result),
2515                         "Failed to enable SMC CAC!", result = tmp_result);
2516
2517         tmp_result = polaris10_enable_power_containment(hwmgr);
2518         PP_ASSERT_WITH_CODE((0 == tmp_result),
2519                         "Failed to enable power containment!", result = tmp_result);
2520
2521         tmp_result = polaris10_power_control_set_level(hwmgr);
2522         PP_ASSERT_WITH_CODE((0 == tmp_result),
2523                         "Failed to power control set level!", result = tmp_result);
2524
2525         tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
2526         PP_ASSERT_WITH_CODE((0 == tmp_result),
2527                         "Failed to enable thermal auto throttle!", result = tmp_result);
2528
2529         tmp_result = polaris10_pcie_performance_request(hwmgr);
2530         PP_ASSERT_WITH_CODE((0 == tmp_result),
2531                         "pcie performance request failed!", result = tmp_result);
2532
2533         return result;
2534 }
2535
2536 int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2537 {
2538
2539         return 0;
2540 }
2541
2542 int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
2543 {
2544
2545         return 0;
2546 }
2547
2548 int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2549 {
2550         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2551
2552         if (data->soft_pp_table) {
2553                 kfree(data->soft_pp_table);
2554                 data->soft_pp_table = NULL;
2555         }
2556
2557         return phm_hwmgr_backend_fini(hwmgr);
2558 }
2559
2560 int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
2561 {
2562         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2563
2564         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2565                         PHM_PlatformCaps_SclkDeepSleep);
2566
2567         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2568                 PHM_PlatformCaps_DynamicPatchPowerState);
2569
2570         if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2571                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2572                                 PHM_PlatformCaps_EnableMVDDControl);
2573
2574         if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2575                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2576                                 PHM_PlatformCaps_ControlVDDCI);
2577
2578         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2579                          PHM_PlatformCaps_TablelessHardwareInterface);
2580
2581         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2582                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
2583
2584         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2585                         PHM_PlatformCaps_DynamicPowerManagement);
2586
2587         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2588                         PHM_PlatformCaps_UnTabledHardwareInterface);
2589
2590         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2591                         PHM_PlatformCaps_TablelessHardwareInterface);
2592
2593         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2594                                         PHM_PlatformCaps_SMC);
2595
2596         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2597                                         PHM_PlatformCaps_NonABMSupportInPPLib);
2598
2599         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2600                                         PHM_PlatformCaps_DynamicUVDState);
2601
2602         /* power tune caps Assume disabled */
2603         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2604                                                 PHM_PlatformCaps_SQRamping);
2605         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2606                                                 PHM_PlatformCaps_DBRamping);
2607         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2608                                                 PHM_PlatformCaps_TDRamping);
2609         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2610                                                 PHM_PlatformCaps_TCPRamping);
2611
2612         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2613                                         PHM_PlatformCaps_PowerContainment);
2614         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2615                                                         PHM_PlatformCaps_CAC);
2616
2617         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2618                                                 PHM_PlatformCaps_RegulatorHot);
2619
2620         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2621                                                 PHM_PlatformCaps_AutomaticDCTransition);
2622
2623         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2624                                                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2625
2626         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2627                                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
2628
2629         if (hwmgr->chip_id == CHIP_POLARIS11)
2630                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2631                                         PHM_PlatformCaps_SPLLShutdownSupport);
2632         return 0;
2633 }
2634
2635 static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
2636 {
2637         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2638
2639         polaris10_initialize_power_tune_defaults(hwmgr);
2640
2641         data->pcie_gen_performance.max = PP_PCIEGen1;
2642         data->pcie_gen_performance.min = PP_PCIEGen3;
2643         data->pcie_gen_power_saving.max = PP_PCIEGen1;
2644         data->pcie_gen_power_saving.min = PP_PCIEGen3;
2645         data->pcie_lane_performance.max = 0;
2646         data->pcie_lane_performance.min = 16;
2647         data->pcie_lane_power_saving.max = 0;
2648         data->pcie_lane_power_saving.min = 16;
2649 }
2650
2651 /**
2652 * Get Leakage VDDC based on leakage ID.
2653 *
2654 * @param    hwmgr  the address of the powerplay hardware manager.
2655 * @return   always 0
2656 */
2657 static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
2658 {
2659         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2660         uint16_t vv_id;
2661         uint16_t vddc = 0;
2662         uint16_t i, j;
2663         uint32_t sclk = 0;
2664         struct phm_ppt_v1_information *table_info =
2665                         (struct phm_ppt_v1_information *)hwmgr->pptable;
2666         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2667                         table_info->vdd_dep_on_sclk;
2668         int result;
2669
2670         for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
2671                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2672                 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2673                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
2674                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2675                                         PHM_PlatformCaps_ClockStretcher)) {
2676                                 for (j = 1; j < sclk_table->count; j++) {
2677                                         if (sclk_table->entries[j].clk == sclk &&
2678                                                         sclk_table->entries[j].cks_enable == 0) {
2679                                                 sclk += 5000;
2680                                                 break;
2681                                         }
2682                                 }
2683                         }
2684
2685
2686                         PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2687                                                         VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
2688                                                 "Error retrieving EVV voltage value!",
2689                                                 continue);
2690
2691
2692                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
2693                         PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
2694                                         "Invalid VDDC value", result = -EINVAL;);
2695
2696                         /* the voltage should not be zero nor equal to leakage ID */
2697                         if (vddc != 0 && vddc != vv_id) {
2698                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2699                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2700                                 data->vddc_leakage.count++;
2701                         }
2702                 }
2703         }
2704
2705         return 0;
2706 }
2707
2708 /**
2709  * Change virtual leakage voltage to actual value.
2710  *
2711  * @param     hwmgr  the address of the powerplay hardware manager.
2712  * @param     pointer to changing voltage
2713  * @param     pointer to leakage table
2714  */
2715 static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2716                 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
2717 {
2718         uint32_t index;
2719
2720         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2721         for (index = 0; index < leakage_table->count; index++) {
2722                 /* if this voltage matches a leakage voltage ID */
2723                 /* patch with actual leakage voltage */
2724                 if (leakage_table->leakage_id[index] == *voltage) {
2725                         *voltage = leakage_table->actual_voltage[index];
2726                         break;
2727                 }
2728         }
2729
2730         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2731                 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2732 }
2733
2734 /**
2735 * Patch voltage lookup table by EVV leakages.
2736 *
2737 * @param     hwmgr  the address of the powerplay hardware manager.
2738 * @param     pointer to voltage lookup table
2739 * @param     pointer to leakage table
2740 * @return     always 0
2741 */
2742 static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2743                 phm_ppt_v1_voltage_lookup_table *lookup_table,
2744                 struct polaris10_leakage_voltage *leakage_table)
2745 {
2746         uint32_t i;
2747
2748         for (i = 0; i < lookup_table->count; i++)
2749                 polaris10_patch_with_vdd_leakage(hwmgr,
2750                                 &lookup_table->entries[i].us_vdd, leakage_table);
2751
2752         return 0;
2753 }
2754
2755 static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2756                 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
2757                 uint16_t *vddc)
2758 {
2759         struct phm_ppt_v1_information *table_info =
2760                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2761         polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2762         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2763                         table_info->max_clock_voltage_on_dc.vddc;
2764         return 0;
2765 }
2766
2767 static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
2768                 struct pp_hwmgr *hwmgr)
2769 {
2770         uint8_t entryId;
2771         uint8_t voltageId;
2772         struct phm_ppt_v1_information *table_info =
2773                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2774
2775         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2776                         table_info->vdd_dep_on_sclk;
2777         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2778                         table_info->vdd_dep_on_mclk;
2779         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2780                         table_info->mm_dep_table;
2781
2782         for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2783                 voltageId = sclk_table->entries[entryId].vddInd;
2784                 sclk_table->entries[entryId].vddc =
2785                                 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2786         }
2787
2788         for (entryId = 0; entryId < mclk_table->count; ++entryId) {
2789                 voltageId = mclk_table->entries[entryId].vddInd;
2790                 mclk_table->entries[entryId].vddc =
2791                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2792         }
2793
2794         for (entryId = 0; entryId < mm_table->count; ++entryId) {
2795                 voltageId = mm_table->entries[entryId].vddcInd;
2796                 mm_table->entries[entryId].vddc =
2797                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2798         }
2799
2800         return 0;
2801
2802 }
2803
2804 static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
2805 {
2806         /* Need to determine if we need calculated voltage. */
2807         return 0;
2808 }
2809
2810 static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
2811 {
2812         /* Need to determine if we need calculated voltage from mm table. */
2813         return 0;
2814 }
2815
2816 static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
2817                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2818 {
2819         uint32_t table_size, i, j;
2820         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
2821         table_size = lookup_table->count;
2822
2823         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2824                 "Lookup table is empty", return -EINVAL);
2825
2826         /* Sorting voltages */
2827         for (i = 0; i < table_size - 1; i++) {
2828                 for (j = i + 1; j > 0; j--) {
2829                         if (lookup_table->entries[j].us_vdd <
2830                                         lookup_table->entries[j - 1].us_vdd) {
2831                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
2832                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
2833                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
2834                         }
2835                 }
2836         }
2837
2838         return 0;
2839 }
2840
2841 static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2842 {
2843         int result = 0;
2844         int tmp_result;
2845         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2846         struct phm_ppt_v1_information *table_info =
2847                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2848
2849         tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
2850                         table_info->vddc_lookup_table, &(data->vddc_leakage));
2851         if (tmp_result)
2852                 result = tmp_result;
2853
2854         tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2855                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2856         if (tmp_result)
2857                 result = tmp_result;
2858
2859         tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2860         if (tmp_result)
2861                 result = tmp_result;
2862
2863         tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
2864         if (tmp_result)
2865                 result = tmp_result;
2866
2867         tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
2868         if (tmp_result)
2869                 result = tmp_result;
2870
2871         tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2872         if (tmp_result)
2873                 result = tmp_result;
2874
2875         return result;
2876 }
2877
2878 static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
2879 {
2880         struct phm_ppt_v1_information *table_info =
2881                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2882
2883         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2884                                                 table_info->vdd_dep_on_sclk;
2885         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2886                                                 table_info->vdd_dep_on_mclk;
2887
2888         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2889                 "VDD dependency on SCLK table is missing.       \
2890                 This table is mandatory", return -EINVAL);
2891         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2892                 "VDD dependency on SCLK table has to have is missing.   \
2893                 This table is mandatory", return -EINVAL);
2894
2895         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2896                 "VDD dependency on MCLK table is missing.       \
2897                 This table is mandatory", return -EINVAL);
2898         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2899                 "VDD dependency on MCLK table has to have is missing.    \
2900                 This table is mandatory", return -EINVAL);
2901
2902         table_info->max_clock_voltage_on_ac.sclk =
2903                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2904         table_info->max_clock_voltage_on_ac.mclk =
2905                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2906         table_info->max_clock_voltage_on_ac.vddc =
2907                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2908         table_info->max_clock_voltage_on_ac.vddci =
2909                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2910
2911         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2912         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2913         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2914         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
2915
2916         return 0;
2917 }
2918
2919 int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2920 {
2921         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2922         struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2923         uint32_t temp_reg;
2924         int result;
2925         struct phm_ppt_v1_information *table_info =
2926                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2927
2928         data->dll_default_on = false;
2929         data->sram_end = SMC_RAM_END;
2930         data->mclk_dpm0_activity_target = 0xa;
2931         data->disable_dpm_mask = 0xFF;
2932         data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2933         data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2934         data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2935         data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2936         data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2937         data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2938         data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2939         data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2940         data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2941         data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2942
2943         data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
2944         data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
2945         data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
2946         data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
2947         data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
2948         data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
2949         data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
2950         data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
2951
2952         data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
2953
2954         data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
2955
2956         /* need to set voltage control types before EVV patching */
2957         data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2958         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2959         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2960
2961         data->enable_tdc_limit_feature = true;
2962         data->enable_pkg_pwr_tracking_feature = true;
2963         data->force_pcie_gen = PP_PCIEGenInvalid;
2964         data->mclk_stutter_mode_threshold = 40000;
2965
2966         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2967                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
2968                 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2969
2970         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2971                         PHM_PlatformCaps_EnableMVDDControl)) {
2972                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2973                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
2974                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
2975                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2976                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
2977                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2978         }
2979
2980         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2981                         PHM_PlatformCaps_ControlVDDCI)) {
2982                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2983                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
2984                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
2985                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2986                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
2987                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2988         }
2989
2990         if (table_info->cac_dtp_table->usClockStretchAmount != 0)
2991                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2992                                         PHM_PlatformCaps_ClockStretcher);
2993
2994         polaris10_set_features_platform_caps(hwmgr);
2995
2996         polaris10_init_dpm_defaults(hwmgr);
2997
2998         /* Get leakage voltage based on leakage ID. */
2999         result = polaris10_get_evv_voltages(hwmgr);
3000
3001         if (result) {
3002                 printk("Get EVV Voltage Failed.  Abort Driver loading!\n");
3003                 return -1;
3004         }
3005
3006         polaris10_complete_dependency_tables(hwmgr);
3007         polaris10_set_private_data_based_on_pptable(hwmgr);
3008
3009         /* Initalize Dynamic State Adjustment Rule Settings */
3010         result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
3011
3012         if (0 == result) {
3013                 struct cgs_system_info sys_info = {0};
3014
3015                 data->is_tlu_enabled = 0;
3016
3017                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
3018                                                         POLARIS10_MAX_HARDWARE_POWERLEVELS;
3019                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3020                 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
3021
3022
3023                 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
3024                         temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3025                         switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3026                         case 0:
3027                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3028                                 break;
3029                         case 1:
3030                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3031                                 break;
3032                         case 2:
3033                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3034                                 break;
3035                         case 3:
3036                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3037                                 break;
3038                         case 4:
3039                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3040                                 break;
3041                         default:
3042                                 PP_ASSERT_WITH_CODE(0,
3043                                 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3044                                 );
3045                                 break;
3046                         }
3047                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3048                 }
3049
3050                 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3051                         hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3052                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3053                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3054
3055                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3056                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3057
3058                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3059
3060                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3061
3062                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3063                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3064
3065                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3066
3067                         table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3068                                                                         (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3069
3070                         table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3071                         table_info->cac_dtp_table->usOperatingTempStep = 1;
3072                         table_info->cac_dtp_table->usOperatingTempHyst = 1;
3073
3074                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3075                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3076
3077                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3078                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3079
3080                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3081                                        table_info->cac_dtp_table->usOperatingTempMinLimit;
3082
3083                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3084                                        table_info->cac_dtp_table->usOperatingTempMaxLimit;
3085
3086                         hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3087                                        table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3088
3089                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3090                                        table_info->cac_dtp_table->usOperatingTempStep;
3091
3092                         hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3093                                        table_info->cac_dtp_table->usTargetOperatingTemp;
3094                 }
3095
3096                 sys_info.size = sizeof(struct cgs_system_info);
3097                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3098                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3099                 if (result)
3100                         data->pcie_gen_cap = 0x30007;
3101                 else
3102                         data->pcie_gen_cap = (uint32_t)sys_info.value;
3103                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3104                         data->pcie_spc_cap = 20;
3105                 sys_info.size = sizeof(struct cgs_system_info);
3106                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3107                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3108                 if (result)
3109                         data->pcie_lane_cap = 0x2f0000;
3110                 else
3111                         data->pcie_lane_cap = (uint32_t)sys_info.value;
3112
3113                 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3114 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3115                 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3116                 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
3117         } else {
3118                 /* Ignore return value in here, we are cleaning up a mess. */
3119                 polaris10_hwmgr_backend_fini(hwmgr);
3120         }
3121
3122         return 0;
3123 }
3124
3125 static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3126 {
3127         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3128         uint32_t level, tmp;
3129
3130         if (!data->pcie_dpm_key_disabled) {
3131                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3132                         level = 0;
3133                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3134                         while (tmp >>= 1)
3135                                 level++;
3136
3137                         if (level)
3138                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3139                                                 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3140                 }
3141         }
3142
3143         if (!data->sclk_dpm_key_disabled) {
3144                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3145                         level = 0;
3146                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3147                         while (tmp >>= 1)
3148                                 level++;
3149
3150                         if (level)
3151                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3152                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3153                                                 (1 << level));
3154                 }
3155         }
3156
3157         if (!data->mclk_dpm_key_disabled) {
3158                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3159                         level = 0;
3160                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3161                         while (tmp >>= 1)
3162                                 level++;
3163
3164                         if (level)
3165                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3166                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3167                                                 (1 << level));
3168                 }
3169         }
3170
3171         return 0;
3172 }
3173
3174 static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3175 {
3176         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3177
3178         phm_apply_dal_min_voltage_request(hwmgr);
3179
3180         if (!data->sclk_dpm_key_disabled) {
3181                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3182                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3183                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
3184                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3185         }
3186
3187         if (!data->mclk_dpm_key_disabled) {
3188                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3189                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3190                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
3191                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3192         }
3193
3194         return 0;
3195 }
3196
3197 static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3198 {
3199         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3200
3201         if (!polaris10_is_dpm_running(hwmgr))
3202                 return -EINVAL;
3203
3204         if (!data->pcie_dpm_key_disabled) {
3205                 smum_send_msg_to_smc(hwmgr->smumgr,
3206                                 PPSMC_MSG_PCIeDPM_UnForceLevel);
3207         }
3208
3209         return polaris10_upload_dpm_level_enable_mask(hwmgr);
3210 }
3211
3212 static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3213 {
3214         struct polaris10_hwmgr *data =
3215                         (struct polaris10_hwmgr *)(hwmgr->backend);
3216         uint32_t level;
3217
3218         if (!data->sclk_dpm_key_disabled)
3219                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3220                         level = phm_get_lowest_enabled_level(hwmgr,
3221                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3222                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3223                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
3224                                                             (1 << level));
3225
3226         }
3227
3228         if (!data->mclk_dpm_key_disabled) {
3229                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3230                         level = phm_get_lowest_enabled_level(hwmgr,
3231                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3232                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3233                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
3234                                                             (1 << level));
3235                 }
3236         }
3237
3238         if (!data->pcie_dpm_key_disabled) {
3239                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3240                         level = phm_get_lowest_enabled_level(hwmgr,
3241                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3242                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3243                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
3244                                                             (level));
3245                 }
3246         }
3247
3248         return 0;
3249
3250 }
3251 static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
3252                                 enum amd_dpm_forced_level level)
3253 {
3254         int ret = 0;
3255
3256         switch (level) {
3257         case AMD_DPM_FORCED_LEVEL_HIGH:
3258                 ret = polaris10_force_dpm_highest(hwmgr);
3259                 if (ret)
3260                         return ret;
3261                 break;
3262         case AMD_DPM_FORCED_LEVEL_LOW:
3263                 ret = polaris10_force_dpm_lowest(hwmgr);
3264                 if (ret)
3265                         return ret;
3266                 break;
3267         case AMD_DPM_FORCED_LEVEL_AUTO:
3268                 ret = polaris10_unforce_dpm_levels(hwmgr);
3269                 if (ret)
3270                         return ret;
3271                 break;
3272         default:
3273                 break;
3274         }
3275
3276         hwmgr->dpm_level = level;
3277
3278         return ret;
3279 }
3280
3281 static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
3282 {
3283         return sizeof(struct polaris10_power_state);
3284 }
3285
3286
3287 static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3288                                 struct pp_power_state *request_ps,
3289                         const struct pp_power_state *current_ps)
3290 {
3291
3292         struct polaris10_power_state *polaris10_ps =
3293                                 cast_phw_polaris10_power_state(&request_ps->hardware);
3294         uint32_t sclk;
3295         uint32_t mclk;
3296         struct PP_Clocks minimum_clocks = {0};
3297         bool disable_mclk_switching;
3298         bool disable_mclk_switching_for_frame_lock;
3299         struct cgs_display_info info = {0};
3300         const struct phm_clock_and_voltage_limits *max_limits;
3301         uint32_t i;
3302         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3303         struct phm_ppt_v1_information *table_info =
3304                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3305         int32_t count;
3306         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3307
3308         data->battery_state = (PP_StateUILabel_Battery ==
3309                         request_ps->classification.ui_label);
3310
3311         PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
3312                                  "VI should always have 2 performance levels",
3313                                 );
3314
3315         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3316                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3317                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3318
3319         /* Cap clock DPM tables at DC MAX if it is in DC. */
3320         if (PP_PowerSource_DC == hwmgr->power_source) {
3321                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3322                         if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3323                                 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3324                         if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3325                                 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
3326                 }
3327         }
3328
3329         polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3330         polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3331
3332         cgs_get_active_displays_info(hwmgr->device, &info);
3333
3334         /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3335
3336         /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3337
3338         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3339                         PHM_PlatformCaps_StablePState)) {
3340                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3341                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3342
3343                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3344                                 count >= 0; count--) {
3345                         if (stable_pstate_sclk >=
3346                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3347                                 stable_pstate_sclk =
3348                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3349                                 break;
3350                         }
3351                 }
3352
3353                 if (count < 0)
3354                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3355
3356                 stable_pstate_mclk = max_limits->mclk;
3357
3358                 minimum_clocks.engineClock = stable_pstate_sclk;
3359                 minimum_clocks.memoryClock = stable_pstate_mclk;
3360         }
3361
3362         if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3363                 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3364
3365         if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3366                 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3367
3368         polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3369
3370         if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3371                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3372                                 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3373                                 "Overdrive sclk exceeds limit",
3374                                 hwmgr->gfx_arbiter.sclk_over_drive =
3375                                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3376
3377                 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3378                         polaris10_ps->performance_levels[1].engine_clock =
3379                                         hwmgr->gfx_arbiter.sclk_over_drive;
3380         }
3381
3382         if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3383                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3384                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3385                                 "Overdrive mclk exceeds limit",
3386                                 hwmgr->gfx_arbiter.mclk_over_drive =
3387                                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3388
3389                 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3390                         polaris10_ps->performance_levels[1].memory_clock =
3391                                         hwmgr->gfx_arbiter.mclk_over_drive;
3392         }
3393
3394         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3395                                     hwmgr->platform_descriptor.platformCaps,
3396                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3397
3398         disable_mclk_switching = (1 < info.display_count) ||
3399                                     disable_mclk_switching_for_frame_lock;
3400
3401         sclk = polaris10_ps->performance_levels[0].engine_clock;
3402         mclk = polaris10_ps->performance_levels[0].memory_clock;
3403
3404         if (disable_mclk_switching)
3405                 mclk = polaris10_ps->performance_levels
3406                 [polaris10_ps->performance_level_count - 1].memory_clock;
3407
3408         if (sclk < minimum_clocks.engineClock)
3409                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3410                                 max_limits->sclk : minimum_clocks.engineClock;
3411
3412         if (mclk < minimum_clocks.memoryClock)
3413                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3414                                 max_limits->mclk : minimum_clocks.memoryClock;
3415
3416         polaris10_ps->performance_levels[0].engine_clock = sclk;
3417         polaris10_ps->performance_levels[0].memory_clock = mclk;
3418
3419         polaris10_ps->performance_levels[1].engine_clock =
3420                 (polaris10_ps->performance_levels[1].engine_clock >=
3421                                 polaris10_ps->performance_levels[0].engine_clock) ?
3422                                                 polaris10_ps->performance_levels[1].engine_clock :
3423                                                 polaris10_ps->performance_levels[0].engine_clock;
3424
3425         if (disable_mclk_switching) {
3426                 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3427                         mclk = polaris10_ps->performance_levels[1].memory_clock;
3428
3429                 polaris10_ps->performance_levels[0].memory_clock = mclk;
3430                 polaris10_ps->performance_levels[1].memory_clock = mclk;
3431         } else {
3432                 if (polaris10_ps->performance_levels[1].memory_clock <
3433                                 polaris10_ps->performance_levels[0].memory_clock)
3434                         polaris10_ps->performance_levels[1].memory_clock =
3435                                         polaris10_ps->performance_levels[0].memory_clock;
3436         }
3437
3438         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3439                         PHM_PlatformCaps_StablePState)) {
3440                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3441                         polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3442                         polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3443                         polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3444                         polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3445                 }
3446         }
3447         return 0;
3448 }
3449
3450
3451 static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3452 {
3453         struct pp_power_state  *ps;
3454         struct polaris10_power_state  *polaris10_ps;
3455
3456         if (hwmgr == NULL)
3457                 return -EINVAL;
3458
3459         ps = hwmgr->request_ps;
3460
3461         if (ps == NULL)
3462                 return -EINVAL;
3463
3464         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3465
3466         if (low)
3467                 return polaris10_ps->performance_levels[0].memory_clock;
3468         else
3469                 return polaris10_ps->performance_levels
3470                                 [polaris10_ps->performance_level_count-1].memory_clock;
3471 }
3472
3473 static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3474 {
3475         struct pp_power_state  *ps;
3476         struct polaris10_power_state  *polaris10_ps;
3477
3478         if (hwmgr == NULL)
3479                 return -EINVAL;
3480
3481         ps = hwmgr->request_ps;
3482
3483         if (ps == NULL)
3484                 return -EINVAL;
3485
3486         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3487
3488         if (low)
3489                 return polaris10_ps->performance_levels[0].engine_clock;
3490         else
3491                 return polaris10_ps->performance_levels
3492                                 [polaris10_ps->performance_level_count-1].engine_clock;
3493 }
3494
3495 static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3496                                         struct pp_hw_power_state *hw_ps)
3497 {
3498         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3499         struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
3500         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3501         uint16_t size;
3502         uint8_t frev, crev;
3503         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3504
3505         /* First retrieve the Boot clocks and VDDC from the firmware info table.
3506          * We assume here that fw_info is unchanged if this call fails.
3507          */
3508         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3509                         hwmgr->device, index,
3510                         &size, &frev, &crev);
3511         if (!fw_info)
3512                 /* During a test, there is no firmware info table. */
3513                 return 0;
3514
3515         /* Patch the state. */
3516         data->vbios_boot_state.sclk_bootup_value =
3517                         le32_to_cpu(fw_info->ulDefaultEngineClock);
3518         data->vbios_boot_state.mclk_bootup_value =
3519                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
3520         data->vbios_boot_state.mvdd_bootup_value =
3521                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3522         data->vbios_boot_state.vddc_bootup_value =
3523                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3524         data->vbios_boot_state.vddci_bootup_value =
3525                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3526         data->vbios_boot_state.pcie_gen_bootup_value =
3527                         phm_get_current_pcie_speed(hwmgr);
3528
3529         data->vbios_boot_state.pcie_lane_bootup_value =
3530                         (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3531
3532         /* set boot power state */
3533         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3534         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3535         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3536         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3537
3538         return 0;
3539 }
3540
3541 static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3542                 void *state, struct pp_power_state *power_state,
3543                 void *pp_table, uint32_t classification_flag)
3544 {
3545         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3546         struct polaris10_power_state  *polaris10_power_state =
3547                         (struct polaris10_power_state *)(&(power_state->hardware));
3548         struct polaris10_performance_level *performance_level;
3549         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3550         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3551                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3552         PPTable_Generic_SubTable_Header *sclk_dep_table =
3553                         (PPTable_Generic_SubTable_Header *)
3554                         (((unsigned long)powerplay_table) +
3555                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3556
3557         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3558                         (ATOM_Tonga_MCLK_Dependency_Table *)
3559                         (((unsigned long)powerplay_table) +
3560                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3561
3562         /* The following fields are not initialized here: id orderedList allStatesList */
3563         power_state->classification.ui_label =
3564                         (le16_to_cpu(state_entry->usClassification) &
3565                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3566                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3567         power_state->classification.flags = classification_flag;
3568         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3569
3570         power_state->classification.temporary_state = false;
3571         power_state->classification.to_be_deleted = false;
3572
3573         power_state->validation.disallowOnDC =
3574                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3575                                         ATOM_Tonga_DISALLOW_ON_DC));
3576
3577         power_state->pcie.lanes = 0;
3578
3579         power_state->display.disableFrameModulation = false;
3580         power_state->display.limitRefreshrate = false;
3581         power_state->display.enableVariBright =
3582                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3583                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3584
3585         power_state->validation.supportedPowerLevels = 0;
3586         power_state->uvd_clocks.VCLK = 0;
3587         power_state->uvd_clocks.DCLK = 0;
3588         power_state->temperatures.min = 0;
3589         power_state->temperatures.max = 0;
3590
3591         performance_level = &(polaris10_power_state->performance_levels
3592                         [polaris10_power_state->performance_level_count++]);
3593
3594         PP_ASSERT_WITH_CODE(
3595                         (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
3596                         "Performance levels exceeds SMC limit!",
3597                         return -1);
3598
3599         PP_ASSERT_WITH_CODE(
3600                         (polaris10_power_state->performance_level_count <=
3601                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3602                         "Performance levels exceeds Driver limit!",
3603                         return -1);
3604
3605         /* Performance levels are arranged from low to high. */
3606         performance_level->memory_clock = mclk_dep_table->entries
3607                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3608         if (sclk_dep_table->ucRevId == 0)
3609                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3610                         [state_entry->ucEngineClockIndexLow].ulSclk;
3611         else if (sclk_dep_table->ucRevId == 1)
3612                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3613                         [state_entry->ucEngineClockIndexLow].ulSclk;
3614         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3615                         state_entry->ucPCIEGenLow);
3616         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3617                         state_entry->ucPCIELaneHigh);
3618
3619         performance_level = &(polaris10_power_state->performance_levels
3620                         [polaris10_power_state->performance_level_count++]);
3621         performance_level->memory_clock = mclk_dep_table->entries
3622                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3623
3624         if (sclk_dep_table->ucRevId == 0)
3625                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3626                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3627         else if (sclk_dep_table->ucRevId == 1)
3628                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3629                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3630
3631         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3632                         state_entry->ucPCIEGenHigh);
3633         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3634                         state_entry->ucPCIELaneHigh);
3635
3636         return 0;
3637 }
3638
3639 static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3640                 unsigned long entry_index, struct pp_power_state *state)
3641 {
3642         int result;
3643         struct polaris10_power_state *ps;
3644         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3645         struct phm_ppt_v1_information *table_info =
3646                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3647         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3648                         table_info->vdd_dep_on_mclk;
3649
3650         state->hardware.magic = PHM_VIslands_Magic;
3651
3652         ps = (struct polaris10_power_state *)(&state->hardware);
3653
3654         result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3655                         polaris10_get_pp_table_entry_callback_func);
3656
3657         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3658          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3659          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3660          */
3661         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3662                 if (dep_mclk_table->entries[0].clk !=
3663                                 data->vbios_boot_state.mclk_bootup_value)
3664                         printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3665                                         "does not match VBIOS boot MCLK level");
3666                 if (dep_mclk_table->entries[0].vddci !=
3667                                 data->vbios_boot_state.vddci_bootup_value)
3668                         printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3669                                         "does not match VBIOS boot VDDCI level");
3670         }
3671
3672         /* set DC compatible flag if this state supports DC */
3673         if (!state->validation.disallowOnDC)
3674                 ps->dc_compatible = true;
3675
3676         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3677                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3678
3679         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3680         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3681
3682         if (!result) {
3683                 uint32_t i;
3684
3685                 switch (state->classification.ui_label) {
3686                 case PP_StateUILabel_Performance:
3687                         data->use_pcie_performance_levels = true;
3688                         for (i = 0; i < ps->performance_level_count; i++) {
3689                                 if (data->pcie_gen_performance.max <
3690                                                 ps->performance_levels[i].pcie_gen)
3691                                         data->pcie_gen_performance.max =
3692                                                         ps->performance_levels[i].pcie_gen;
3693
3694                                 if (data->pcie_gen_performance.min >
3695                                                 ps->performance_levels[i].pcie_gen)
3696                                         data->pcie_gen_performance.min =
3697                                                         ps->performance_levels[i].pcie_gen;
3698
3699                                 if (data->pcie_lane_performance.max <
3700                                                 ps->performance_levels[i].pcie_lane)
3701                                         data->pcie_lane_performance.max =
3702                                                         ps->performance_levels[i].pcie_lane;
3703                                 if (data->pcie_lane_performance.min >
3704                                                 ps->performance_levels[i].pcie_lane)
3705                                         data->pcie_lane_performance.min =
3706                                                         ps->performance_levels[i].pcie_lane;
3707                         }
3708                         break;
3709                 case PP_StateUILabel_Battery:
3710                         data->use_pcie_power_saving_levels = true;
3711
3712                         for (i = 0; i < ps->performance_level_count; i++) {
3713                                 if (data->pcie_gen_power_saving.max <
3714                                                 ps->performance_levels[i].pcie_gen)
3715                                         data->pcie_gen_power_saving.max =
3716                                                         ps->performance_levels[i].pcie_gen;
3717
3718                                 if (data->pcie_gen_power_saving.min >
3719                                                 ps->performance_levels[i].pcie_gen)
3720                                         data->pcie_gen_power_saving.min =
3721                                                         ps->performance_levels[i].pcie_gen;
3722
3723                                 if (data->pcie_lane_power_saving.max <
3724                                                 ps->performance_levels[i].pcie_lane)
3725                                         data->pcie_lane_power_saving.max =
3726                                                         ps->performance_levels[i].pcie_lane;
3727
3728                                 if (data->pcie_lane_power_saving.min >
3729                                                 ps->performance_levels[i].pcie_lane)
3730                                         data->pcie_lane_power_saving.min =
3731                                                         ps->performance_levels[i].pcie_lane;
3732                         }
3733                         break;
3734                 default:
3735                         break;
3736                 }
3737         }
3738         return 0;
3739 }
3740
3741 static void
3742 polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
3743 {
3744         uint32_t sclk, mclk, activity_percent;
3745         uint32_t offset;
3746         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3747
3748         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3749
3750         sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3751
3752         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3753
3754         mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3755         seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
3756                         mclk / 100, sclk / 100);
3757
3758         offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
3759         activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3760         activity_percent += 0x80;
3761         activity_percent >>= 8;
3762
3763         seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3764
3765         seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
3766
3767         seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
3768 }
3769
3770 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3771 {
3772         const struct phm_set_power_state_input *states =
3773                         (const struct phm_set_power_state_input *)input;
3774         const struct polaris10_power_state *polaris10_ps =
3775                         cast_const_phw_polaris10_power_state(states->pnew_state);
3776         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3777         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3778         uint32_t sclk = polaris10_ps->performance_levels
3779                         [polaris10_ps->performance_level_count - 1].engine_clock;
3780         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3781         uint32_t mclk = polaris10_ps->performance_levels
3782                         [polaris10_ps->performance_level_count - 1].memory_clock;
3783         struct PP_Clocks min_clocks = {0};
3784         uint32_t i;
3785         struct cgs_display_info info = {0};
3786
3787         data->need_update_smu7_dpm_table = 0;
3788
3789         for (i = 0; i < sclk_table->count; i++) {
3790                 if (sclk == sclk_table->dpm_levels[i].value)
3791                         break;
3792         }
3793
3794         if (i >= sclk_table->count)
3795                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3796         else {
3797         /* TODO: Check SCLK in DAL's minimum clocks
3798          * in case DeepSleep divider update is required.
3799          */
3800                 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3801                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
3802                                 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
3803                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3804         }
3805
3806         for (i = 0; i < mclk_table->count; i++) {
3807                 if (mclk == mclk_table->dpm_levels[i].value)
3808                         break;
3809         }
3810
3811         if (i >= mclk_table->count)
3812                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3813
3814         cgs_get_active_displays_info(hwmgr->device, &info);
3815
3816         if (data->display_timing.num_existing_displays != info.display_count)
3817                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3818
3819         return 0;
3820 }
3821
3822 static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3823                 const struct polaris10_power_state *polaris10_ps)
3824 {
3825         uint32_t i;
3826         uint32_t sclk, max_sclk = 0;
3827         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3828         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3829
3830         for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3831                 sclk = polaris10_ps->performance_levels[i].engine_clock;
3832                 if (max_sclk < sclk)
3833                         max_sclk = sclk;
3834         }
3835
3836         for (i = 0; i < dpm_table->sclk_table.count; i++) {
3837                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3838                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3839                                         dpm_table->pcie_speed_table.dpm_levels
3840                                         [dpm_table->pcie_speed_table.count - 1].value :
3841                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
3842         }
3843
3844         return 0;
3845 }
3846
3847 static int polaris10_request_link_speed_change_before_state_change(
3848                 struct pp_hwmgr *hwmgr, const void *input)
3849 {
3850         const struct phm_set_power_state_input *states =
3851                         (const struct phm_set_power_state_input *)input;
3852         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3853         const struct polaris10_power_state *polaris10_nps =
3854                         cast_const_phw_polaris10_power_state(states->pnew_state);
3855         const struct polaris10_power_state *polaris10_cps =
3856                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
3857
3858         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
3859         uint16_t current_link_speed;
3860
3861         if (data->force_pcie_gen == PP_PCIEGenInvalid)
3862                 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
3863         else
3864                 current_link_speed = data->force_pcie_gen;
3865
3866         data->force_pcie_gen = PP_PCIEGenInvalid;
3867         data->pspp_notify_required = false;
3868
3869         if (target_link_speed > current_link_speed) {
3870                 switch (target_link_speed) {
3871                 case PP_PCIEGen3:
3872                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
3873                                 break;
3874                         data->force_pcie_gen = PP_PCIEGen2;
3875                         if (current_link_speed == PP_PCIEGen2)
3876                                 break;
3877                 case PP_PCIEGen2:
3878                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
3879                                 break;
3880                 default:
3881                         data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
3882                         break;
3883                 }
3884         } else {
3885                 if (target_link_speed < current_link_speed)
3886                         data->pspp_notify_required = true;
3887         }
3888
3889         return 0;
3890 }
3891
3892 static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3893 {
3894         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3895
3896         if (0 == data->need_update_smu7_dpm_table)
3897                 return 0;
3898
3899         if ((0 == data->sclk_dpm_key_disabled) &&
3900                 (data->need_update_smu7_dpm_table &
3901                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3902                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3903                                 "Trying to freeze SCLK DPM when DPM is disabled",
3904                                 );
3905                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3906                                 PPSMC_MSG_SCLKDPM_FreezeLevel),
3907                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3908                                 return -1);
3909         }
3910
3911         if ((0 == data->mclk_dpm_key_disabled) &&
3912                 (data->need_update_smu7_dpm_table &
3913                  DPMTABLE_OD_UPDATE_MCLK)) {
3914                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3915                                 "Trying to freeze MCLK DPM when DPM is disabled",
3916                                 );
3917                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3918                                 PPSMC_MSG_MCLKDPM_FreezeLevel),
3919                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3920                                 return -1);
3921         }
3922
3923         return 0;
3924 }
3925
3926 static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
3927                 struct pp_hwmgr *hwmgr, const void *input)
3928 {
3929         int result = 0;
3930         const struct phm_set_power_state_input *states =
3931                         (const struct phm_set_power_state_input *)input;
3932         const struct polaris10_power_state *polaris10_ps =
3933                         cast_const_phw_polaris10_power_state(states->pnew_state);
3934         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3935         uint32_t sclk = polaris10_ps->performance_levels
3936                         [polaris10_ps->performance_level_count - 1].engine_clock;
3937         uint32_t mclk = polaris10_ps->performance_levels
3938                         [polaris10_ps->performance_level_count - 1].memory_clock;
3939         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3940
3941         struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
3942         uint32_t dpm_count, clock_percent;
3943         uint32_t i;
3944
3945         if (0 == data->need_update_smu7_dpm_table)
3946                 return 0;
3947
3948         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3949                 dpm_table->sclk_table.dpm_levels
3950                 [dpm_table->sclk_table.count - 1].value = sclk;
3951
3952                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3953                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3954                 /* Need to do calculation based on the golden DPM table
3955                  * as the Heatmap GPU Clock axis is also based on the default values
3956                  */
3957                         PP_ASSERT_WITH_CODE(
3958                                 (golden_dpm_table->sclk_table.dpm_levels
3959                                                 [golden_dpm_table->sclk_table.count - 1].value != 0),
3960                                 "Divide by 0!",
3961                                 return -1);
3962                         dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
3963
3964                         for (i = dpm_count; i > 1; i--) {
3965                                 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
3966                                         clock_percent =
3967                                               ((sclk
3968                                                 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
3969                                                 ) * 100)
3970                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3971
3972                                         dpm_table->sclk_table.dpm_levels[i].value =
3973                                                         golden_dpm_table->sclk_table.dpm_levels[i].value +
3974                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
3975                                                                 clock_percent)/100;
3976
3977                                 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
3978                                         clock_percent =
3979                                                 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
3980                                                 - sclk) * 100)
3981                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3982
3983                                         dpm_table->sclk_table.dpm_levels[i].value =
3984                                                         golden_dpm_table->sclk_table.dpm_levels[i].value -
3985                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
3986                                                                         clock_percent) / 100;
3987                                 } else
3988                                         dpm_table->sclk_table.dpm_levels[i].value =
3989                                                         golden_dpm_table->sclk_table.dpm_levels[i].value;
3990                         }
3991                 }
3992         }
3993
3994         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3995                 dpm_table->mclk_table.dpm_levels
3996                         [dpm_table->mclk_table.count - 1].value = mclk;
3997
3998                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3999                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4000
4001                         PP_ASSERT_WITH_CODE(
4002                                         (golden_dpm_table->mclk_table.dpm_levels
4003                                                 [golden_dpm_table->mclk_table.count-1].value != 0),
4004                                         "Divide by 0!",
4005                                         return -1);
4006                         dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
4007                         for (i = dpm_count; i > 1; i--) {
4008                                 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
4009                                         clock_percent = ((mclk -
4010                                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
4011                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4012
4013                                         dpm_table->mclk_table.dpm_levels[i].value =
4014                                                         golden_dpm_table->mclk_table.dpm_levels[i].value +
4015                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4016                                                         clock_percent) / 100;
4017
4018                                 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
4019                                         clock_percent = (
4020                                          (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
4021                                         * 100)
4022                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4023
4024                                         dpm_table->mclk_table.dpm_levels[i].value =
4025                                                         golden_dpm_table->mclk_table.dpm_levels[i].value -
4026                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4027                                                                         clock_percent) / 100;
4028                                 } else
4029                                         dpm_table->mclk_table.dpm_levels[i].value =
4030                                                         golden_dpm_table->mclk_table.dpm_levels[i].value;
4031                         }
4032                 }
4033         }
4034
4035         if (data->need_update_smu7_dpm_table &
4036                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4037                 result = polaris10_populate_all_graphic_levels(hwmgr);
4038                 PP_ASSERT_WITH_CODE((0 == result),
4039                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4040                                 return result);
4041         }
4042
4043         if (data->need_update_smu7_dpm_table &
4044                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4045                 /*populate MCLK dpm table to SMU7 */
4046                 result = polaris10_populate_all_memory_levels(hwmgr);
4047                 PP_ASSERT_WITH_CODE((0 == result),
4048                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4049                                 return result);
4050         }
4051
4052         return result;
4053 }
4054
4055 static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4056                           struct polaris10_single_dpm_table *dpm_table,
4057                         uint32_t low_limit, uint32_t high_limit)
4058 {
4059         uint32_t i;
4060
4061         for (i = 0; i < dpm_table->count; i++) {
4062                 if ((dpm_table->dpm_levels[i].value < low_limit)
4063                 || (dpm_table->dpm_levels[i].value > high_limit))
4064                         dpm_table->dpm_levels[i].enabled = false;
4065                 else
4066                         dpm_table->dpm_levels[i].enabled = true;
4067         }
4068
4069         return 0;
4070 }
4071
4072 static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4073                 const struct polaris10_power_state *polaris10_ps)
4074 {
4075         int result = 0;
4076         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4077         uint32_t high_limit_count;
4078
4079         PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
4080                         "power state did not have any performance level",
4081                         return -1);
4082
4083         high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
4084
4085         polaris10_trim_single_dpm_states(hwmgr,
4086                         &(data->dpm_table.sclk_table),
4087                         polaris10_ps->performance_levels[0].engine_clock,
4088                         polaris10_ps->performance_levels[high_limit_count].engine_clock);
4089
4090         polaris10_trim_single_dpm_states(hwmgr,
4091                         &(data->dpm_table.mclk_table),
4092                         polaris10_ps->performance_levels[0].memory_clock,
4093                         polaris10_ps->performance_levels[high_limit_count].memory_clock);
4094
4095         return result;
4096 }
4097
4098 static int polaris10_generate_dpm_level_enable_mask(
4099                 struct pp_hwmgr *hwmgr, const void *input)
4100 {
4101         int result;
4102         const struct phm_set_power_state_input *states =
4103                         (const struct phm_set_power_state_input *)input;
4104         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4105         const struct polaris10_power_state *polaris10_ps =
4106                         cast_const_phw_polaris10_power_state(states->pnew_state);
4107
4108         result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
4109         if (result)
4110                 return result;
4111
4112         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4113                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4114         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4115                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4116         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4117                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4118
4119         return 0;
4120 }
4121
4122 int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4123 {
4124         return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4125                         PPSMC_MSG_UVDDPM_Enable :
4126                         PPSMC_MSG_UVDDPM_Disable);
4127 }
4128
4129 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4130 {
4131         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4132                         PPSMC_MSG_VCEDPM_Enable :
4133                         PPSMC_MSG_VCEDPM_Disable);
4134 }
4135
4136 int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4137 {
4138         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4139                         PPSMC_MSG_SAMUDPM_Enable :
4140                         PPSMC_MSG_SAMUDPM_Disable);
4141 }
4142
4143 int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4144 {
4145         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4146         uint32_t mm_boot_level_offset, mm_boot_level_value;
4147         struct phm_ppt_v1_information *table_info =
4148                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4149
4150         if (!bgate) {
4151                 data->smc_state_table.UvdBootLevel = 0;
4152                 if (table_info->mm_dep_table->count > 0)
4153                         data->smc_state_table.UvdBootLevel =
4154                                         (uint8_t) (table_info->mm_dep_table->count - 1);
4155                 mm_boot_level_offset = data->dpm_table_start +
4156                                 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4157                 mm_boot_level_offset /= 4;
4158                 mm_boot_level_offset *= 4;
4159                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4160                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4161                 mm_boot_level_value &= 0x00FFFFFF;
4162                 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4163                 cgs_write_ind_register(hwmgr->device,
4164                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4165
4166                 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4167                                 PHM_PlatformCaps_UVDDPM) ||
4168                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4169                                 PHM_PlatformCaps_StablePState))
4170                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4171                                         PPSMC_MSG_UVDDPM_SetEnabledMask,
4172                                         (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4173         }
4174
4175         return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
4176 }
4177
4178 static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4179 {
4180         const struct phm_set_power_state_input *states =
4181                         (const struct phm_set_power_state_input *)input;
4182         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4183         const struct polaris10_power_state *polaris10_nps =
4184                         cast_const_phw_polaris10_power_state(states->pnew_state);
4185         const struct polaris10_power_state *polaris10_cps =
4186                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
4187
4188         uint32_t mm_boot_level_offset, mm_boot_level_value;
4189         struct phm_ppt_v1_information *table_info =
4190                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4191
4192         if (polaris10_nps->vce_clks.evclk > 0 &&
4193         (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
4194
4195                 data->smc_state_table.VceBootLevel =
4196                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4197
4198                 mm_boot_level_offset = data->dpm_table_start +
4199                                 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4200                 mm_boot_level_offset /= 4;
4201                 mm_boot_level_offset *= 4;
4202                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4203                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4204                 mm_boot_level_value &= 0xFF00FFFF;
4205                 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4206                 cgs_write_ind_register(hwmgr->device,
4207                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4208
4209                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4210                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4211                                         PPSMC_MSG_VCEDPM_SetEnabledMask,
4212                                         (uint32_t)1 << data->smc_state_table.VceBootLevel);
4213
4214                         polaris10_enable_disable_vce_dpm(hwmgr, true);
4215                 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4216                                 polaris10_cps != NULL &&
4217                                 polaris10_cps->vce_clks.evclk > 0)
4218                         polaris10_enable_disable_vce_dpm(hwmgr, false);
4219         }
4220
4221         return 0;
4222 }
4223
4224 int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4225 {
4226         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4227         uint32_t mm_boot_level_offset, mm_boot_level_value;
4228
4229         if (!bgate) {
4230                 data->smc_state_table.SamuBootLevel = 0;
4231                 mm_boot_level_offset = data->dpm_table_start +
4232                                 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4233                 mm_boot_level_offset /= 4;
4234                 mm_boot_level_offset *= 4;
4235                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4236                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4237                 mm_boot_level_value &= 0xFFFFFF00;
4238                 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4239                 cgs_write_ind_register(hwmgr->device,
4240                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4241
4242                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4243                                 PHM_PlatformCaps_StablePState))
4244                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4245                                         PPSMC_MSG_SAMUDPM_SetEnabledMask,
4246                                         (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4247         }
4248
4249         return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
4250 }
4251
4252 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4253 {
4254         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4255
4256         int result = 0;
4257         uint32_t low_sclk_interrupt_threshold = 0;
4258
4259         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4260                         PHM_PlatformCaps_SclkThrottleLowNotification)
4261                 && (hwmgr->gfx_arbiter.sclk_threshold !=
4262                                 data->low_sclk_interrupt_threshold)) {
4263                 data->low_sclk_interrupt_threshold =
4264                                 hwmgr->gfx_arbiter.sclk_threshold;
4265                 low_sclk_interrupt_threshold =
4266                                 data->low_sclk_interrupt_threshold;
4267
4268                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4269
4270                 result = polaris10_copy_bytes_to_smc(
4271                                 hwmgr->smumgr,
4272                                 data->dpm_table_start +
4273                                 offsetof(SMU74_Discrete_DpmTable,
4274                                         LowSclkInterruptThreshold),
4275                                 (uint8_t *)&low_sclk_interrupt_threshold,
4276                                 sizeof(uint32_t),
4277                                 data->sram_end);
4278         }
4279
4280         return result;
4281 }
4282
4283 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4284 {
4285         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4286
4287         if (data->need_update_smu7_dpm_table &
4288                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4289                 return polaris10_program_memory_timing_parameters(hwmgr);
4290
4291         return 0;
4292 }
4293
4294 static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4295 {
4296         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4297
4298         if (0 == data->need_update_smu7_dpm_table)
4299                 return 0;
4300
4301         if ((0 == data->sclk_dpm_key_disabled) &&
4302                 (data->need_update_smu7_dpm_table &
4303                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4304
4305                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4306                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4307                                 );
4308                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4309                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4310                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4311                         return -1);
4312         }
4313
4314         if ((0 == data->mclk_dpm_key_disabled) &&
4315                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4316
4317                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4318                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4319                                 );
4320                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4321                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4322                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4323                     return -1);
4324         }
4325
4326         data->need_update_smu7_dpm_table = 0;
4327
4328         return 0;
4329 }
4330
4331 static int polaris10_notify_link_speed_change_after_state_change(
4332                 struct pp_hwmgr *hwmgr, const void *input)
4333 {
4334         const struct phm_set_power_state_input *states =
4335                         (const struct phm_set_power_state_input *)input;
4336         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4337         const struct polaris10_power_state *polaris10_ps =
4338                         cast_const_phw_polaris10_power_state(states->pnew_state);
4339         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
4340         uint8_t  request;
4341
4342         if (data->pspp_notify_required) {
4343                 if (target_link_speed == PP_PCIEGen3)
4344                         request = PCIE_PERF_REQ_GEN3;
4345                 else if (target_link_speed == PP_PCIEGen2)
4346                         request = PCIE_PERF_REQ_GEN2;
4347                 else
4348                         request = PCIE_PERF_REQ_GEN1;
4349
4350                 if (request == PCIE_PERF_REQ_GEN1 &&
4351                                 phm_get_current_pcie_speed(hwmgr) > 0)
4352                         return 0;
4353
4354                 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4355                         if (PP_PCIEGen2 == target_link_speed)
4356                                 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4357                         else
4358                                 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4359                 }
4360         }
4361
4362         return 0;
4363 }
4364
4365 static int polaris10_notify_smc_display(struct pp_hwmgr *hwmgr)
4366 {
4367         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4368
4369         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4370                 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
4371         return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ?  0 : -EINVAL;
4372 }
4373
4374 static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4375 {
4376         int tmp_result, result = 0;
4377         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4378
4379         tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4380         PP_ASSERT_WITH_CODE((0 == tmp_result),
4381                         "Failed to find DPM states clocks in DPM table!",
4382                         result = tmp_result);
4383
4384         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4385                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4386                 tmp_result =
4387                         polaris10_request_link_speed_change_before_state_change(hwmgr, input);
4388                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4389                                 "Failed to request link speed change before state change!",
4390                                 result = tmp_result);
4391         }
4392
4393         tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
4394         PP_ASSERT_WITH_CODE((0 == tmp_result),
4395                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4396
4397         tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4398         PP_ASSERT_WITH_CODE((0 == tmp_result),
4399                         "Failed to populate and upload SCLK MCLK DPM levels!",
4400                         result = tmp_result);
4401
4402         tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
4403         PP_ASSERT_WITH_CODE((0 == tmp_result),
4404                         "Failed to generate DPM level enabled mask!",
4405                         result = tmp_result);
4406
4407         tmp_result = polaris10_update_vce_dpm(hwmgr, input);
4408         PP_ASSERT_WITH_CODE((0 == tmp_result),
4409                         "Failed to update VCE DPM!",
4410                         result = tmp_result);
4411
4412         tmp_result = polaris10_update_sclk_threshold(hwmgr);
4413         PP_ASSERT_WITH_CODE((0 == tmp_result),
4414                         "Failed to update SCLK threshold!",
4415                         result = tmp_result);
4416
4417         tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
4418         PP_ASSERT_WITH_CODE((0 == tmp_result),
4419                         "Failed to program memory timing parameters!",
4420                         result = tmp_result);
4421
4422         tmp_result = polaris10_notify_smc_display(hwmgr);
4423         PP_ASSERT_WITH_CODE((0 == tmp_result),
4424                         "Failed to notify smc display settings!",
4425                         result = tmp_result);
4426
4427         tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4428         PP_ASSERT_WITH_CODE((0 == tmp_result),
4429                         "Failed to unfreeze SCLK MCLK DPM!",
4430                         result = tmp_result);
4431
4432         tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
4433         PP_ASSERT_WITH_CODE((0 == tmp_result),
4434                         "Failed to upload DPM level enabled mask!",
4435                         result = tmp_result);
4436
4437         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4438                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4439                 tmp_result =
4440                         polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
4441                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4442                                 "Failed to notify link speed change after state change!",
4443                                 result = tmp_result);
4444         }
4445         data->apply_optimized_settings = false;
4446         return result;
4447 }
4448
4449 static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4450 {
4451         hwmgr->thermal_controller.
4452         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4453
4454         if (phm_is_hw_access_blocked(hwmgr))
4455                 return 0;
4456
4457         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4458                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4459 }
4460
4461
4462 int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4463 {
4464         PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4465
4466         return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
4467 }
4468
4469 int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4470 {
4471         uint32_t num_active_displays = 0;
4472         struct cgs_display_info info = {0};
4473         info.mode_info = NULL;
4474
4475         cgs_get_active_displays_info(hwmgr->device, &info);
4476
4477         num_active_displays = info.display_count;
4478
4479         if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4480                 polaris10_notify_smc_display_change(hwmgr, false);
4481
4482         return 0;
4483 }
4484
4485 /**
4486 * Programs the display gap
4487 *
4488 * @param    hwmgr  the address of the powerplay hardware manager.
4489 * @return   always OK
4490 */
4491 int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
4492 {
4493         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4494         uint32_t num_active_displays = 0;
4495         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4496         uint32_t display_gap2;
4497         uint32_t pre_vbi_time_in_us;
4498         uint32_t frame_time_in_us;
4499         uint32_t ref_clock;
4500         uint32_t refresh_rate = 0;
4501         struct cgs_display_info info = {0};
4502         struct cgs_mode_info mode_info;
4503
4504         info.mode_info = &mode_info;
4505
4506         cgs_get_active_displays_info(hwmgr->device, &info);
4507         num_active_displays = info.display_count;
4508
4509         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4510         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4511
4512         ref_clock = mode_info.ref_clock;
4513         refresh_rate = mode_info.refresh_rate;
4514
4515         if (0 == refresh_rate)
4516                 refresh_rate = 60;
4517
4518         frame_time_in_us = 1000000 / refresh_rate;
4519
4520         pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4521         data->frame_time_x2 = frame_time_in_us * 2 / 100;
4522
4523         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4524
4525         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4526
4527         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4528
4529         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4530
4531         return 0;
4532 }
4533
4534
4535 int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4536 {
4537         return polaris10_program_display_gap(hwmgr);
4538 }
4539
4540 /**
4541 *  Set maximum target operating fan output RPM
4542 *
4543 * @param    hwmgr:  the address of the powerplay hardware manager.
4544 * @param    usMaxFanRpm:  max operating fan RPM value.
4545 * @return   The response that came from the SMC.
4546 */
4547 static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4548 {
4549         hwmgr->thermal_controller.
4550         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4551
4552         if (phm_is_hw_access_blocked(hwmgr))
4553                 return 0;
4554
4555         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4556                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4557 }
4558
4559 int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
4560                                         const void *thermal_interrupt_info)
4561 {
4562         return 0;
4563 }
4564
4565 bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4566 {
4567         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4568         bool is_update_required = false;
4569         struct cgs_display_info info = {0, 0, NULL};
4570
4571         cgs_get_active_displays_info(hwmgr->device, &info);
4572
4573         if (data->display_timing.num_existing_displays != info.display_count)
4574                 is_update_required = true;
4575 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4576         if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4577                 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
4578                 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4579                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4580                                 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4581                         is_update_required = true;
4582 */
4583         return is_update_required;
4584 }
4585
4586 static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4587                                                            const struct polaris10_performance_level *pl2)
4588 {
4589         return ((pl1->memory_clock == pl2->memory_clock) &&
4590                   (pl1->engine_clock == pl2->engine_clock) &&
4591                   (pl1->pcie_gen == pl2->pcie_gen) &&
4592                   (pl1->pcie_lane == pl2->pcie_lane));
4593 }
4594
4595 int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
4596 {
4597         const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4598         const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
4599         int i;
4600
4601         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4602                 return -EINVAL;
4603
4604         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4605         if (psa->performance_level_count != psb->performance_level_count) {
4606                 *equal = false;
4607                 return 0;
4608         }
4609
4610         for (i = 0; i < psa->performance_level_count; i++) {
4611                 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4612                         /* If we have found even one performance level pair that is different the states are different. */
4613                         *equal = false;
4614                         return 0;
4615                 }
4616         }
4617
4618         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4619         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4620         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4621         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4622
4623         return 0;
4624 }
4625
4626 int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
4627 {
4628         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4629
4630         uint32_t vbios_version;
4631
4632         /*  Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4633
4634         phm_get_mc_microcode_version(hwmgr);
4635         vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4636         /*  Full version of MC ucode has already been loaded. */
4637         if (vbios_version == 0) {
4638                 data->need_long_memory_training = false;
4639                 return 0;
4640         }
4641
4642         data->need_long_memory_training = false;
4643
4644 /*
4645  *      PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4646         pfd = &tonga_mcmeFirmware;
4647         if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
4648                 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
4649                                         pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4650                                         pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4651 */
4652         return 0;
4653 }
4654
4655 /**
4656  * Read clock related registers.
4657  *
4658  * @param    hwmgr  the address of the powerplay hardware manager.
4659  * @return   always 0
4660  */
4661 static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
4662 {
4663         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4664
4665         data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4666                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4667                                                 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4668
4669         data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4670                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4671                                                 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4672
4673         data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4674                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4675                                                 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4676
4677         return 0;
4678 }
4679
4680 /**
4681  * Find out if memory is GDDR5.
4682  *
4683  * @param    hwmgr  the address of the powerplay hardware manager.
4684  * @return   always 0
4685  */
4686 static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
4687 {
4688         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4689         uint32_t temp;
4690
4691         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4692
4693         data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4694                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4695                          MC_SEQ_MISC0_GDDR5_SHIFT));
4696
4697         return 0;
4698 }
4699
4700 /**
4701  * Enables Dynamic Power Management by SMC
4702  *
4703  * @param    hwmgr  the address of the powerplay hardware manager.
4704  * @return   always 0
4705  */
4706 static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4707 {
4708         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4709                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
4710
4711         return 0;
4712 }
4713
4714 /**
4715  * Initialize PowerGating States for different engines
4716  *
4717  * @param    hwmgr  the address of the powerplay hardware manager.
4718  * @return   always 0
4719  */
4720 static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
4721 {
4722         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4723
4724         data->uvd_power_gated = false;
4725         data->vce_power_gated = false;
4726         data->samu_power_gated = false;
4727
4728         return 0;
4729 }
4730
4731 static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4732 {
4733         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4734         data->low_sclk_interrupt_threshold = 0;
4735
4736         return 0;
4737 }
4738
4739 int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
4740 {
4741         int tmp_result, result = 0;
4742
4743         polaris10_upload_mc_firmware(hwmgr);
4744
4745         tmp_result = polaris10_read_clock_registers(hwmgr);
4746         PP_ASSERT_WITH_CODE((0 == tmp_result),
4747                         "Failed to read clock registers!", result = tmp_result);
4748
4749         tmp_result = polaris10_get_memory_type(hwmgr);
4750         PP_ASSERT_WITH_CODE((0 == tmp_result),
4751                         "Failed to get memory type!", result = tmp_result);
4752
4753         tmp_result = polaris10_enable_acpi_power_management(hwmgr);
4754         PP_ASSERT_WITH_CODE((0 == tmp_result),
4755                         "Failed to enable ACPI power management!", result = tmp_result);
4756
4757         tmp_result = polaris10_init_power_gate_state(hwmgr);
4758         PP_ASSERT_WITH_CODE((0 == tmp_result),
4759                         "Failed to init power gate state!", result = tmp_result);
4760
4761         tmp_result = phm_get_mc_microcode_version(hwmgr);
4762         PP_ASSERT_WITH_CODE((0 == tmp_result),
4763                         "Failed to get MC microcode version!", result = tmp_result);
4764
4765         tmp_result = polaris10_init_sclk_threshold(hwmgr);
4766         PP_ASSERT_WITH_CODE((0 == tmp_result),
4767                         "Failed to init sclk threshold!", result = tmp_result);
4768
4769         return result;
4770 }
4771
4772 static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
4773 {
4774         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4775
4776         if (!data->soft_pp_table) {
4777                 data->soft_pp_table = kmemdup(hwmgr->soft_pp_table,
4778                                               hwmgr->soft_pp_table_size,
4779                                               GFP_KERNEL);
4780                 if (!data->soft_pp_table)
4781                         return -ENOMEM;
4782         }
4783
4784         *table = (char *)&data->soft_pp_table;
4785
4786         return hwmgr->soft_pp_table_size;
4787 }
4788
4789 static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
4790 {
4791         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4792
4793         if (!data->soft_pp_table) {
4794                 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
4795                 if (!data->soft_pp_table)
4796                         return -ENOMEM;
4797         }
4798
4799         memcpy(data->soft_pp_table, buf, size);
4800
4801         hwmgr->soft_pp_table = data->soft_pp_table;
4802
4803         /* TODO: re-init powerplay to implement modified pptable */
4804
4805         return 0;
4806 }
4807
4808 static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
4809                 enum pp_clock_type type, uint32_t mask)
4810 {
4811         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4812
4813         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
4814                 return -EINVAL;
4815
4816         switch (type) {
4817         case PP_SCLK:
4818                 if (!data->sclk_dpm_key_disabled)
4819                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4820                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
4821                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
4822                 break;
4823         case PP_MCLK:
4824                 if (!data->mclk_dpm_key_disabled)
4825                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4826                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
4827                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
4828                 break;
4829         case PP_PCIE:
4830         {
4831                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4832                 uint32_t level = 0;
4833
4834                 while (tmp >>= 1)
4835                         level++;
4836
4837                 if (!data->pcie_dpm_key_disabled)
4838                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4839                                         PPSMC_MSG_PCIeDPM_ForceLevel,
4840                                         level);
4841                 break;
4842         }
4843         default:
4844                 break;
4845         }
4846
4847         return 0;
4848 }
4849
4850 static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
4851 {
4852         uint32_t speedCntl = 0;
4853
4854         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
4855         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
4856                         ixPCIE_LC_SPEED_CNTL);
4857         return((uint16_t)PHM_GET_FIELD(speedCntl,
4858                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4859 }
4860
4861 static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
4862                 enum pp_clock_type type, char *buf)
4863 {
4864         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4865         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4866         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4867         struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4868         int i, now, size = 0;
4869         uint32_t clock, pcie_speed;
4870
4871         switch (type) {
4872         case PP_SCLK:
4873                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4874                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4875
4876                 for (i = 0; i < sclk_table->count; i++) {
4877                         if (clock > sclk_table->dpm_levels[i].value)
4878                                 continue;
4879                         break;
4880                 }
4881                 now = i;
4882
4883                 for (i = 0; i < sclk_table->count; i++)
4884                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4885                                         i, sclk_table->dpm_levels[i].value / 100,
4886                                         (i == now) ? "*" : "");
4887                 break;
4888         case PP_MCLK:
4889                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4890                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4891
4892                 for (i = 0; i < mclk_table->count; i++) {
4893                         if (clock > mclk_table->dpm_levels[i].value)
4894                                 continue;
4895                         break;
4896                 }
4897                 now = i;
4898
4899                 for (i = 0; i < mclk_table->count; i++)
4900                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4901                                         i, mclk_table->dpm_levels[i].value / 100,
4902                                         (i == now) ? "*" : "");
4903                 break;
4904         case PP_PCIE:
4905                 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
4906                 for (i = 0; i < pcie_table->count; i++) {
4907                         if (pcie_speed != pcie_table->dpm_levels[i].value)
4908                                 continue;
4909                         break;
4910                 }
4911                 now = i;
4912
4913                 for (i = 0; i < pcie_table->count; i++)
4914                         size += sprintf(buf + size, "%d: %s %s\n", i,
4915                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
4916                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
4917                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
4918                                         (i == now) ? "*" : "");
4919                 break;
4920         default:
4921                 break;
4922         }
4923         return size;
4924 }
4925
4926 static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4927 {
4928         if (mode) {
4929                 /* stop auto-manage */
4930                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4931                                 PHM_PlatformCaps_MicrocodeFanControl))
4932                         polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
4933                 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
4934         } else
4935                 /* restart auto-manage */
4936                 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
4937
4938         return 0;
4939 }
4940
4941 static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4942 {
4943         if (hwmgr->fan_ctrl_is_in_default_mode)
4944                 return hwmgr->fan_ctrl_default_mode;
4945         else
4946                 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4947                                 CG_FDO_CTRL2, FDO_PWM_MODE);
4948 }
4949
4950 static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
4951         .backend_init = &polaris10_hwmgr_backend_init,
4952         .backend_fini = &polaris10_hwmgr_backend_fini,
4953         .asic_setup = &polaris10_setup_asic_task,
4954         .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
4955         .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
4956         .force_dpm_level = &polaris10_force_dpm_level,
4957         .power_state_set = polaris10_set_power_state_tasks,
4958         .get_power_state_size = polaris10_get_power_state_size,
4959         .get_mclk = polaris10_dpm_get_mclk,
4960         .get_sclk = polaris10_dpm_get_sclk,
4961         .patch_boot_state = polaris10_dpm_patch_boot_state,
4962         .get_pp_table_entry = polaris10_get_pp_table_entry,
4963         .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
4964         .print_current_perforce_level = polaris10_print_current_perforce_level,
4965         .powerdown_uvd = polaris10_phm_powerdown_uvd,
4966         .powergate_uvd = polaris10_phm_powergate_uvd,
4967         .powergate_vce = polaris10_phm_powergate_vce,
4968         .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
4969         .update_clock_gatings = polaris10_phm_update_clock_gatings,
4970         .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
4971         .display_config_changed = polaris10_display_configuration_changed_task,
4972         .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
4973         .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
4974         .get_temperature = polaris10_thermal_get_temperature,
4975         .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
4976         .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
4977         .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
4978         .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
4979         .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
4980         .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
4981         .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
4982         .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
4983         .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
4984         .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
4985         .check_states_equal = polaris10_check_states_equal,
4986         .set_fan_control_mode = polaris10_set_fan_control_mode,
4987         .get_fan_control_mode = polaris10_get_fan_control_mode,
4988         .get_pp_table = polaris10_get_pp_table,
4989         .set_pp_table = polaris10_set_pp_table,
4990         .force_clock_level = polaris10_force_clock_level,
4991         .print_clock_levels = polaris10_print_clock_levels,
4992         .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
4993 };
4994
4995 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
4996 {
4997         struct polaris10_hwmgr  *data;
4998
4999         data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL);
5000         if (data == NULL)
5001                 return -ENOMEM;
5002
5003         hwmgr->backend = data;
5004         hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
5005         hwmgr->pptable_func = &tonga_pptable_funcs;
5006         pp_polaris10_thermal_initialize(hwmgr);
5007
5008         return 0;
5009 }