2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/module.h>
24 #include <linux/slab.h>
26 #include "linux/delay.h"
29 #include "amd_powerplay.h"
30 #include "vega10_smumgr.h"
31 #include "hardwaremanager.h"
32 #include "ppatomfwctrl.h"
33 #include "atomfirmware.h"
34 #include "cgs_common.h"
35 #include "vega10_powertune.h"
37 #include "smu9_driver_if.h"
38 #include "vega10_inc.h"
40 #include "pppcielanes.h"
41 #include "vega10_hwmgr.h"
42 #include "vega10_processpptables.h"
43 #include "vega10_pptable.h"
44 #include "vega10_thermal.h"
47 #include "amd_pcie_helpers.h"
48 #include "cgs_linux.h"
49 #include "ppinterrupt.h"
52 #define VOLTAGE_SCALE 4
53 #define VOLTAGE_VID_OFFSET_SCALE1 625
54 #define VOLTAGE_VID_OFFSET_SCALE2 100
56 #define HBM_MEMORY_CHANNEL_WIDTH 128
58 uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
60 #define MEM_FREQ_LOW_LATENCY 25000
61 #define MEM_FREQ_HIGH_LATENCY 80000
62 #define MEM_LATENCY_HIGH 245
63 #define MEM_LATENCY_LOW 35
64 #define MEM_LATENCY_ERR 0xFFFF
66 #define mmDF_CS_AON0_DramBaseAddress0 0x0044
67 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
69 //DF_CS_AON0_DramBaseAddress0
70 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
71 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
72 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
73 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
74 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
75 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
76 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
77 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
78 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
79 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
81 const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
83 struct vega10_power_state *cast_phw_vega10_power_state(
84 struct pp_hw_power_state *hw_ps)
86 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
87 "Invalid Powerstate Type!",
90 return (struct vega10_power_state *)hw_ps;
93 const struct vega10_power_state *cast_const_phw_vega10_power_state(
94 const struct pp_hw_power_state *hw_ps)
96 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
97 "Invalid Powerstate Type!",
100 return (const struct vega10_power_state *)hw_ps;
103 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
105 struct vega10_hwmgr *data =
106 (struct vega10_hwmgr *)(hwmgr->backend);
108 data->registry_data.sclk_dpm_key_disabled =
109 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
110 data->registry_data.socclk_dpm_key_disabled =
111 hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;
112 data->registry_data.mclk_dpm_key_disabled =
113 hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
115 data->registry_data.dcefclk_dpm_key_disabled =
116 hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;
118 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
119 data->registry_data.power_containment_support = 1;
120 data->registry_data.enable_pkg_pwr_tracking_feature = 1;
121 data->registry_data.enable_tdc_limit_feature = 1;
124 data->registry_data.pcie_dpm_key_disabled = 1;
125 data->registry_data.disable_water_mark = 0;
127 data->registry_data.fan_control_support = 1;
128 data->registry_data.thermal_support = 1;
129 data->registry_data.fw_ctf_enabled = 1;
131 data->registry_data.avfs_support = 1;
132 data->registry_data.led_dpm_enabled = 1;
134 data->registry_data.vr0hot_enabled = 1;
135 data->registry_data.vr1hot_enabled = 1;
136 data->registry_data.regulator_hot_gpio_support = 1;
138 data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT;
139 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
140 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
141 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
142 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
143 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
144 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
145 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
146 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
147 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
148 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
149 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
150 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
152 data->gfxclk_average_alpha = PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT;
153 data->socclk_average_alpha = PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT;
154 data->uclk_average_alpha = PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT;
155 data->gfx_activity_average_alpha = PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT;
158 static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
160 struct vega10_hwmgr *data =
161 (struct vega10_hwmgr *)(hwmgr->backend);
162 struct phm_ppt_v2_information *table_info =
163 (struct phm_ppt_v2_information *)hwmgr->pptable;
164 struct cgs_system_info sys_info = {0};
167 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
168 PHM_PlatformCaps_SclkDeepSleep);
170 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
171 PHM_PlatformCaps_DynamicPatchPowerState);
173 if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE)
174 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
175 PHM_PlatformCaps_ControlVDDCI);
177 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
178 PHM_PlatformCaps_TablelessHardwareInterface);
180 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
181 PHM_PlatformCaps_EnableSMU7ThermalManagement);
183 sys_info.size = sizeof(struct cgs_system_info);
184 sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
185 result = cgs_query_system_info(hwmgr->device, &sys_info);
187 if (!result && (sys_info.value & AMD_PG_SUPPORT_UVD))
188 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
189 PHM_PlatformCaps_UVDPowerGating);
191 if (!result && (sys_info.value & AMD_PG_SUPPORT_VCE))
192 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
193 PHM_PlatformCaps_VCEPowerGating);
195 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
196 PHM_PlatformCaps_UnTabledHardwareInterface);
198 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
199 PHM_PlatformCaps_FanSpeedInTableIsRPM);
201 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
202 PHM_PlatformCaps_ODFuzzyFanControlSupport);
204 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
205 PHM_PlatformCaps_DynamicPowerManagement);
207 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
208 PHM_PlatformCaps_SMC);
210 /* power tune caps */
211 /* assume disabled */
212 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
213 PHM_PlatformCaps_PowerContainment);
214 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
215 PHM_PlatformCaps_SQRamping);
216 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
217 PHM_PlatformCaps_DBRamping);
218 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
219 PHM_PlatformCaps_TDRamping);
220 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
221 PHM_PlatformCaps_TCPRamping);
223 if (data->registry_data.power_containment_support)
224 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
225 PHM_PlatformCaps_PowerContainment);
226 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
227 PHM_PlatformCaps_CAC);
229 if (table_info->tdp_table->usClockStretchAmount &&
230 data->registry_data.clock_stretcher_support)
231 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
232 PHM_PlatformCaps_ClockStretcher);
234 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
235 PHM_PlatformCaps_RegulatorHot);
236 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
237 PHM_PlatformCaps_AutomaticDCTransition);
239 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
240 PHM_PlatformCaps_UVDDPM);
241 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
242 PHM_PlatformCaps_VCEDPM);
247 static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
249 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
252 vega10_initialize_power_tune_defaults(hwmgr);
254 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
255 data->smu_features[i].smu_feature_id = 0xffff;
256 data->smu_features[i].smu_feature_bitmap = 1 << i;
257 data->smu_features[i].enabled = false;
258 data->smu_features[i].supported = false;
261 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
262 FEATURE_DPM_PREFETCHER_BIT;
263 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
264 FEATURE_DPM_GFXCLK_BIT;
265 data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
266 FEATURE_DPM_UCLK_BIT;
267 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
268 FEATURE_DPM_SOCCLK_BIT;
269 data->smu_features[GNLD_DPM_UVD].smu_feature_id =
271 data->smu_features[GNLD_DPM_VCE].smu_feature_id =
273 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
274 FEATURE_DPM_MP0CLK_BIT;
275 data->smu_features[GNLD_DPM_LINK].smu_feature_id =
276 FEATURE_DPM_LINK_BIT;
277 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
278 FEATURE_DPM_DCEFCLK_BIT;
279 data->smu_features[GNLD_ULV].smu_feature_id =
281 data->smu_features[GNLD_AVFS].smu_feature_id =
283 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
284 FEATURE_DS_GFXCLK_BIT;
285 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
286 FEATURE_DS_SOCCLK_BIT;
287 data->smu_features[GNLD_DS_LCLK].smu_feature_id =
289 data->smu_features[GNLD_PPT].smu_feature_id =
291 data->smu_features[GNLD_TDC].smu_feature_id =
293 data->smu_features[GNLD_THERMAL].smu_feature_id =
295 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
296 FEATURE_GFX_PER_CU_CG_BIT;
297 data->smu_features[GNLD_RM].smu_feature_id =
299 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
300 FEATURE_DS_DCEFCLK_BIT;
301 data->smu_features[GNLD_ACDC].smu_feature_id =
303 data->smu_features[GNLD_VR0HOT].smu_feature_id =
305 data->smu_features[GNLD_VR1HOT].smu_feature_id =
307 data->smu_features[GNLD_FW_CTF].smu_feature_id =
309 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
310 FEATURE_LED_DISPLAY_BIT;
311 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
312 FEATURE_FAN_CONTROL_BIT;
313 data->smu_features[GNLD_VOLTAGE_CONTROLLER].smu_feature_id =
314 FEATURE_VOLTAGE_CONTROLLER_BIT;
316 if (!data->registry_data.prefetcher_dpm_key_disabled)
317 data->smu_features[GNLD_DPM_PREFETCHER].supported = true;
319 if (!data->registry_data.sclk_dpm_key_disabled)
320 data->smu_features[GNLD_DPM_GFXCLK].supported = true;
322 if (!data->registry_data.mclk_dpm_key_disabled)
323 data->smu_features[GNLD_DPM_UCLK].supported = true;
325 if (!data->registry_data.socclk_dpm_key_disabled)
326 data->smu_features[GNLD_DPM_SOCCLK].supported = true;
328 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
329 PHM_PlatformCaps_UVDDPM))
330 data->smu_features[GNLD_DPM_UVD].supported = true;
332 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
333 PHM_PlatformCaps_VCEDPM))
334 data->smu_features[GNLD_DPM_VCE].supported = true;
336 if (!data->registry_data.pcie_dpm_key_disabled)
337 data->smu_features[GNLD_DPM_LINK].supported = true;
339 if (!data->registry_data.dcefclk_dpm_key_disabled)
340 data->smu_features[GNLD_DPM_DCEFCLK].supported = true;
342 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
343 PHM_PlatformCaps_SclkDeepSleep) &&
344 data->registry_data.sclk_deep_sleep_support) {
345 data->smu_features[GNLD_DS_GFXCLK].supported = true;
346 data->smu_features[GNLD_DS_SOCCLK].supported = true;
347 data->smu_features[GNLD_DS_LCLK].supported = true;
350 if (data->registry_data.enable_pkg_pwr_tracking_feature)
351 data->smu_features[GNLD_PPT].supported = true;
353 if (data->registry_data.enable_tdc_limit_feature)
354 data->smu_features[GNLD_TDC].supported = true;
356 if (data->registry_data.thermal_support)
357 data->smu_features[GNLD_THERMAL].supported = true;
359 if (data->registry_data.fan_control_support)
360 data->smu_features[GNLD_FAN_CONTROL].supported = true;
362 if (data->registry_data.fw_ctf_enabled)
363 data->smu_features[GNLD_FW_CTF].supported = true;
365 if (data->registry_data.avfs_support)
366 data->smu_features[GNLD_AVFS].supported = true;
368 if (data->registry_data.led_dpm_enabled)
369 data->smu_features[GNLD_LED_DISPLAY].supported = true;
371 if (data->registry_data.vr1hot_enabled)
372 data->smu_features[GNLD_VR1HOT].supported = true;
374 if (data->registry_data.vr0hot_enabled)
375 data->smu_features[GNLD_VR0HOT].supported = true;
379 #ifdef PPLIB_VEGA10_EVV_SUPPORT
380 static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
381 phm_ppt_v1_voltage_lookup_table *lookup_table,
382 uint16_t virtual_voltage_id, int32_t *socclk)
386 struct phm_ppt_v2_information *table_info =
387 (struct phm_ppt_v2_information *)(hwmgr->pptable);
389 PP_ASSERT_WITH_CODE(lookup_table->count != 0,
390 "Lookup table is empty",
393 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */
394 for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) {
395 voltage_id = table_info->vdd_dep_on_socclk->entries[entry_id].vddInd;
396 if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id)
400 PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count,
401 "Can't find requested voltage id in vdd_dep_on_socclk table!",
404 *socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk;
409 #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01
411 * Get Leakage VDDC based on leakage ID.
413 * @param hwmgr the address of the powerplay hardware manager.
416 static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
418 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
423 struct phm_ppt_v2_information *table_info =
424 (struct phm_ppt_v2_information *)hwmgr->pptable;
425 struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table =
426 table_info->vdd_dep_on_socclk;
429 for (i = 0; i < VEGA10_MAX_LEAKAGE_COUNT; i++) {
430 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
432 if (!vega10_get_socclk_for_voltage_evv(hwmgr,
433 table_info->vddc_lookup_table, vv_id, &sclk)) {
434 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
435 PHM_PlatformCaps_ClockStretcher)) {
436 for (j = 1; j < socclk_table->count; j++) {
437 if (socclk_table->entries[j].clk == sclk &&
438 socclk_table->entries[j].cks_enable == 0) {
445 PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
446 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
447 "Error retrieving EVV voltage value!",
451 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
452 PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
453 "Invalid VDDC value", result = -EINVAL;);
455 /* the voltage should not be zero nor equal to leakage ID */
456 if (vddc != 0 && vddc != vv_id) {
457 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
458 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
459 data->vddc_leakage.count++;
468 * Change virtual leakage voltage to actual value.
470 * @param hwmgr the address of the powerplay hardware manager.
471 * @param pointer to changing voltage
472 * @param pointer to leakage table
474 static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
475 uint16_t *voltage, struct vega10_leakage_voltage *leakage_table)
479 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
480 for (index = 0; index < leakage_table->count; index++) {
481 /* if this voltage matches a leakage voltage ID */
482 /* patch with actual leakage voltage */
483 if (leakage_table->leakage_id[index] == *voltage) {
484 *voltage = leakage_table->actual_voltage[index];
489 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
490 pr_info("Voltage value looks like a Leakage ID \
491 but it's not patched\n");
495 * Patch voltage lookup table by EVV leakages.
497 * @param hwmgr the address of the powerplay hardware manager.
498 * @param pointer to voltage lookup table
499 * @param pointer to leakage table
502 static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
503 phm_ppt_v1_voltage_lookup_table *lookup_table,
504 struct vega10_leakage_voltage *leakage_table)
508 for (i = 0; i < lookup_table->count; i++)
509 vega10_patch_with_vdd_leakage(hwmgr,
510 &lookup_table->entries[i].us_vdd, leakage_table);
515 static int vega10_patch_clock_voltage_limits_with_vddc_leakage(
516 struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table,
519 vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
525 static int vega10_patch_voltage_dependency_tables_with_lookup_table(
526 struct pp_hwmgr *hwmgr)
530 struct phm_ppt_v2_information *table_info =
531 (struct phm_ppt_v2_information *)(hwmgr->pptable);
532 struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table =
533 table_info->vdd_dep_on_socclk;
534 struct phm_ppt_v1_clock_voltage_dependency_table *gfxclk_table =
535 table_info->vdd_dep_on_sclk;
536 struct phm_ppt_v1_clock_voltage_dependency_table *dcefclk_table =
537 table_info->vdd_dep_on_dcefclk;
538 struct phm_ppt_v1_clock_voltage_dependency_table *pixclk_table =
539 table_info->vdd_dep_on_pixclk;
540 struct phm_ppt_v1_clock_voltage_dependency_table *dspclk_table =
541 table_info->vdd_dep_on_dispclk;
542 struct phm_ppt_v1_clock_voltage_dependency_table *phyclk_table =
543 table_info->vdd_dep_on_phyclk;
544 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
545 table_info->vdd_dep_on_mclk;
546 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
547 table_info->mm_dep_table;
549 for (entry_id = 0; entry_id < socclk_table->count; entry_id++) {
550 voltage_id = socclk_table->entries[entry_id].vddInd;
551 socclk_table->entries[entry_id].vddc =
552 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
555 for (entry_id = 0; entry_id < gfxclk_table->count; entry_id++) {
556 voltage_id = gfxclk_table->entries[entry_id].vddInd;
557 gfxclk_table->entries[entry_id].vddc =
558 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
561 for (entry_id = 0; entry_id < dcefclk_table->count; entry_id++) {
562 voltage_id = dcefclk_table->entries[entry_id].vddInd;
563 dcefclk_table->entries[entry_id].vddc =
564 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
567 for (entry_id = 0; entry_id < pixclk_table->count; entry_id++) {
568 voltage_id = pixclk_table->entries[entry_id].vddInd;
569 pixclk_table->entries[entry_id].vddc =
570 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
573 for (entry_id = 0; entry_id < dspclk_table->count; entry_id++) {
574 voltage_id = dspclk_table->entries[entry_id].vddInd;
575 dspclk_table->entries[entry_id].vddc =
576 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
579 for (entry_id = 0; entry_id < phyclk_table->count; entry_id++) {
580 voltage_id = phyclk_table->entries[entry_id].vddInd;
581 phyclk_table->entries[entry_id].vddc =
582 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
585 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
586 voltage_id = mclk_table->entries[entry_id].vddInd;
587 mclk_table->entries[entry_id].vddc =
588 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
589 voltage_id = mclk_table->entries[entry_id].vddciInd;
590 mclk_table->entries[entry_id].vddci =
591 table_info->vddci_lookup_table->entries[voltage_id].us_vdd;
592 voltage_id = mclk_table->entries[entry_id].mvddInd;
593 mclk_table->entries[entry_id].mvdd =
594 table_info->vddmem_lookup_table->entries[voltage_id].us_vdd;
597 for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
598 voltage_id = mm_table->entries[entry_id].vddcInd;
599 mm_table->entries[entry_id].vddc =
600 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
607 static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr,
608 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
610 uint32_t table_size, i, j;
611 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
613 PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count,
614 "Lookup table is empty", return -EINVAL);
616 table_size = lookup_table->count;
618 /* Sorting voltages */
619 for (i = 0; i < table_size - 1; i++) {
620 for (j = i + 1; j > 0; j--) {
621 if (lookup_table->entries[j].us_vdd <
622 lookup_table->entries[j - 1].us_vdd) {
623 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
624 lookup_table->entries[j - 1] = lookup_table->entries[j];
625 lookup_table->entries[j] = tmp_voltage_lookup_record;
633 static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
637 struct phm_ppt_v2_information *table_info =
638 (struct phm_ppt_v2_information *)(hwmgr->pptable);
639 #ifdef PPLIB_VEGA10_EVV_SUPPORT
640 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
642 tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr,
643 table_info->vddc_lookup_table, &(data->vddc_leakage));
647 tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
648 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
653 tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
657 tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
664 static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
666 struct phm_ppt_v2_information *table_info =
667 (struct phm_ppt_v2_information *)(hwmgr->pptable);
668 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
669 table_info->vdd_dep_on_socclk;
670 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
671 table_info->vdd_dep_on_mclk;
673 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
674 "VDD dependency on SCLK table is missing. \
675 This table is mandatory", return -EINVAL);
676 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
677 "VDD dependency on SCLK table is empty. \
678 This table is mandatory", return -EINVAL);
680 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table,
681 "VDD dependency on MCLK table is missing. \
682 This table is mandatory", return -EINVAL);
683 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
684 "VDD dependency on MCLK table is empty. \
685 This table is mandatory", return -EINVAL);
687 table_info->max_clock_voltage_on_ac.sclk =
688 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
689 table_info->max_clock_voltage_on_ac.mclk =
690 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
691 table_info->max_clock_voltage_on_ac.vddc =
692 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
693 table_info->max_clock_voltage_on_ac.vddci =
694 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
696 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
697 table_info->max_clock_voltage_on_ac.sclk;
698 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
699 table_info->max_clock_voltage_on_ac.mclk;
700 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
701 table_info->max_clock_voltage_on_ac.vddc;
702 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
703 table_info->max_clock_voltage_on_ac.vddci;
708 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
710 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
711 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
713 kfree(hwmgr->backend);
714 hwmgr->backend = NULL;
719 static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
722 struct vega10_hwmgr *data;
723 uint32_t config_telemetry = 0;
724 struct pp_atomfwctrl_voltage_table vol_table;
725 struct cgs_system_info sys_info = {0};
727 data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
731 hwmgr->backend = data;
733 vega10_set_default_registry_data(hwmgr);
735 data->disable_dpm_mask = 0xff;
736 data->workload_mask = 0xff;
738 /* need to set voltage control types before EVV patching */
739 data->vddc_control = VEGA10_VOLTAGE_CONTROL_NONE;
740 data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE;
741 data->vddci_control = VEGA10_VOLTAGE_CONTROL_NONE;
744 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
745 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
746 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
747 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2,
749 config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) |
750 (vol_table.telemetry_offset & 0xff);
751 data->vddc_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
754 kfree(hwmgr->backend);
755 hwmgr->backend = NULL;
756 PP_ASSERT_WITH_CODE(false,
757 "VDDCR_SOC is not SVID2!",
762 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
763 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) {
764 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
765 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2,
768 ((vol_table.telemetry_slope << 24) & 0xff000000) |
769 ((vol_table.telemetry_offset << 16) & 0xff0000);
770 data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
775 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
776 PHM_PlatformCaps_ControlVDDCI)) {
777 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
778 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
779 data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO;
782 data->config_telemetry = config_telemetry;
784 vega10_set_features_platform_caps(hwmgr);
786 vega10_init_dpm_defaults(hwmgr);
788 #ifdef PPLIB_VEGA10_EVV_SUPPORT
789 /* Get leakage voltage based on leakage ID. */
790 PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr),
791 "Get EVV Voltage Failed. Abort Driver loading!",
795 /* Patch our voltage dependency table with actual leakage voltage
796 * We need to perform leakage translation before it's used by other functions
798 vega10_complete_dependency_tables(hwmgr);
800 /* Parse pptable data read from VBIOS */
801 vega10_set_private_data_based_on_pptable(hwmgr);
803 data->is_tlu_enabled = false;
805 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
806 VEGA10_MAX_HARDWARE_POWERLEVELS;
807 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
808 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
810 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
811 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
812 hwmgr->platform_descriptor.clockStep.engineClock = 500;
813 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
815 sys_info.size = sizeof(struct cgs_system_info);
816 sys_info.info_id = CGS_SYSTEM_INFO_GFX_CU_INFO;
817 result = cgs_query_system_info(hwmgr->device, &sys_info);
818 data->total_active_cus = sys_info.value;
819 /* Setup default Overdrive Fan control settings */
820 data->odn_fan_table.target_fan_speed =
821 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
822 data->odn_fan_table.target_temperature =
823 hwmgr->thermal_controller.
824 advanceFanControlParameters.ucTargetTemperature;
825 data->odn_fan_table.min_performance_clock =
826 hwmgr->thermal_controller.advanceFanControlParameters.
827 ulMinFanSCLKAcousticLimit;
828 data->odn_fan_table.min_fan_limit =
829 hwmgr->thermal_controller.
830 advanceFanControlParameters.usFanPWMMinLimit *
831 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
836 static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
838 struct vega10_hwmgr *data =
839 (struct vega10_hwmgr *)(hwmgr->backend);
841 data->low_sclk_interrupt_threshold = 0;
846 static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
848 struct vega10_hwmgr *data =
849 (struct vega10_hwmgr *)(hwmgr->backend);
850 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
852 struct pp_atomfwctrl_voltage_table table;
858 ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM,
859 VOLTAGE_OBJ_GPIO_LUT, &table);
862 tmp = table.mask_low;
863 for (i = 0, j = 0; i < 32; i++) {
865 mask |= (uint32_t)(i << (8 * j));
873 pp_table->LedPin0 = (uint8_t)(mask & 0xff);
874 pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff);
875 pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff);
879 static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr)
881 PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr),
882 "Failed to init sclk threshold!",
885 PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr),
886 "Failed to set up led dpm config!",
892 static bool vega10_is_dpm_running(struct pp_hwmgr *hwmgr)
894 uint32_t features_enabled;
896 if (!vega10_get_smc_features(hwmgr->smumgr, &features_enabled)) {
897 if (features_enabled & SMC_DPM_FEATURES)
904 * Remove repeated voltage values and create table with unique values.
906 * @param hwmgr the address of the powerplay hardware manager.
907 * @param vol_table the pointer to changing voltage table
908 * @return 0 in success
911 static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr,
912 struct pp_atomfwctrl_voltage_table *vol_table)
917 struct pp_atomfwctrl_voltage_table *table;
919 PP_ASSERT_WITH_CODE(vol_table,
920 "Voltage Table empty.", return -EINVAL);
921 table = kzalloc(sizeof(struct pp_atomfwctrl_voltage_table),
927 table->mask_low = vol_table->mask_low;
928 table->phase_delay = vol_table->phase_delay;
930 for (i = 0; i < vol_table->count; i++) {
931 vvalue = vol_table->entries[i].value;
934 for (j = 0; j < table->count; j++) {
935 if (vvalue == table->entries[j].value) {
942 table->entries[table->count].value = vvalue;
943 table->entries[table->count].smio_low =
944 vol_table->entries[i].smio_low;
949 memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table));
955 static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
956 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
957 struct pp_atomfwctrl_voltage_table *vol_table)
961 PP_ASSERT_WITH_CODE(dep_table->count,
962 "Voltage Dependency Table empty.",
965 vol_table->mask_low = 0;
966 vol_table->phase_delay = 0;
967 vol_table->count = dep_table->count;
969 for (i = 0; i < vol_table->count; i++) {
970 vol_table->entries[i].value = dep_table->entries[i].mvdd;
971 vol_table->entries[i].smio_low = 0;
974 PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr,
976 "Failed to trim MVDD Table!",
982 static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr,
983 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
984 struct pp_atomfwctrl_voltage_table *vol_table)
988 PP_ASSERT_WITH_CODE(dep_table->count,
989 "Voltage Dependency Table empty.",
992 vol_table->mask_low = 0;
993 vol_table->phase_delay = 0;
994 vol_table->count = dep_table->count;
996 for (i = 0; i < dep_table->count; i++) {
997 vol_table->entries[i].value = dep_table->entries[i].vddci;
998 vol_table->entries[i].smio_low = 0;
1001 PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table),
1002 "Failed to trim VDDCI table.",
1008 static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr,
1009 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1010 struct pp_atomfwctrl_voltage_table *vol_table)
1014 PP_ASSERT_WITH_CODE(dep_table->count,
1015 "Voltage Dependency Table empty.",
1018 vol_table->mask_low = 0;
1019 vol_table->phase_delay = 0;
1020 vol_table->count = dep_table->count;
1022 for (i = 0; i < vol_table->count; i++) {
1023 vol_table->entries[i].value = dep_table->entries[i].vddc;
1024 vol_table->entries[i].smio_low = 0;
1030 /* ---- Voltage Tables ----
1031 * If the voltage table would be bigger than
1032 * what will fit into the state table on
1033 * the SMC keep only the higher entries.
1035 static void vega10_trim_voltage_table_to_fit_state_table(
1036 struct pp_hwmgr *hwmgr,
1037 uint32_t max_vol_steps,
1038 struct pp_atomfwctrl_voltage_table *vol_table)
1040 unsigned int i, diff;
1042 if (vol_table->count <= max_vol_steps)
1045 diff = vol_table->count - max_vol_steps;
1047 for (i = 0; i < max_vol_steps; i++)
1048 vol_table->entries[i] = vol_table->entries[i + diff];
1050 vol_table->count = max_vol_steps;
1054 * Create Voltage Tables.
1056 * @param hwmgr the address of the powerplay hardware manager.
1059 static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1061 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
1062 struct phm_ppt_v2_information *table_info =
1063 (struct phm_ppt_v2_information *)hwmgr->pptable;
1066 if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1067 data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1068 result = vega10_get_mvdd_voltage_table(hwmgr,
1069 table_info->vdd_dep_on_mclk,
1070 &(data->mvdd_voltage_table));
1071 PP_ASSERT_WITH_CODE(!result,
1072 "Failed to retrieve MVDDC table!",
1076 if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1077 result = vega10_get_vddci_voltage_table(hwmgr,
1078 table_info->vdd_dep_on_mclk,
1079 &(data->vddci_voltage_table));
1080 PP_ASSERT_WITH_CODE(!result,
1081 "Failed to retrieve VDDCI_MEM table!",
1085 if (data->vddc_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1086 data->vddc_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1087 result = vega10_get_vdd_voltage_table(hwmgr,
1088 table_info->vdd_dep_on_sclk,
1089 &(data->vddc_voltage_table));
1090 PP_ASSERT_WITH_CODE(!result,
1091 "Failed to retrieve VDDCR_SOC table!",
1095 PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16,
1096 "Too many voltage values for VDDC. Trimming to fit state table.",
1097 vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1098 16, &(data->vddc_voltage_table)));
1100 PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16,
1101 "Too many voltage values for VDDCI. Trimming to fit state table.",
1102 vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1103 16, &(data->vddci_voltage_table)));
1105 PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16,
1106 "Too many voltage values for MVDD. Trimming to fit state table.",
1107 vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1108 16, &(data->mvdd_voltage_table)));
1115 * @fn vega10_init_dpm_state
1116 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
1118 * @param dpm_state - the address of the DPM Table to initiailize.
1121 static void vega10_init_dpm_state(struct vega10_dpm_state *dpm_state)
1123 dpm_state->soft_min_level = 0xff;
1124 dpm_state->soft_max_level = 0xff;
1125 dpm_state->hard_min_level = 0xff;
1126 dpm_state->hard_max_level = 0xff;
1129 static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr,
1130 struct vega10_single_dpm_table *dpm_table,
1131 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
1135 for (i = 0; i < dep_table->count; i++) {
1136 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value !=
1137 dep_table->entries[i].clk) {
1138 dpm_table->dpm_levels[dpm_table->count].value =
1139 dep_table->entries[i].clk;
1140 dpm_table->dpm_levels[dpm_table->count].enabled = true;
1145 static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1147 struct vega10_hwmgr *data =
1148 (struct vega10_hwmgr *)(hwmgr->backend);
1149 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
1150 struct phm_ppt_v2_information *table_info =
1151 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1152 struct phm_ppt_v1_pcie_table *bios_pcie_table =
1153 table_info->pcie_table;
1156 PP_ASSERT_WITH_CODE(bios_pcie_table->count,
1157 "Incorrect number of PCIE States from VBIOS!",
1160 for (i = 0; i < NUM_LINK_LEVELS - 1; i++) {
1161 if (data->registry_data.pcieSpeedOverride)
1162 pcie_table->pcie_gen[i] =
1163 data->registry_data.pcieSpeedOverride;
1165 pcie_table->pcie_gen[i] =
1166 bios_pcie_table->entries[i].gen_speed;
1168 if (data->registry_data.pcieLaneOverride)
1169 pcie_table->pcie_lane[i] =
1170 data->registry_data.pcieLaneOverride;
1172 pcie_table->pcie_lane[i] =
1173 bios_pcie_table->entries[i].lane_width;
1175 if (data->registry_data.pcieClockOverride)
1176 pcie_table->lclk[i] =
1177 data->registry_data.pcieClockOverride;
1179 pcie_table->lclk[i] =
1180 bios_pcie_table->entries[i].pcie_sclk;
1182 pcie_table->count++;
1185 if (data->registry_data.pcieSpeedOverride)
1186 pcie_table->pcie_gen[i] = data->registry_data.pcieSpeedOverride;
1188 pcie_table->pcie_gen[i] =
1189 bios_pcie_table->entries[bios_pcie_table->count - 1].gen_speed;
1191 if (data->registry_data.pcieLaneOverride)
1192 pcie_table->pcie_lane[i] = data->registry_data.pcieLaneOverride;
1194 pcie_table->pcie_lane[i] =
1195 bios_pcie_table->entries[bios_pcie_table->count - 1].lane_width;
1197 if (data->registry_data.pcieClockOverride)
1198 pcie_table->lclk[i] = data->registry_data.pcieClockOverride;
1200 pcie_table->lclk[i] =
1201 bios_pcie_table->entries[bios_pcie_table->count - 1].pcie_sclk;
1203 pcie_table->count++;
1209 * This function is to initialize all DPM state tables
1210 * for SMU based on the dependency table.
1211 * Dynamic state patching function will then trim these
1212 * state tables to the allowed range based
1213 * on the power policy or external client requests,
1214 * such as UVD request, etc.
1216 static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1218 struct vega10_hwmgr *data =
1219 (struct vega10_hwmgr *)(hwmgr->backend);
1220 struct phm_ppt_v2_information *table_info =
1221 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1222 struct vega10_single_dpm_table *dpm_table;
1225 struct phm_ppt_v1_clock_voltage_dependency_table *dep_soc_table =
1226 table_info->vdd_dep_on_socclk;
1227 struct phm_ppt_v1_clock_voltage_dependency_table *dep_gfx_table =
1228 table_info->vdd_dep_on_sclk;
1229 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1230 table_info->vdd_dep_on_mclk;
1231 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_mm_table =
1232 table_info->mm_dep_table;
1233 struct phm_ppt_v1_clock_voltage_dependency_table *dep_dcef_table =
1234 table_info->vdd_dep_on_dcefclk;
1235 struct phm_ppt_v1_clock_voltage_dependency_table *dep_pix_table =
1236 table_info->vdd_dep_on_pixclk;
1237 struct phm_ppt_v1_clock_voltage_dependency_table *dep_disp_table =
1238 table_info->vdd_dep_on_dispclk;
1239 struct phm_ppt_v1_clock_voltage_dependency_table *dep_phy_table =
1240 table_info->vdd_dep_on_phyclk;
1242 PP_ASSERT_WITH_CODE(dep_soc_table,
1243 "SOCCLK dependency table is missing. This table is mandatory",
1245 PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1,
1246 "SOCCLK dependency table is empty. This table is mandatory",
1249 PP_ASSERT_WITH_CODE(dep_gfx_table,
1250 "GFXCLK dependency table is missing. This table is mandatory",
1252 PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1,
1253 "GFXCLK dependency table is empty. This table is mandatory",
1256 PP_ASSERT_WITH_CODE(dep_mclk_table,
1257 "MCLK dependency table is missing. This table is mandatory",
1259 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1260 "MCLK dependency table has to have is missing. This table is mandatory",
1263 /* Initialize Sclk DPM table based on allow Sclk values */
1264 data->dpm_table.soc_table.count = 0;
1265 data->dpm_table.gfx_table.count = 0;
1266 data->dpm_table.dcef_table.count = 0;
1268 dpm_table = &(data->dpm_table.soc_table);
1269 vega10_setup_default_single_dpm_table(hwmgr,
1273 vega10_init_dpm_state(&(dpm_table->dpm_state));
1275 dpm_table = &(data->dpm_table.gfx_table);
1276 vega10_setup_default_single_dpm_table(hwmgr,
1279 vega10_init_dpm_state(&(dpm_table->dpm_state));
1281 /* Initialize Mclk DPM table based on allow Mclk values */
1282 data->dpm_table.mem_table.count = 0;
1283 dpm_table = &(data->dpm_table.mem_table);
1284 vega10_setup_default_single_dpm_table(hwmgr,
1287 vega10_init_dpm_state(&(dpm_table->dpm_state));
1289 data->dpm_table.eclk_table.count = 0;
1290 dpm_table = &(data->dpm_table.eclk_table);
1291 for (i = 0; i < dep_mm_table->count; i++) {
1292 if (i == 0 || dpm_table->dpm_levels
1293 [dpm_table->count - 1].value !=
1294 dep_mm_table->entries[i].eclk) {
1295 dpm_table->dpm_levels[dpm_table->count].value =
1296 dep_mm_table->entries[i].eclk;
1297 dpm_table->dpm_levels[dpm_table->count].enabled =
1298 (i == 0) ? true : false;
1302 vega10_init_dpm_state(&(dpm_table->dpm_state));
1304 data->dpm_table.vclk_table.count = 0;
1305 data->dpm_table.dclk_table.count = 0;
1306 dpm_table = &(data->dpm_table.vclk_table);
1307 for (i = 0; i < dep_mm_table->count; i++) {
1308 if (i == 0 || dpm_table->dpm_levels
1309 [dpm_table->count - 1].value !=
1310 dep_mm_table->entries[i].vclk) {
1311 dpm_table->dpm_levels[dpm_table->count].value =
1312 dep_mm_table->entries[i].vclk;
1313 dpm_table->dpm_levels[dpm_table->count].enabled =
1314 (i == 0) ? true : false;
1318 vega10_init_dpm_state(&(dpm_table->dpm_state));
1320 dpm_table = &(data->dpm_table.dclk_table);
1321 for (i = 0; i < dep_mm_table->count; i++) {
1322 if (i == 0 || dpm_table->dpm_levels
1323 [dpm_table->count - 1].value !=
1324 dep_mm_table->entries[i].dclk) {
1325 dpm_table->dpm_levels[dpm_table->count].value =
1326 dep_mm_table->entries[i].dclk;
1327 dpm_table->dpm_levels[dpm_table->count].enabled =
1328 (i == 0) ? true : false;
1332 vega10_init_dpm_state(&(dpm_table->dpm_state));
1334 /* Assume there is no headless Vega10 for now */
1335 dpm_table = &(data->dpm_table.dcef_table);
1336 vega10_setup_default_single_dpm_table(hwmgr,
1340 vega10_init_dpm_state(&(dpm_table->dpm_state));
1342 dpm_table = &(data->dpm_table.pixel_table);
1343 vega10_setup_default_single_dpm_table(hwmgr,
1347 vega10_init_dpm_state(&(dpm_table->dpm_state));
1349 dpm_table = &(data->dpm_table.display_table);
1350 vega10_setup_default_single_dpm_table(hwmgr,
1354 vega10_init_dpm_state(&(dpm_table->dpm_state));
1356 dpm_table = &(data->dpm_table.phy_table);
1357 vega10_setup_default_single_dpm_table(hwmgr,
1361 vega10_init_dpm_state(&(dpm_table->dpm_state));
1363 vega10_setup_default_pcie_table(hwmgr);
1365 /* save a copy of the default DPM table */
1366 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1367 sizeof(struct vega10_dpm_table));
1369 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1370 PHM_PlatformCaps_ODNinACSupport) ||
1371 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1372 PHM_PlatformCaps_ODNinDCSupport)) {
1373 data->odn_dpm_table.odn_core_clock_dpm_levels.
1374 number_of_performance_levels = data->dpm_table.gfx_table.count;
1375 for (i = 0; i < data->dpm_table.gfx_table.count; i++) {
1376 data->odn_dpm_table.odn_core_clock_dpm_levels.
1377 performance_level_entries[i].clock =
1378 data->dpm_table.gfx_table.dpm_levels[i].value;
1379 data->odn_dpm_table.odn_core_clock_dpm_levels.
1380 performance_level_entries[i].enabled = true;
1383 data->odn_dpm_table.vdd_dependency_on_sclk.count =
1384 dep_gfx_table->count;
1385 for (i = 0; i < dep_gfx_table->count; i++) {
1386 data->odn_dpm_table.vdd_dependency_on_sclk.entries[i].clk =
1387 dep_gfx_table->entries[i].clk;
1388 data->odn_dpm_table.vdd_dependency_on_sclk.entries[i].vddInd =
1389 dep_gfx_table->entries[i].vddInd;
1390 data->odn_dpm_table.vdd_dependency_on_sclk.entries[i].cks_enable =
1391 dep_gfx_table->entries[i].cks_enable;
1392 data->odn_dpm_table.vdd_dependency_on_sclk.entries[i].cks_voffset =
1393 dep_gfx_table->entries[i].cks_voffset;
1396 data->odn_dpm_table.odn_memory_clock_dpm_levels.
1397 number_of_performance_levels = data->dpm_table.mem_table.count;
1398 for (i = 0; i < data->dpm_table.mem_table.count; i++) {
1399 data->odn_dpm_table.odn_memory_clock_dpm_levels.
1400 performance_level_entries[i].clock =
1401 data->dpm_table.mem_table.dpm_levels[i].value;
1402 data->odn_dpm_table.odn_memory_clock_dpm_levels.
1403 performance_level_entries[i].enabled = true;
1406 data->odn_dpm_table.vdd_dependency_on_mclk.count = dep_mclk_table->count;
1407 for (i = 0; i < dep_mclk_table->count; i++) {
1408 data->odn_dpm_table.vdd_dependency_on_mclk.entries[i].clk =
1409 dep_mclk_table->entries[i].clk;
1410 data->odn_dpm_table.vdd_dependency_on_mclk.entries[i].vddInd =
1411 dep_mclk_table->entries[i].vddInd;
1412 data->odn_dpm_table.vdd_dependency_on_mclk.entries[i].vddci =
1413 dep_mclk_table->entries[i].vddci;
1421 * @fn vega10_populate_ulv_state
1422 * @brief Function to provide parameters for Utral Low Voltage state to SMC.
1424 * @param hwmgr - the address of the hardware manager.
1427 static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)
1429 struct vega10_hwmgr *data =
1430 (struct vega10_hwmgr *)(hwmgr->backend);
1431 struct phm_ppt_v2_information *table_info =
1432 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1434 data->smc_state_table.pp_table.UlvOffsetVid =
1435 (uint8_t)(table_info->us_ulv_voltage_offset *
1436 VOLTAGE_VID_OFFSET_SCALE2 /
1437 VOLTAGE_VID_OFFSET_SCALE1);
1439 data->smc_state_table.pp_table.UlvSmnclkDid =
1440 (uint8_t)(table_info->us_ulv_smnclk_did);
1441 data->smc_state_table.pp_table.UlvMp1clkDid =
1442 (uint8_t)(table_info->us_ulv_mp1clk_did);
1443 data->smc_state_table.pp_table.UlvGfxclkBypass =
1444 (uint8_t)(table_info->us_ulv_gfxclk_bypass);
1445 data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 =
1446 (uint8_t)(data->vddc_voltage_table.psi0_enable);
1447 data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 =
1448 (uint8_t)(data->vddc_voltage_table.psi1_enable);
1453 static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr,
1454 uint32_t lclock, uint8_t *curr_lclk_did)
1456 struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1458 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1460 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1462 "Failed to get LCLK clock settings from VBIOS!",
1465 *curr_lclk_did = dividers.ulDid;
1470 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
1473 struct vega10_hwmgr *data =
1474 (struct vega10_hwmgr *)(hwmgr->backend);
1475 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1476 struct vega10_pcie_table *pcie_table =
1477 &(data->dpm_table.pcie_table);
1480 for (i = 0; i < pcie_table->count; i++) {
1481 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[i];
1482 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i];
1484 result = vega10_populate_single_lclk_level(hwmgr,
1485 pcie_table->lclk[i], &(pp_table->LclkDid[i]));
1487 pr_info("Populate LClock Level %d Failed!\n", i);
1493 while (i < NUM_LINK_LEVELS) {
1494 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j];
1495 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j];
1497 result = vega10_populate_single_lclk_level(hwmgr,
1498 pcie_table->lclk[j], &(pp_table->LclkDid[i]));
1500 pr_info("Populate LClock Level %d Failed!\n", i);
1510 * Populates single SMC GFXSCLK structure using the provided engine clock
1512 * @param hwmgr the address of the hardware manager
1513 * @param gfx_clock the GFX clock to use to populate the structure.
1514 * @param current_gfxclk_level location in PPTable for the SMC GFXCLK structure.
1517 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
1518 uint32_t gfx_clock, PllSetting_t *current_gfxclk_level)
1520 struct phm_ppt_v2_information *table_info =
1521 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1522 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk =
1523 table_info->vdd_dep_on_sclk;
1524 struct vega10_hwmgr *data =
1525 (struct vega10_hwmgr *)(hwmgr->backend);
1526 struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1529 if (data->apply_overdrive_next_settings_mask &
1530 DPMTABLE_OD_UPDATE_VDDC)
1531 dep_on_sclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1532 &(data->odn_dpm_table.vdd_dependency_on_sclk);
1534 PP_ASSERT_WITH_CODE(dep_on_sclk,
1535 "Invalid SOC_VDD-GFX_CLK Dependency Table!",
1538 for (i = 0; i < dep_on_sclk->count; i++) {
1539 if (dep_on_sclk->entries[i].clk == gfx_clock)
1543 PP_ASSERT_WITH_CODE(dep_on_sclk->count > i,
1544 "Cannot find gfx_clk in SOC_VDD-GFX_CLK!",
1546 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1547 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK,
1548 gfx_clock, ÷rs),
1549 "Failed to get GFX Clock settings from VBIOS!",
1552 /* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */
1553 current_gfxclk_level->FbMult =
1554 cpu_to_le32(dividers.ulPll_fb_mult);
1555 /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */
1556 current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;
1557 current_gfxclk_level->SsFbMult =
1558 cpu_to_le32(dividers.ulPll_ss_fbsmult);
1559 current_gfxclk_level->SsSlewFrac =
1560 cpu_to_le16(dividers.usPll_ss_slew_frac);
1561 current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);
1567 * @brief Populates single SMC SOCCLK structure using the provided clock.
1569 * @param hwmgr - the address of the hardware manager.
1570 * @param soc_clock - the SOC clock to use to populate the structure.
1571 * @param current_socclk_level - location in PPTable for the SMC SOCCLK structure.
1572 * @return 0 on success..
1574 static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr,
1575 uint32_t soc_clock, uint8_t *current_soc_did,
1576 uint8_t *current_vol_index)
1578 struct phm_ppt_v2_information *table_info =
1579 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1580 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_soc =
1581 table_info->vdd_dep_on_socclk;
1582 struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1585 PP_ASSERT_WITH_CODE(dep_on_soc,
1586 "Invalid SOC_VDD-SOC_CLK Dependency Table!",
1588 for (i = 0; i < dep_on_soc->count; i++) {
1589 if (dep_on_soc->entries[i].clk == soc_clock)
1592 PP_ASSERT_WITH_CODE(dep_on_soc->count > i,
1593 "Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency Table",
1595 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1596 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1597 soc_clock, ÷rs),
1598 "Failed to get SOC Clock settings from VBIOS!",
1601 *current_soc_did = (uint8_t)dividers.ulDid;
1602 *current_vol_index = (uint8_t)(dep_on_soc->entries[i].vddInd);
1607 uint16_t vega10_locate_vddc_given_clock(struct pp_hwmgr *hwmgr,
1609 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
1613 for (i = 0; i < dep_table->count; i++) {
1614 if (dep_table->entries[i].clk == clk)
1615 return dep_table->entries[i].vddc;
1618 pr_info("[LocateVddcGivenClock] Cannot locate SOC Vddc for this clock!");
1623 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1625 * @param hwmgr the address of the hardware manager
1627 static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1629 struct vega10_hwmgr *data =
1630 (struct vega10_hwmgr *)(hwmgr->backend);
1631 struct phm_ppt_v2_information *table_info =
1632 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1633 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
1634 table_info->vdd_dep_on_socclk;
1635 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1636 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
1640 for (i = 0; i < dpm_table->count; i++) {
1641 result = vega10_populate_single_gfx_level(hwmgr,
1642 dpm_table->dpm_levels[i].value,
1643 &(pp_table->GfxclkLevel[i]));
1649 while (i < NUM_GFXCLK_DPM_LEVELS) {
1650 result = vega10_populate_single_gfx_level(hwmgr,
1651 dpm_table->dpm_levels[j].value,
1652 &(pp_table->GfxclkLevel[i]));
1658 pp_table->GfxclkSlewRate =
1659 cpu_to_le16(table_info->us_gfxclk_slew_rate);
1661 dpm_table = &(data->dpm_table.soc_table);
1662 for (i = 0; i < dpm_table->count; i++) {
1663 pp_table->SocVid[i] =
1664 (uint8_t)convert_to_vid(
1665 vega10_locate_vddc_given_clock(hwmgr,
1666 dpm_table->dpm_levels[i].value,
1668 result = vega10_populate_single_soc_level(hwmgr,
1669 dpm_table->dpm_levels[i].value,
1670 &(pp_table->SocclkDid[i]),
1671 &(pp_table->SocDpmVoltageIndex[i]));
1677 while (i < NUM_SOCCLK_DPM_LEVELS) {
1678 pp_table->SocVid[i] = pp_table->SocVid[j];
1679 result = vega10_populate_single_soc_level(hwmgr,
1680 dpm_table->dpm_levels[j].value,
1681 &(pp_table->SocclkDid[i]),
1682 &(pp_table->SocDpmVoltageIndex[i]));
1692 * @brief Populates single SMC GFXCLK structure using the provided clock.
1694 * @param hwmgr - the address of the hardware manager.
1695 * @param mem_clock - the memory clock to use to populate the structure.
1696 * @return 0 on success..
1698 static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1699 uint32_t mem_clock, uint8_t *current_mem_vid,
1700 PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind)
1702 struct vega10_hwmgr *data =
1703 (struct vega10_hwmgr *)(hwmgr->backend);
1704 struct phm_ppt_v2_information *table_info =
1705 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1706 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk =
1707 table_info->vdd_dep_on_mclk;
1708 struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1711 if (data->apply_overdrive_next_settings_mask &
1712 DPMTABLE_OD_UPDATE_VDDC)
1713 dep_on_mclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1714 &data->odn_dpm_table.vdd_dependency_on_mclk;
1716 PP_ASSERT_WITH_CODE(dep_on_mclk,
1717 "Invalid SOC_VDD-UCLK Dependency Table!",
1720 for (i = 0; i < dep_on_mclk->count; i++) {
1721 if (dep_on_mclk->entries[i].clk == mem_clock)
1725 PP_ASSERT_WITH_CODE(dep_on_mclk->count > i,
1726 "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!",
1729 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1730 hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, ÷rs),
1731 "Failed to get UCLK settings from VBIOS!",
1735 (uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd));
1736 *current_mem_soc_vind =
1737 (uint8_t)(dep_on_mclk->entries[i].vddInd);
1738 current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult);
1739 current_memclk_level->Did = (uint8_t)(dividers.ulDid);
1741 PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1,
1742 "Invalid Divider ID!",
1749 * @brief Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states.
1751 * @param pHwMgr - the address of the hardware manager.
1752 * @return PP_Result_OK on success.
1754 static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1756 struct vega10_hwmgr *data =
1757 (struct vega10_hwmgr *)(hwmgr->backend);
1758 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1759 struct vega10_single_dpm_table *dpm_table =
1760 &(data->dpm_table.mem_table);
1762 uint32_t i, j, reg, mem_channels;
1764 for (i = 0; i < dpm_table->count; i++) {
1765 result = vega10_populate_single_memory_level(hwmgr,
1766 dpm_table->dpm_levels[i].value,
1767 &(pp_table->MemVid[i]),
1768 &(pp_table->UclkLevel[i]),
1769 &(pp_table->MemSocVoltageIndex[i]));
1775 while (i < NUM_UCLK_DPM_LEVELS) {
1776 result = vega10_populate_single_memory_level(hwmgr,
1777 dpm_table->dpm_levels[j].value,
1778 &(pp_table->MemVid[i]),
1779 &(pp_table->UclkLevel[i]),
1780 &(pp_table->MemSocVoltageIndex[i]));
1786 reg = soc15_get_register_offset(DF_HWID, 0,
1787 mmDF_CS_AON0_DramBaseAddress0_BASE_IDX,
1788 mmDF_CS_AON0_DramBaseAddress0);
1789 mem_channels = (cgs_read_register(hwmgr->device, reg) &
1790 DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
1791 DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
1792 pp_table->NumMemoryChannels = cpu_to_le16(mem_channels);
1793 pp_table->MemoryChannelWidth =
1794 cpu_to_le16(HBM_MEMORY_CHANNEL_WIDTH *
1795 channel_number[mem_channels]);
1797 pp_table->LowestUclkReservedForUlv =
1798 (uint8_t)(data->lowest_uclk_reserved_for_ulv);
1803 static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr,
1804 DSPCLK_e disp_clock)
1806 struct vega10_hwmgr *data =
1807 (struct vega10_hwmgr *)(hwmgr->backend);
1808 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1809 struct phm_ppt_v2_information *table_info =
1810 (struct phm_ppt_v2_information *)
1812 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
1814 uint16_t clk = 0, vddc = 0;
1817 switch (disp_clock) {
1818 case DSPCLK_DCEFCLK:
1819 dep_table = table_info->vdd_dep_on_dcefclk;
1821 case DSPCLK_DISPCLK:
1822 dep_table = table_info->vdd_dep_on_dispclk;
1825 dep_table = table_info->vdd_dep_on_pixclk;
1828 dep_table = table_info->vdd_dep_on_phyclk;
1834 PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS,
1835 "Number Of Entries Exceeded maximum!",
1838 for (i = 0; i < dep_table->count; i++) {
1839 clk = (uint16_t)(dep_table->entries[i].clk / 100);
1840 vddc = table_info->vddc_lookup_table->
1841 entries[dep_table->entries[i].vddInd].us_vdd;
1842 vid = (uint8_t)convert_to_vid(vddc);
1843 pp_table->DisplayClockTable[disp_clock][i].Freq =
1845 pp_table->DisplayClockTable[disp_clock][i].Vid =
1849 while (i < NUM_DSPCLK_LEVELS) {
1850 pp_table->DisplayClockTable[disp_clock][i].Freq =
1852 pp_table->DisplayClockTable[disp_clock][i].Vid =
1860 static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr)
1864 for (i = 0; i < DSPCLK_COUNT; i++) {
1865 PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i),
1866 "Failed to populate Clock in DisplayClockTable!",
1873 static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr,
1874 uint32_t eclock, uint8_t *current_eclk_did,
1875 uint8_t *current_soc_vol)
1877 struct phm_ppt_v2_information *table_info =
1878 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1879 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
1880 table_info->mm_dep_table;
1881 struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1884 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1885 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1887 "Failed to get ECLK clock settings from VBIOS!",
1890 *current_eclk_did = (uint8_t)dividers.ulDid;
1892 for (i = 0; i < dep_table->count; i++) {
1893 if (dep_table->entries[i].eclk == eclock)
1894 *current_soc_vol = dep_table->entries[i].vddcInd;
1900 static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr)
1902 struct vega10_hwmgr *data =
1903 (struct vega10_hwmgr *)(hwmgr->backend);
1904 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1905 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table);
1906 int result = -EINVAL;
1909 for (i = 0; i < dpm_table->count; i++) {
1910 result = vega10_populate_single_eclock_level(hwmgr,
1911 dpm_table->dpm_levels[i].value,
1912 &(pp_table->EclkDid[i]),
1913 &(pp_table->VceDpmVoltageIndex[i]));
1919 while (i < NUM_VCE_DPM_LEVELS) {
1920 result = vega10_populate_single_eclock_level(hwmgr,
1921 dpm_table->dpm_levels[j].value,
1922 &(pp_table->EclkDid[i]),
1923 &(pp_table->VceDpmVoltageIndex[i]));
1932 static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr,
1933 uint32_t vclock, uint8_t *current_vclk_did)
1935 struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1937 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1938 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1940 "Failed to get VCLK clock settings from VBIOS!",
1943 *current_vclk_did = (uint8_t)dividers.ulDid;
1948 static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr,
1949 uint32_t dclock, uint8_t *current_dclk_did)
1951 struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1953 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1954 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1956 "Failed to get DCLK clock settings from VBIOS!",
1959 *current_dclk_did = (uint8_t)dividers.ulDid;
1964 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)
1966 struct vega10_hwmgr *data =
1967 (struct vega10_hwmgr *)(hwmgr->backend);
1968 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1969 struct vega10_single_dpm_table *vclk_dpm_table =
1970 &(data->dpm_table.vclk_table);
1971 struct vega10_single_dpm_table *dclk_dpm_table =
1972 &(data->dpm_table.dclk_table);
1973 struct phm_ppt_v2_information *table_info =
1974 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1975 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
1976 table_info->mm_dep_table;
1977 int result = -EINVAL;
1980 for (i = 0; i < vclk_dpm_table->count; i++) {
1981 result = vega10_populate_single_vclock_level(hwmgr,
1982 vclk_dpm_table->dpm_levels[i].value,
1983 &(pp_table->VclkDid[i]));
1989 while (i < NUM_UVD_DPM_LEVELS) {
1990 result = vega10_populate_single_vclock_level(hwmgr,
1991 vclk_dpm_table->dpm_levels[j].value,
1992 &(pp_table->VclkDid[i]));
1998 for (i = 0; i < dclk_dpm_table->count; i++) {
1999 result = vega10_populate_single_dclock_level(hwmgr,
2000 dclk_dpm_table->dpm_levels[i].value,
2001 &(pp_table->DclkDid[i]));
2007 while (i < NUM_UVD_DPM_LEVELS) {
2008 result = vega10_populate_single_dclock_level(hwmgr,
2009 dclk_dpm_table->dpm_levels[j].value,
2010 &(pp_table->DclkDid[i]));
2016 for (i = 0; i < dep_table->count; i++) {
2017 if (dep_table->entries[i].vclk ==
2018 vclk_dpm_table->dpm_levels[i].value &&
2019 dep_table->entries[i].dclk ==
2020 dclk_dpm_table->dpm_levels[i].value)
2021 pp_table->UvdDpmVoltageIndex[i] =
2022 dep_table->entries[i].vddcInd;
2028 while (i < NUM_UVD_DPM_LEVELS) {
2029 pp_table->UvdDpmVoltageIndex[i] = dep_table->entries[j].vddcInd;
2036 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)
2038 struct vega10_hwmgr *data =
2039 (struct vega10_hwmgr *)(hwmgr->backend);
2040 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2041 struct phm_ppt_v2_information *table_info =
2042 (struct phm_ppt_v2_information *)(hwmgr->pptable);
2043 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2044 table_info->vdd_dep_on_sclk;
2047 for (i = 0; dep_table->count; i++) {
2048 pp_table->CksEnable[i] = dep_table->entries[i].cks_enable;
2049 pp_table->CksVidOffset[i] = convert_to_vid(
2050 dep_table->entries[i].cks_voffset);
2056 static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
2058 struct vega10_hwmgr *data =
2059 (struct vega10_hwmgr *)(hwmgr->backend);
2060 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2061 struct phm_ppt_v2_information *table_info =
2062 (struct phm_ppt_v2_information *)(hwmgr->pptable);
2063 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2064 table_info->vdd_dep_on_sclk;
2065 struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
2069 pp_table->MinVoltageVid = (uint8_t)0xff;
2070 pp_table->MaxVoltageVid = (uint8_t)0;
2072 if (data->smu_features[GNLD_AVFS].supported) {
2073 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
2075 pp_table->MinVoltageVid = (uint8_t)
2076 convert_to_vid((uint16_t)(avfs_params.ulMaxVddc));
2077 pp_table->MaxVoltageVid = (uint8_t)
2078 convert_to_vid((uint16_t)(avfs_params.ulMinVddc));
2079 pp_table->BtcGbVdroopTableCksOn.a0 =
2080 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0);
2081 pp_table->BtcGbVdroopTableCksOn.a1 =
2082 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1);
2083 pp_table->BtcGbVdroopTableCksOn.a2 =
2084 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2);
2086 pp_table->BtcGbVdroopTableCksOff.a0 =
2087 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA0);
2088 pp_table->BtcGbVdroopTableCksOff.a1 =
2089 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA1);
2090 pp_table->BtcGbVdroopTableCksOff.a2 =
2091 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA2);
2093 pp_table->AvfsGbCksOn.m1 =
2094 cpu_to_le32(avfs_params.ulGbFuseTableCksonM1);
2095 pp_table->AvfsGbCksOn.m2 =
2096 cpu_to_le16(avfs_params.usGbFuseTableCksonM2);
2097 pp_table->AvfsGbCksOn.b =
2098 cpu_to_le32(avfs_params.ulGbFuseTableCksonB);
2099 pp_table->AvfsGbCksOn.m1_shift = 24;
2100 pp_table->AvfsGbCksOn.m2_shift = 12;
2102 pp_table->AvfsGbCksOff.m1 =
2103 cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1);
2104 pp_table->AvfsGbCksOff.m2 =
2105 cpu_to_le16(avfs_params.usGbFuseTableCksoffM2);
2106 pp_table->AvfsGbCksOff.b =
2107 cpu_to_le32(avfs_params.ulGbFuseTableCksoffB);
2108 pp_table->AvfsGbCksOff.m1_shift = 24;
2109 pp_table->AvfsGbCksOff.m2_shift = 12;
2111 pp_table->AConstant[0] =
2112 cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0);
2113 pp_table->AConstant[1] =
2114 cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1);
2115 pp_table->AConstant[2] =
2116 cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2);
2117 pp_table->DC_tol_sigma =
2118 cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2119 pp_table->Platform_mean =
2120 cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean);
2121 pp_table->PSM_Age_CompFactor =
2122 cpu_to_le16(avfs_params.usPsmAgeComfactor);
2123 pp_table->Platform_sigma =
2124 cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2126 for (i = 0; i < dep_table->count; i++)
2127 pp_table->StaticVoltageOffsetVid[i] = (uint8_t)
2128 (dep_table->entries[i].sclk_offset *
2129 VOLTAGE_VID_OFFSET_SCALE2 /
2130 VOLTAGE_VID_OFFSET_SCALE1);
2132 pp_table->OverrideBtcGbCksOn =
2133 avfs_params.ucEnableGbVdroopTableCkson;
2134 pp_table->OverrideAvfsGbCksOn =
2135 avfs_params.ucEnableGbFuseTableCkson;
2137 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2138 data->disp_clk_quad_eqn_a) &&
2139 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2140 data->disp_clk_quad_eqn_b)) {
2141 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2142 (int32_t)data->disp_clk_quad_eqn_a;
2143 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2144 (int16_t)data->disp_clk_quad_eqn_b;
2145 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2146 (int32_t)data->disp_clk_quad_eqn_c;
2148 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2149 (int32_t)avfs_params.ulDispclk2GfxclkM1;
2150 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2151 (int16_t)avfs_params.usDispclk2GfxclkM2;
2152 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2153 (int32_t)avfs_params.ulDispclk2GfxclkB;
2156 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24;
2157 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12;
2159 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2160 data->dcef_clk_quad_eqn_a) &&
2161 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2162 data->dcef_clk_quad_eqn_b)) {
2163 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2164 (int32_t)data->dcef_clk_quad_eqn_a;
2165 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2166 (int16_t)data->dcef_clk_quad_eqn_b;
2167 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2168 (int32_t)data->dcef_clk_quad_eqn_c;
2170 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2171 (int32_t)avfs_params.ulDcefclk2GfxclkM1;
2172 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2173 (int16_t)avfs_params.usDcefclk2GfxclkM2;
2174 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2175 (int32_t)avfs_params.ulDcefclk2GfxclkB;
2178 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24;
2179 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12;
2181 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2182 data->pixel_clk_quad_eqn_a) &&
2183 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2184 data->pixel_clk_quad_eqn_b)) {
2185 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2186 (int32_t)data->pixel_clk_quad_eqn_a;
2187 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2188 (int16_t)data->pixel_clk_quad_eqn_b;
2189 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2190 (int32_t)data->pixel_clk_quad_eqn_c;
2192 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2193 (int32_t)avfs_params.ulPixelclk2GfxclkM1;
2194 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2195 (int16_t)avfs_params.usPixelclk2GfxclkM2;
2196 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2197 (int32_t)avfs_params.ulPixelclk2GfxclkB;
2200 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24;
2201 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12;
2203 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2204 data->phy_clk_quad_eqn_a) &&
2205 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2206 data->phy_clk_quad_eqn_b)) {
2207 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2208 (int32_t)data->phy_clk_quad_eqn_a;
2209 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2210 (int16_t)data->phy_clk_quad_eqn_b;
2211 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2212 (int32_t)data->phy_clk_quad_eqn_c;
2214 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2215 (int32_t)avfs_params.ulPhyclk2GfxclkM1;
2216 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2217 (int16_t)avfs_params.usPhyclk2GfxclkM2;
2218 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2219 (int32_t)avfs_params.ulPhyclk2GfxclkB;
2222 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24;
2223 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12;
2225 data->smu_features[GNLD_AVFS].supported = false;
2232 static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
2234 struct vega10_hwmgr *data =
2235 (struct vega10_hwmgr *)(hwmgr->backend);
2236 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2237 struct pp_atomfwctrl_gpio_parameters gpio_params = {0};
2240 result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params);
2242 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2243 PHM_PlatformCaps_RegulatorHot) &&
2244 (data->registry_data.regulator_hot_gpio_support)) {
2245 pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio;
2246 pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity;
2247 pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio;
2248 pp_table->VR1HotPolarity = gpio_params.ucVR1HotPolarity;
2250 pp_table->VR0HotGpio = 0;
2251 pp_table->VR0HotPolarity = 0;
2252 pp_table->VR1HotGpio = 0;
2253 pp_table->VR1HotPolarity = 0;
2256 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2257 PHM_PlatformCaps_AutomaticDCTransition) &&
2258 (data->registry_data.ac_dc_switch_gpio_support)) {
2259 pp_table->AcDcGpio = gpio_params.ucAcDcGpio;
2260 pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity;
2262 pp_table->AcDcGpio = 0;
2263 pp_table->AcDcPolarity = 0;
2270 static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
2272 struct vega10_hwmgr *data =
2273 (struct vega10_hwmgr *)(hwmgr->backend);
2275 if (data->smu_features[GNLD_AVFS].supported) {
2277 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
2279 data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2280 "[avfs_control] Attempt to Enable AVFS feature Failed!",
2282 data->smu_features[GNLD_AVFS].enabled = true;
2284 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
2286 data->smu_features[GNLD_AVFS].smu_feature_id),
2287 "[avfs_control] Attempt to Disable AVFS feature Failed!",
2289 data->smu_features[GNLD_AVFS].enabled = false;
2297 * Initializes the SMC table and uploads it
2299 * @param hwmgr the address of the powerplay hardware manager.
2300 * @param pInput the pointer to input data (PowerState)
2303 static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
2306 struct vega10_hwmgr *data =
2307 (struct vega10_hwmgr *)(hwmgr->backend);
2308 struct phm_ppt_v2_information *table_info =
2309 (struct phm_ppt_v2_information *)(hwmgr->pptable);
2310 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2311 struct pp_atomfwctrl_voltage_table voltage_table;
2313 result = vega10_setup_default_dpm_tables(hwmgr);
2314 PP_ASSERT_WITH_CODE(!result,
2315 "Failed to setup default DPM tables!",
2318 pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC,
2319 VOLTAGE_OBJ_SVID2, &voltage_table);
2320 pp_table->MaxVidStep = voltage_table.max_vid_step;
2322 pp_table->GfxDpmVoltageMode =
2323 (uint8_t)(table_info->uc_gfx_dpm_voltage_mode);
2324 pp_table->SocDpmVoltageMode =
2325 (uint8_t)(table_info->uc_soc_dpm_voltage_mode);
2326 pp_table->UclkDpmVoltageMode =
2327 (uint8_t)(table_info->uc_uclk_dpm_voltage_mode);
2328 pp_table->UvdDpmVoltageMode =
2329 (uint8_t)(table_info->uc_uvd_dpm_voltage_mode);
2330 pp_table->VceDpmVoltageMode =
2331 (uint8_t)(table_info->uc_vce_dpm_voltage_mode);
2332 pp_table->Mp0DpmVoltageMode =
2333 (uint8_t)(table_info->uc_mp0_dpm_voltage_mode);
2334 pp_table->DisplayDpmVoltageMode =
2335 (uint8_t)(table_info->uc_dcef_dpm_voltage_mode);
2337 if (data->registry_data.ulv_support &&
2338 table_info->us_ulv_voltage_offset) {
2339 result = vega10_populate_ulv_state(hwmgr);
2340 PP_ASSERT_WITH_CODE(!result,
2341 "Failed to initialize ULV state!",
2345 result = vega10_populate_smc_link_levels(hwmgr);
2346 PP_ASSERT_WITH_CODE(!result,
2347 "Failed to initialize Link Level!",
2350 result = vega10_populate_all_graphic_levels(hwmgr);
2351 PP_ASSERT_WITH_CODE(!result,
2352 "Failed to initialize Graphics Level!",
2355 result = vega10_populate_all_memory_levels(hwmgr);
2356 PP_ASSERT_WITH_CODE(!result,
2357 "Failed to initialize Memory Level!",
2360 result = vega10_populate_all_display_clock_levels(hwmgr);
2361 PP_ASSERT_WITH_CODE(!result,
2362 "Failed to initialize Display Level!",
2365 result = vega10_populate_smc_vce_levels(hwmgr);
2366 PP_ASSERT_WITH_CODE(!result,
2367 "Failed to initialize VCE Level!",
2370 result = vega10_populate_smc_uvd_levels(hwmgr);
2371 PP_ASSERT_WITH_CODE(!result,
2372 "Failed to initialize UVD Level!",
2375 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2376 PHM_PlatformCaps_ClockStretcher)) {
2377 result = vega10_populate_clock_stretcher_table(hwmgr);
2378 PP_ASSERT_WITH_CODE(!result,
2379 "Failed to populate Clock Stretcher Table!",
2383 result = vega10_populate_avfs_parameters(hwmgr);
2384 PP_ASSERT_WITH_CODE(!result,
2385 "Failed to initialize AVFS Parameters!",
2388 result = vega10_populate_gpio_parameters(hwmgr);
2389 PP_ASSERT_WITH_CODE(!result,
2390 "Failed to initialize GPIO Parameters!",
2393 pp_table->GfxclkAverageAlpha = (uint8_t)
2394 (data->gfxclk_average_alpha);
2395 pp_table->SocclkAverageAlpha = (uint8_t)
2396 (data->socclk_average_alpha);
2397 pp_table->UclkAverageAlpha = (uint8_t)
2398 (data->uclk_average_alpha);
2399 pp_table->GfxActivityAverageAlpha = (uint8_t)
2400 (data->gfx_activity_average_alpha);
2402 result = vega10_copy_table_to_smc(hwmgr->smumgr,
2403 (uint8_t *)pp_table, PPTABLE);
2404 PP_ASSERT_WITH_CODE(!result,
2405 "Failed to upload PPtable!", return result);
2407 if (data->smu_features[GNLD_AVFS].supported) {
2408 uint32_t features_enabled;
2409 result = vega10_get_smc_features(hwmgr->smumgr, &features_enabled);
2410 PP_ASSERT_WITH_CODE(!result,
2411 "Failed to Retrieve Enabled Features!",
2413 if (!(features_enabled & (1 << FEATURE_AVFS_BIT))) {
2414 result = vega10_perform_btc(hwmgr->smumgr);
2415 PP_ASSERT_WITH_CODE(!result,
2416 "Failed to Perform BTC!",
2418 result = vega10_avfs_enable(hwmgr, true);
2419 PP_ASSERT_WITH_CODE(!result,
2420 "Attempt to enable AVFS feature Failed!",
2422 result = vega10_save_vft_table(hwmgr->smumgr,
2423 (uint8_t *)&(data->smc_state_table.avfs_table));
2424 PP_ASSERT_WITH_CODE(!result,
2425 "Attempt to save VFT table Failed!",
2428 data->smu_features[GNLD_AVFS].enabled = true;
2429 result = vega10_restore_vft_table(hwmgr->smumgr,
2430 (uint8_t *)&(data->smc_state_table.avfs_table));
2431 PP_ASSERT_WITH_CODE(!result,
2432 "Attempt to restore VFT table Failed!",
2440 static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
2442 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
2444 if (data->smu_features[GNLD_THERMAL].supported) {
2445 if (data->smu_features[GNLD_THERMAL].enabled)
2446 pr_info("THERMAL Feature Already enabled!");
2448 PP_ASSERT_WITH_CODE(
2449 !vega10_enable_smc_features(hwmgr->smumgr,
2451 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2452 "Enable THERMAL Feature Failed!",
2454 data->smu_features[GNLD_THERMAL].enabled = true;
2460 static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
2462 struct vega10_hwmgr *data =
2463 (struct vega10_hwmgr *)(hwmgr->backend);
2465 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2466 PHM_PlatformCaps_RegulatorHot)) {
2467 if (data->smu_features[GNLD_VR0HOT].supported) {
2468 PP_ASSERT_WITH_CODE(
2469 !vega10_enable_smc_features(hwmgr->smumgr,
2471 data->smu_features[GNLD_VR0HOT].smu_feature_bitmap),
2472 "Attempt to Enable VR0 Hot feature Failed!",
2474 data->smu_features[GNLD_VR0HOT].enabled = true;
2476 if (data->smu_features[GNLD_VR1HOT].supported) {
2477 PP_ASSERT_WITH_CODE(
2478 !vega10_enable_smc_features(hwmgr->smumgr,
2480 data->smu_features[GNLD_VR1HOT].smu_feature_bitmap),
2481 "Attempt to Enable VR0 Hot feature Failed!",
2483 data->smu_features[GNLD_VR1HOT].enabled = true;
2490 static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
2492 struct vega10_hwmgr *data =
2493 (struct vega10_hwmgr *)(hwmgr->backend);
2495 if (data->registry_data.ulv_support) {
2496 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
2497 true, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2498 "Enable ULV Feature Failed!",
2500 data->smu_features[GNLD_ULV].enabled = true;
2506 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2508 struct vega10_hwmgr *data =
2509 (struct vega10_hwmgr *)(hwmgr->backend);
2511 if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2512 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
2513 true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2514 "Attempt to Enable DS_GFXCLK Feature Failed!",
2516 data->smu_features[GNLD_DS_GFXCLK].enabled = true;
2519 if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2520 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
2521 true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2522 "Attempt to Enable DS_GFXCLK Feature Failed!",
2524 data->smu_features[GNLD_DS_SOCCLK].enabled = true;
2527 if (data->smu_features[GNLD_DS_LCLK].supported) {
2528 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
2529 true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2530 "Attempt to Enable DS_GFXCLK Feature Failed!",
2532 data->smu_features[GNLD_DS_LCLK].enabled = true;
2539 * @brief Tell SMC to enabled the supported DPMs.
2541 * @param hwmgr - the address of the powerplay hardware manager.
2542 * @Param bitmap - bitmap for the features to enabled.
2543 * @return 0 on at least one DPM is successfully enabled.
2545 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2547 struct vega10_hwmgr *data =
2548 (struct vega10_hwmgr *)(hwmgr->backend);
2549 uint32_t i, feature_mask = 0;
2551 for (i = 0; i < GNLD_DPM_MAX; i++) {
2552 if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2553 if (data->smu_features[i].supported) {
2554 if (!data->smu_features[i].enabled) {
2555 feature_mask |= data->smu_features[i].
2557 data->smu_features[i].enabled = true;
2563 if (vega10_enable_smc_features(hwmgr->smumgr,
2564 true, feature_mask)) {
2565 for (i = 0; i < GNLD_DPM_MAX; i++) {
2566 if (data->smu_features[i].smu_feature_bitmap &
2568 data->smu_features[i].enabled = false;
2572 if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2573 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
2574 true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2575 "Attempt to Enable LED DPM feature Failed!", return -EINVAL);
2576 data->smu_features[GNLD_LED_DISPLAY].enabled = true;
2579 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2580 PHM_PlatformCaps_Falcon_QuickTransition)) {
2581 if (data->smu_features[GNLD_ACDC].supported) {
2582 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
2583 true, data->smu_features[GNLD_ACDC].smu_feature_bitmap),
2584 "Attempt to Enable DS_GFXCLK Feature Failed!",
2586 data->smu_features[GNLD_ACDC].enabled = true;
2593 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2595 struct vega10_hwmgr *data =
2596 (struct vega10_hwmgr *)(hwmgr->backend);
2597 int tmp_result, result = 0;
2599 tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
2600 PPSMC_MSG_ConfigureTelemetry, data->config_telemetry);
2601 PP_ASSERT_WITH_CODE(!tmp_result,
2602 "Failed to configure telemetry!",
2605 vega10_set_tools_address(hwmgr->smumgr);
2607 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
2608 PPSMC_MSG_NumOfDisplays, 0);
2610 tmp_result = (!vega10_is_dpm_running(hwmgr)) ? 0 : -1;
2611 PP_ASSERT_WITH_CODE(!tmp_result,
2612 "DPM is already running right , skipping re-enablement!",
2615 tmp_result = vega10_construct_voltage_tables(hwmgr);
2616 PP_ASSERT_WITH_CODE(!tmp_result,
2617 "Failed to contruct voltage tables!",
2618 result = tmp_result);
2620 tmp_result = vega10_init_smc_table(hwmgr);
2621 PP_ASSERT_WITH_CODE(!tmp_result,
2622 "Failed to initialize SMC table!",
2623 result = tmp_result);
2625 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2626 PHM_PlatformCaps_ThermalController)) {
2627 tmp_result = vega10_enable_thermal_protection(hwmgr);
2628 PP_ASSERT_WITH_CODE(!tmp_result,
2629 "Failed to enable thermal protection!",
2630 result = tmp_result);
2633 tmp_result = vega10_enable_vrhot_feature(hwmgr);
2634 PP_ASSERT_WITH_CODE(!tmp_result,
2635 "Failed to enable VR hot feature!",
2636 result = tmp_result);
2638 tmp_result = vega10_enable_ulv(hwmgr);
2639 PP_ASSERT_WITH_CODE(!tmp_result,
2640 "Failed to enable ULV!",
2641 result = tmp_result);
2643 tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr);
2644 PP_ASSERT_WITH_CODE(!tmp_result,
2645 "Failed to enable deep sleep master switch!",
2646 result = tmp_result);
2648 tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES);
2649 PP_ASSERT_WITH_CODE(!tmp_result,
2650 "Failed to start DPM!", result = tmp_result);
2652 tmp_result = vega10_enable_power_containment(hwmgr);
2653 PP_ASSERT_WITH_CODE(!tmp_result,
2654 "Failed to enable power containment!",
2655 result = tmp_result);
2657 tmp_result = vega10_power_control_set_level(hwmgr);
2658 PP_ASSERT_WITH_CODE(!tmp_result,
2659 "Failed to power control set level!",
2660 result = tmp_result);
2665 static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr)
2667 return sizeof(struct vega10_power_state);
2670 static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
2671 void *state, struct pp_power_state *power_state,
2672 void *pp_table, uint32_t classification_flag)
2674 struct vega10_power_state *vega10_power_state =
2675 cast_phw_vega10_power_state(&(power_state->hardware));
2676 struct vega10_performance_level *performance_level;
2677 ATOM_Vega10_State *state_entry = (ATOM_Vega10_State *)state;
2678 ATOM_Vega10_POWERPLAYTABLE *powerplay_table =
2679 (ATOM_Vega10_POWERPLAYTABLE *)pp_table;
2680 ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table =
2681 (ATOM_Vega10_SOCCLK_Dependency_Table *)
2682 (((unsigned long)powerplay_table) +
2683 le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset));
2684 ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
2685 (ATOM_Vega10_GFXCLK_Dependency_Table *)
2686 (((unsigned long)powerplay_table) +
2687 le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
2688 ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table =
2689 (ATOM_Vega10_MCLK_Dependency_Table *)
2690 (((unsigned long)powerplay_table) +
2691 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
2694 /* The following fields are not initialized here:
2695 * id orderedList allStatesList
2697 power_state->classification.ui_label =
2698 (le16_to_cpu(state_entry->usClassification) &
2699 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
2700 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
2701 power_state->classification.flags = classification_flag;
2702 /* NOTE: There is a classification2 flag in BIOS
2703 * that is not being used right now
2705 power_state->classification.temporary_state = false;
2706 power_state->classification.to_be_deleted = false;
2708 power_state->validation.disallowOnDC =
2709 ((le32_to_cpu(state_entry->ulCapsAndSettings) &
2710 ATOM_Vega10_DISALLOW_ON_DC) != 0);
2712 power_state->display.disableFrameModulation = false;
2713 power_state->display.limitRefreshrate = false;
2714 power_state->display.enableVariBright =
2715 ((le32_to_cpu(state_entry->ulCapsAndSettings) &
2716 ATOM_Vega10_ENABLE_VARIBRIGHT) != 0);
2718 power_state->validation.supportedPowerLevels = 0;
2719 power_state->uvd_clocks.VCLK = 0;
2720 power_state->uvd_clocks.DCLK = 0;
2721 power_state->temperatures.min = 0;
2722 power_state->temperatures.max = 0;
2724 performance_level = &(vega10_power_state->performance_levels
2725 [vega10_power_state->performance_level_count++]);
2727 PP_ASSERT_WITH_CODE(
2728 (vega10_power_state->performance_level_count <
2729 NUM_GFXCLK_DPM_LEVELS),
2730 "Performance levels exceeds SMC limit!",
2733 PP_ASSERT_WITH_CODE(
2734 (vega10_power_state->performance_level_count <=
2735 hwmgr->platform_descriptor.
2736 hardwareActivityPerformanceLevels),
2737 "Performance levels exceeds Driver limit!",
2740 /* Performance levels are arranged from low to high. */
2741 performance_level->soc_clock = socclk_dep_table->entries
2742 [state_entry->ucSocClockIndexLow].ulClk;
2743 performance_level->gfx_clock = gfxclk_dep_table->entries
2744 [state_entry->ucGfxClockIndexLow].ulClk;
2745 performance_level->mem_clock = mclk_dep_table->entries
2746 [state_entry->ucMemClockIndexLow].ulMemClk;
2748 performance_level = &(vega10_power_state->performance_levels
2749 [vega10_power_state->performance_level_count++]);
2751 performance_level->soc_clock = socclk_dep_table->entries
2752 [state_entry->ucSocClockIndexHigh].ulClk;
2753 performance_level->gfx_clock = gfxclk_dep_table->entries
2754 [state_entry->ucGfxClockIndexHigh].ulClk;
2755 performance_level->mem_clock = mclk_dep_table->entries
2756 [state_entry->ucMemClockIndexHigh].ulMemClk;
2760 static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
2761 unsigned long entry_index, struct pp_power_state *state)
2764 struct vega10_power_state *ps;
2766 state->hardware.magic = PhwVega10_Magic;
2768 ps = cast_phw_vega10_power_state(&state->hardware);
2770 result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state,
2771 vega10_get_pp_table_entry_callback_func);
2774 * This is the earliest time we have all the dependency table
2775 * and the VBIOS boot state
2777 /* set DC compatible flag if this state supports DC */
2778 if (!state->validation.disallowOnDC)
2779 ps->dc_compatible = true;
2781 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
2782 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
2787 static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr,
2788 struct pp_hw_power_state *hw_ps)
2793 static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
2794 struct pp_power_state *request_ps,
2795 const struct pp_power_state *current_ps)
2797 struct vega10_power_state *vega10_ps =
2798 cast_phw_vega10_power_state(&request_ps->hardware);
2801 struct PP_Clocks minimum_clocks = {0};
2802 bool disable_mclk_switching;
2803 bool disable_mclk_switching_for_frame_lock;
2804 bool disable_mclk_switching_for_vr;
2805 bool force_mclk_high;
2806 struct cgs_display_info info = {0};
2807 const struct phm_clock_and_voltage_limits *max_limits;
2809 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
2810 struct phm_ppt_v2_information *table_info =
2811 (struct phm_ppt_v2_information *)(hwmgr->pptable);
2813 uint32_t stable_pstate_sclk_dpm_percentage;
2814 uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
2817 data->battery_state = (PP_StateUILabel_Battery ==
2818 request_ps->classification.ui_label);
2820 if (vega10_ps->performance_level_count != 2)
2821 pr_info("VI should always have 2 performance levels");
2823 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
2824 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
2825 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
2827 /* Cap clock DPM tables at DC MAX if it is in DC. */
2828 if (PP_PowerSource_DC == hwmgr->power_source) {
2829 for (i = 0; i < vega10_ps->performance_level_count; i++) {
2830 if (vega10_ps->performance_levels[i].mem_clock >
2832 vega10_ps->performance_levels[i].mem_clock =
2834 if (vega10_ps->performance_levels[i].gfx_clock >
2836 vega10_ps->performance_levels[i].gfx_clock =
2841 vega10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
2842 vega10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
2844 cgs_get_active_displays_info(hwmgr->device, &info);
2846 /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
2847 minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
2848 /* minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; */
2850 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2851 PHM_PlatformCaps_StablePState)) {
2852 PP_ASSERT_WITH_CODE(
2853 data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 &&
2854 data->registry_data.stable_pstate_sclk_dpm_percentage <= 100,
2855 "percent sclk value must range from 1% to 100%, setting default value",
2856 stable_pstate_sclk_dpm_percentage = 75);
2858 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
2859 stable_pstate_sclk = (max_limits->sclk *
2860 stable_pstate_sclk_dpm_percentage) / 100;
2862 for (count = table_info->vdd_dep_on_sclk->count - 1;
2863 count >= 0; count--) {
2864 if (stable_pstate_sclk >=
2865 table_info->vdd_dep_on_sclk->entries[count].clk) {
2866 stable_pstate_sclk =
2867 table_info->vdd_dep_on_sclk->entries[count].clk;
2873 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
2875 stable_pstate_mclk = max_limits->mclk;
2877 minimum_clocks.engineClock = stable_pstate_sclk;
2878 minimum_clocks.memoryClock = stable_pstate_mclk;
2881 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
2882 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
2884 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
2885 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
2887 vega10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
2889 if (hwmgr->gfx_arbiter.sclk_over_drive) {
2890 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
2891 hwmgr->platform_descriptor.overdriveLimit.engineClock),
2892 "Overdrive sclk exceeds limit",
2893 hwmgr->gfx_arbiter.sclk_over_drive =
2894 hwmgr->platform_descriptor.overdriveLimit.engineClock);
2896 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
2897 vega10_ps->performance_levels[1].gfx_clock =
2898 hwmgr->gfx_arbiter.sclk_over_drive;
2901 if (hwmgr->gfx_arbiter.mclk_over_drive) {
2902 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
2903 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
2904 "Overdrive mclk exceeds limit",
2905 hwmgr->gfx_arbiter.mclk_over_drive =
2906 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
2908 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
2909 vega10_ps->performance_levels[1].mem_clock =
2910 hwmgr->gfx_arbiter.mclk_over_drive;
2913 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
2914 hwmgr->platform_descriptor.platformCaps,
2915 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
2916 disable_mclk_switching_for_vr = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2917 PHM_PlatformCaps_DisableMclkSwitchForVR);
2918 force_mclk_high = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2919 PHM_PlatformCaps_ForceMclkHigh);
2921 disable_mclk_switching = (info.display_count > 1) ||
2922 disable_mclk_switching_for_frame_lock ||
2923 disable_mclk_switching_for_vr ||
2926 sclk = vega10_ps->performance_levels[0].gfx_clock;
2927 mclk = vega10_ps->performance_levels[0].mem_clock;
2929 if (sclk < minimum_clocks.engineClock)
2930 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
2931 max_limits->sclk : minimum_clocks.engineClock;
2933 if (mclk < minimum_clocks.memoryClock)
2934 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
2935 max_limits->mclk : minimum_clocks.memoryClock;
2937 vega10_ps->performance_levels[0].gfx_clock = sclk;
2938 vega10_ps->performance_levels[0].mem_clock = mclk;
2940 vega10_ps->performance_levels[1].gfx_clock =
2941 (vega10_ps->performance_levels[1].gfx_clock >=
2942 vega10_ps->performance_levels[0].gfx_clock) ?
2943 vega10_ps->performance_levels[1].gfx_clock :
2944 vega10_ps->performance_levels[0].gfx_clock;
2946 if (disable_mclk_switching) {
2947 /* Set Mclk the max of level 0 and level 1 */
2948 if (mclk < vega10_ps->performance_levels[1].mem_clock)
2949 mclk = vega10_ps->performance_levels[1].mem_clock;
2951 /* Find the lowest MCLK frequency that is within
2952 * the tolerable latency defined in DAL
2955 for (i = 0; i < data->mclk_latency_table.count; i++) {
2956 if ((data->mclk_latency_table.entries[i].latency <= latency) &&
2957 (data->mclk_latency_table.entries[i].frequency >=
2958 vega10_ps->performance_levels[0].mem_clock) &&
2959 (data->mclk_latency_table.entries[i].frequency <=
2960 vega10_ps->performance_levels[1].mem_clock))
2961 mclk = data->mclk_latency_table.entries[i].frequency;
2963 vega10_ps->performance_levels[0].mem_clock = mclk;
2965 if (vega10_ps->performance_levels[1].mem_clock <
2966 vega10_ps->performance_levels[0].mem_clock)
2967 vega10_ps->performance_levels[1].mem_clock =
2968 vega10_ps->performance_levels[0].mem_clock;
2971 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2972 PHM_PlatformCaps_StablePState)) {
2973 for (i = 0; i < vega10_ps->performance_level_count; i++) {
2974 vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk;
2975 vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk;
2982 static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
2984 const struct phm_set_power_state_input *states =
2985 (const struct phm_set_power_state_input *)input;
2986 const struct vega10_power_state *vega10_ps =
2987 cast_const_phw_vega10_power_state(states->pnew_state);
2988 struct vega10_hwmgr *data =
2989 (struct vega10_hwmgr *)(hwmgr->backend);
2990 struct vega10_single_dpm_table *sclk_table =
2991 &(data->dpm_table.gfx_table);
2992 uint32_t sclk = vega10_ps->performance_levels
2993 [vega10_ps->performance_level_count - 1].gfx_clock;
2994 struct vega10_single_dpm_table *mclk_table =
2995 &(data->dpm_table.mem_table);
2996 uint32_t mclk = vega10_ps->performance_levels
2997 [vega10_ps->performance_level_count - 1].mem_clock;
2998 struct PP_Clocks min_clocks = {0};
3000 struct cgs_display_info info = {0};
3002 data->need_update_dpm_table = 0;
3004 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3005 PHM_PlatformCaps_ODNinACSupport) ||
3006 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3007 PHM_PlatformCaps_ODNinDCSupport)) {
3008 for (i = 0; i < sclk_table->count; i++) {
3009 if (sclk == sclk_table->dpm_levels[i].value)
3013 if (!(data->apply_overdrive_next_settings_mask &
3014 DPMTABLE_OD_UPDATE_SCLK) && i >= sclk_table->count) {
3015 /* Check SCLK in DAL's minimum clocks
3016 * in case DeepSleep divider update is required.
3018 if (data->display_timing.min_clock_in_sr !=
3019 min_clocks.engineClockInSR &&
3020 (min_clocks.engineClockInSR >=
3021 VEGA10_MINIMUM_ENGINE_CLOCK ||
3022 data->display_timing.min_clock_in_sr >=
3023 VEGA10_MINIMUM_ENGINE_CLOCK))
3024 data->need_update_dpm_table |= DPMTABLE_UPDATE_SCLK;
3027 cgs_get_active_displays_info(hwmgr->device, &info);
3029 if (data->display_timing.num_existing_displays !=
3031 data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
3033 for (i = 0; i < sclk_table->count; i++) {
3034 if (sclk == sclk_table->dpm_levels[i].value)
3038 if (i >= sclk_table->count)
3039 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3041 /* Check SCLK in DAL's minimum clocks
3042 * in case DeepSleep divider update is required.
3044 if (data->display_timing.min_clock_in_sr !=
3045 min_clocks.engineClockInSR &&
3046 (min_clocks.engineClockInSR >=
3047 VEGA10_MINIMUM_ENGINE_CLOCK ||
3048 data->display_timing.min_clock_in_sr >=
3049 VEGA10_MINIMUM_ENGINE_CLOCK))
3050 data->need_update_dpm_table |= DPMTABLE_UPDATE_SCLK;
3053 for (i = 0; i < mclk_table->count; i++) {
3054 if (mclk == mclk_table->dpm_levels[i].value)
3058 cgs_get_active_displays_info(hwmgr->device, &info);
3060 if (i >= mclk_table->count)
3061 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3063 if (data->display_timing.num_existing_displays !=
3064 info.display_count ||
3065 i >= mclk_table->count)
3066 data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
3071 static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
3072 struct pp_hwmgr *hwmgr, const void *input)
3075 const struct phm_set_power_state_input *states =
3076 (const struct phm_set_power_state_input *)input;
3077 const struct vega10_power_state *vega10_ps =
3078 cast_const_phw_vega10_power_state(states->pnew_state);
3079 struct vega10_hwmgr *data =
3080 (struct vega10_hwmgr *)(hwmgr->backend);
3081 uint32_t sclk = vega10_ps->performance_levels
3082 [vega10_ps->performance_level_count - 1].gfx_clock;
3083 uint32_t mclk = vega10_ps->performance_levels
3084 [vega10_ps->performance_level_count - 1].mem_clock;
3085 struct vega10_dpm_table *dpm_table = &data->dpm_table;
3086 struct vega10_dpm_table *golden_dpm_table =
3087 &data->golden_dpm_table;
3088 uint32_t dpm_count, clock_percent;
3091 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3092 PHM_PlatformCaps_ODNinACSupport) ||
3093 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3094 PHM_PlatformCaps_ODNinDCSupport)) {
3096 if (!data->need_update_dpm_table &&
3097 !data->apply_optimized_settings &&
3098 !data->apply_overdrive_next_settings_mask)
3101 if (data->apply_overdrive_next_settings_mask &
3102 DPMTABLE_OD_UPDATE_SCLK) {
3104 dpm_count < dpm_table->gfx_table.count;
3106 dpm_table->gfx_table.dpm_levels[dpm_count].enabled =
3107 data->odn_dpm_table.odn_core_clock_dpm_levels.
3108 performance_level_entries[dpm_count].enabled;
3109 dpm_table->gfx_table.dpm_levels[dpm_count].value =
3110 data->odn_dpm_table.odn_core_clock_dpm_levels.
3111 performance_level_entries[dpm_count].clock;
3115 if (data->apply_overdrive_next_settings_mask &
3116 DPMTABLE_OD_UPDATE_MCLK) {
3118 dpm_count < dpm_table->mem_table.count;
3120 dpm_table->mem_table.dpm_levels[dpm_count].enabled =
3121 data->odn_dpm_table.odn_memory_clock_dpm_levels.
3122 performance_level_entries[dpm_count].enabled;
3123 dpm_table->mem_table.dpm_levels[dpm_count].value =
3124 data->odn_dpm_table.odn_memory_clock_dpm_levels.
3125 performance_level_entries[dpm_count].clock;
3129 if ((data->need_update_dpm_table & DPMTABLE_UPDATE_SCLK) ||
3130 data->apply_optimized_settings ||
3131 (data->apply_overdrive_next_settings_mask &
3132 DPMTABLE_OD_UPDATE_SCLK)) {
3133 result = vega10_populate_all_graphic_levels(hwmgr);
3134 PP_ASSERT_WITH_CODE(!result,
3135 "Failed to populate SCLK during \
3136 PopulateNewDPMClocksStates Function!",
3140 if ((data->need_update_dpm_table & DPMTABLE_UPDATE_MCLK) ||
3141 (data->apply_overdrive_next_settings_mask &
3142 DPMTABLE_OD_UPDATE_MCLK)){
3143 result = vega10_populate_all_memory_levels(hwmgr);
3144 PP_ASSERT_WITH_CODE(!result,
3145 "Failed to populate MCLK during \
3146 PopulateNewDPMClocksStates Function!",
3150 if (!data->need_update_dpm_table &&
3151 !data->apply_optimized_settings)
3154 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK &&
3155 data->smu_features[GNLD_DPM_GFXCLK].supported) {
3157 gfx_table.dpm_levels[dpm_table->gfx_table.count - 1].
3160 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3161 PHM_PlatformCaps_OD6PlusinACSupport) ||
3162 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3163 PHM_PlatformCaps_OD6PlusinDCSupport)) {
3164 /* Need to do calculation based on the golden DPM table
3165 * as the Heatmap GPU Clock axis is also based on
3166 * the default values
3168 PP_ASSERT_WITH_CODE(
3169 golden_dpm_table->gfx_table.dpm_levels
3170 [golden_dpm_table->gfx_table.count - 1].value,
3174 dpm_count = dpm_table->gfx_table.count < 2 ?
3175 0 : dpm_table->gfx_table.count - 2;
3176 for (i = dpm_count; i > 1; i--) {
3177 if (sclk > golden_dpm_table->gfx_table.dpm_levels
3178 [golden_dpm_table->gfx_table.count - 1].value) {
3180 ((sclk - golden_dpm_table->gfx_table.dpm_levels
3181 [golden_dpm_table->gfx_table.count - 1].value) *
3183 golden_dpm_table->gfx_table.dpm_levels
3184 [golden_dpm_table->gfx_table.count - 1].value;
3186 dpm_table->gfx_table.dpm_levels[i].value =
3187 golden_dpm_table->gfx_table.dpm_levels[i].value +
3188 (golden_dpm_table->gfx_table.dpm_levels[i].value *
3189 clock_percent) / 100;
3190 } else if (golden_dpm_table->
3191 gfx_table.dpm_levels[dpm_table->gfx_table.count-1].value >
3194 ((golden_dpm_table->gfx_table.dpm_levels
3195 [golden_dpm_table->gfx_table.count - 1].value -
3197 golden_dpm_table->gfx_table.dpm_levels
3198 [golden_dpm_table->gfx_table.count-1].value;
3200 dpm_table->gfx_table.dpm_levels[i].value =
3201 golden_dpm_table->gfx_table.dpm_levels[i].value -
3202 (golden_dpm_table->gfx_table.dpm_levels[i].value *
3203 clock_percent) / 100;
3205 dpm_table->gfx_table.dpm_levels[i].value =
3206 golden_dpm_table->gfx_table.dpm_levels[i].value;
3211 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK &&
3212 data->smu_features[GNLD_DPM_UCLK].supported) {
3214 mem_table.dpm_levels[dpm_table->mem_table.count - 1].
3217 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3218 PHM_PlatformCaps_OD6PlusinACSupport) ||
3219 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3220 PHM_PlatformCaps_OD6PlusinDCSupport)) {
3222 PP_ASSERT_WITH_CODE(
3223 golden_dpm_table->mem_table.dpm_levels
3224 [golden_dpm_table->mem_table.count - 1].value,
3228 dpm_count = dpm_table->mem_table.count < 2 ?
3229 0 : dpm_table->mem_table.count - 2;
3230 for (i = dpm_count; i > 1; i--) {
3231 if (mclk > golden_dpm_table->mem_table.dpm_levels
3232 [golden_dpm_table->mem_table.count-1].value) {
3233 clock_percent = ((mclk -
3234 golden_dpm_table->mem_table.dpm_levels
3235 [golden_dpm_table->mem_table.count-1].value) *
3237 golden_dpm_table->mem_table.dpm_levels
3238 [golden_dpm_table->mem_table.count-1].value;
3240 dpm_table->mem_table.dpm_levels[i].value =
3241 golden_dpm_table->mem_table.dpm_levels[i].value +
3242 (golden_dpm_table->mem_table.dpm_levels[i].value *
3243 clock_percent) / 100;
3244 } else if (golden_dpm_table->mem_table.dpm_levels
3245 [dpm_table->mem_table.count-1].value > mclk) {
3246 clock_percent = ((golden_dpm_table->mem_table.dpm_levels
3247 [golden_dpm_table->mem_table.count-1].value - mclk) *
3249 golden_dpm_table->mem_table.dpm_levels
3250 [golden_dpm_table->mem_table.count-1].value;
3252 dpm_table->mem_table.dpm_levels[i].value =
3253 golden_dpm_table->mem_table.dpm_levels[i].value -
3254 (golden_dpm_table->mem_table.dpm_levels[i].value *
3255 clock_percent) / 100;
3257 dpm_table->mem_table.dpm_levels[i].value =
3258 golden_dpm_table->mem_table.dpm_levels[i].value;
3263 if ((data->need_update_dpm_table &
3264 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) ||
3265 data->apply_optimized_settings) {
3266 result = vega10_populate_all_graphic_levels(hwmgr);
3267 PP_ASSERT_WITH_CODE(!result,
3268 "Failed to populate SCLK during \
3269 PopulateNewDPMClocksStates Function!",
3273 if (data->need_update_dpm_table &
3274 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
3275 result = vega10_populate_all_memory_levels(hwmgr);
3276 PP_ASSERT_WITH_CODE(!result,
3277 "Failed to populate MCLK during \
3278 PopulateNewDPMClocksStates Function!",
3286 static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3287 struct vega10_single_dpm_table *dpm_table,
3288 uint32_t low_limit, uint32_t high_limit)
3292 for (i = 0; i < dpm_table->count; i++) {
3293 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3294 (dpm_table->dpm_levels[i].value > high_limit))
3295 dpm_table->dpm_levels[i].enabled = false;
3297 dpm_table->dpm_levels[i].enabled = true;
3302 static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr,
3303 struct vega10_single_dpm_table *dpm_table,
3304 uint32_t low_limit, uint32_t high_limit,
3305 uint32_t disable_dpm_mask)
3309 for (i = 0; i < dpm_table->count; i++) {
3310 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3311 (dpm_table->dpm_levels[i].value > high_limit))
3312 dpm_table->dpm_levels[i].enabled = false;
3313 else if (!((1 << i) & disable_dpm_mask))
3314 dpm_table->dpm_levels[i].enabled = false;
3316 dpm_table->dpm_levels[i].enabled = true;
3321 static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr,
3322 const struct vega10_power_state *vega10_ps)
3324 struct vega10_hwmgr *data =
3325 (struct vega10_hwmgr *)(hwmgr->backend);
3326 uint32_t high_limit_count;
3328 PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1),
3329 "power state did not have any performance level",
3332 high_limit_count = (vega10_ps->performance_level_count == 1) ? 0 : 1;
3334 vega10_trim_single_dpm_states(hwmgr,
3335 &(data->dpm_table.soc_table),
3336 vega10_ps->performance_levels[0].soc_clock,
3337 vega10_ps->performance_levels[high_limit_count].soc_clock);
3339 vega10_trim_single_dpm_states_with_mask(hwmgr,
3340 &(data->dpm_table.gfx_table),
3341 vega10_ps->performance_levels[0].gfx_clock,
3342 vega10_ps->performance_levels[high_limit_count].gfx_clock,
3343 data->disable_dpm_mask);
3345 vega10_trim_single_dpm_states(hwmgr,
3346 &(data->dpm_table.mem_table),
3347 vega10_ps->performance_levels[0].mem_clock,
3348 vega10_ps->performance_levels[high_limit_count].mem_clock);
3353 static uint32_t vega10_find_lowest_dpm_level(
3354 struct vega10_single_dpm_table *table)
3358 for (i = 0; i < table->count; i++) {
3359 if (table->dpm_levels[i].enabled)
3366 static uint32_t vega10_find_highest_dpm_level(
3367 struct vega10_single_dpm_table *table)
3371 if (table->count <= MAX_REGULAR_DPM_NUMBER) {
3372 for (i = table->count; i > 0; i--) {
3373 if (table->dpm_levels[i - 1].enabled)
3377 pr_info("DPM Table Has Too Many Entries!");
3378 return MAX_REGULAR_DPM_NUMBER - 1;
3384 static void vega10_apply_dal_minimum_voltage_request(
3385 struct pp_hwmgr *hwmgr)
3390 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
3392 struct vega10_hwmgr *data =
3393 (struct vega10_hwmgr *)(hwmgr->backend);
3395 vega10_apply_dal_minimum_voltage_request(hwmgr);
3397 if (!data->registry_data.sclk_dpm_key_disabled) {
3398 if (data->smc_state_table.gfx_boot_level !=
3399 data->dpm_table.gfx_table.dpm_state.soft_min_level) {
3400 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
3402 PPSMC_MSG_SetSoftMinGfxclkByIndex,
3403 data->smc_state_table.gfx_boot_level),
3404 "Failed to set soft min sclk index!",
3406 data->dpm_table.gfx_table.dpm_state.soft_min_level =
3407 data->smc_state_table.gfx_boot_level;
3411 if (!data->registry_data.mclk_dpm_key_disabled) {
3412 if (data->smc_state_table.mem_boot_level !=
3413 data->dpm_table.mem_table.dpm_state.soft_min_level) {
3414 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
3416 PPSMC_MSG_SetSoftMinUclkByIndex,
3417 data->smc_state_table.mem_boot_level),
3418 "Failed to set soft min mclk index!",
3421 data->dpm_table.mem_table.dpm_state.soft_min_level =
3422 data->smc_state_table.mem_boot_level;
3429 static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
3431 struct vega10_hwmgr *data =
3432 (struct vega10_hwmgr *)(hwmgr->backend);
3434 vega10_apply_dal_minimum_voltage_request(hwmgr);
3436 if (!data->registry_data.sclk_dpm_key_disabled) {
3437 if (data->smc_state_table.gfx_max_level !=
3438 data->dpm_table.gfx_table.dpm_state.soft_max_level) {
3439 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
3441 PPSMC_MSG_SetSoftMaxGfxclkByIndex,
3442 data->smc_state_table.gfx_max_level),
3443 "Failed to set soft max sclk index!",
3445 data->dpm_table.gfx_table.dpm_state.soft_max_level =
3446 data->smc_state_table.gfx_max_level;
3450 if (!data->registry_data.mclk_dpm_key_disabled) {
3451 if (data->smc_state_table.mem_max_level !=
3452 data->dpm_table.mem_table.dpm_state.soft_max_level) {
3453 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
3455 PPSMC_MSG_SetSoftMaxUclkByIndex,
3456 data->smc_state_table.mem_max_level),
3457 "Failed to set soft max mclk index!",
3459 data->dpm_table.mem_table.dpm_state.soft_max_level =
3460 data->smc_state_table.mem_max_level;
3467 static int vega10_generate_dpm_level_enable_mask(
3468 struct pp_hwmgr *hwmgr, const void *input)
3470 struct vega10_hwmgr *data =
3471 (struct vega10_hwmgr *)(hwmgr->backend);
3472 const struct phm_set_power_state_input *states =
3473 (const struct phm_set_power_state_input *)input;
3474 const struct vega10_power_state *vega10_ps =
3475 cast_const_phw_vega10_power_state(states->pnew_state);
3478 PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
3479 "Attempt to Trim DPM States Failed!",
3482 data->smc_state_table.gfx_boot_level =
3483 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3484 data->smc_state_table.gfx_max_level =
3485 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3486 data->smc_state_table.mem_boot_level =
3487 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3488 data->smc_state_table.mem_max_level =
3489 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3491 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3492 "Attempt to upload DPM Bootup Levels Failed!",
3494 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3495 "Attempt to upload DPM Max Levels Failed!",
3497 for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++)
3498 data->dpm_table.gfx_table.dpm_levels[i].enabled = true;
3501 for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++)
3502 data->dpm_table.mem_table.dpm_levels[i].enabled = true;
3507 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
3509 struct vega10_hwmgr *data =
3510 (struct vega10_hwmgr *)(hwmgr->backend);
3512 if (data->smu_features[GNLD_DPM_VCE].supported) {
3513 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
3515 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
3516 "Attempt to Enable/Disable DPM VCE Failed!",
3518 data->smu_features[GNLD_DPM_VCE].enabled = enable;
3524 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
3526 struct vega10_hwmgr *data =
3527 (struct vega10_hwmgr *)(hwmgr->backend);
3529 uint32_t low_sclk_interrupt_threshold = 0;
3531 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3532 PHM_PlatformCaps_SclkThrottleLowNotification)
3533 && (hwmgr->gfx_arbiter.sclk_threshold !=
3534 data->low_sclk_interrupt_threshold)) {
3535 data->low_sclk_interrupt_threshold =
3536 hwmgr->gfx_arbiter.sclk_threshold;
3537 low_sclk_interrupt_threshold =
3538 data->low_sclk_interrupt_threshold;
3540 data->smc_state_table.pp_table.LowGfxclkInterruptThreshold =
3541 cpu_to_le32(low_sclk_interrupt_threshold);
3543 /* This message will also enable SmcToHost Interrupt */
3544 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3545 PPSMC_MSG_SetLowGfxclkInterruptThreshold,
3546 (uint32_t)low_sclk_interrupt_threshold);
3552 static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
3555 int tmp_result, result = 0;
3556 struct vega10_hwmgr *data =
3557 (struct vega10_hwmgr *)(hwmgr->backend);
3558 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
3560 tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
3561 PP_ASSERT_WITH_CODE(!tmp_result,
3562 "Failed to find DPM states clocks in DPM table!",
3563 result = tmp_result);
3565 tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
3566 PP_ASSERT_WITH_CODE(!tmp_result,
3567 "Failed to populate and upload SCLK MCLK DPM levels!",
3568 result = tmp_result);
3570 tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input);
3571 PP_ASSERT_WITH_CODE(!tmp_result,
3572 "Failed to generate DPM level enabled mask!",
3573 result = tmp_result);
3575 tmp_result = vega10_update_sclk_threshold(hwmgr);
3576 PP_ASSERT_WITH_CODE(!tmp_result,
3577 "Failed to update SCLK threshold!",
3578 result = tmp_result);
3580 result = vega10_copy_table_to_smc(hwmgr->smumgr,
3581 (uint8_t *)pp_table, PPTABLE);
3582 PP_ASSERT_WITH_CODE(!result,
3583 "Failed to upload PPtable!", return result);
3585 data->apply_optimized_settings = false;
3586 data->apply_overdrive_next_settings_mask = 0;
3591 static int vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3593 struct pp_power_state *ps;
3594 struct vega10_power_state *vega10_ps;
3599 ps = hwmgr->request_ps;
3604 vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3607 return vega10_ps->performance_levels[0].gfx_clock;
3609 return vega10_ps->performance_levels
3610 [vega10_ps->performance_level_count - 1].gfx_clock;
3613 static int vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3615 struct pp_power_state *ps;
3616 struct vega10_power_state *vega10_ps;
3621 ps = hwmgr->request_ps;
3626 vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3629 return vega10_ps->performance_levels[0].mem_clock;
3631 return vega10_ps->performance_levels
3632 [vega10_ps->performance_level_count-1].mem_clock;
3635 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3636 void *value, int *size)
3638 uint32_t sclk_idx, mclk_idx, activity_percent = 0;
3639 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
3640 struct vega10_dpm_table *dpm_table = &data->dpm_table;
3644 case AMDGPU_PP_SENSOR_GFX_SCLK:
3645 ret = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetCurrentGfxclkIndex);
3647 vega10_read_arg_from_smc(hwmgr->smumgr, &sclk_idx);
3648 *((uint32_t *)value) = dpm_table->gfx_table.dpm_levels[sclk_idx].value;
3652 case AMDGPU_PP_SENSOR_GFX_MCLK:
3653 ret = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetCurrentUclkIndex);
3655 vega10_read_arg_from_smc(hwmgr->smumgr, &mclk_idx);
3656 *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
3660 case AMDGPU_PP_SENSOR_GPU_LOAD:
3661 ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetAverageGfxActivity, 0);
3663 vega10_read_arg_from_smc(hwmgr->smumgr, &activity_percent);
3664 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
3668 case AMDGPU_PP_SENSOR_GPU_TEMP:
3669 *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr);
3672 case AMDGPU_PP_SENSOR_UVD_POWER:
3673 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
3676 case AMDGPU_PP_SENSOR_VCE_POWER:
3677 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
3687 static int vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
3690 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3691 PPSMC_MSG_SetUclkFastSwitch,
3695 int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
3696 struct pp_display_clock_request *clock_req)
3699 enum amd_pp_clock_type clk_type = clock_req->clock_type;
3700 uint32_t clk_freq = clock_req->clock_freq_in_khz / 100;
3701 DSPCLK_e clk_select = 0;
3702 uint32_t clk_request = 0;
3705 case amd_pp_dcef_clock:
3706 clk_select = DSPCLK_DCEFCLK;
3708 case amd_pp_disp_clock:
3709 clk_select = DSPCLK_DISPCLK;
3711 case amd_pp_pixel_clock:
3712 clk_select = DSPCLK_PIXCLK;
3714 case amd_pp_phy_clock:
3715 clk_select = DSPCLK_PHYCLK;
3718 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
3724 clk_request = (clk_freq << 16) | clk_select;
3725 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3726 PPSMC_MSG_RequestDisplayClockByFreq,
3733 static int vega10_notify_smc_display_config_after_ps_adjustment(
3734 struct pp_hwmgr *hwmgr)
3736 struct vega10_hwmgr *data =
3737 (struct vega10_hwmgr *)(hwmgr->backend);
3738 struct vega10_single_dpm_table *dpm_table =
3739 &data->dpm_table.dcef_table;
3740 uint32_t num_active_disps = 0;
3741 struct cgs_display_info info = {0};
3742 struct PP_Clocks min_clocks = {0};
3744 struct pp_display_clock_request clock_req;
3746 info.mode_info = NULL;
3748 cgs_get_active_displays_info(hwmgr->device, &info);
3750 num_active_disps = info.display_count;
3752 if (num_active_disps > 1)
3753 vega10_notify_smc_display_change(hwmgr, false);
3755 vega10_notify_smc_display_change(hwmgr, true);
3757 min_clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk;
3758 min_clocks.dcefClockInSR = hwmgr->display_config.min_dcef_deep_sleep_set_clk;
3760 for (i = 0; i < dpm_table->count; i++) {
3761 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock)
3765 if (i < dpm_table->count) {
3766 clock_req.clock_type = amd_pp_dcef_clock;
3767 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value;
3768 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {
3769 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
3770 hwmgr->smumgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
3771 min_clocks.dcefClockInSR),
3772 "Attempt to set divider for DCEFCLK Failed!",);
3774 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
3776 pr_info("Cannot find requested DCEFCLK!");
3781 static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3783 struct vega10_hwmgr *data =
3784 (struct vega10_hwmgr *)(hwmgr->backend);
3786 data->smc_state_table.gfx_boot_level =
3787 data->smc_state_table.gfx_max_level =
3788 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3789 data->smc_state_table.mem_boot_level =
3790 data->smc_state_table.mem_max_level =
3791 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3793 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3794 "Failed to upload boot level to highest!",
3797 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3798 "Failed to upload dpm max level to highest!",
3804 static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3806 struct vega10_hwmgr *data =
3807 (struct vega10_hwmgr *)(hwmgr->backend);
3809 data->smc_state_table.gfx_boot_level =
3810 data->smc_state_table.gfx_max_level =
3811 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3812 data->smc_state_table.mem_boot_level =
3813 data->smc_state_table.mem_max_level =
3814 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3816 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3817 "Failed to upload boot level to highest!",
3820 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3821 "Failed to upload dpm max level to highest!",
3828 static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3830 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
3832 data->smc_state_table.gfx_boot_level =
3833 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3834 data->smc_state_table.gfx_max_level =
3835 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3836 data->smc_state_table.mem_boot_level =
3837 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3838 data->smc_state_table.mem_max_level =
3839 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3841 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3842 "Failed to upload DPM Bootup Levels!",
3845 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3846 "Failed to upload DPM Max Levels!",
3851 static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
3852 enum amd_dpm_forced_level level)
3857 case AMD_DPM_FORCED_LEVEL_HIGH:
3858 ret = vega10_force_dpm_highest(hwmgr);
3862 case AMD_DPM_FORCED_LEVEL_LOW:
3863 ret = vega10_force_dpm_lowest(hwmgr);
3867 case AMD_DPM_FORCED_LEVEL_AUTO:
3868 ret = vega10_unforce_dpm_levels(hwmgr);
3876 hwmgr->dpm_level = level;
3881 static int vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
3884 /* stop auto-manage */
3885 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3886 PHM_PlatformCaps_MicrocodeFanControl))
3887 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
3888 vega10_fan_ctrl_set_static_mode(hwmgr, mode);
3890 /* restart auto-manage */
3891 vega10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
3896 static int vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
3900 if (hwmgr->fan_ctrl_is_in_default_mode) {
3901 return hwmgr->fan_ctrl_default_mode;
3903 reg = soc15_get_register_offset(THM_HWID, 0,
3904 mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
3905 return (cgs_read_register(hwmgr->device, reg) &
3906 CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >>
3907 CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
3911 static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr,
3912 struct amd_pp_simple_clock_info *info)
3914 struct phm_ppt_v2_information *table_info =
3915 (struct phm_ppt_v2_information *)hwmgr->pptable;
3916 struct phm_clock_and_voltage_limits *max_limits =
3917 &table_info->max_clock_voltage_on_ac;
3919 info->engine_max_clock = max_limits->sclk;
3920 info->memory_max_clock = max_limits->mclk;
3925 static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
3926 struct pp_clock_levels_with_latency *clocks)
3928 struct phm_ppt_v2_information *table_info =
3929 (struct phm_ppt_v2_information *)hwmgr->pptable;
3930 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
3931 table_info->vdd_dep_on_sclk;
3934 for (i = 0; i < dep_table->count; i++) {
3935 if (dep_table->entries[i].clk) {
3936 clocks->data[clocks->num_levels].clocks_in_khz =
3937 dep_table->entries[i].clk;
3938 clocks->num_levels++;
3944 static uint32_t vega10_get_mem_latency(struct pp_hwmgr *hwmgr,
3947 if (clock >= MEM_FREQ_LOW_LATENCY &&
3948 clock < MEM_FREQ_HIGH_LATENCY)
3949 return MEM_LATENCY_HIGH;
3950 else if (clock >= MEM_FREQ_HIGH_LATENCY)
3951 return MEM_LATENCY_LOW;
3953 return MEM_LATENCY_ERR;
3956 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
3957 struct pp_clock_levels_with_latency *clocks)
3959 struct phm_ppt_v2_information *table_info =
3960 (struct phm_ppt_v2_information *)hwmgr->pptable;
3961 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
3962 table_info->vdd_dep_on_mclk;
3963 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
3966 clocks->num_levels = 0;
3967 data->mclk_latency_table.count = 0;
3969 for (i = 0; i < dep_table->count; i++) {
3970 if (dep_table->entries[i].clk) {
3971 clocks->data[clocks->num_levels].clocks_in_khz =
3972 data->mclk_latency_table.entries
3973 [data->mclk_latency_table.count].frequency =
3974 dep_table->entries[i].clk;
3975 clocks->data[clocks->num_levels].latency_in_us =
3976 data->mclk_latency_table.entries
3977 [data->mclk_latency_table.count].latency =
3978 vega10_get_mem_latency(hwmgr,
3979 dep_table->entries[i].clk);
3980 clocks->num_levels++;
3981 data->mclk_latency_table.count++;
3986 static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
3987 struct pp_clock_levels_with_latency *clocks)
3989 struct phm_ppt_v2_information *table_info =
3990 (struct phm_ppt_v2_information *)hwmgr->pptable;
3991 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
3992 table_info->vdd_dep_on_dcefclk;
3995 for (i = 0; i < dep_table->count; i++) {
3996 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
3997 clocks->data[i].latency_in_us = 0;
3998 clocks->num_levels++;
4002 static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
4003 struct pp_clock_levels_with_latency *clocks)
4005 struct phm_ppt_v2_information *table_info =
4006 (struct phm_ppt_v2_information *)hwmgr->pptable;
4007 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4008 table_info->vdd_dep_on_socclk;
4011 for (i = 0; i < dep_table->count; i++) {
4012 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
4013 clocks->data[i].latency_in_us = 0;
4014 clocks->num_levels++;
4018 static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
4019 enum amd_pp_clock_type type,
4020 struct pp_clock_levels_with_latency *clocks)
4023 case amd_pp_sys_clock:
4024 vega10_get_sclks(hwmgr, clocks);
4026 case amd_pp_mem_clock:
4027 vega10_get_memclocks(hwmgr, clocks);
4029 case amd_pp_dcef_clock:
4030 vega10_get_dcefclocks(hwmgr, clocks);
4032 case amd_pp_soc_clock:
4033 vega10_get_socclocks(hwmgr, clocks);
4042 static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
4043 enum amd_pp_clock_type type,
4044 struct pp_clock_levels_with_voltage *clocks)
4046 struct phm_ppt_v2_information *table_info =
4047 (struct phm_ppt_v2_information *)hwmgr->pptable;
4048 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
4052 case amd_pp_mem_clock:
4053 dep_table = table_info->vdd_dep_on_mclk;
4055 case amd_pp_dcef_clock:
4056 dep_table = table_info->vdd_dep_on_dcefclk;
4058 case amd_pp_disp_clock:
4059 dep_table = table_info->vdd_dep_on_dispclk;
4061 case amd_pp_pixel_clock:
4062 dep_table = table_info->vdd_dep_on_pixclk;
4064 case amd_pp_phy_clock:
4065 dep_table = table_info->vdd_dep_on_phyclk;
4071 for (i = 0; i < dep_table->count; i++) {
4072 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
4073 clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->
4074 entries[dep_table->entries[i].vddInd].us_vdd);
4075 clocks->num_levels++;
4078 if (i < dep_table->count)
4084 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
4085 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
4087 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4088 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
4092 if (!data->registry_data.disable_water_mark) {
4093 for (i = 0; i < wm_with_clock_ranges->num_wm_sets_dmif; i++) {
4094 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
4095 cpu_to_le16((uint16_t)
4096 (wm_with_clock_ranges->wm_sets_dmif[i].wm_min_dcefclk_in_khz) /
4098 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
4099 cpu_to_le16((uint16_t)
4100 (wm_with_clock_ranges->wm_sets_dmif[i].wm_max_dcefclk_in_khz) /
4102 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
4103 cpu_to_le16((uint16_t)
4104 (wm_with_clock_ranges->wm_sets_dmif[i].wm_min_memclk_in_khz) /
4106 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
4107 cpu_to_le16((uint16_t)
4108 (wm_with_clock_ranges->wm_sets_dmif[i].wm_max_memclk_in_khz) /
4110 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = (uint8_t)
4111 wm_with_clock_ranges->wm_sets_dmif[i].wm_set_id;
4114 for (i = 0; i < wm_with_clock_ranges->num_wm_sets_mcif; i++) {
4115 table->WatermarkRow[WM_SOCCLK][i].MinClock =
4116 cpu_to_le16((uint16_t)
4117 (wm_with_clock_ranges->wm_sets_mcif[i].wm_min_socclk_in_khz) /
4119 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
4120 cpu_to_le16((uint16_t)
4121 (wm_with_clock_ranges->wm_sets_mcif[i].wm_max_socclk_in_khz) /
4123 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
4124 cpu_to_le16((uint16_t)
4125 (wm_with_clock_ranges->wm_sets_mcif[i].wm_min_memclk_in_khz) /
4127 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
4128 cpu_to_le16((uint16_t)
4129 (wm_with_clock_ranges->wm_sets_mcif[i].wm_max_memclk_in_khz) /
4131 table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t)
4132 wm_with_clock_ranges->wm_sets_mcif[i].wm_set_id;
4134 data->water_marks_bitmap = WaterMarksExist;
4140 static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
4141 enum pp_clock_type type, uint32_t mask)
4143 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4146 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
4151 if (data->registry_data.sclk_dpm_key_disabled)
4154 for (i = 0; i < 32; i++) {
4155 if (mask & (1 << i))
4159 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
4161 PPSMC_MSG_SetSoftMinGfxclkByIndex,
4163 "Failed to set soft min sclk index!",
4168 if (data->registry_data.mclk_dpm_key_disabled)
4171 for (i = 0; i < 32; i++) {
4172 if (mask & (1 << i))
4176 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
4178 PPSMC_MSG_SetSoftMinUclkByIndex,
4180 "Failed to set soft min mclk index!",
4185 if (data->registry_data.pcie_dpm_key_disabled)
4188 for (i = 0; i < 32; i++) {
4189 if (mask & (1 << i))
4193 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
4195 PPSMC_MSG_SetMinLinkDpmByIndex,
4197 "Failed to set min pcie index!",
4207 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
4208 enum pp_clock_type type, char *buf)
4210 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4211 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4212 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4213 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
4214 int i, now, size = 0;
4218 if (data->registry_data.sclk_dpm_key_disabled)
4221 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
4222 PPSMC_MSG_GetCurrentGfxclkIndex),
4223 "Attempt to get current sclk index Failed!",
4225 PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr,
4227 "Attempt to read sclk index Failed!",
4230 for (i = 0; i < sclk_table->count; i++)
4231 size += sprintf(buf + size, "%d: %uMhz %s\n",
4232 i, sclk_table->dpm_levels[i].value / 100,
4233 (i == now) ? "*" : "");
4236 if (data->registry_data.mclk_dpm_key_disabled)
4239 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
4240 PPSMC_MSG_GetCurrentUclkIndex),
4241 "Attempt to get current mclk index Failed!",
4243 PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr,
4245 "Attempt to read mclk index Failed!",
4248 for (i = 0; i < mclk_table->count; i++)
4249 size += sprintf(buf + size, "%d: %uMhz %s\n",
4250 i, mclk_table->dpm_levels[i].value / 100,
4251 (i == now) ? "*" : "");
4254 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
4255 PPSMC_MSG_GetCurrentLinkIndex),
4256 "Attempt to get current mclk index Failed!",
4258 PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr,
4260 "Attempt to read mclk index Failed!",
4263 for (i = 0; i < pcie_table->count; i++)
4264 size += sprintf(buf + size, "%d: %s %s\n", i,
4265 (pcie_table->pcie_gen[i] == 0) ? "2.5GB, x1" :
4266 (pcie_table->pcie_gen[i] == 1) ? "5.0GB, x16" :
4267 (pcie_table->pcie_gen[i] == 2) ? "8.0GB, x16" : "",
4268 (i == now) ? "*" : "");
4276 static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4278 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4280 uint32_t num_turned_on_displays = 1;
4281 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
4282 struct cgs_display_info info = {0};
4284 if ((data->water_marks_bitmap & WaterMarksExist) &&
4285 !(data->water_marks_bitmap & WaterMarksLoaded)) {
4286 result = vega10_copy_table_to_smc(hwmgr->smumgr,
4287 (uint8_t *)wm_table, WMTABLE);
4288 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
4289 data->water_marks_bitmap |= WaterMarksLoaded;
4292 if (data->water_marks_bitmap & WaterMarksLoaded) {
4293 cgs_get_active_displays_info(hwmgr->device, &info);
4294 num_turned_on_displays = info.display_count;
4295 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4296 PPSMC_MSG_NumOfDisplays, num_turned_on_displays);
4302 int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4304 struct vega10_hwmgr *data =
4305 (struct vega10_hwmgr *)(hwmgr->backend);
4307 if (data->smu_features[GNLD_DPM_UVD].supported) {
4308 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
4310 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
4311 "Attempt to Enable/Disable DPM UVD Failed!",
4313 data->smu_features[GNLD_DPM_UVD].enabled = enable;
4318 static int vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
4320 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4322 data->vce_power_gated = bgate;
4323 return vega10_enable_disable_vce_dpm(hwmgr, !bgate);
4326 static int vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
4328 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4330 data->uvd_power_gated = bgate;
4331 return vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
4334 static inline bool vega10_are_power_levels_equal(
4335 const struct vega10_performance_level *pl1,
4336 const struct vega10_performance_level *pl2)
4338 return ((pl1->soc_clock == pl2->soc_clock) &&
4339 (pl1->gfx_clock == pl2->gfx_clock) &&
4340 (pl1->mem_clock == pl2->mem_clock));
4343 static int vega10_check_states_equal(struct pp_hwmgr *hwmgr,
4344 const struct pp_hw_power_state *pstate1,
4345 const struct pp_hw_power_state *pstate2, bool *equal)
4347 const struct vega10_power_state *psa;
4348 const struct vega10_power_state *psb;
4351 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4354 psa = cast_const_phw_vega10_power_state(pstate1);
4355 psb = cast_const_phw_vega10_power_state(pstate2);
4356 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4357 if (psa->performance_level_count != psb->performance_level_count) {
4362 for (i = 0; i < psa->performance_level_count; i++) {
4363 if (!vega10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4364 /* If we have found even one performance level pair that is different the states are different. */
4370 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4371 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4372 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4373 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4379 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4381 struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
4382 bool is_update_required = false;
4383 struct cgs_display_info info = {0, 0, NULL};
4385 cgs_get_active_displays_info(hwmgr->device, &info);
4387 if (data->display_timing.num_existing_displays != info.display_count)
4388 is_update_required = true;
4390 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4391 if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr)
4392 is_update_required = true;
4395 return is_update_required;
4398 static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
4399 .backend_init = vega10_hwmgr_backend_init,
4400 .backend_fini = vega10_hwmgr_backend_fini,
4401 .asic_setup = vega10_setup_asic_task,
4402 .dynamic_state_management_enable = vega10_enable_dpm_tasks,
4403 .get_num_of_pp_table_entries =
4404 vega10_get_number_of_powerplay_table_entries,
4405 .get_power_state_size = vega10_get_power_state_size,
4406 .get_pp_table_entry = vega10_get_pp_table_entry,
4407 .patch_boot_state = vega10_patch_boot_state,
4408 .apply_state_adjust_rules = vega10_apply_state_adjust_rules,
4409 .power_state_set = vega10_set_power_state_tasks,
4410 .get_sclk = vega10_dpm_get_sclk,
4411 .get_mclk = vega10_dpm_get_mclk,
4412 .notify_smc_display_config_after_ps_adjustment =
4413 vega10_notify_smc_display_config_after_ps_adjustment,
4414 .force_dpm_level = vega10_dpm_force_dpm_level,
4415 .get_temperature = vega10_thermal_get_temperature,
4416 .stop_thermal_controller = vega10_thermal_stop_thermal_controller,
4417 .get_fan_speed_info = vega10_fan_ctrl_get_fan_speed_info,
4418 .get_fan_speed_percent = vega10_fan_ctrl_get_fan_speed_percent,
4419 .set_fan_speed_percent = vega10_fan_ctrl_set_fan_speed_percent,
4420 .reset_fan_speed_to_default =
4421 vega10_fan_ctrl_reset_fan_speed_to_default,
4422 .get_fan_speed_rpm = vega10_fan_ctrl_get_fan_speed_rpm,
4423 .set_fan_speed_rpm = vega10_fan_ctrl_set_fan_speed_rpm,
4424 .uninitialize_thermal_controller =
4425 vega10_thermal_ctrl_uninitialize_thermal_controller,
4426 .set_fan_control_mode = vega10_set_fan_control_mode,
4427 .get_fan_control_mode = vega10_get_fan_control_mode,
4428 .read_sensor = vega10_read_sensor,
4429 .get_dal_power_level = vega10_get_dal_power_level,
4430 .get_clock_by_type_with_latency = vega10_get_clock_by_type_with_latency,
4431 .get_clock_by_type_with_voltage = vega10_get_clock_by_type_with_voltage,
4432 .set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges,
4433 .display_clock_voltage_request = vega10_display_clock_voltage_request,
4434 .force_clock_level = vega10_force_clock_level,
4435 .print_clock_levels = vega10_print_clock_levels,
4436 .display_config_changed = vega10_display_configuration_changed_task,
4437 .powergate_uvd = vega10_power_gate_uvd,
4438 .powergate_vce = vega10_power_gate_vce,
4439 .check_states_equal = vega10_check_states_equal,
4440 .check_smc_update_required_for_display_configuration =
4441 vega10_check_smc_update_required_for_display_configuration,
4444 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
4446 hwmgr->hwmgr_func = &vega10_hwmgr_funcs;
4447 hwmgr->pptable_func = &vega10_pptable_funcs;
4448 pp_vega10_thermal_initialize(hwmgr);