drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "vega10_thermal.h"
  25 #include "vega10_hwmgr.h"
  26 #include "vega10_smumgr.h"
  27 #include "vega10_ppsmc.h"
  28 #include "vega10_inc.h"
  29 #include "pp_soc15.h"
  30 #include "pp_debug.h"
  31
  32 static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
  33 {
  34         PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
  35                                 PPSMC_MSG_GetCurrentRpm),
  36                         "Attempt to get current RPM from SMC Failed!",
  37                         return -1);
  38         PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr,
  39                         current_rpm),
  40                         "Attempt to read current RPM from SMC Failed!",
  41                         return -1);
  42         return 0;
  43 }
  44
  45 int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
  46                 struct phm_fan_speed_info *fan_speed_info)
  47 {
  48
  49         if (hwmgr->thermal_controller.fanInfo.bNoFan)
  50                 return 0;
  51
  52         fan_speed_info->supports_percent_read = true;
  53         fan_speed_info->supports_percent_write = true;
  54         fan_speed_info->min_percent = 0;
  55         fan_speed_info->max_percent = 100;
  56
  57         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
  58                         PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
  59                 hwmgr->thermal_controller.fanInfo.
  60                 ucTachometerPulsesPerRevolution) {
  61                 fan_speed_info->supports_rpm_read = true;
  62                 fan_speed_info->supports_rpm_write = true;
  63                 fan_speed_info->min_rpm =
  64                                 hwmgr->thermal_controller.fanInfo.ulMinRPM;
  65                 fan_speed_info->max_rpm =
  66                                 hwmgr->thermal_controller.fanInfo.ulMaxRPM;
  67         } else {
  68                 fan_speed_info->min_rpm = 0;
  69                 fan_speed_info->max_rpm = 0;
  70         }
  71
  72         return 0;
  73 }
  74
  75 int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
  76                 uint32_t *speed)
  77 {
  78         uint32_t current_rpm;
  79         uint32_t percent = 0;
  80
  81         if (hwmgr->thermal_controller.fanInfo.bNoFan)
  82                 return 0;
  83
  84         if (vega10_get_current_rpm(hwmgr, &current_rpm))
  85                 return -1;
  86
  87         if (hwmgr->thermal_controller.
  88                         advanceFanControlParameters.usMaxFanRPM != 0)
  89                 percent = current_rpm * 100 /
  90                         hwmgr->thermal_controller.
  91                         advanceFanControlParameters.usMaxFanRPM;
  92
  93         *speed = percent > 100 ? 100 : percent;
  94
  95         return 0;
  96 }
  97
  98 int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
  99 {
 100         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 101         uint32_t tach_period;
 102         uint32_t crystal_clock_freq;
 103         int result = 0;
 104
 105         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 106                 return -1;
 107
 108         if (data->smu_features[GNLD_FAN_CONTROL].supported)
 109                 result = vega10_get_current_rpm(hwmgr, speed);
 110         else {
 111                 uint32_t reg = soc15_get_register_offset(THM_HWID, 0,
 112                                 mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);
 113                 tach_period = (cgs_read_register(hwmgr->device,
 114                                 reg) & CG_TACH_STATUS__TACH_PERIOD_MASK) >>
 115                                 CG_TACH_STATUS__TACH_PERIOD__SHIFT;
 116
 117                 if (tach_period == 0)
 118                         return -EINVAL;
 119
 120                 crystal_clock_freq = smu7_get_xclk(hwmgr);
 121
 122                 *speed = 60 * crystal_clock_freq * 10000 / tach_period;
 123         }
 124
 125         return result;
 126 }
 127
 128 /**
 129 * Set Fan Speed Control to static mode,
 130 * so that the user can decide what speed to use.
 131 * @param    hwmgr  the address of the powerplay hardware manager.
 132 *           mode the fan control mode, 0 default, 1 by percent, 5, by RPM
 133 * @exception Should always succeed.
 134 */
 135 int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
 136 {
 137         uint32_t reg;
 138
 139         reg = soc15_get_register_offset(THM_HWID, 0,
 140                         mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
 141
 142         if (hwmgr->fan_ctrl_is_in_default_mode) {
 143                 hwmgr->fan_ctrl_default_mode =
 144                                 (cgs_read_register(hwmgr->device, reg) &
 145                                 CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >>
 146                                 CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
 147                 hwmgr->tmin = (cgs_read_register(hwmgr->device, reg) &
 148                                 CG_FDO_CTRL2__TMIN_MASK) >>
 149                                 CG_FDO_CTRL2__TMIN__SHIFT;
 150                 hwmgr->fan_ctrl_is_in_default_mode = false;
 151         }
 152
 153         cgs_write_register(hwmgr->device, reg,
 154                         (cgs_read_register(hwmgr->device, reg) &
 155                         ~CG_FDO_CTRL2__TMIN_MASK) |
 156                         (0 << CG_FDO_CTRL2__TMIN__SHIFT));
 157         cgs_write_register(hwmgr->device, reg,
 158                         (cgs_read_register(hwmgr->device, reg) &
 159                         ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
 160                         (mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
 161
 162         return 0;
 163 }
 164
 165 /**
 166 * Reset Fan Speed Control to default mode.
 167 * @param    hwmgr  the address of the powerplay hardware manager.
 168 * @exception Should always succeed.
 169 */
 170 int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
 171 {
 172         uint32_t reg;
 173
 174         reg = soc15_get_register_offset(THM_HWID, 0,
 175                         mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
 176
 177         if (!hwmgr->fan_ctrl_is_in_default_mode) {
 178                 cgs_write_register(hwmgr->device, reg,
 179                                 (cgs_read_register(hwmgr->device, reg) &
 180                                 ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
 181                                 (hwmgr->fan_ctrl_default_mode <<
 182                                 CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
 183                 cgs_write_register(hwmgr->device, reg,
 184                                 (cgs_read_register(hwmgr->device, reg) &
 185                                 ~CG_FDO_CTRL2__TMIN_MASK) |
 186                                 (hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
 187                 hwmgr->fan_ctrl_is_in_default_mode = true;
 188         }
 189
 190         return 0;
 191 }
 192
 193 /**
 194  * @fn vega10_enable_fan_control_feature
 195  * @brief Enables the SMC Fan Control Feature.
 196  *
 197  * @param    hwmgr - the address of the powerplay hardware manager.
 198  * @return   0 on success. -1 otherwise.
 199  */
 200 static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
 201 {
 202         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 203
 204         if (data->smu_features[GNLD_FAN_CONTROL].supported) {
 205                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
 206                                 hwmgr->smumgr, true,
 207                                 data->smu_features[GNLD_FAN_CONTROL].
 208                                 smu_feature_bitmap),
 209                                 "Attempt to Enable FAN CONTROL feature Failed!",
 210                                 return -1);
 211                 data->smu_features[GNLD_FAN_CONTROL].enabled = true;
 212         }
 213
 214         return 0;
 215 }
 216
 217 static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
 218 {
 219         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 220
 221         if (data->smu_features[GNLD_FAN_CONTROL].supported) {
 222                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
 223                                 hwmgr->smumgr, false,
 224                                 data->smu_features[GNLD_FAN_CONTROL].
 225                                 smu_feature_bitmap),
 226                                 "Attempt to Enable FAN CONTROL feature Failed!",
 227                                 return -1);
 228                 data->smu_features[GNLD_FAN_CONTROL].enabled = false;
 229         }
 230
 231         return 0;
 232 }
 233
 234 int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
 235 {
 236         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 237                 return -1;
 238
 239         PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr),
 240                         "Attempt to Enable SMC FAN CONTROL Feature Failed!",
 241                         return -1);
 242
 243         return 0;
 244 }
 245
 246
 247 int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
 248 {
 249         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 250
 251         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 252                 return -1;
 253
 254         if (data->smu_features[GNLD_FAN_CONTROL].supported) {
 255                 PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr),
 256                                 "Attempt to Disable SMC FAN CONTROL Feature Failed!",
 257                                 return -1);
 258         }
 259         return 0;
 260 }
 261
 262 /**
 263 * Set Fan Speed in percent.
 264 * @param    hwmgr  the address of the powerplay hardware manager.
 265 * @param    speed is the percentage value (0% - 100%) to be set.
 266 * @exception Fails is the 100% setting appears to be 0.
 267 */
 268 int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
 269                 uint32_t speed)
 270 {
 271         uint32_t duty100;
 272         uint32_t duty;
 273         uint64_t tmp64;
 274         uint32_t reg;
 275
 276         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 277                 return 0;
 278
 279         if (speed > 100)
 280                 speed = 100;
 281
 282         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 283                         PHM_PlatformCaps_MicrocodeFanControl))
 284                 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
 285
 286         reg = soc15_get_register_offset(THM_HWID, 0,
 287                         mmCG_FDO_CTRL1_BASE_IDX, mmCG_FDO_CTRL1);
 288
 289         duty100 = (cgs_read_register(hwmgr->device, reg) &
 290                         CG_FDO_CTRL1__FMAX_DUTY100_MASK) >>
 291                         CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
 292
 293         if (duty100 == 0)
 294                 return -EINVAL;
 295
 296         tmp64 = (uint64_t)speed * duty100;
 297         do_div(tmp64, 100);
 298         duty = (uint32_t)tmp64;
 299
 300         reg = soc15_get_register_offset(THM_HWID, 0,
 301                         mmCG_FDO_CTRL0_BASE_IDX, mmCG_FDO_CTRL0);
 302         cgs_write_register(hwmgr->device, reg,
 303                         (cgs_read_register(hwmgr->device, reg) &
 304                         ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK) |
 305                         (duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT));
 306
 307         return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
 308 }
 309
 310 /**
 311 * Reset Fan Speed to default.
 312 * @param    hwmgr  the address of the powerplay hardware manager.
 313 * @exception Always succeeds.
 314 */
 315 int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
 316 {
 317         int result;
 318
 319         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 320                 return 0;
 321
 322         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 323                         PHM_PlatformCaps_MicrocodeFanControl)) {
 324                 result = vega10_fan_ctrl_set_static_mode(hwmgr,
 325                                 FDO_PWM_MODE_STATIC);
 326                 if (!result)
 327                         result = vega10_fan_ctrl_start_smc_fan_control(hwmgr);
 328         } else
 329                 result = vega10_fan_ctrl_set_default_mode(hwmgr);
 330
 331         return result;
 332 }
 333
 334 /**
 335 * Set Fan Speed in RPM.
 336 * @param    hwmgr  the address of the powerplay hardware manager.
 337 * @param    speed is the percentage value (min - max) to be set.
 338 * @exception Fails is the speed not lie between min and max.
 339 */
 340 int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
 341 {
 342         uint32_t tach_period;
 343         uint32_t crystal_clock_freq;
 344         int result = 0;
 345         uint32_t reg;
 346
 347         if (hwmgr->thermal_controller.fanInfo.bNoFan ||
 348                         (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
 349                         (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
 350                 return -1;
 351
 352         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 353                         PHM_PlatformCaps_MicrocodeFanControl))
 354                 result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
 355
 356         if (!result) {
 357                 crystal_clock_freq = smu7_get_xclk(hwmgr);
 358                 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
 359                 reg = soc15_get_register_offset(THM_HWID, 0,
 360                                 mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);
 361                 cgs_write_register(hwmgr->device, reg,
 362                                 (cgs_read_register(hwmgr->device, reg) &
 363                                 ~CG_TACH_STATUS__TACH_PERIOD_MASK) |
 364                                 (tach_period << CG_TACH_STATUS__TACH_PERIOD__SHIFT));
 365         }
 366         return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
 367 }
 368
 369 /**
 370 * Reads the remote temperature from the SIslands thermal controller.
 371 *
 372 * @param    hwmgr The address of the hardware manager.
 373 */
 374 int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
 375 {
 376         int temp;
 377         uint32_t reg;
 378
 379         reg = soc15_get_register_offset(THM_HWID, 0,
 380                         mmCG_TACH_STATUS_BASE_IDX,  mmCG_MULT_THERMAL_STATUS);
 381
 382         temp = cgs_read_register(hwmgr->device, reg);
 383
 384         temp = (temp & CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK) >>
 385                         CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT;
 386
 387         temp = temp & 0x1ff;
 388
 389         temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
 390
 391         return temp;
 392 }
 393
 394 /**
 395 * Set the requested temperature range for high and low alert signals
 396 *
 397 * @param    hwmgr The address of the hardware manager.
 398 * @param    range Temperature range to be programmed for
 399 *           high and low alert signals
 400 * @exception PP_Result_BadInput if the input data is not valid.
 401 */
 402 static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
 403                 struct PP_TemperatureRange *range)
 404 {
 405         uint32_t low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *
 406                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
 407         uint32_t high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *
 408                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
 409         uint32_t val, reg;
 410
 411         if (low < range->min)
 412                 low = range->min;
 413         if (high > range->max)
 414                 high = range->max;
 415
 416         if (low > high)
 417                 return -EINVAL;
 418
 419         reg = soc15_get_register_offset(THM_HWID, 0,
 420                         mmTHM_THERMAL_INT_CTRL_BASE_IDX, mmTHM_THERMAL_INT_CTRL);
 421
 422         val = cgs_read_register(hwmgr->device, reg);
 423
 424         val &= (~THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK);
 425         val |=  (5 << THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT);
 426
 427         val &= (~THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK);
 428         val |= (1 << THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT);
 429
 430         val &= (~THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK);
 431         val |= ((high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
 432                         << THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT);
 433
 434         val &= (~THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK);
 435         val |= ((low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
 436                         << THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT);
 437
 438         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
 439
 440         cgs_write_register(hwmgr->device, reg, val);
 441
 442         reg = soc15_get_register_offset(THM_HWID, 0,
 443                         mmTHM_TCON_HTC_BASE_IDX, mmTHM_TCON_HTC);
 444
 445         return 0;
 446 }
 447
 448 /**
 449 * Programs thermal controller one-time setting registers
 450 *
 451 * @param    hwmgr The address of the hardware manager.
 452 */
 453 static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
 454 {
 455         uint32_t reg;
 456
 457         if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
 458                 reg = soc15_get_register_offset(THM_HWID, 0,
 459                                 mmCG_TACH_CTRL_BASE_IDX, mmCG_TACH_CTRL);
 460                 cgs_write_register(hwmgr->device, reg,
 461                                 (cgs_read_register(hwmgr->device, reg) &
 462                                 ~CG_TACH_CTRL__EDGE_PER_REV_MASK) |
 463                                 ((hwmgr->thermal_controller.fanInfo.
 464                                 ucTachometerPulsesPerRevolution - 1) <<
 465                                 CG_TACH_CTRL__EDGE_PER_REV__SHIFT));
 466         }
 467
 468         reg = soc15_get_register_offset(THM_HWID, 0,
 469                         mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
 470         cgs_write_register(hwmgr->device, reg,
 471                         (cgs_read_register(hwmgr->device, reg) &
 472                         ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK) |
 473                         (0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT));
 474
 475         return 0;
 476 }
 477
 478 /**
 479 * Enable thermal alerts on the RV770 thermal controller.
 480 *
 481 * @param    hwmgr The address of the hardware manager.
 482 */
 483 static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
 484 {
 485         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 486         uint32_t val = 0;
 487         uint32_t reg;
 488
 489         if (data->smu_features[GNLD_FW_CTF].supported) {
 490                 if (data->smu_features[GNLD_FW_CTF].enabled)
 491                         printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
 492
 493                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
 494                                 true,
 495                                 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
 496                                 "Attempt to Enable FW CTF feature Failed!",
 497                                 return -1);
 498                 data->smu_features[GNLD_FW_CTF].enabled = true;
 499         }
 500
 501         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
 502         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
 503         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
 504
 505         reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);
 506         cgs_write_register(hwmgr->device, reg, val);
 507
 508         return 0;
 509 }
 510
 511 /**
 512 * Disable thermal alerts on the RV770 thermal controller.
 513 * @param    hwmgr The address of the hardware manager.
 514 */
 515 int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
 516 {
 517         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 518         uint32_t reg;
 519
 520         if (data->smu_features[GNLD_FW_CTF].supported) {
 521                 if (!data->smu_features[GNLD_FW_CTF].enabled)
 522                         printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
 523
 524
 525                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
 526                         false,
 527                         data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
 528                         "Attempt to disable FW CTF feature Failed!",
 529                         return -1);
 530                 data->smu_features[GNLD_FW_CTF].enabled = false;
 531         }
 532
 533         reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);
 534         cgs_write_register(hwmgr->device, reg, 0);
 535
 536         return 0;
 537 }
 538
 539 /**
 540 * Uninitialize the thermal controller.
 541 * Currently just disables alerts.
 542 * @param    hwmgr The address of the hardware manager.
 543 */
 544 int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
 545 {
 546         int result = vega10_thermal_disable_alert(hwmgr);
 547
 548         if (!hwmgr->thermal_controller.fanInfo.bNoFan)
 549                 vega10_fan_ctrl_set_default_mode(hwmgr);
 550
 551         return result;
 552 }
 553
 554 /**
 555 * Set up the fan table to control the fan using the SMC.
 556 * @param    hwmgr  the address of the powerplay hardware manager.
 557 * @param    pInput the pointer to input data
 558 * @param    pOutput the pointer to output data
 559 * @param    pStorage the pointer to temporary storage
 560 * @param    Result the last failure code
 561 * @return   result from set temperature range routine
 562 */
 563 int tf_vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
 564                 void *input, void *output, void *storage, int result)
 565 {
 566         int ret;
 567         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 568         PPTable_t *table = &(data->smc_state_table.pp_table);
 569
 570         if (!data->smu_features[GNLD_FAN_CONTROL].supported)
 571                 return 0;
 572
 573         table->FanMaximumRpm = (uint16_t)hwmgr->thermal_controller.
 574                         advanceFanControlParameters.usMaxFanRPM;
 575         table->FanThrottlingRpm = hwmgr->thermal_controller.
 576                         advanceFanControlParameters.usFanRPMMaxLimit;
 577         table->FanAcousticLimitRpm = (uint16_t)(hwmgr->thermal_controller.
 578                         advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
 579         table->FanTargetTemperature = hwmgr->thermal_controller.
 580                         advanceFanControlParameters.usTMax;
 581
 582         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 583                                 PPSMC_MSG_SetFanTemperatureTarget,
 584                                 (uint32_t)table->FanTargetTemperature);
 585
 586         table->FanPwmMin = hwmgr->thermal_controller.
 587                         advanceFanControlParameters.usPWMMin * 255 / 100;
 588         table->FanTargetGfxclk = (uint16_t)(hwmgr->thermal_controller.
 589                         advanceFanControlParameters.ulTargetGfxClk);
 590         table->FanGainEdge = hwmgr->thermal_controller.
 591                         advanceFanControlParameters.usFanGainEdge;
 592         table->FanGainHotspot = hwmgr->thermal_controller.
 593                         advanceFanControlParameters.usFanGainHotspot;
 594         table->FanGainLiquid = hwmgr->thermal_controller.
 595                         advanceFanControlParameters.usFanGainLiquid;
 596         table->FanGainVrVddc = hwmgr->thermal_controller.
 597                         advanceFanControlParameters.usFanGainVrVddc;
 598         table->FanGainVrMvdd = hwmgr->thermal_controller.
 599                         advanceFanControlParameters.usFanGainVrMvdd;
 600         table->FanGainPlx = hwmgr->thermal_controller.
 601                         advanceFanControlParameters.usFanGainPlx;
 602         table->FanGainHbm = hwmgr->thermal_controller.
 603                         advanceFanControlParameters.usFanGainHbm;
 604         table->FanZeroRpmEnable = hwmgr->thermal_controller.
 605                         advanceFanControlParameters.ucEnableZeroRPM;
 606         table->FanStopTemp = hwmgr->thermal_controller.
 607                         advanceFanControlParameters.usZeroRPMStopTemperature;
 608         table->FanStartTemp = hwmgr->thermal_controller.
 609                         advanceFanControlParameters.usZeroRPMStartTemperature;
 610
 611         ret = vega10_copy_table_to_smc(hwmgr->smumgr,
 612                         (uint8_t *)(&(data->smc_state_table.pp_table)), PPTABLE);
 613         if (ret)
 614                 pr_info("Failed to update Fan Control Table in PPTable!");
 615
 616         return ret;
 617 }
 618
 619 /**
 620 * Start the fan control on the SMC.
 621 * @param    hwmgr  the address of the powerplay hardware manager.
 622 * @param    pInput the pointer to input data
 623 * @param    pOutput the pointer to output data
 624 * @param    pStorage the pointer to temporary storage
 625 * @param    Result the last failure code
 626 * @return   result from set temperature range routine
 627 */
 628 int tf_vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
 629                 void *input, void *output, void *storage, int result)
 630 {
 631 /* If the fantable setup has failed we could have disabled
 632  * PHM_PlatformCaps_MicrocodeFanControl even after
 633  * this function was included in the table.
 634  * Make sure that we still think controlling the fan is OK.
 635 */
 636         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 637                         PHM_PlatformCaps_MicrocodeFanControl)) {
 638                 vega10_fan_ctrl_start_smc_fan_control(hwmgr);
 639                 vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
 640         }
 641
 642         return 0;
 643 }
 644
 645 /**
 646 * Set temperature range for high and low alerts
 647 * @param    hwmgr  the address of the powerplay hardware manager.
 648 * @param    pInput the pointer to input data
 649 * @param    pOutput the pointer to output data
 650 * @param    pStorage the pointer to temporary storage
 651 * @param    Result the last failure code
 652 * @return   result from set temperature range routine
 653 */
 654 int tf_vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
 655                 void *input, void *output, void *storage, int result)
 656 {
 657         struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input;
 658
 659         if (range == NULL)
 660                 return -EINVAL;
 661
 662         return vega10_thermal_set_temperature_range(hwmgr, range);
 663 }
 664
 665 /**
 666 * Programs one-time setting registers
 667 * @param    hwmgr  the address of the powerplay hardware manager.
 668 * @param    pInput the pointer to input data
 669 * @param    pOutput the pointer to output data
 670 * @param    pStorage the pointer to temporary storage
 671 * @param    Result the last failure code
 672 * @return   result from initialize thermal controller routine
 673 */
 674 int tf_vega10_thermal_initialize(struct pp_hwmgr *hwmgr,
 675                 void *input, void *output, void *storage, int result)
 676 {
 677         return vega10_thermal_initialize(hwmgr);
 678 }
 679
 680 /**
 681 * Enable high and low alerts
 682 * @param    hwmgr  the address of the powerplay hardware manager.
 683 * @param    pInput the pointer to input data
 684 * @param    pOutput the pointer to output data
 685 * @param    pStorage the pointer to temporary storage
 686 * @param    Result the last failure code
 687 * @return   result from enable alert routine
 688 */
 689 int tf_vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr,
 690                 void *input, void *output, void *storage, int result)
 691 {
 692         return vega10_thermal_enable_alert(hwmgr);
 693 }
 694
 695 /**
 696 * Disable high and low alerts
 697 * @param    hwmgr  the address of the powerplay hardware manager.
 698 * @param    pInput the pointer to input data
 699 * @param    pOutput the pointer to output data
 700 * @param    pStorage the pointer to temporary storage
 701 * @param    Result the last failure code
 702 * @return   result from disable alert routine
 703 */
 704 static int tf_vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr,
 705                 void *input, void *output, void *storage, int result)
 706 {
 707         return vega10_thermal_disable_alert(hwmgr);
 708 }
 709
 710 static struct phm_master_table_item
 711 vega10_thermal_start_thermal_controller_master_list[] = {
 712         { .tableFunction = tf_vega10_thermal_initialize },
 713         { .tableFunction = tf_vega10_thermal_set_temperature_range },
 714         { .tableFunction = tf_vega10_thermal_enable_alert },
 715 /* We should restrict performance levels to low before we halt the SMC.
 716  * On the other hand we are still in boot state when we do this
 717  * so it would be pointless.
 718  * If this assumption changes we have to revisit this table.
 719  */
 720         { .tableFunction = tf_vega10_thermal_setup_fan_table },
 721         { .tableFunction = tf_vega10_thermal_start_smc_fan_control },
 722         { }
 723 };
 724
 725 static struct phm_master_table_header
 726 vega10_thermal_start_thermal_controller_master = {
 727         0,
 728         PHM_MasterTableFlag_None,
 729         vega10_thermal_start_thermal_controller_master_list
 730 };
 731
 732 static struct phm_master_table_item
 733 vega10_thermal_set_temperature_range_master_list[] = {
 734         { .tableFunction = tf_vega10_thermal_disable_alert },
 735         { .tableFunction = tf_vega10_thermal_set_temperature_range },
 736         { .tableFunction = tf_vega10_thermal_enable_alert },
 737         { }
 738 };
 739
 740 struct phm_master_table_header
 741 vega10_thermal_set_temperature_range_master = {
 742         0,
 743         PHM_MasterTableFlag_None,
 744         vega10_thermal_set_temperature_range_master_list
 745 };
 746
 747 int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
 748 {
 749         if (!hwmgr->thermal_controller.fanInfo.bNoFan) {
 750                 vega10_fan_ctrl_set_default_mode(hwmgr);
 751                 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
 752         }
 753         return 0;
 754 }
 755
 756 /**
 757 * Initializes the thermal controller related functions
 758 * in the Hardware Manager structure.
 759 * @param    hwmgr The address of the hardware manager.
 760 * @exception Any error code from the low-level communication.
 761 */
 762 int pp_vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
 763 {
 764         int result;
 765
 766         result = phm_construct_table(hwmgr,
 767                         &vega10_thermal_set_temperature_range_master,
 768                         &(hwmgr->set_temperature_range));
 769
 770         if (!result) {
 771                 result = phm_construct_table(hwmgr,
 772                                 &vega10_thermal_start_thermal_controller_master,
 773                                 &(hwmgr->start_thermal_controller));
 774                 if (result)
 775                         phm_destroy_table(hwmgr,
 776                                         &(hwmgr->set_temperature_range));
 777         }
 778
 779         if (!result)
 780                 hwmgr->fan_ctrl_is_in_default_mode = true;
 781         return result;
 782 }
 783