drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "vega10_thermal.h"
  25 #include "vega10_hwmgr.h"
  26 #include "vega10_smumgr.h"
  27 #include "vega10_ppsmc.h"
  28 #include "vega10_inc.h"
  29 #include "pp_soc15.h"
  30 #include "pp_debug.h"
  31
  32 static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
  33 {
  34         PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
  35                                 PPSMC_MSG_GetCurrentRpm),
  36                         "Attempt to get current RPM from SMC Failed!",
  37                         return -1);
  38         PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr,
  39                         current_rpm),
  40                         "Attempt to read current RPM from SMC Failed!",
  41                         return -1);
  42         return 0;
  43 }
  44
  45 int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
  46                 struct phm_fan_speed_info *fan_speed_info)
  47 {
  48
  49         if (hwmgr->thermal_controller.fanInfo.bNoFan)
  50                 return 0;
  51
  52         fan_speed_info->supports_percent_read = true;
  53         fan_speed_info->supports_percent_write = true;
  54         fan_speed_info->min_percent = 0;
  55         fan_speed_info->max_percent = 100;
  56
  57         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
  58                         PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
  59                 hwmgr->thermal_controller.fanInfo.
  60                 ucTachometerPulsesPerRevolution) {
  61                 fan_speed_info->supports_rpm_read = true;
  62                 fan_speed_info->supports_rpm_write = true;
  63                 fan_speed_info->min_rpm =
  64                                 hwmgr->thermal_controller.fanInfo.ulMinRPM;
  65                 fan_speed_info->max_rpm =
  66                                 hwmgr->thermal_controller.fanInfo.ulMaxRPM;
  67         } else {
  68                 fan_speed_info->min_rpm = 0;
  69                 fan_speed_info->max_rpm = 0;
  70         }
  71
  72         return 0;
  73 }
  74
  75 int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
  76                 uint32_t *speed)
  77 {
  78         uint32_t current_rpm;
  79         uint32_t percent = 0;
  80
  81         if (hwmgr->thermal_controller.fanInfo.bNoFan)
  82                 return 0;
  83
  84         if (vega10_get_current_rpm(hwmgr, &current_rpm))
  85                 return -1;
  86
  87         if (hwmgr->thermal_controller.
  88                         advanceFanControlParameters.usMaxFanRPM != 0)
  89                 percent = current_rpm * 100 /
  90                         hwmgr->thermal_controller.
  91                         advanceFanControlParameters.usMaxFanRPM;
  92
  93         *speed = percent > 100 ? 100 : percent;
  94
  95         return 0;
  96 }
  97
  98 int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
  99 {
 100         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 101         uint32_t tach_period;
 102         uint32_t crystal_clock_freq;
 103         int result = 0;
 104
 105         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 106                 return -1;
 107
 108         if (data->smu_features[GNLD_FAN_CONTROL].supported)
 109                 result = vega10_get_current_rpm(hwmgr, speed);
 110         else {
 111                 uint32_t reg = soc15_get_register_offset(THM_HWID, 0,
 112                                 mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);
 113                 tach_period = (cgs_read_register(hwmgr->device,
 114                                 reg) & CG_TACH_STATUS__TACH_PERIOD_MASK) >>
 115                                 CG_TACH_STATUS__TACH_PERIOD__SHIFT;
 116
 117                 if (tach_period == 0)
 118                         return -EINVAL;
 119
 120                 crystal_clock_freq = smu7_get_xclk(hwmgr);
 121
 122                 *speed = 60 * crystal_clock_freq * 10000 / tach_period;
 123         }
 124
 125         return result;
 126 }
 127
 128 /**
 129 * Set Fan Speed Control to static mode,
 130 * so that the user can decide what speed to use.
 131 * @param    hwmgr  the address of the powerplay hardware manager.
 132 *           mode the fan control mode, 0 default, 1 by percent, 5, by RPM
 133 * @exception Should always succeed.
 134 */
 135 int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
 136 {
 137         uint32_t reg;
 138
 139         reg = soc15_get_register_offset(THM_HWID, 0,
 140                         mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
 141
 142         if (hwmgr->fan_ctrl_is_in_default_mode) {
 143                 hwmgr->fan_ctrl_default_mode =
 144                                 (cgs_read_register(hwmgr->device, reg) &
 145                                 CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >>
 146                                 CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
 147                 hwmgr->tmin = (cgs_read_register(hwmgr->device, reg) &
 148                                 CG_FDO_CTRL2__TMIN_MASK) >>
 149                                 CG_FDO_CTRL2__TMIN__SHIFT;
 150                 hwmgr->fan_ctrl_is_in_default_mode = false;
 151         }
 152
 153         cgs_write_register(hwmgr->device, reg,
 154                         (cgs_read_register(hwmgr->device, reg) &
 155                         ~CG_FDO_CTRL2__TMIN_MASK) |
 156                         (0 << CG_FDO_CTRL2__TMIN__SHIFT));
 157         cgs_write_register(hwmgr->device, reg,
 158                         (cgs_read_register(hwmgr->device, reg) &
 159                         ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
 160                         (mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
 161
 162         return 0;
 163 }
 164
 165 /**
 166 * Reset Fan Speed Control to default mode.
 167 * @param    hwmgr  the address of the powerplay hardware manager.
 168 * @exception Should always succeed.
 169 */
 170 int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
 171 {
 172         uint32_t reg;
 173
 174         reg = soc15_get_register_offset(THM_HWID, 0,
 175                         mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
 176
 177         if (!hwmgr->fan_ctrl_is_in_default_mode) {
 178                 cgs_write_register(hwmgr->device, reg,
 179                                 (cgs_read_register(hwmgr->device, reg) &
 180                                 ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
 181                                 (hwmgr->fan_ctrl_default_mode <<
 182                                 CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
 183                 cgs_write_register(hwmgr->device, reg,
 184                                 (cgs_read_register(hwmgr->device, reg) &
 185                                 ~CG_FDO_CTRL2__TMIN_MASK) |
 186                                 (hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
 187                 hwmgr->fan_ctrl_is_in_default_mode = true;
 188         }
 189
 190         return 0;
 191 }
 192
 193 /**
 194  * @fn vega10_enable_fan_control_feature
 195  * @brief Enables the SMC Fan Control Feature.
 196  *
 197  * @param    hwmgr - the address of the powerplay hardware manager.
 198  * @return   0 on success. -1 otherwise.
 199  */
 200 static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
 201 {
 202         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 203
 204         if (data->smu_features[GNLD_FAN_CONTROL].supported) {
 205                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
 206                                 hwmgr->smumgr, true,
 207                                 data->smu_features[GNLD_FAN_CONTROL].
 208                                 smu_feature_bitmap),
 209                                 "Attempt to Enable FAN CONTROL feature Failed!",
 210                                 return -1);
 211                 data->smu_features[GNLD_FAN_CONTROL].enabled = true;
 212         }
 213
 214         return 0;
 215 }
 216
 217 static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
 218 {
 219         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 220
 221         if (data->smu_features[GNLD_FAN_CONTROL].supported) {
 222                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
 223                                 hwmgr->smumgr, false,
 224                                 data->smu_features[GNLD_FAN_CONTROL].
 225                                 smu_feature_bitmap),
 226                                 "Attempt to Enable FAN CONTROL feature Failed!",
 227                                 return -1);
 228                 data->smu_features[GNLD_FAN_CONTROL].enabled = false;
 229         }
 230
 231         return 0;
 232 }
 233
 234 int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
 235 {
 236         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 237                 return -1;
 238
 239         PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr),
 240                         "Attempt to Enable SMC FAN CONTROL Feature Failed!",
 241                         return -1);
 242
 243         return 0;
 244 }
 245
 246
 247 int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
 248 {
 249         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 250
 251         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 252                 return -1;
 253
 254         if (data->smu_features[GNLD_FAN_CONTROL].supported) {
 255                 PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr),
 256                                 "Attempt to Disable SMC FAN CONTROL Feature Failed!",
 257                                 return -1);
 258         }
 259         return 0;
 260 }
 261
 262 /**
 263 * Set Fan Speed in percent.
 264 * @param    hwmgr  the address of the powerplay hardware manager.
 265 * @param    speed is the percentage value (0% - 100%) to be set.
 266 * @exception Fails is the 100% setting appears to be 0.
 267 */
 268 int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
 269                 uint32_t speed)
 270 {
 271         uint32_t duty100;
 272         uint32_t duty;
 273         uint64_t tmp64;
 274         uint32_t reg;
 275
 276         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 277                 return 0;
 278
 279         if (speed > 100)
 280                 speed = 100;
 281
 282         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 283                         PHM_PlatformCaps_MicrocodeFanControl))
 284                 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
 285
 286         reg = soc15_get_register_offset(THM_HWID, 0,
 287                         mmCG_FDO_CTRL1_BASE_IDX, mmCG_FDO_CTRL1);
 288
 289         duty100 = (cgs_read_register(hwmgr->device, reg) &
 290                         CG_FDO_CTRL1__FMAX_DUTY100_MASK) >>
 291                         CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
 292
 293         if (duty100 == 0)
 294                 return -EINVAL;
 295
 296         tmp64 = (uint64_t)speed * duty100;
 297         do_div(tmp64, 100);
 298         duty = (uint32_t)tmp64;
 299
 300         reg = soc15_get_register_offset(THM_HWID, 0,
 301                         mmCG_FDO_CTRL0_BASE_IDX, mmCG_FDO_CTRL0);
 302         cgs_write_register(hwmgr->device, reg,
 303                         (cgs_read_register(hwmgr->device, reg) &
 304                         ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK) |
 305                         (duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT));
 306
 307         return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
 308 }
 309
 310 /**
 311 * Reset Fan Speed to default.
 312 * @param    hwmgr  the address of the powerplay hardware manager.
 313 * @exception Always succeeds.
 314 */
 315 int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
 316 {
 317         int result;
 318
 319         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 320                 return 0;
 321
 322         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 323                         PHM_PlatformCaps_MicrocodeFanControl)) {
 324                 result = vega10_fan_ctrl_set_static_mode(hwmgr,
 325                                 FDO_PWM_MODE_STATIC);
 326                 if (!result)
 327                         result = vega10_fan_ctrl_start_smc_fan_control(hwmgr);
 328         } else
 329                 result = vega10_fan_ctrl_set_default_mode(hwmgr);
 330
 331         return result;
 332 }
 333
 334 /**
 335 * Set Fan Speed in RPM.
 336 * @param    hwmgr  the address of the powerplay hardware manager.
 337 * @param    speed is the percentage value (min - max) to be set.
 338 * @exception Fails is the speed not lie between min and max.
 339 */
 340 int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
 341 {
 342         uint32_t tach_period;
 343         uint32_t crystal_clock_freq;
 344         int result = 0;
 345         uint32_t reg;
 346
 347         if (hwmgr->thermal_controller.fanInfo.bNoFan ||
 348                         (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
 349                         (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
 350                 return -1;
 351
 352         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 353                         PHM_PlatformCaps_MicrocodeFanControl))
 354                 result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
 355
 356         if (!result) {
 357                 crystal_clock_freq = smu7_get_xclk(hwmgr);
 358                 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
 359                 reg = soc15_get_register_offset(THM_HWID, 0,
 360                                 mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);
 361                 cgs_write_register(hwmgr->device, reg,
 362                                 (cgs_read_register(hwmgr->device, reg) &
 363                                 ~CG_TACH_STATUS__TACH_PERIOD_MASK) |
 364                                 (tach_period << CG_TACH_STATUS__TACH_PERIOD__SHIFT));
 365         }
 366         return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
 367 }
 368
 369 /**
 370 * Reads the remote temperature from the SIslands thermal controller.
 371 *
 372 * @param    hwmgr The address of the hardware manager.
 373 */
 374 int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
 375 {
 376         int temp;
 377         uint32_t reg;
 378
 379         reg = soc15_get_register_offset(THM_HWID, 0,
 380                         mmCG_TACH_STATUS_BASE_IDX,  mmCG_MULT_THERMAL_STATUS);
 381
 382         temp = cgs_read_register(hwmgr->device, reg);
 383
 384         temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
 385                         CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
 386
 387         /* Bit 9 means the reading is lower than the lowest usable value. */
 388         if (temp & 0x200)
 389                 temp = VEGA10_THERMAL_MAXIMUM_TEMP_READING;
 390         else
 391                 temp = temp & 0x1ff;
 392
 393         temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
 394
 395         return temp;
 396 }
 397
 398 /**
 399 * Set the requested temperature range for high and low alert signals
 400 *
 401 * @param    hwmgr The address of the hardware manager.
 402 * @param    range Temperature range to be programmed for
 403 *           high and low alert signals
 404 * @exception PP_Result_BadInput if the input data is not valid.
 405 */
 406 static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
 407                 struct PP_TemperatureRange *range)
 408 {
 409         uint32_t low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *
 410                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
 411         uint32_t high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *
 412                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
 413         uint32_t val, reg;
 414
 415         if (low < range->min)
 416                 low = range->min;
 417         if (high > range->max)
 418                 high = range->max;
 419
 420         if (low > high)
 421                 return -EINVAL;
 422
 423         reg = soc15_get_register_offset(THM_HWID, 0,
 424                         mmTHM_THERMAL_INT_CTRL_BASE_IDX, mmTHM_THERMAL_INT_CTRL);
 425
 426         val = cgs_read_register(hwmgr->device, reg);
 427         val &= ~(THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK);
 428         val |= (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES) <<
 429                         THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT;
 430         val &= ~(THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK);
 431         val |= (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES) <<
 432                         THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT;
 433         cgs_write_register(hwmgr->device, reg, val);
 434
 435         reg = soc15_get_register_offset(THM_HWID, 0,
 436                         mmTHM_TCON_HTC_BASE_IDX, mmTHM_TCON_HTC);
 437
 438         val = cgs_read_register(hwmgr->device, reg);
 439         val &= ~(THM_TCON_HTC__HTC_TMP_LMT_MASK);
 440         val |= (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES) <<
 441                         THM_TCON_HTC__HTC_TMP_LMT__SHIFT;
 442         cgs_write_register(hwmgr->device, reg, val);
 443
 444         return 0;
 445 }
 446
 447 /**
 448 * Programs thermal controller one-time setting registers
 449 *
 450 * @param    hwmgr The address of the hardware manager.
 451 */
 452 static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
 453 {
 454         uint32_t reg;
 455
 456         if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
 457                 reg = soc15_get_register_offset(THM_HWID, 0,
 458                                 mmCG_TACH_CTRL_BASE_IDX, mmCG_TACH_CTRL);
 459                 cgs_write_register(hwmgr->device, reg,
 460                                 (cgs_read_register(hwmgr->device, reg) &
 461                                 ~CG_TACH_CTRL__EDGE_PER_REV_MASK) |
 462                                 ((hwmgr->thermal_controller.fanInfo.
 463                                 ucTachometerPulsesPerRevolution - 1) <<
 464                                 CG_TACH_CTRL__EDGE_PER_REV__SHIFT));
 465         }
 466
 467         reg = soc15_get_register_offset(THM_HWID, 0,
 468                         mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
 469         cgs_write_register(hwmgr->device, reg,
 470                         (cgs_read_register(hwmgr->device, reg) &
 471                         ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK) |
 472                         (0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT));
 473
 474         return 0;
 475 }
 476
 477 /**
 478 * Enable thermal alerts on the RV770 thermal controller.
 479 *
 480 * @param    hwmgr The address of the hardware manager.
 481 */
 482 static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
 483 {
 484         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 485
 486         if (data->smu_features[GNLD_FW_CTF].supported) {
 487                 if (data->smu_features[GNLD_FW_CTF].enabled)
 488                         printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
 489         }
 490
 491         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
 492                         true,
 493                         data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
 494                         "Attempt to Enable FW CTF feature Failed!",
 495                         return -1);
 496         data->smu_features[GNLD_FW_CTF].enabled = true;
 497         return 0;
 498 }
 499
 500 /**
 501 * Disable thermal alerts on the RV770 thermal controller.
 502 * @param    hwmgr The address of the hardware manager.
 503 */
 504 static int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
 505 {
 506         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 507
 508         if (data->smu_features[GNLD_FW_CTF].supported) {
 509                 if (!data->smu_features[GNLD_FW_CTF].enabled)
 510                         printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
 511         }
 512
 513         PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
 514                         false,
 515                         data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
 516                         "Attempt to disable FW CTF feature Failed!",
 517                         return -1);
 518         data->smu_features[GNLD_FW_CTF].enabled = false;
 519         return 0;
 520 }
 521
 522 /**
 523 * Uninitialize the thermal controller.
 524 * Currently just disables alerts.
 525 * @param    hwmgr The address of the hardware manager.
 526 */
 527 int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
 528 {
 529         int result = vega10_thermal_disable_alert(hwmgr);
 530
 531         if (!hwmgr->thermal_controller.fanInfo.bNoFan)
 532                 vega10_fan_ctrl_set_default_mode(hwmgr);
 533
 534         return result;
 535 }
 536
 537 /**
 538 * Set up the fan table to control the fan using the SMC.
 539 * @param    hwmgr  the address of the powerplay hardware manager.
 540 * @param    pInput the pointer to input data
 541 * @param    pOutput the pointer to output data
 542 * @param    pStorage the pointer to temporary storage
 543 * @param    Result the last failure code
 544 * @return   result from set temperature range routine
 545 */
 546 int tf_vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
 547                 void *input, void *output, void *storage, int result)
 548 {
 549         int ret;
 550         struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
 551         PPTable_t *table = &(data->smc_state_table.pp_table);
 552
 553         if (!data->smu_features[GNLD_FAN_CONTROL].supported)
 554                 return 0;
 555
 556         table->FanMaximumRpm = (uint16_t)hwmgr->thermal_controller.
 557                         advanceFanControlParameters.usMaxFanRPM;
 558         table->FanThrottlingRpm = hwmgr->thermal_controller.
 559                         advanceFanControlParameters.usFanRPMMaxLimit;
 560         table->FanAcousticLimitRpm = (uint16_t)(hwmgr->thermal_controller.
 561                         advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
 562         table->FanTargetTemperature = hwmgr->thermal_controller.
 563                         advanceFanControlParameters.usTMax;
 564         table->FanPwmMin = hwmgr->thermal_controller.
 565                         advanceFanControlParameters.usPWMMin * 255 / 100;
 566         table->FanTargetGfxclk = (uint16_t)(hwmgr->thermal_controller.
 567                         advanceFanControlParameters.ulTargetGfxClk);
 568         table->FanGainEdge = hwmgr->thermal_controller.
 569                         advanceFanControlParameters.usFanGainEdge;
 570         table->FanGainHotspot = hwmgr->thermal_controller.
 571                         advanceFanControlParameters.usFanGainHotspot;
 572         table->FanGainLiquid = hwmgr->thermal_controller.
 573                         advanceFanControlParameters.usFanGainLiquid;
 574         table->FanGainVrVddc = hwmgr->thermal_controller.
 575                         advanceFanControlParameters.usFanGainVrVddc;
 576         table->FanGainVrMvdd = hwmgr->thermal_controller.
 577                         advanceFanControlParameters.usFanGainVrMvdd;
 578         table->FanGainPlx = hwmgr->thermal_controller.
 579                         advanceFanControlParameters.usFanGainPlx;
 580         table->FanGainHbm = hwmgr->thermal_controller.
 581                         advanceFanControlParameters.usFanGainHbm;
 582         table->FanZeroRpmEnable = hwmgr->thermal_controller.
 583                         advanceFanControlParameters.ucEnableZeroRPM;
 584         table->FanStopTemp = hwmgr->thermal_controller.
 585                         advanceFanControlParameters.usZeroRPMStopTemperature;
 586         table->FanStartTemp = hwmgr->thermal_controller.
 587                         advanceFanControlParameters.usZeroRPMStartTemperature;
 588
 589         ret = vega10_copy_table_to_smc(hwmgr->smumgr,
 590                         (uint8_t *)(&(data->smc_state_table.pp_table)), PPTABLE);
 591         if (ret)
 592                 pr_info("Failed to update Fan Control Table in PPTable!");
 593
 594         return ret;
 595 }
 596
 597 /**
 598 * Start the fan control on the SMC.
 599 * @param    hwmgr  the address of the powerplay hardware manager.
 600 * @param    pInput the pointer to input data
 601 * @param    pOutput the pointer to output data
 602 * @param    pStorage the pointer to temporary storage
 603 * @param    Result the last failure code
 604 * @return   result from set temperature range routine
 605 */
 606 int tf_vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
 607                 void *input, void *output, void *storage, int result)
 608 {
 609 /* If the fantable setup has failed we could have disabled
 610  * PHM_PlatformCaps_MicrocodeFanControl even after
 611  * this function was included in the table.
 612  * Make sure that we still think controlling the fan is OK.
 613 */
 614         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 615                         PHM_PlatformCaps_MicrocodeFanControl)) {
 616                 vega10_fan_ctrl_start_smc_fan_control(hwmgr);
 617                 vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
 618         }
 619
 620         return 0;
 621 }
 622
 623 /**
 624 * Set temperature range for high and low alerts
 625 * @param    hwmgr  the address of the powerplay hardware manager.
 626 * @param    pInput the pointer to input data
 627 * @param    pOutput the pointer to output data
 628 * @param    pStorage the pointer to temporary storage
 629 * @param    Result the last failure code
 630 * @return   result from set temperature range routine
 631 */
 632 int tf_vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
 633                 void *input, void *output, void *storage, int result)
 634 {
 635         struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input;
 636
 637         if (range == NULL)
 638                 return -EINVAL;
 639
 640         return vega10_thermal_set_temperature_range(hwmgr, range);
 641 }
 642
 643 /**
 644 * Programs one-time setting registers
 645 * @param    hwmgr  the address of the powerplay hardware manager.
 646 * @param    pInput the pointer to input data
 647 * @param    pOutput the pointer to output data
 648 * @param    pStorage the pointer to temporary storage
 649 * @param    Result the last failure code
 650 * @return   result from initialize thermal controller routine
 651 */
 652 int tf_vega10_thermal_initialize(struct pp_hwmgr *hwmgr,
 653                 void *input, void *output, void *storage, int result)
 654 {
 655         return vega10_thermal_initialize(hwmgr);
 656 }
 657
 658 /**
 659 * Enable high and low alerts
 660 * @param    hwmgr  the address of the powerplay hardware manager.
 661 * @param    pInput the pointer to input data
 662 * @param    pOutput the pointer to output data
 663 * @param    pStorage the pointer to temporary storage
 664 * @param    Result the last failure code
 665 * @return   result from enable alert routine
 666 */
 667 int tf_vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr,
 668                 void *input, void *output, void *storage, int result)
 669 {
 670         return vega10_thermal_enable_alert(hwmgr);
 671 }
 672
 673 /**
 674 * Disable high and low alerts
 675 * @param    hwmgr  the address of the powerplay hardware manager.
 676 * @param    pInput the pointer to input data
 677 * @param    pOutput the pointer to output data
 678 * @param    pStorage the pointer to temporary storage
 679 * @param    Result the last failure code
 680 * @return   result from disable alert routine
 681 */
 682 static int tf_vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr,
 683                 void *input, void *output, void *storage, int result)
 684 {
 685         return vega10_thermal_disable_alert(hwmgr);
 686 }
 687
 688 static struct phm_master_table_item
 689 vega10_thermal_start_thermal_controller_master_list[] = {
 690         {NULL, tf_vega10_thermal_initialize},
 691         {NULL, tf_vega10_thermal_set_temperature_range},
 692         {NULL, tf_vega10_thermal_enable_alert},
 693 /* We should restrict performance levels to low before we halt the SMC.
 694  * On the other hand we are still in boot state when we do this
 695  * so it would be pointless.
 696  * If this assumption changes we have to revisit this table.
 697  */
 698         {NULL, tf_vega10_thermal_setup_fan_table},
 699         {NULL, tf_vega10_thermal_start_smc_fan_control},
 700         {NULL, NULL}
 701 };
 702
 703 static struct phm_master_table_header
 704 vega10_thermal_start_thermal_controller_master = {
 705         0,
 706         PHM_MasterTableFlag_None,
 707         vega10_thermal_start_thermal_controller_master_list
 708 };
 709
 710 static struct phm_master_table_item
 711 vega10_thermal_set_temperature_range_master_list[] = {
 712         {NULL, tf_vega10_thermal_disable_alert},
 713         {NULL, tf_vega10_thermal_set_temperature_range},
 714         {NULL, tf_vega10_thermal_enable_alert},
 715         {NULL, NULL}
 716 };
 717
 718 struct phm_master_table_header
 719 vega10_thermal_set_temperature_range_master = {
 720         0,
 721         PHM_MasterTableFlag_None,
 722         vega10_thermal_set_temperature_range_master_list
 723 };
 724
 725 int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
 726 {
 727         if (!hwmgr->thermal_controller.fanInfo.bNoFan) {
 728                 vega10_fan_ctrl_set_default_mode(hwmgr);
 729                 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
 730         }
 731         return 0;
 732 }
 733
 734 /**
 735 * Initializes the thermal controller related functions
 736 * in the Hardware Manager structure.
 737 * @param    hwmgr The address of the hardware manager.
 738 * @exception Any error code from the low-level communication.
 739 */
 740 int pp_vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
 741 {
 742         int result;
 743
 744         result = phm_construct_table(hwmgr,
 745                         &vega10_thermal_set_temperature_range_master,
 746                         &(hwmgr->set_temperature_range));
 747
 748         if (!result) {
 749                 result = phm_construct_table(hwmgr,
 750                                 &vega10_thermal_start_thermal_controller_master,
 751                                 &(hwmgr->start_thermal_controller));
 752                 if (result)
 753                         phm_destroy_table(hwmgr,
 754                                         &(hwmgr->set_temperature_range));
 755         }
 756
 757         if (!result)
 758                 hwmgr->fan_ctrl_is_in_default_mode = true;
 759         return result;
 760 }
 761