drivers/gpu/drm/armada/armada_crtc.c

   1 /*
   2  * Copyright (C) 2012 Russell King
   3  *  Rewritten from the dovefb driver, and Armada510 manuals.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <drm/drmP.h>
  14 #include <drm/drm_crtc_helper.h>
  15 #include <drm/drm_plane_helper.h>
  16 #include "armada_crtc.h"
  17 #include "armada_drm.h"
  18 #include "armada_fb.h"
  19 #include "armada_gem.h"
  20 #include "armada_hw.h"
  21
  22 struct armada_frame_work {
  23         struct drm_pending_vblank_event *event;
  24         struct armada_regs regs[4];
  25         struct drm_framebuffer *old_fb;
  26 };
  27
  28 enum csc_mode {
  29         CSC_AUTO = 0,
  30         CSC_YUV_CCIR601 = 1,
  31         CSC_YUV_CCIR709 = 2,
  32         CSC_RGB_COMPUTER = 1,
  33         CSC_RGB_STUDIO = 2,
  34 };
  35
  36 static const uint32_t armada_primary_formats[] = {
  37         DRM_FORMAT_UYVY,
  38         DRM_FORMAT_YUYV,
  39         DRM_FORMAT_VYUY,
  40         DRM_FORMAT_YVYU,
  41         DRM_FORMAT_ARGB8888,
  42         DRM_FORMAT_ABGR8888,
  43         DRM_FORMAT_XRGB8888,
  44         DRM_FORMAT_XBGR8888,
  45         DRM_FORMAT_RGB888,
  46         DRM_FORMAT_BGR888,
  47         DRM_FORMAT_ARGB1555,
  48         DRM_FORMAT_ABGR1555,
  49         DRM_FORMAT_RGB565,
  50         DRM_FORMAT_BGR565,
  51 };
  52
  53 /*
  54  * A note about interlacing.  Let's consider HDMI 1920x1080i.
  55  * The timing parameters we have from X are:
  56  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  57  *  1920 2448 2492 2640  1080 1084 1094 1125
  58  * Which get translated to:
  59  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  60  *  1920 2448 2492 2640   540  542  547  562
  61  *
  62  * This is how it is defined by CEA-861-D - line and pixel numbers are
  63  * referenced to the rising edge of VSYNC and HSYNC.  Total clocks per
  64  * line: 2640.  The odd frame, the first active line is at line 21, and
  65  * the even frame, the first active line is 584.
  66  *
  67  * LN:    560     561     562     563             567     568    569
  68  * DE:    ~~~|____________________________//__________________________
  69  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  70  * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
  71  *  22 blanking lines.  VSYNC at 1320 (referenced to the HSYNC rising edge).
  72  *
  73  * LN:    1123   1124    1125      1               5       6      7
  74  * DE:    ~~~|____________________________//__________________________
  75  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  76  * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
  77  *  23 blanking lines
  78  *
  79  * The Armada LCD Controller line and pixel numbers are, like X timings,
  80  * referenced to the top left of the active frame.
  81  *
  82  * So, translating these to our LCD controller:
  83  *  Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
  84  *  Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
  85  * Note: Vsync front porch remains constant!
  86  *
  87  * if (odd_frame) {
  88  *   vtotal = mode->crtc_vtotal + 1;
  89  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
  90  *   vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
  91  * } else {
  92  *   vtotal = mode->crtc_vtotal;
  93  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
  94  *   vhorizpos = mode->crtc_hsync_start;
  95  * }
  96  * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
  97  *
  98  * So, we need to reprogram these registers on each vsync event:
  99  *  LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
 100  *
 101  * Note: we do not use the frame done interrupts because these appear
 102  * to happen too early, and lead to jitter on the display (presumably
 103  * they occur at the end of the last active line, before the vsync back
 104  * porch, which we're reprogramming.)
 105  */
 106
 107 void
 108 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
 109 {
 110         while (regs->offset != ~0) {
 111                 void __iomem *reg = dcrtc->base + regs->offset;
 112                 uint32_t val;
 113
 114                 val = regs->mask;
 115                 if (val != 0)
 116                         val &= readl_relaxed(reg);
 117                 writel_relaxed(val | regs->val, reg);
 118                 ++regs;
 119         }
 120 }
 121
 122 #define dpms_blanked(dpms)      ((dpms) != DRM_MODE_DPMS_ON)
 123
 124 static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
 125 {
 126         uint32_t dumb_ctrl;
 127
 128         dumb_ctrl = dcrtc->cfg_dumb_ctrl;
 129
 130         if (!dpms_blanked(dcrtc->dpms))
 131                 dumb_ctrl |= CFG_DUMB_ENA;
 132
 133         /*
 134          * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
 135          * be using SPI or GPIO.  If we set this to DUMB_BLANK, we will
 136          * force LCD_D[23:0] to output blank color, overriding the GPIO or
 137          * SPI usage.  So leave it as-is unless in DUMB24_RGB888_0 mode.
 138          */
 139         if (dpms_blanked(dcrtc->dpms) &&
 140             (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
 141                 dumb_ctrl &= ~DUMB_MASK;
 142                 dumb_ctrl |= DUMB_BLANK;
 143         }
 144
 145         /*
 146          * The documentation doesn't indicate what the normal state of
 147          * the sync signals are.  Sebastian Hesselbart kindly probed
 148          * these signals on his board to determine their state.
 149          *
 150          * The non-inverted state of the sync signals is active high.
 151          * Setting these bits makes the appropriate signal active low.
 152          */
 153         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
 154                 dumb_ctrl |= CFG_INV_CSYNC;
 155         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
 156                 dumb_ctrl |= CFG_INV_HSYNC;
 157         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
 158                 dumb_ctrl |= CFG_INV_VSYNC;
 159
 160         if (dcrtc->dumb_ctrl != dumb_ctrl) {
 161                 dcrtc->dumb_ctrl = dumb_ctrl;
 162                 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
 163         }
 164 }
 165
 166 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
 167         int x, int y, struct armada_regs *regs, bool interlaced)
 168 {
 169         struct armada_gem_object *obj = drm_fb_obj(fb);
 170         unsigned pitch = fb->pitches[0];
 171         unsigned offset = y * pitch + x * fb->bits_per_pixel / 8;
 172         uint32_t addr_odd, addr_even;
 173         unsigned i = 0;
 174
 175         DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
 176                 pitch, x, y, fb->bits_per_pixel);
 177
 178         addr_odd = addr_even = obj->dev_addr + offset;
 179
 180         if (interlaced) {
 181                 addr_even += pitch;
 182                 pitch *= 2;
 183         }
 184
 185         /* write offset, base, and pitch */
 186         armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
 187         armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
 188         armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
 189
 190         return i;
 191 }
 192
 193 void armada_drm_vbl_event_add(struct armada_crtc *dcrtc,
 194         struct armada_vbl_event *evt)
 195 {
 196         unsigned long flags;
 197         bool not_on_list;
 198
 199         WARN_ON(drm_vblank_get(dcrtc->crtc.dev, dcrtc->num));
 200
 201         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 202         not_on_list = list_empty(&evt->node);
 203         if (not_on_list)
 204                 list_add_tail(&evt->node, &dcrtc->vbl_list);
 205         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 206
 207         if (!not_on_list)
 208                 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
 209 }
 210
 211 void armada_drm_vbl_event_remove(struct armada_crtc *dcrtc,
 212         struct armada_vbl_event *evt)
 213 {
 214         if (!list_empty(&evt->node)) {
 215                 list_del_init(&evt->node);
 216                 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
 217         }
 218 }
 219
 220 static void armada_drm_vbl_event_run(struct armada_crtc *dcrtc)
 221 {
 222         struct armada_vbl_event *e, *n;
 223
 224         list_for_each_entry_safe(e, n, &dcrtc->vbl_list, node) {
 225                 list_del_init(&e->node);
 226                 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
 227                 e->fn(dcrtc, e->data);
 228         }
 229 }
 230
 231 static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc,
 232         struct armada_frame_work *work)
 233 {
 234         struct drm_device *dev = dcrtc->crtc.dev;
 235         int ret;
 236
 237         ret = drm_vblank_get(dev, dcrtc->num);
 238         if (ret) {
 239                 DRM_ERROR("failed to acquire vblank counter\n");
 240                 return ret;
 241         }
 242
 243         if (cmpxchg(&dcrtc->frame_work, NULL, work)) {
 244                 drm_vblank_put(dev, dcrtc->num);
 245                 ret = -EBUSY;
 246         }
 247
 248         return ret;
 249 }
 250
 251 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc,
 252         struct armada_frame_work *work)
 253 {
 254         struct drm_device *dev = dcrtc->crtc.dev;
 255         unsigned long flags;
 256
 257         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 258         armada_drm_crtc_update_regs(dcrtc, work->regs);
 259         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 260
 261         if (work->event) {
 262                 spin_lock_irqsave(&dev->event_lock, flags);
 263                 drm_send_vblank_event(dev, dcrtc->num, work->event);
 264                 spin_unlock_irqrestore(&dev->event_lock, flags);
 265         }
 266
 267         drm_vblank_put(dev, dcrtc->num);
 268
 269         /* Finally, queue the process-half of the cleanup. */
 270         __armada_drm_queue_unref_work(dcrtc->crtc.dev, work->old_fb);
 271         kfree(work);
 272 }
 273
 274 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
 275         struct drm_framebuffer *fb, bool force)
 276 {
 277         struct armada_frame_work *work;
 278
 279         if (!fb)
 280                 return;
 281
 282         if (force) {
 283                 /* Display is disabled, so just drop the old fb */
 284                 drm_framebuffer_unreference(fb);
 285                 return;
 286         }
 287
 288         work = kmalloc(sizeof(*work), GFP_KERNEL);
 289         if (work) {
 290                 int i = 0;
 291                 work->event = NULL;
 292                 work->old_fb = fb;
 293                 armada_reg_queue_end(work->regs, i);
 294
 295                 if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0)
 296                         return;
 297
 298                 kfree(work);
 299         }
 300
 301         /*
 302          * Oops - just drop the reference immediately and hope for
 303          * the best.  The worst that will happen is the buffer gets
 304          * reused before it has finished being displayed.
 305          */
 306         drm_framebuffer_unreference(fb);
 307 }
 308
 309 static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
 310 {
 311         struct armada_frame_work *work;
 312
 313         /*
 314          * Tell the DRM core that vblank IRQs aren't going to happen for
 315          * a while.  This cleans up any pending vblank events for us.
 316          */
 317         drm_crtc_vblank_off(&dcrtc->crtc);
 318
 319         /* Handle any pending flip event. */
 320         work = xchg(&dcrtc->frame_work, NULL);
 321         if (work)
 322                 armada_drm_crtc_complete_frame_work(dcrtc, work);
 323 }
 324
 325 void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b,
 326         int idx)
 327 {
 328 }
 329
 330 void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 331         int idx)
 332 {
 333 }
 334
 335 /* The mode_config.mutex will be held for this call */
 336 static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
 337 {
 338         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 339
 340         if (dcrtc->dpms != dpms) {
 341                 dcrtc->dpms = dpms;
 342                 if (!IS_ERR(dcrtc->clk) && !dpms_blanked(dpms))
 343                         WARN_ON(clk_prepare_enable(dcrtc->clk));
 344                 armada_drm_crtc_update(dcrtc);
 345                 if (!IS_ERR(dcrtc->clk) && dpms_blanked(dpms))
 346                         clk_disable_unprepare(dcrtc->clk);
 347                 if (dpms_blanked(dpms))
 348                         armada_drm_vblank_off(dcrtc);
 349                 else
 350                         drm_crtc_vblank_on(&dcrtc->crtc);
 351         }
 352 }
 353
 354 /*
 355  * Prepare for a mode set.  Turn off overlay to ensure that we don't end
 356  * up with the overlay size being bigger than the active screen size.
 357  * We rely upon X refreshing this state after the mode set has completed.
 358  *
 359  * The mode_config.mutex will be held for this call
 360  */
 361 static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
 362 {
 363         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 364         struct drm_plane *plane;
 365
 366         /*
 367          * If we have an overlay plane associated with this CRTC, disable
 368          * it before the modeset to avoid its coordinates being outside
 369          * the new mode parameters.
 370          */
 371         plane = dcrtc->plane;
 372         if (plane)
 373                 drm_plane_force_disable(plane);
 374 }
 375
 376 /* The mode_config.mutex will be held for this call */
 377 static void armada_drm_crtc_commit(struct drm_crtc *crtc)
 378 {
 379         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 380
 381         if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
 382                 dcrtc->dpms = DRM_MODE_DPMS_ON;
 383                 armada_drm_crtc_update(dcrtc);
 384         }
 385 }
 386
 387 /* The mode_config.mutex will be held for this call */
 388 static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
 389         const struct drm_display_mode *mode, struct drm_display_mode *adj)
 390 {
 391         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 392         int ret;
 393
 394         /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
 395         if (!dcrtc->variant->has_spu_adv_reg &&
 396             adj->flags & DRM_MODE_FLAG_INTERLACE)
 397                 return false;
 398
 399         /* Check whether the display mode is possible */
 400         ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
 401         if (ret)
 402                 return false;
 403
 404         return true;
 405 }
 406
 407 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
 408 {
 409         void __iomem *base = dcrtc->base;
 410
 411         if (stat & DMA_FF_UNDERFLOW)
 412                 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
 413         if (stat & GRA_FF_UNDERFLOW)
 414                 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
 415
 416         if (stat & VSYNC_IRQ)
 417                 drm_handle_vblank(dcrtc->crtc.dev, dcrtc->num);
 418
 419         spin_lock(&dcrtc->irq_lock);
 420         armada_drm_vbl_event_run(dcrtc);
 421
 422         if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
 423                 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
 424                 uint32_t val;
 425
 426                 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
 427                 writel_relaxed(dcrtc->v[i].spu_v_h_total,
 428                                base + LCD_SPUT_V_H_TOTAL);
 429
 430                 val = readl_relaxed(base + LCD_SPU_ADV_REG);
 431                 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
 432                 val |= dcrtc->v[i].spu_adv_reg;
 433                 writel_relaxed(val, base + LCD_SPU_ADV_REG);
 434         }
 435
 436         if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
 437                 writel_relaxed(dcrtc->cursor_hw_pos,
 438                                base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 439                 writel_relaxed(dcrtc->cursor_hw_sz,
 440                                base + LCD_SPU_HWC_HPXL_VLN);
 441                 armada_updatel(CFG_HWC_ENA,
 442                                CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
 443                                base + LCD_SPU_DMA_CTRL0);
 444                 dcrtc->cursor_update = false;
 445                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 446         }
 447
 448         spin_unlock(&dcrtc->irq_lock);
 449
 450         if (stat & GRA_FRAME_IRQ) {
 451                 struct armada_frame_work *work = xchg(&dcrtc->frame_work, NULL);
 452
 453                 if (work)
 454                         armada_drm_crtc_complete_frame_work(dcrtc, work);
 455
 456                 wake_up(&dcrtc->frame_wait);
 457         }
 458 }
 459
 460 static irqreturn_t armada_drm_irq(int irq, void *arg)
 461 {
 462         struct armada_crtc *dcrtc = arg;
 463         u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
 464
 465         /*
 466          * This is rediculous - rather than writing bits to clear, we
 467          * have to set the actual status register value.  This is racy.
 468          */
 469         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 470
 471         /* Mask out those interrupts we haven't enabled */
 472         v = stat & dcrtc->irq_ena;
 473
 474         if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
 475                 armada_drm_crtc_irq(dcrtc, stat);
 476                 return IRQ_HANDLED;
 477         }
 478         return IRQ_NONE;
 479 }
 480
 481 /* These are locked by dev->vbl_lock */
 482 void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
 483 {
 484         if (dcrtc->irq_ena & mask) {
 485                 dcrtc->irq_ena &= ~mask;
 486                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 487         }
 488 }
 489
 490 void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
 491 {
 492         if ((dcrtc->irq_ena & mask) != mask) {
 493                 dcrtc->irq_ena |= mask;
 494                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 495                 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
 496                         writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 497         }
 498 }
 499
 500 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
 501 {
 502         struct drm_display_mode *adj = &dcrtc->crtc.mode;
 503         uint32_t val = 0;
 504
 505         if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
 506                 val |= CFG_CSC_YUV_CCIR709;
 507         if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
 508                 val |= CFG_CSC_RGB_STUDIO;
 509
 510         /*
 511          * In auto mode, set the colorimetry, based upon the HDMI spec.
 512          * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
 513          * ITU601.  It may be more appropriate to set this depending on
 514          * the source - but what if the graphic frame is YUV and the
 515          * video frame is RGB?
 516          */
 517         if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
 518              !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
 519             (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
 520                 if (dcrtc->csc_yuv_mode == CSC_AUTO)
 521                         val |= CFG_CSC_YUV_CCIR709;
 522         }
 523
 524         /*
 525          * We assume we're connected to a TV-like device, so the YUV->RGB
 526          * conversion should produce a limited range.  We should set this
 527          * depending on the connectors attached to this CRTC, and what
 528          * kind of device they report being connected.
 529          */
 530         if (dcrtc->csc_rgb_mode == CSC_AUTO)
 531                 val |= CFG_CSC_RGB_STUDIO;
 532
 533         return val;
 534 }
 535
 536 /* The mode_config.mutex will be held for this call */
 537 static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
 538         struct drm_display_mode *mode, struct drm_display_mode *adj,
 539         int x, int y, struct drm_framebuffer *old_fb)
 540 {
 541         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 542         struct armada_regs regs[17];
 543         uint32_t lm, rm, tm, bm, val, sclk;
 544         unsigned long flags;
 545         unsigned i;
 546         bool interlaced;
 547
 548         drm_framebuffer_reference(crtc->primary->fb);
 549
 550         interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
 551
 552         i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb,
 553                                     x, y, regs, interlaced);
 554
 555         rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
 556         lm = adj->crtc_htotal - adj->crtc_hsync_end;
 557         bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
 558         tm = adj->crtc_vtotal - adj->crtc_vsync_end;
 559
 560         DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
 561                 adj->crtc_hdisplay,
 562                 adj->crtc_hsync_start,
 563                 adj->crtc_hsync_end,
 564                 adj->crtc_htotal, lm, rm);
 565         DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
 566                 adj->crtc_vdisplay,
 567                 adj->crtc_vsync_start,
 568                 adj->crtc_vsync_end,
 569                 adj->crtc_vtotal, tm, bm);
 570
 571         /* Wait for pending flips to complete */
 572         wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
 573
 574         drm_crtc_vblank_off(crtc);
 575
 576         val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
 577         if (val != dcrtc->dumb_ctrl) {
 578                 dcrtc->dumb_ctrl = val;
 579                 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
 580         }
 581
 582         /*
 583          * If we are blanked, we would have disabled the clock.  Re-enable
 584          * it so that compute_clock() does the right thing.
 585          */
 586         if (!IS_ERR(dcrtc->clk) && dpms_blanked(dcrtc->dpms))
 587                 WARN_ON(clk_prepare_enable(dcrtc->clk));
 588
 589         /* Now compute the divider for real */
 590         dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
 591
 592         /* Ensure graphic fifo is enabled */
 593         armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
 594         armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
 595
 596         if (interlaced ^ dcrtc->interlaced) {
 597                 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
 598                         drm_vblank_get(dcrtc->crtc.dev, dcrtc->num);
 599                 else
 600                         drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
 601                 dcrtc->interlaced = interlaced;
 602         }
 603
 604         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 605
 606         /* Even interlaced/progressive frame */
 607         dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
 608                                     adj->crtc_htotal;
 609         dcrtc->v[1].spu_v_porch = tm << 16 | bm;
 610         val = adj->crtc_hsync_start;
 611         dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 612                 dcrtc->variant->spu_adv_reg;
 613
 614         if (interlaced) {
 615                 /* Odd interlaced frame */
 616                 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
 617                                                 (1 << 16);
 618                 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
 619                 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
 620                 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 621                         dcrtc->variant->spu_adv_reg;
 622         } else {
 623                 dcrtc->v[0] = dcrtc->v[1];
 624         }
 625
 626         val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
 627
 628         armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
 629         armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN);
 630         armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN);
 631         armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
 632         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
 633         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
 634                            LCD_SPUT_V_H_TOTAL);
 635
 636         if (dcrtc->variant->has_spu_adv_reg) {
 637                 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
 638                                      ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
 639                                      ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
 640         }
 641
 642         val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
 643         val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
 644         val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
 645
 646         if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
 647                 val |= CFG_PALETTE_ENA;
 648
 649         if (interlaced)
 650                 val |= CFG_GRA_FTOGGLE;
 651
 652         armada_reg_queue_mod(regs, i, val, CFG_GRAFORMAT |
 653                              CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
 654                                          CFG_SWAPYU | CFG_YUV2RGB) |
 655                              CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
 656                              LCD_SPU_DMA_CTRL0);
 657
 658         val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
 659         armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
 660
 661         val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
 662         armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
 663         armada_reg_queue_end(regs, i);
 664
 665         armada_drm_crtc_update_regs(dcrtc, regs);
 666         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 667
 668         armada_drm_crtc_update(dcrtc);
 669
 670         drm_crtc_vblank_on(crtc);
 671         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 672
 673         return 0;
 674 }
 675
 676 /* The mode_config.mutex will be held for this call */
 677 static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 678         struct drm_framebuffer *old_fb)
 679 {
 680         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 681         struct armada_regs regs[4];
 682         unsigned i;
 683
 684         i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs,
 685                                     dcrtc->interlaced);
 686         armada_reg_queue_end(regs, i);
 687
 688         /* Wait for pending flips to complete */
 689         wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
 690
 691         /* Take a reference to the new fb as we're using it */
 692         drm_framebuffer_reference(crtc->primary->fb);
 693
 694         /* Update the base in the CRTC */
 695         armada_drm_crtc_update_regs(dcrtc, regs);
 696
 697         /* Drop our previously held reference */
 698         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 699
 700         return 0;
 701 }
 702
 703 /* The mode_config.mutex will be held for this call */
 704 static void armada_drm_crtc_disable(struct drm_crtc *crtc)
 705 {
 706         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 707
 708         armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 709         armada_drm_crtc_finish_fb(dcrtc, crtc->primary->fb, true);
 710
 711         /* Power down most RAMs and FIFOs */
 712         writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
 713                        CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
 714                        CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
 715 }
 716
 717 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
 718         .dpms           = armada_drm_crtc_dpms,
 719         .prepare        = armada_drm_crtc_prepare,
 720         .commit         = armada_drm_crtc_commit,
 721         .mode_fixup     = armada_drm_crtc_mode_fixup,
 722         .mode_set       = armada_drm_crtc_mode_set,
 723         .mode_set_base  = armada_drm_crtc_mode_set_base,
 724         .disable        = armada_drm_crtc_disable,
 725 };
 726
 727 static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
 728         unsigned stride, unsigned width, unsigned height)
 729 {
 730         uint32_t addr;
 731         unsigned y;
 732
 733         addr = SRAM_HWC32_RAM1;
 734         for (y = 0; y < height; y++) {
 735                 uint32_t *p = &pix[y * stride];
 736                 unsigned x;
 737
 738                 for (x = 0; x < width; x++, p++) {
 739                         uint32_t val = *p;
 740
 741                         val = (val & 0xff00ff00) |
 742                               (val & 0x000000ff) << 16 |
 743                               (val & 0x00ff0000) >> 16;
 744
 745                         writel_relaxed(val,
 746                                        base + LCD_SPU_SRAM_WRDAT);
 747                         writel_relaxed(addr | SRAM_WRITE,
 748                                        base + LCD_SPU_SRAM_CTRL);
 749                         readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 750                         addr += 1;
 751                         if ((addr & 0x00ff) == 0)
 752                                 addr += 0xf00;
 753                         if ((addr & 0x30ff) == 0)
 754                                 addr = SRAM_HWC32_RAM2;
 755                 }
 756         }
 757 }
 758
 759 static void armada_drm_crtc_cursor_tran(void __iomem *base)
 760 {
 761         unsigned addr;
 762
 763         for (addr = 0; addr < 256; addr++) {
 764                 /* write the default value */
 765                 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
 766                 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
 767                                base + LCD_SPU_SRAM_CTRL);
 768         }
 769 }
 770
 771 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
 772 {
 773         uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
 774         uint32_t yoff, yscr, h = dcrtc->cursor_h;
 775         uint32_t para1;
 776
 777         /*
 778          * Calculate the visible width and height of the cursor,
 779          * screen position, and the position in the cursor bitmap.
 780          */
 781         if (dcrtc->cursor_x < 0) {
 782                 xoff = -dcrtc->cursor_x;
 783                 xscr = 0;
 784                 w -= min(xoff, w);
 785         } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
 786                 xoff = 0;
 787                 xscr = dcrtc->cursor_x;
 788                 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
 789         } else {
 790                 xoff = 0;
 791                 xscr = dcrtc->cursor_x;
 792         }
 793
 794         if (dcrtc->cursor_y < 0) {
 795                 yoff = -dcrtc->cursor_y;
 796                 yscr = 0;
 797                 h -= min(yoff, h);
 798         } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
 799                 yoff = 0;
 800                 yscr = dcrtc->cursor_y;
 801                 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
 802         } else {
 803                 yoff = 0;
 804                 yscr = dcrtc->cursor_y;
 805         }
 806
 807         /* On interlaced modes, the vertical cursor size must be halved */
 808         s = dcrtc->cursor_w;
 809         if (dcrtc->interlaced) {
 810                 s *= 2;
 811                 yscr /= 2;
 812                 h /= 2;
 813         }
 814
 815         if (!dcrtc->cursor_obj || !h || !w) {
 816                 spin_lock_irq(&dcrtc->irq_lock);
 817                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 818                 dcrtc->cursor_update = false;
 819                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 820                 spin_unlock_irq(&dcrtc->irq_lock);
 821                 return 0;
 822         }
 823
 824         para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
 825         armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
 826                        dcrtc->base + LCD_SPU_SRAM_PARA1);
 827
 828         /*
 829          * Initialize the transparency if the SRAM was powered down.
 830          * We must also reload the cursor data as well.
 831          */
 832         if (!(para1 & CFG_CSB_256x32)) {
 833                 armada_drm_crtc_cursor_tran(dcrtc->base);
 834                 reload = true;
 835         }
 836
 837         if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
 838                 spin_lock_irq(&dcrtc->irq_lock);
 839                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 840                 dcrtc->cursor_update = false;
 841                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 842                 spin_unlock_irq(&dcrtc->irq_lock);
 843                 reload = true;
 844         }
 845         if (reload) {
 846                 struct armada_gem_object *obj = dcrtc->cursor_obj;
 847                 uint32_t *pix;
 848                 /* Set the top-left corner of the cursor image */
 849                 pix = obj->addr;
 850                 pix += yoff * s + xoff;
 851                 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
 852         }
 853
 854         /* Reload the cursor position, size and enable in the IRQ handler */
 855         spin_lock_irq(&dcrtc->irq_lock);
 856         dcrtc->cursor_hw_pos = yscr << 16 | xscr;
 857         dcrtc->cursor_hw_sz = h << 16 | w;
 858         dcrtc->cursor_update = true;
 859         armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 860         spin_unlock_irq(&dcrtc->irq_lock);
 861
 862         return 0;
 863 }
 864
 865 static void cursor_update(void *data)
 866 {
 867         armada_drm_crtc_cursor_update(data, true);
 868 }
 869
 870 static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
 871         struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
 872 {
 873         struct drm_device *dev = crtc->dev;
 874         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 875         struct armada_gem_object *obj = NULL;
 876         int ret;
 877
 878         /* If no cursor support, replicate drm's return value */
 879         if (!dcrtc->variant->has_spu_adv_reg)
 880                 return -ENXIO;
 881
 882         if (handle && w > 0 && h > 0) {
 883                 /* maximum size is 64x32 or 32x64 */
 884                 if (w > 64 || h > 64 || (w > 32 && h > 32))
 885                         return -ENOMEM;
 886
 887                 obj = armada_gem_object_lookup(dev, file, handle);
 888                 if (!obj)
 889                         return -ENOENT;
 890
 891                 /* Must be a kernel-mapped object */
 892                 if (!obj->addr) {
 893                         drm_gem_object_unreference_unlocked(&obj->obj);
 894                         return -EINVAL;
 895                 }
 896
 897                 if (obj->obj.size < w * h * 4) {
 898                         DRM_ERROR("buffer is too small\n");
 899                         drm_gem_object_unreference_unlocked(&obj->obj);
 900                         return -ENOMEM;
 901                 }
 902         }
 903
 904         mutex_lock(&dev->struct_mutex);
 905         if (dcrtc->cursor_obj) {
 906                 dcrtc->cursor_obj->update = NULL;
 907                 dcrtc->cursor_obj->update_data = NULL;
 908                 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
 909         }
 910         dcrtc->cursor_obj = obj;
 911         dcrtc->cursor_w = w;
 912         dcrtc->cursor_h = h;
 913         ret = armada_drm_crtc_cursor_update(dcrtc, true);
 914         if (obj) {
 915                 obj->update_data = dcrtc;
 916                 obj->update = cursor_update;
 917         }
 918         mutex_unlock(&dev->struct_mutex);
 919
 920         return ret;
 921 }
 922
 923 static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 924 {
 925         struct drm_device *dev = crtc->dev;
 926         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 927         int ret;
 928
 929         /* If no cursor support, replicate drm's return value */
 930         if (!dcrtc->variant->has_spu_adv_reg)
 931                 return -EFAULT;
 932
 933         mutex_lock(&dev->struct_mutex);
 934         dcrtc->cursor_x = x;
 935         dcrtc->cursor_y = y;
 936         ret = armada_drm_crtc_cursor_update(dcrtc, false);
 937         mutex_unlock(&dev->struct_mutex);
 938
 939         return ret;
 940 }
 941
 942 static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
 943 {
 944         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 945         struct armada_private *priv = crtc->dev->dev_private;
 946
 947         if (dcrtc->cursor_obj)
 948                 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
 949
 950         priv->dcrtc[dcrtc->num] = NULL;
 951         drm_crtc_cleanup(&dcrtc->crtc);
 952
 953         if (!IS_ERR(dcrtc->clk))
 954                 clk_disable_unprepare(dcrtc->clk);
 955
 956         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
 957
 958         of_node_put(dcrtc->crtc.port);
 959
 960         kfree(dcrtc);
 961 }
 962
 963 /*
 964  * The mode_config lock is held here, to prevent races between this
 965  * and a mode_set.
 966  */
 967 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
 968         struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
 969 {
 970         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 971         struct armada_frame_work *work;
 972         unsigned i;
 973         int ret;
 974
 975         /* We don't support changing the pixel format */
 976         if (fb->pixel_format != crtc->primary->fb->pixel_format)
 977                 return -EINVAL;
 978
 979         work = kmalloc(sizeof(*work), GFP_KERNEL);
 980         if (!work)
 981                 return -ENOMEM;
 982
 983         work->event = event;
 984         work->old_fb = dcrtc->crtc.primary->fb;
 985
 986         i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
 987                                     dcrtc->interlaced);
 988         armada_reg_queue_end(work->regs, i);
 989
 990         /*
 991          * Ensure that we hold a reference on the new framebuffer.
 992          * This has to match the behaviour in mode_set.
 993          */
 994         drm_framebuffer_reference(fb);
 995
 996         ret = armada_drm_crtc_queue_frame_work(dcrtc, work);
 997         if (ret) {
 998                 /* Undo our reference above */
 999                 drm_framebuffer_unreference(fb);
1000                 kfree(work);
1001                 return ret;
1002         }
1003
1004         /*
1005          * Don't take a reference on the new framebuffer;
1006          * drm_mode_page_flip_ioctl() has already grabbed a reference and
1007          * will _not_ drop that reference on successful return from this
1008          * function.  Simply mark this new framebuffer as the current one.
1009          */
1010         dcrtc->crtc.primary->fb = fb;
1011
1012         /*
1013          * Finally, if the display is blanked, we won't receive an
1014          * interrupt, so complete it now.
1015          */
1016         if (dpms_blanked(dcrtc->dpms)) {
1017                 struct armada_frame_work *work = xchg(&dcrtc->frame_work, NULL);
1018
1019                 if (work)
1020                         armada_drm_crtc_complete_frame_work(dcrtc, work);
1021         }
1022
1023         return 0;
1024 }
1025
1026 static int
1027 armada_drm_crtc_set_property(struct drm_crtc *crtc,
1028         struct drm_property *property, uint64_t val)
1029 {
1030         struct armada_private *priv = crtc->dev->dev_private;
1031         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1032         bool update_csc = false;
1033
1034         if (property == priv->csc_yuv_prop) {
1035                 dcrtc->csc_yuv_mode = val;
1036                 update_csc = true;
1037         } else if (property == priv->csc_rgb_prop) {
1038                 dcrtc->csc_rgb_mode = val;
1039                 update_csc = true;
1040         }
1041
1042         if (update_csc) {
1043                 uint32_t val;
1044
1045                 val = dcrtc->spu_iopad_ctrl |
1046                       armada_drm_crtc_calculate_csc(dcrtc);
1047                 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1048         }
1049
1050         return 0;
1051 }
1052
1053 static struct drm_crtc_funcs armada_crtc_funcs = {
1054         .cursor_set     = armada_drm_crtc_cursor_set,
1055         .cursor_move    = armada_drm_crtc_cursor_move,
1056         .destroy        = armada_drm_crtc_destroy,
1057         .set_config     = drm_crtc_helper_set_config,
1058         .page_flip      = armada_drm_crtc_page_flip,
1059         .set_property   = armada_drm_crtc_set_property,
1060 };
1061
1062 static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
1063         { CSC_AUTO,        "Auto" },
1064         { CSC_YUV_CCIR601, "CCIR601" },
1065         { CSC_YUV_CCIR709, "CCIR709" },
1066 };
1067
1068 static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
1069         { CSC_AUTO,         "Auto" },
1070         { CSC_RGB_COMPUTER, "Computer system" },
1071         { CSC_RGB_STUDIO,   "Studio" },
1072 };
1073
1074 static int armada_drm_crtc_create_properties(struct drm_device *dev)
1075 {
1076         struct armada_private *priv = dev->dev_private;
1077
1078         if (priv->csc_yuv_prop)
1079                 return 0;
1080
1081         priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1082                                 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1083                                 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1084         priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1085                                 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1086                                 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1087
1088         if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1089                 return -ENOMEM;
1090
1091         return 0;
1092 }
1093
1094 static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
1095         struct resource *res, int irq, const struct armada_variant *variant,
1096         struct device_node *port)
1097 {
1098         struct armada_private *priv = drm->dev_private;
1099         struct armada_crtc *dcrtc;
1100         struct drm_plane *primary;
1101         void __iomem *base;
1102         int ret;
1103
1104         ret = armada_drm_crtc_create_properties(drm);
1105         if (ret)
1106                 return ret;
1107
1108         base = devm_ioremap_resource(dev, res);
1109         if (IS_ERR(base))
1110                 return PTR_ERR(base);
1111
1112         dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1113         if (!dcrtc) {
1114                 DRM_ERROR("failed to allocate Armada crtc\n");
1115                 return -ENOMEM;
1116         }
1117
1118         if (dev != drm->dev)
1119                 dev_set_drvdata(dev, dcrtc);
1120
1121         dcrtc->variant = variant;
1122         dcrtc->base = base;
1123         dcrtc->num = drm->mode_config.num_crtc;
1124         dcrtc->clk = ERR_PTR(-EINVAL);
1125         dcrtc->csc_yuv_mode = CSC_AUTO;
1126         dcrtc->csc_rgb_mode = CSC_AUTO;
1127         dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1128         dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1129         spin_lock_init(&dcrtc->irq_lock);
1130         dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1131         INIT_LIST_HEAD(&dcrtc->vbl_list);
1132         init_waitqueue_head(&dcrtc->frame_wait);
1133
1134         /* Initialize some registers which we don't otherwise set */
1135         writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1136         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1137         writel_relaxed(dcrtc->spu_iopad_ctrl,
1138                        dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1139         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1140         writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1141                        CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1142                        CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1143         writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
1144         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN);
1145         writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
1146         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
1147
1148         ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1149                                dcrtc);
1150         if (ret < 0) {
1151                 kfree(dcrtc);
1152                 return ret;
1153         }
1154
1155         if (dcrtc->variant->init) {
1156                 ret = dcrtc->variant->init(dcrtc, dev);
1157                 if (ret) {
1158                         kfree(dcrtc);
1159                         return ret;
1160                 }
1161         }
1162
1163         /* Ensure AXI pipeline is enabled */
1164         armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1165
1166         priv->dcrtc[dcrtc->num] = dcrtc;
1167
1168         dcrtc->crtc.port = port;
1169
1170         primary = drm_primary_helper_create_plane(drm, armada_primary_formats,
1171                                         ARRAY_SIZE(armada_primary_formats));
1172         if (!primary)
1173                 return -ENOMEM;
1174
1175         ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, primary, NULL,
1176                                         &armada_crtc_funcs);
1177         if (ret)
1178                 goto err_crtc_init;
1179
1180         drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1181
1182         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1183                                    dcrtc->csc_yuv_mode);
1184         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1185                                    dcrtc->csc_rgb_mode);
1186
1187         return armada_overlay_plane_create(drm, 1 << dcrtc->num);
1188
1189 err_crtc_init:
1190         primary->funcs->destroy(primary);
1191         return ret;
1192 }
1193
1194 static int
1195 armada_lcd_bind(struct device *dev, struct device *master, void *data)
1196 {
1197         struct platform_device *pdev = to_platform_device(dev);
1198         struct drm_device *drm = data;
1199         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1200         int irq = platform_get_irq(pdev, 0);
1201         const struct armada_variant *variant;
1202         struct device_node *port = NULL;
1203
1204         if (irq < 0)
1205                 return irq;
1206
1207         if (!dev->of_node) {
1208                 const struct platform_device_id *id;
1209
1210                 id = platform_get_device_id(pdev);
1211                 if (!id)
1212                         return -ENXIO;
1213
1214                 variant = (const struct armada_variant *)id->driver_data;
1215         } else {
1216                 const struct of_device_id *match;
1217                 struct device_node *np, *parent = dev->of_node;
1218
1219                 match = of_match_device(dev->driver->of_match_table, dev);
1220                 if (!match)
1221                         return -ENXIO;
1222
1223                 np = of_get_child_by_name(parent, "ports");
1224                 if (np)
1225                         parent = np;
1226                 port = of_get_child_by_name(parent, "port");
1227                 of_node_put(np);
1228                 if (!port) {
1229                         dev_err(dev, "no port node found in %s\n",
1230                                 parent->full_name);
1231                         return -ENXIO;
1232                 }
1233
1234                 variant = match->data;
1235         }
1236
1237         return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
1238 }
1239
1240 static void
1241 armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1242 {
1243         struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1244
1245         armada_drm_crtc_destroy(&dcrtc->crtc);
1246 }
1247
1248 static const struct component_ops armada_lcd_ops = {
1249         .bind = armada_lcd_bind,
1250         .unbind = armada_lcd_unbind,
1251 };
1252
1253 static int armada_lcd_probe(struct platform_device *pdev)
1254 {
1255         return component_add(&pdev->dev, &armada_lcd_ops);
1256 }
1257
1258 static int armada_lcd_remove(struct platform_device *pdev)
1259 {
1260         component_del(&pdev->dev, &armada_lcd_ops);
1261         return 0;
1262 }
1263
1264 static struct of_device_id armada_lcd_of_match[] = {
1265         {
1266                 .compatible     = "marvell,dove-lcd",
1267                 .data           = &armada510_ops,
1268         },
1269         {}
1270 };
1271 MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1272
1273 static const struct platform_device_id armada_lcd_platform_ids[] = {
1274         {
1275                 .name           = "armada-lcd",
1276                 .driver_data    = (unsigned long)&armada510_ops,
1277         }, {
1278                 .name           = "armada-510-lcd",
1279                 .driver_data    = (unsigned long)&armada510_ops,
1280         },
1281         { },
1282 };
1283 MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1284
1285 struct platform_driver armada_lcd_platform_driver = {
1286         .probe  = armada_lcd_probe,
1287         .remove = armada_lcd_remove,
1288         .driver = {
1289                 .name   = "armada-lcd",
1290                 .owner  =  THIS_MODULE,
1291                 .of_match_table = armada_lcd_of_match,
1292         },
1293         .id_table = armada_lcd_platform_ids,
1294 };