drivers/gpu/drm/armada/armada_crtc.c

   1 /*
   2  * Copyright (C) 2012 Russell King
   3  *  Rewritten from the dovefb driver, and Armada510 manuals.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9 #include <linux/clk.h>
  10 #include <drm/drmP.h>
  11 #include <drm/drm_crtc_helper.h>
  12 #include "armada_crtc.h"
  13 #include "armada_drm.h"
  14 #include "armada_fb.h"
  15 #include "armada_gem.h"
  16 #include "armada_hw.h"
  17
  18 struct armada_frame_work {
  19         struct drm_pending_vblank_event *event;
  20         struct armada_regs regs[4];
  21         struct drm_framebuffer *old_fb;
  22 };
  23
  24 enum csc_mode {
  25         CSC_AUTO = 0,
  26         CSC_YUV_CCIR601 = 1,
  27         CSC_YUV_CCIR709 = 2,
  28         CSC_RGB_COMPUTER = 1,
  29         CSC_RGB_STUDIO = 2,
  30 };
  31
  32 /*
  33  * A note about interlacing.  Let's consider HDMI 1920x1080i.
  34  * The timing parameters we have from X are:
  35  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  36  *  1920 2448 2492 2640  1080 1084 1094 1125
  37  * Which get translated to:
  38  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  39  *  1920 2448 2492 2640   540  542  547  562
  40  *
  41  * This is how it is defined by CEA-861-D - line and pixel numbers are
  42  * referenced to the rising edge of VSYNC and HSYNC.  Total clocks per
  43  * line: 2640.  The odd frame, the first active line is at line 21, and
  44  * the even frame, the first active line is 584.
  45  *
  46  * LN:    560     561     562     563             567     568    569
  47  * DE:    ~~~|____________________________//__________________________
  48  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  49  * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
  50  *  22 blanking lines.  VSYNC at 1320 (referenced to the HSYNC rising edge).
  51  *
  52  * LN:    1123   1124    1125      1               5       6      7
  53  * DE:    ~~~|____________________________//__________________________
  54  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  55  * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
  56  *  23 blanking lines
  57  *
  58  * The Armada LCD Controller line and pixel numbers are, like X timings,
  59  * referenced to the top left of the active frame.
  60  *
  61  * So, translating these to our LCD controller:
  62  *  Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
  63  *  Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
  64  * Note: Vsync front porch remains constant!
  65  *
  66  * if (odd_frame) {
  67  *   vtotal = mode->crtc_vtotal + 1;
  68  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
  69  *   vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
  70  * } else {
  71  *   vtotal = mode->crtc_vtotal;
  72  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
  73  *   vhorizpos = mode->crtc_hsync_start;
  74  * }
  75  * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
  76  *
  77  * So, we need to reprogram these registers on each vsync event:
  78  *  LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
  79  *
  80  * Note: we do not use the frame done interrupts because these appear
  81  * to happen too early, and lead to jitter on the display (presumably
  82  * they occur at the end of the last active line, before the vsync back
  83  * porch, which we're reprogramming.)
  84  */
  85
  86 void
  87 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
  88 {
  89         while (regs->offset != ~0) {
  90                 void __iomem *reg = dcrtc->base + regs->offset;
  91                 uint32_t val;
  92
  93                 val = regs->mask;
  94                 if (val != 0)
  95                         val &= readl_relaxed(reg);
  96                 writel_relaxed(val | regs->val, reg);
  97                 ++regs;
  98         }
  99 }
 100
 101 #define dpms_blanked(dpms)      ((dpms) != DRM_MODE_DPMS_ON)
 102
 103 static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
 104 {
 105         uint32_t dumb_ctrl;
 106
 107         dumb_ctrl = dcrtc->cfg_dumb_ctrl;
 108
 109         if (!dpms_blanked(dcrtc->dpms))
 110                 dumb_ctrl |= CFG_DUMB_ENA;
 111
 112         /*
 113          * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
 114          * be using SPI or GPIO.  If we set this to DUMB_BLANK, we will
 115          * force LCD_D[23:0] to output blank color, overriding the GPIO or
 116          * SPI usage.  So leave it as-is unless in DUMB24_RGB888_0 mode.
 117          */
 118         if (dpms_blanked(dcrtc->dpms) &&
 119             (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
 120                 dumb_ctrl &= ~DUMB_MASK;
 121                 dumb_ctrl |= DUMB_BLANK;
 122         }
 123
 124         /*
 125          * The documentation doesn't indicate what the normal state of
 126          * the sync signals are.  Sebastian Hesselbart kindly probed
 127          * these signals on his board to determine their state.
 128          *
 129          * The non-inverted state of the sync signals is active high.
 130          * Setting these bits makes the appropriate signal active low.
 131          */
 132         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
 133                 dumb_ctrl |= CFG_INV_CSYNC;
 134         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
 135                 dumb_ctrl |= CFG_INV_HSYNC;
 136         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
 137                 dumb_ctrl |= CFG_INV_VSYNC;
 138
 139         if (dcrtc->dumb_ctrl != dumb_ctrl) {
 140                 dcrtc->dumb_ctrl = dumb_ctrl;
 141                 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
 142         }
 143 }
 144
 145 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
 146         int x, int y, struct armada_regs *regs, bool interlaced)
 147 {
 148         struct armada_gem_object *obj = drm_fb_obj(fb);
 149         unsigned pitch = fb->pitches[0];
 150         unsigned offset = y * pitch + x * fb->bits_per_pixel / 8;
 151         uint32_t addr_odd, addr_even;
 152         unsigned i = 0;
 153
 154         DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
 155                 pitch, x, y, fb->bits_per_pixel);
 156
 157         addr_odd = addr_even = obj->dev_addr + offset;
 158
 159         if (interlaced) {
 160                 addr_even += pitch;
 161                 pitch *= 2;
 162         }
 163
 164         /* write offset, base, and pitch */
 165         armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
 166         armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
 167         armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
 168
 169         return i;
 170 }
 171
 172 static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc,
 173         struct armada_frame_work *work)
 174 {
 175         struct drm_device *dev = dcrtc->crtc.dev;
 176         unsigned long flags;
 177         int ret;
 178
 179         ret = drm_vblank_get(dev, dcrtc->num);
 180         if (ret) {
 181                 DRM_ERROR("failed to acquire vblank counter\n");
 182                 return ret;
 183         }
 184
 185         spin_lock_irqsave(&dev->event_lock, flags);
 186         if (!dcrtc->frame_work)
 187                 dcrtc->frame_work = work;
 188         else
 189                 ret = -EBUSY;
 190         spin_unlock_irqrestore(&dev->event_lock, flags);
 191
 192         if (ret)
 193                 drm_vblank_put(dev, dcrtc->num);
 194
 195         return ret;
 196 }
 197
 198 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc)
 199 {
 200         struct drm_device *dev = dcrtc->crtc.dev;
 201         struct armada_frame_work *work = dcrtc->frame_work;
 202
 203         dcrtc->frame_work = NULL;
 204
 205         armada_drm_crtc_update_regs(dcrtc, work->regs);
 206
 207         if (work->event)
 208                 drm_send_vblank_event(dev, dcrtc->num, work->event);
 209
 210         drm_vblank_put(dev, dcrtc->num);
 211
 212         /* Finally, queue the process-half of the cleanup. */
 213         __armada_drm_queue_unref_work(dcrtc->crtc.dev, work->old_fb);
 214         kfree(work);
 215 }
 216
 217 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
 218         struct drm_framebuffer *fb, bool force)
 219 {
 220         struct armada_frame_work *work;
 221
 222         if (!fb)
 223                 return;
 224
 225         if (force) {
 226                 /* Display is disabled, so just drop the old fb */
 227                 drm_framebuffer_unreference(fb);
 228                 return;
 229         }
 230
 231         work = kmalloc(sizeof(*work), GFP_KERNEL);
 232         if (work) {
 233                 int i = 0;
 234                 work->event = NULL;
 235                 work->old_fb = fb;
 236                 armada_reg_queue_end(work->regs, i);
 237
 238                 if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0)
 239                         return;
 240
 241                 kfree(work);
 242         }
 243
 244         /*
 245          * Oops - just drop the reference immediately and hope for
 246          * the best.  The worst that will happen is the buffer gets
 247          * reused before it has finished being displayed.
 248          */
 249         drm_framebuffer_unreference(fb);
 250 }
 251
 252 static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
 253 {
 254         struct drm_device *dev = dcrtc->crtc.dev;
 255
 256         /*
 257          * Tell the DRM core that vblank IRQs aren't going to happen for
 258          * a while.  This cleans up any pending vblank events for us.
 259          */
 260         drm_vblank_off(dev, dcrtc->num);
 261
 262         /* Handle any pending flip event. */
 263         spin_lock_irq(&dev->event_lock);
 264         if (dcrtc->frame_work)
 265                 armada_drm_crtc_complete_frame_work(dcrtc);
 266         spin_unlock_irq(&dev->event_lock);
 267 }
 268
 269 void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b,
 270         int idx)
 271 {
 272 }
 273
 274 void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 275         int idx)
 276 {
 277 }
 278
 279 /* The mode_config.mutex will be held for this call */
 280 static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
 281 {
 282         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 283
 284         if (dcrtc->dpms != dpms) {
 285                 dcrtc->dpms = dpms;
 286                 armada_drm_crtc_update(dcrtc);
 287                 if (dpms_blanked(dpms))
 288                         armada_drm_vblank_off(dcrtc);
 289         }
 290 }
 291
 292 /*
 293  * Prepare for a mode set.  Turn off overlay to ensure that we don't end
 294  * up with the overlay size being bigger than the active screen size.
 295  * We rely upon X refreshing this state after the mode set has completed.
 296  *
 297  * The mode_config.mutex will be held for this call
 298  */
 299 static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
 300 {
 301         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 302         struct drm_plane *plane;
 303
 304         /*
 305          * If we have an overlay plane associated with this CRTC, disable
 306          * it before the modeset to avoid its coordinates being outside
 307          * the new mode parameters.  DRM doesn't provide help with this.
 308          */
 309         plane = dcrtc->plane;
 310         if (plane) {
 311                 struct drm_framebuffer *fb = plane->fb;
 312
 313                 plane->funcs->disable_plane(plane);
 314                 plane->fb = NULL;
 315                 plane->crtc = NULL;
 316                 drm_framebuffer_unreference(fb);
 317         }
 318 }
 319
 320 /* The mode_config.mutex will be held for this call */
 321 static void armada_drm_crtc_commit(struct drm_crtc *crtc)
 322 {
 323         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 324
 325         if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
 326                 dcrtc->dpms = DRM_MODE_DPMS_ON;
 327                 armada_drm_crtc_update(dcrtc);
 328         }
 329 }
 330
 331 /* The mode_config.mutex will be held for this call */
 332 static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
 333         const struct drm_display_mode *mode, struct drm_display_mode *adj)
 334 {
 335         struct armada_private *priv = crtc->dev->dev_private;
 336         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 337         int ret;
 338
 339         /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
 340         if (!priv->variant->has_spu_adv_reg &&
 341             adj->flags & DRM_MODE_FLAG_INTERLACE)
 342                 return false;
 343
 344         /* Check whether the display mode is possible */
 345         ret = priv->variant->crtc_compute_clock(dcrtc, adj, NULL);
 346         if (ret)
 347                 return false;
 348
 349         return true;
 350 }
 351
 352 void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
 353 {
 354         struct armada_vbl_event *e, *n;
 355         void __iomem *base = dcrtc->base;
 356
 357         if (stat & DMA_FF_UNDERFLOW)
 358                 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
 359         if (stat & GRA_FF_UNDERFLOW)
 360                 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
 361
 362         if (stat & VSYNC_IRQ)
 363                 drm_handle_vblank(dcrtc->crtc.dev, dcrtc->num);
 364
 365         spin_lock(&dcrtc->irq_lock);
 366
 367         list_for_each_entry_safe(e, n, &dcrtc->vbl_list, node) {
 368                 list_del_init(&e->node);
 369                 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
 370                 e->fn(dcrtc, e->data);
 371         }
 372
 373         if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
 374                 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
 375                 uint32_t val;
 376
 377                 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
 378                 writel_relaxed(dcrtc->v[i].spu_v_h_total,
 379                                base + LCD_SPUT_V_H_TOTAL);
 380
 381                 val = readl_relaxed(base + LCD_SPU_ADV_REG);
 382                 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
 383                 val |= dcrtc->v[i].spu_adv_reg;
 384                 writel_relaxed(val, base + LCD_SPU_ADV_REG);
 385         }
 386
 387         if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
 388                 writel_relaxed(dcrtc->cursor_hw_pos,
 389                                base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 390                 writel_relaxed(dcrtc->cursor_hw_sz,
 391                                base + LCD_SPU_HWC_HPXL_VLN);
 392                 armada_updatel(CFG_HWC_ENA,
 393                                CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
 394                                base + LCD_SPU_DMA_CTRL0);
 395                 dcrtc->cursor_update = false;
 396                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 397         }
 398
 399         spin_unlock(&dcrtc->irq_lock);
 400
 401         if (stat & GRA_FRAME_IRQ) {
 402                 struct drm_device *dev = dcrtc->crtc.dev;
 403
 404                 spin_lock(&dev->event_lock);
 405                 if (dcrtc->frame_work)
 406                         armada_drm_crtc_complete_frame_work(dcrtc);
 407                 spin_unlock(&dev->event_lock);
 408
 409                 wake_up(&dcrtc->frame_wait);
 410         }
 411 }
 412
 413 /* These are locked by dev->vbl_lock */
 414 void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
 415 {
 416         if (dcrtc->irq_ena & mask) {
 417                 dcrtc->irq_ena &= ~mask;
 418                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 419         }
 420 }
 421
 422 void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
 423 {
 424         if ((dcrtc->irq_ena & mask) != mask) {
 425                 dcrtc->irq_ena |= mask;
 426                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 427                 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
 428                         writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 429         }
 430 }
 431
 432 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
 433 {
 434         struct drm_display_mode *adj = &dcrtc->crtc.mode;
 435         uint32_t val = 0;
 436
 437         if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
 438                 val |= CFG_CSC_YUV_CCIR709;
 439         if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
 440                 val |= CFG_CSC_RGB_STUDIO;
 441
 442         /*
 443          * In auto mode, set the colorimetry, based upon the HDMI spec.
 444          * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
 445          * ITU601.  It may be more appropriate to set this depending on
 446          * the source - but what if the graphic frame is YUV and the
 447          * video frame is RGB?
 448          */
 449         if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
 450              !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
 451             (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
 452                 if (dcrtc->csc_yuv_mode == CSC_AUTO)
 453                         val |= CFG_CSC_YUV_CCIR709;
 454         }
 455
 456         /*
 457          * We assume we're connected to a TV-like device, so the YUV->RGB
 458          * conversion should produce a limited range.  We should set this
 459          * depending on the connectors attached to this CRTC, and what
 460          * kind of device they report being connected.
 461          */
 462         if (dcrtc->csc_rgb_mode == CSC_AUTO)
 463                 val |= CFG_CSC_RGB_STUDIO;
 464
 465         return val;
 466 }
 467
 468 /* The mode_config.mutex will be held for this call */
 469 static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
 470         struct drm_display_mode *mode, struct drm_display_mode *adj,
 471         int x, int y, struct drm_framebuffer *old_fb)
 472 {
 473         struct armada_private *priv = crtc->dev->dev_private;
 474         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 475         struct armada_regs regs[17];
 476         uint32_t lm, rm, tm, bm, val, sclk;
 477         unsigned long flags;
 478         unsigned i;
 479         bool interlaced;
 480
 481         drm_framebuffer_reference(crtc->primary->fb);
 482
 483         interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
 484
 485         i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb,
 486                                     x, y, regs, interlaced);
 487
 488         rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
 489         lm = adj->crtc_htotal - adj->crtc_hsync_end;
 490         bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
 491         tm = adj->crtc_vtotal - adj->crtc_vsync_end;
 492
 493         DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
 494                 adj->crtc_hdisplay,
 495                 adj->crtc_hsync_start,
 496                 adj->crtc_hsync_end,
 497                 adj->crtc_htotal, lm, rm);
 498         DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
 499                 adj->crtc_vdisplay,
 500                 adj->crtc_vsync_start,
 501                 adj->crtc_vsync_end,
 502                 adj->crtc_vtotal, tm, bm);
 503
 504         /* Wait for pending flips to complete */
 505         wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
 506
 507         drm_vblank_pre_modeset(crtc->dev, dcrtc->num);
 508
 509         crtc->mode = *adj;
 510
 511         val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
 512         if (val != dcrtc->dumb_ctrl) {
 513                 dcrtc->dumb_ctrl = val;
 514                 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
 515         }
 516
 517         /* Now compute the divider for real */
 518         priv->variant->crtc_compute_clock(dcrtc, adj, &sclk);
 519
 520         /* Ensure graphic fifo is enabled */
 521         armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
 522         armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
 523
 524         if (interlaced ^ dcrtc->interlaced) {
 525                 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
 526                         drm_vblank_get(dcrtc->crtc.dev, dcrtc->num);
 527                 else
 528                         drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
 529                 dcrtc->interlaced = interlaced;
 530         }
 531
 532         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 533
 534         /* Even interlaced/progressive frame */
 535         dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
 536                                     adj->crtc_htotal;
 537         dcrtc->v[1].spu_v_porch = tm << 16 | bm;
 538         val = adj->crtc_hsync_start;
 539         dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 540                 priv->variant->spu_adv_reg;
 541
 542         if (interlaced) {
 543                 /* Odd interlaced frame */
 544                 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
 545                                                 (1 << 16);
 546                 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
 547                 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
 548                 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 549                         priv->variant->spu_adv_reg;
 550         } else {
 551                 dcrtc->v[0] = dcrtc->v[1];
 552         }
 553
 554         val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
 555
 556         armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
 557         armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN);
 558         armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN);
 559         armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
 560         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
 561         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
 562                            LCD_SPUT_V_H_TOTAL);
 563
 564         if (priv->variant->has_spu_adv_reg) {
 565                 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
 566                                      ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
 567                                      ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
 568         }
 569
 570         val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
 571         val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
 572         val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
 573
 574         if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
 575                 val |= CFG_PALETTE_ENA;
 576
 577         if (interlaced)
 578                 val |= CFG_GRA_FTOGGLE;
 579
 580         armada_reg_queue_mod(regs, i, val, CFG_GRAFORMAT |
 581                              CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
 582                                          CFG_SWAPYU | CFG_YUV2RGB) |
 583                              CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
 584                              LCD_SPU_DMA_CTRL0);
 585
 586         val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
 587         armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
 588
 589         val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
 590         armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
 591         armada_reg_queue_end(regs, i);
 592
 593         armada_drm_crtc_update_regs(dcrtc, regs);
 594         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 595
 596         armada_drm_crtc_update(dcrtc);
 597
 598         drm_vblank_post_modeset(crtc->dev, dcrtc->num);
 599         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 600
 601         return 0;
 602 }
 603
 604 /* The mode_config.mutex will be held for this call */
 605 static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 606         struct drm_framebuffer *old_fb)
 607 {
 608         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 609         struct armada_regs regs[4];
 610         unsigned i;
 611
 612         i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs,
 613                                     dcrtc->interlaced);
 614         armada_reg_queue_end(regs, i);
 615
 616         /* Wait for pending flips to complete */
 617         wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
 618
 619         /* Take a reference to the new fb as we're using it */
 620         drm_framebuffer_reference(crtc->primary->fb);
 621
 622         /* Update the base in the CRTC */
 623         armada_drm_crtc_update_regs(dcrtc, regs);
 624
 625         /* Drop our previously held reference */
 626         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 627
 628         return 0;
 629 }
 630
 631 static void armada_drm_crtc_load_lut(struct drm_crtc *crtc)
 632 {
 633 }
 634
 635 /* The mode_config.mutex will be held for this call */
 636 static void armada_drm_crtc_disable(struct drm_crtc *crtc)
 637 {
 638         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 639
 640         armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 641         armada_drm_crtc_finish_fb(dcrtc, crtc->primary->fb, true);
 642
 643         /* Power down most RAMs and FIFOs */
 644         writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
 645                        CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
 646                        CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
 647 }
 648
 649 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
 650         .dpms           = armada_drm_crtc_dpms,
 651         .prepare        = armada_drm_crtc_prepare,
 652         .commit         = armada_drm_crtc_commit,
 653         .mode_fixup     = armada_drm_crtc_mode_fixup,
 654         .mode_set       = armada_drm_crtc_mode_set,
 655         .mode_set_base  = armada_drm_crtc_mode_set_base,
 656         .load_lut       = armada_drm_crtc_load_lut,
 657         .disable        = armada_drm_crtc_disable,
 658 };
 659
 660 static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
 661         unsigned stride, unsigned width, unsigned height)
 662 {
 663         uint32_t addr;
 664         unsigned y;
 665
 666         addr = SRAM_HWC32_RAM1;
 667         for (y = 0; y < height; y++) {
 668                 uint32_t *p = &pix[y * stride];
 669                 unsigned x;
 670
 671                 for (x = 0; x < width; x++, p++) {
 672                         uint32_t val = *p;
 673
 674                         val = (val & 0xff00ff00) |
 675                               (val & 0x000000ff) << 16 |
 676                               (val & 0x00ff0000) >> 16;
 677
 678                         writel_relaxed(val,
 679                                        base + LCD_SPU_SRAM_WRDAT);
 680                         writel_relaxed(addr | SRAM_WRITE,
 681                                        base + LCD_SPU_SRAM_CTRL);
 682                         readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 683                         addr += 1;
 684                         if ((addr & 0x00ff) == 0)
 685                                 addr += 0xf00;
 686                         if ((addr & 0x30ff) == 0)
 687                                 addr = SRAM_HWC32_RAM2;
 688                 }
 689         }
 690 }
 691
 692 static void armada_drm_crtc_cursor_tran(void __iomem *base)
 693 {
 694         unsigned addr;
 695
 696         for (addr = 0; addr < 256; addr++) {
 697                 /* write the default value */
 698                 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
 699                 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
 700                                base + LCD_SPU_SRAM_CTRL);
 701         }
 702 }
 703
 704 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
 705 {
 706         uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
 707         uint32_t yoff, yscr, h = dcrtc->cursor_h;
 708         uint32_t para1;
 709
 710         /*
 711          * Calculate the visible width and height of the cursor,
 712          * screen position, and the position in the cursor bitmap.
 713          */
 714         if (dcrtc->cursor_x < 0) {
 715                 xoff = -dcrtc->cursor_x;
 716                 xscr = 0;
 717                 w -= min(xoff, w);
 718         } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
 719                 xoff = 0;
 720                 xscr = dcrtc->cursor_x;
 721                 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
 722         } else {
 723                 xoff = 0;
 724                 xscr = dcrtc->cursor_x;
 725         }
 726
 727         if (dcrtc->cursor_y < 0) {
 728                 yoff = -dcrtc->cursor_y;
 729                 yscr = 0;
 730                 h -= min(yoff, h);
 731         } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
 732                 yoff = 0;
 733                 yscr = dcrtc->cursor_y;
 734                 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
 735         } else {
 736                 yoff = 0;
 737                 yscr = dcrtc->cursor_y;
 738         }
 739
 740         /* On interlaced modes, the vertical cursor size must be halved */
 741         s = dcrtc->cursor_w;
 742         if (dcrtc->interlaced) {
 743                 s *= 2;
 744                 yscr /= 2;
 745                 h /= 2;
 746         }
 747
 748         if (!dcrtc->cursor_obj || !h || !w) {
 749                 spin_lock_irq(&dcrtc->irq_lock);
 750                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 751                 dcrtc->cursor_update = false;
 752                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 753                 spin_unlock_irq(&dcrtc->irq_lock);
 754                 return 0;
 755         }
 756
 757         para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
 758         armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
 759                        dcrtc->base + LCD_SPU_SRAM_PARA1);
 760
 761         /*
 762          * Initialize the transparency if the SRAM was powered down.
 763          * We must also reload the cursor data as well.
 764          */
 765         if (!(para1 & CFG_CSB_256x32)) {
 766                 armada_drm_crtc_cursor_tran(dcrtc->base);
 767                 reload = true;
 768         }
 769
 770         if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
 771                 spin_lock_irq(&dcrtc->irq_lock);
 772                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 773                 dcrtc->cursor_update = false;
 774                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 775                 spin_unlock_irq(&dcrtc->irq_lock);
 776                 reload = true;
 777         }
 778         if (reload) {
 779                 struct armada_gem_object *obj = dcrtc->cursor_obj;
 780                 uint32_t *pix;
 781                 /* Set the top-left corner of the cursor image */
 782                 pix = obj->addr;
 783                 pix += yoff * s + xoff;
 784                 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
 785         }
 786
 787         /* Reload the cursor position, size and enable in the IRQ handler */
 788         spin_lock_irq(&dcrtc->irq_lock);
 789         dcrtc->cursor_hw_pos = yscr << 16 | xscr;
 790         dcrtc->cursor_hw_sz = h << 16 | w;
 791         dcrtc->cursor_update = true;
 792         armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 793         spin_unlock_irq(&dcrtc->irq_lock);
 794
 795         return 0;
 796 }
 797
 798 static void cursor_update(void *data)
 799 {
 800         armada_drm_crtc_cursor_update(data, true);
 801 }
 802
 803 static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
 804         struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
 805 {
 806         struct drm_device *dev = crtc->dev;
 807         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 808         struct armada_private *priv = crtc->dev->dev_private;
 809         struct armada_gem_object *obj = NULL;
 810         int ret;
 811
 812         /* If no cursor support, replicate drm's return value */
 813         if (!priv->variant->has_spu_adv_reg)
 814                 return -ENXIO;
 815
 816         if (handle && w > 0 && h > 0) {
 817                 /* maximum size is 64x32 or 32x64 */
 818                 if (w > 64 || h > 64 || (w > 32 && h > 32))
 819                         return -ENOMEM;
 820
 821                 obj = armada_gem_object_lookup(dev, file, handle);
 822                 if (!obj)
 823                         return -ENOENT;
 824
 825                 /* Must be a kernel-mapped object */
 826                 if (!obj->addr) {
 827                         drm_gem_object_unreference_unlocked(&obj->obj);
 828                         return -EINVAL;
 829                 }
 830
 831                 if (obj->obj.size < w * h * 4) {
 832                         DRM_ERROR("buffer is too small\n");
 833                         drm_gem_object_unreference_unlocked(&obj->obj);
 834                         return -ENOMEM;
 835                 }
 836         }
 837
 838         mutex_lock(&dev->struct_mutex);
 839         if (dcrtc->cursor_obj) {
 840                 dcrtc->cursor_obj->update = NULL;
 841                 dcrtc->cursor_obj->update_data = NULL;
 842                 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
 843         }
 844         dcrtc->cursor_obj = obj;
 845         dcrtc->cursor_w = w;
 846         dcrtc->cursor_h = h;
 847         ret = armada_drm_crtc_cursor_update(dcrtc, true);
 848         if (obj) {
 849                 obj->update_data = dcrtc;
 850                 obj->update = cursor_update;
 851         }
 852         mutex_unlock(&dev->struct_mutex);
 853
 854         return ret;
 855 }
 856
 857 static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 858 {
 859         struct drm_device *dev = crtc->dev;
 860         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 861         struct armada_private *priv = crtc->dev->dev_private;
 862         int ret;
 863
 864         /* If no cursor support, replicate drm's return value */
 865         if (!priv->variant->has_spu_adv_reg)
 866                 return -EFAULT;
 867
 868         mutex_lock(&dev->struct_mutex);
 869         dcrtc->cursor_x = x;
 870         dcrtc->cursor_y = y;
 871         ret = armada_drm_crtc_cursor_update(dcrtc, false);
 872         mutex_unlock(&dev->struct_mutex);
 873
 874         return ret;
 875 }
 876
 877 static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
 878 {
 879         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 880         struct armada_private *priv = crtc->dev->dev_private;
 881
 882         if (dcrtc->cursor_obj)
 883                 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
 884
 885         priv->dcrtc[dcrtc->num] = NULL;
 886         drm_crtc_cleanup(&dcrtc->crtc);
 887
 888         if (!IS_ERR(dcrtc->clk))
 889                 clk_disable_unprepare(dcrtc->clk);
 890
 891         kfree(dcrtc);
 892 }
 893
 894 /*
 895  * The mode_config lock is held here, to prevent races between this
 896  * and a mode_set.
 897  */
 898 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
 899         struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
 900 {
 901         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 902         struct armada_frame_work *work;
 903         struct drm_device *dev = crtc->dev;
 904         unsigned long flags;
 905         unsigned i;
 906         int ret;
 907
 908         /* We don't support changing the pixel format */
 909         if (fb->pixel_format != crtc->primary->fb->pixel_format)
 910                 return -EINVAL;
 911
 912         work = kmalloc(sizeof(*work), GFP_KERNEL);
 913         if (!work)
 914                 return -ENOMEM;
 915
 916         work->event = event;
 917         work->old_fb = dcrtc->crtc.primary->fb;
 918
 919         i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
 920                                     dcrtc->interlaced);
 921         armada_reg_queue_end(work->regs, i);
 922
 923         /*
 924          * Hold the old framebuffer for the work - DRM appears to drop our
 925          * reference to the old framebuffer in drm_mode_page_flip_ioctl().
 926          */
 927         drm_framebuffer_reference(work->old_fb);
 928
 929         ret = armada_drm_crtc_queue_frame_work(dcrtc, work);
 930         if (ret) {
 931                 /*
 932                  * Undo our reference above; DRM does not drop the reference
 933                  * to this object on error, so that's okay.
 934                  */
 935                 drm_framebuffer_unreference(work->old_fb);
 936                 kfree(work);
 937                 return ret;
 938         }
 939
 940         /*
 941          * Don't take a reference on the new framebuffer;
 942          * drm_mode_page_flip_ioctl() has already grabbed a reference and
 943          * will _not_ drop that reference on successful return from this
 944          * function.  Simply mark this new framebuffer as the current one.
 945          */
 946         dcrtc->crtc.primary->fb = fb;
 947
 948         /*
 949          * Finally, if the display is blanked, we won't receive an
 950          * interrupt, so complete it now.
 951          */
 952         if (dpms_blanked(dcrtc->dpms)) {
 953                 spin_lock_irqsave(&dev->event_lock, flags);
 954                 if (dcrtc->frame_work)
 955                         armada_drm_crtc_complete_frame_work(dcrtc);
 956                 spin_unlock_irqrestore(&dev->event_lock, flags);
 957         }
 958
 959         return 0;
 960 }
 961
 962 static int
 963 armada_drm_crtc_set_property(struct drm_crtc *crtc,
 964         struct drm_property *property, uint64_t val)
 965 {
 966         struct armada_private *priv = crtc->dev->dev_private;
 967         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 968         bool update_csc = false;
 969
 970         if (property == priv->csc_yuv_prop) {
 971                 dcrtc->csc_yuv_mode = val;
 972                 update_csc = true;
 973         } else if (property == priv->csc_rgb_prop) {
 974                 dcrtc->csc_rgb_mode = val;
 975                 update_csc = true;
 976         }
 977
 978         if (update_csc) {
 979                 uint32_t val;
 980
 981                 val = dcrtc->spu_iopad_ctrl |
 982                       armada_drm_crtc_calculate_csc(dcrtc);
 983                 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
 984         }
 985
 986         return 0;
 987 }
 988
 989 static struct drm_crtc_funcs armada_crtc_funcs = {
 990         .cursor_set     = armada_drm_crtc_cursor_set,
 991         .cursor_move    = armada_drm_crtc_cursor_move,
 992         .destroy        = armada_drm_crtc_destroy,
 993         .set_config     = drm_crtc_helper_set_config,
 994         .page_flip      = armada_drm_crtc_page_flip,
 995         .set_property   = armada_drm_crtc_set_property,
 996 };
 997
 998 static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
 999         { CSC_AUTO,        "Auto" },
1000         { CSC_YUV_CCIR601, "CCIR601" },
1001         { CSC_YUV_CCIR709, "CCIR709" },
1002 };
1003
1004 static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
1005         { CSC_AUTO,         "Auto" },
1006         { CSC_RGB_COMPUTER, "Computer system" },
1007         { CSC_RGB_STUDIO,   "Studio" },
1008 };
1009
1010 static int armada_drm_crtc_create_properties(struct drm_device *dev)
1011 {
1012         struct armada_private *priv = dev->dev_private;
1013
1014         if (priv->csc_yuv_prop)
1015                 return 0;
1016
1017         priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1018                                 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1019                                 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1020         priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1021                                 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1022                                 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1023
1024         if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1025                 return -ENOMEM;
1026
1027         return 0;
1028 }
1029
1030 int armada_drm_crtc_create(struct drm_device *dev, unsigned num,
1031         struct resource *res)
1032 {
1033         struct armada_private *priv = dev->dev_private;
1034         struct armada_crtc *dcrtc;
1035         void __iomem *base;
1036         int ret;
1037
1038         ret = armada_drm_crtc_create_properties(dev);
1039         if (ret)
1040                 return ret;
1041
1042         base = devm_request_and_ioremap(dev->dev, res);
1043         if (!base) {
1044                 DRM_ERROR("failed to ioremap register\n");
1045                 return -ENOMEM;
1046         }
1047
1048         dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1049         if (!dcrtc) {
1050                 DRM_ERROR("failed to allocate Armada crtc\n");
1051                 return -ENOMEM;
1052         }
1053
1054         dcrtc->base = base;
1055         dcrtc->num = num;
1056         dcrtc->clk = ERR_PTR(-EINVAL);
1057         dcrtc->csc_yuv_mode = CSC_AUTO;
1058         dcrtc->csc_rgb_mode = CSC_AUTO;
1059         dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1060         dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1061         spin_lock_init(&dcrtc->irq_lock);
1062         dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1063         INIT_LIST_HEAD(&dcrtc->vbl_list);
1064         init_waitqueue_head(&dcrtc->frame_wait);
1065
1066         /* Initialize some registers which we don't otherwise set */
1067         writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1068         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1069         writel_relaxed(dcrtc->spu_iopad_ctrl,
1070                        dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1071         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1072         writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1073                        CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1074                        CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1075         writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
1076         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN);
1077
1078         if (priv->variant->crtc_init) {
1079                 ret = priv->variant->crtc_init(dcrtc);
1080                 if (ret) {
1081                         kfree(dcrtc);
1082                         return ret;
1083                 }
1084         }
1085
1086         /* Ensure AXI pipeline is enabled */
1087         armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1088
1089         priv->dcrtc[dcrtc->num] = dcrtc;
1090
1091         drm_crtc_init(dev, &dcrtc->crtc, &armada_crtc_funcs);
1092         drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1093
1094         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1095                                    dcrtc->csc_yuv_mode);
1096         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1097                                    dcrtc->csc_rgb_mode);
1098
1099         return armada_overlay_plane_create(dev, 1 << dcrtc->num);
1100 }