2 * Copyright (C) 2014 Traphandler
3 * Copyright (C) 2014 Free Electrons
4 * Copyright (C) 2014 Atmel
6 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
7 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef DRM_ATMEL_HLCDC_H
23 #define DRM_ATMEL_HLCDC_H
25 #include <linux/clk.h>
26 #include <linux/dmapool.h>
27 #include <linux/irqdomain.h>
28 #include <linux/mfd/atmel-hlcdc.h>
29 #include <linux/pwm.h>
31 #include <drm/drm_atomic.h>
32 #include <drm/drm_atomic_helper.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_cma_helper.h>
36 #include <drm/drm_gem_cma_helper.h>
37 #include <drm/drm_panel.h>
38 #include <drm/drm_plane_helper.h>
41 #define ATMEL_HLCDC_LAYER_CHER 0x0
42 #define ATMEL_HLCDC_LAYER_CHDR 0x4
43 #define ATMEL_HLCDC_LAYER_CHSR 0x8
44 #define ATMEL_HLCDC_LAYER_EN BIT(0)
45 #define ATMEL_HLCDC_LAYER_UPDATE BIT(1)
46 #define ATMEL_HLCDC_LAYER_A2Q BIT(2)
47 #define ATMEL_HLCDC_LAYER_RST BIT(8)
49 #define ATMEL_HLCDC_LAYER_IER 0xc
50 #define ATMEL_HLCDC_LAYER_IDR 0x10
51 #define ATMEL_HLCDC_LAYER_IMR 0x14
52 #define ATMEL_HLCDC_LAYER_ISR 0x18
53 #define ATMEL_HLCDC_LAYER_DFETCH BIT(0)
54 #define ATMEL_HLCDC_LAYER_LFETCH BIT(1)
55 #define ATMEL_HLCDC_LAYER_DMA_IRQ(p) BIT(2 + (8 * (p)))
56 #define ATMEL_HLCDC_LAYER_DSCR_IRQ(p) BIT(3 + (8 * (p)))
57 #define ATMEL_HLCDC_LAYER_ADD_IRQ(p) BIT(4 + (8 * (p)))
58 #define ATMEL_HLCDC_LAYER_DONE_IRQ(p) BIT(5 + (8 * (p)))
59 #define ATMEL_HLCDC_LAYER_OVR_IRQ(p) BIT(6 + (8 * (p)))
61 #define ATMEL_HLCDC_LAYER_PLANE_HEAD(p) (((p) * 0x10) + 0x1c)
62 #define ATMEL_HLCDC_LAYER_PLANE_ADDR(p) (((p) * 0x10) + 0x20)
63 #define ATMEL_HLCDC_LAYER_PLANE_CTRL(p) (((p) * 0x10) + 0x24)
64 #define ATMEL_HLCDC_LAYER_PLANE_NEXT(p) (((p) * 0x10) + 0x28)
66 #define ATMEL_HLCDC_LAYER_DMA_CFG 0
67 #define ATMEL_HLCDC_LAYER_DMA_SIF BIT(0)
68 #define ATMEL_HLCDC_LAYER_DMA_BLEN_MASK GENMASK(5, 4)
69 #define ATMEL_HLCDC_LAYER_DMA_BLEN_SINGLE (0 << 4)
70 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR4 (1 << 4)
71 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR8 (2 << 4)
72 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 (3 << 4)
73 #define ATMEL_HLCDC_LAYER_DMA_DLBO BIT(8)
74 #define ATMEL_HLCDC_LAYER_DMA_ROTDIS BIT(12)
75 #define ATMEL_HLCDC_LAYER_DMA_LOCKDIS BIT(13)
77 #define ATMEL_HLCDC_LAYER_FORMAT_CFG 1
78 #define ATMEL_HLCDC_LAYER_RGB (0 << 0)
79 #define ATMEL_HLCDC_LAYER_CLUT (1 << 0)
80 #define ATMEL_HLCDC_LAYER_YUV (2 << 0)
81 #define ATMEL_HLCDC_RGB_MODE(m) \
82 (ATMEL_HLCDC_LAYER_RGB | (((m) & 0xf) << 4))
83 #define ATMEL_HLCDC_CLUT_MODE(m) \
84 (ATMEL_HLCDC_LAYER_CLUT | (((m) & 0x3) << 8))
85 #define ATMEL_HLCDC_YUV_MODE(m) \
86 (ATMEL_HLCDC_LAYER_YUV | (((m) & 0xf) << 12))
87 #define ATMEL_HLCDC_YUV422ROT BIT(16)
88 #define ATMEL_HLCDC_YUV422SWP BIT(17)
89 #define ATMEL_HLCDC_DSCALEOPT BIT(20)
91 #define ATMEL_HLCDC_XRGB4444_MODE ATMEL_HLCDC_RGB_MODE(0)
92 #define ATMEL_HLCDC_ARGB4444_MODE ATMEL_HLCDC_RGB_MODE(1)
93 #define ATMEL_HLCDC_RGBA4444_MODE ATMEL_HLCDC_RGB_MODE(2)
94 #define ATMEL_HLCDC_RGB565_MODE ATMEL_HLCDC_RGB_MODE(3)
95 #define ATMEL_HLCDC_ARGB1555_MODE ATMEL_HLCDC_RGB_MODE(4)
96 #define ATMEL_HLCDC_XRGB8888_MODE ATMEL_HLCDC_RGB_MODE(9)
97 #define ATMEL_HLCDC_RGB888_MODE ATMEL_HLCDC_RGB_MODE(10)
98 #define ATMEL_HLCDC_ARGB8888_MODE ATMEL_HLCDC_RGB_MODE(12)
99 #define ATMEL_HLCDC_RGBA8888_MODE ATMEL_HLCDC_RGB_MODE(13)
101 #define ATMEL_HLCDC_AYUV_MODE ATMEL_HLCDC_YUV_MODE(0)
102 #define ATMEL_HLCDC_YUYV_MODE ATMEL_HLCDC_YUV_MODE(1)
103 #define ATMEL_HLCDC_UYVY_MODE ATMEL_HLCDC_YUV_MODE(2)
104 #define ATMEL_HLCDC_YVYU_MODE ATMEL_HLCDC_YUV_MODE(3)
105 #define ATMEL_HLCDC_VYUY_MODE ATMEL_HLCDC_YUV_MODE(4)
106 #define ATMEL_HLCDC_NV61_MODE ATMEL_HLCDC_YUV_MODE(5)
107 #define ATMEL_HLCDC_YUV422_MODE ATMEL_HLCDC_YUV_MODE(6)
108 #define ATMEL_HLCDC_NV21_MODE ATMEL_HLCDC_YUV_MODE(7)
109 #define ATMEL_HLCDC_YUV420_MODE ATMEL_HLCDC_YUV_MODE(8)
111 #define ATMEL_HLCDC_LAYER_POS(x, y) ((x) | ((y) << 16))
112 #define ATMEL_HLCDC_LAYER_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16))
114 #define ATMEL_HLCDC_LAYER_CRKEY BIT(0)
115 #define ATMEL_HLCDC_LAYER_INV BIT(1)
116 #define ATMEL_HLCDC_LAYER_ITER2BL BIT(2)
117 #define ATMEL_HLCDC_LAYER_ITER BIT(3)
118 #define ATMEL_HLCDC_LAYER_REVALPHA BIT(4)
119 #define ATMEL_HLCDC_LAYER_GAEN BIT(5)
120 #define ATMEL_HLCDC_LAYER_LAEN BIT(6)
121 #define ATMEL_HLCDC_LAYER_OVR BIT(7)
122 #define ATMEL_HLCDC_LAYER_DMA BIT(8)
123 #define ATMEL_HLCDC_LAYER_REP BIT(9)
124 #define ATMEL_HLCDC_LAYER_DSTKEY BIT(10)
125 #define ATMEL_HLCDC_LAYER_DISCEN BIT(11)
126 #define ATMEL_HLCDC_LAYER_GA_SHIFT 16
127 #define ATMEL_HLCDC_LAYER_GA_MASK \
128 GENMASK(23, ATMEL_HLCDC_LAYER_GA_SHIFT)
129 #define ATMEL_HLCDC_LAYER_GA(x) \
130 ((x) << ATMEL_HLCDC_LAYER_GA_SHIFT)
132 #define ATMEL_HLCDC_LAYER_DISC_POS(x, y) ((x) | ((y) << 16))
133 #define ATMEL_HLCDC_LAYER_DISC_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16))
135 #define ATMEL_HLCDC_LAYER_SCALER_FACTORS(x, y) ((x) | ((y) << 16))
136 #define ATMEL_HLCDC_LAYER_SCALER_ENABLE BIT(31)
138 #define ATMEL_HLCDC_LAYER_MAX_PLANES 3
140 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED BIT(0)
141 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED BIT(1)
142 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE BIT(2)
143 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN BIT(3)
145 #define ATMEL_HLCDC_MAX_LAYERS 6
148 * Atmel HLCDC Layer registers layout structure
150 * Each HLCDC layer has its own register organization and a given register
151 * can be placed differently on 2 different layers depending on its
153 * This structure stores common registers layout for a given layer and is
154 * used by HLCDC layer code to choose the appropriate register to write to
157 * For all fields, a value of zero means "unsupported".
159 * See Atmel's datasheet for a detailled description of these registers.
161 * @xstride: xstride registers
162 * @pstride: pstride registers
163 * @pos: position register
164 * @size: displayed size register
165 * @memsize: memory size register
166 * @default_color: default color register
167 * @chroma_key: chroma key register
168 * @chroma_key_mask: chroma key mask register
169 * @general_config: general layer config register
170 * @sacler_config: scaler factors register
171 * @phicoeffs: X/Y PHI coefficient registers
172 * @disc_pos: discard area position register
173 * @disc_size: discard area size register
174 * @csc: color space conversion register
176 struct atmel_hlcdc_layer_cfg_layout {
177 int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
178 int pstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
197 * Atmel HLCDC DMA descriptor structure
199 * This structure is used by the HLCDC DMA engine to schedule a DMA transfer.
201 * The structure fields must remain in this specific order, because they're
202 * used by the HLCDC DMA engine, which expect them in this order.
203 * HLCDC DMA descriptors must be aligned on 64 bits.
205 * @addr: buffer DMA address
206 * @ctrl: DMA transfer options
207 * @next: next DMA descriptor to fetch
208 * @self: descriptor DMA address
210 struct atmel_hlcdc_dma_channel_dscr {
215 } __aligned(sizeof(u64));
218 * Atmel HLCDC layer types
220 enum atmel_hlcdc_layer_type {
221 ATMEL_HLCDC_NO_LAYER,
222 ATMEL_HLCDC_BASE_LAYER,
223 ATMEL_HLCDC_OVERLAY_LAYER,
224 ATMEL_HLCDC_CURSOR_LAYER,
225 ATMEL_HLCDC_PP_LAYER,
229 * Atmel HLCDC Supported formats structure
231 * This structure list all the formats supported by a given layer.
233 * @nformats: number of supported formats
234 * @formats: supported formats
236 struct atmel_hlcdc_formats {
242 * Atmel HLCDC Layer description structure
244 * This structure describes the capabilities provided by a given layer.
249 * @regs_offset: offset of the layer registers from the HLCDC registers base
250 * @cfgs_offset: CFGX registers offset from the layer registers base
251 * @formats: supported formats
252 * @layout: config registers layout
253 * @max_width: maximum width supported by this layer (0 means unlimited)
254 * @max_height: maximum height supported by this layer (0 means unlimited)
256 struct atmel_hlcdc_layer_desc {
258 enum atmel_hlcdc_layer_type type;
262 struct atmel_hlcdc_formats *formats;
263 struct atmel_hlcdc_layer_cfg_layout layout;
271 * A layer can be a DRM plane of a post processing layer used to render
272 * HLCDC composition into memory.
274 * @desc: layer description
275 * @regmap: pointer to the HLCDC regmap
277 struct atmel_hlcdc_layer {
278 const struct atmel_hlcdc_layer_desc *desc;
279 struct regmap *regmap;
285 * @base: base DRM plane structure
286 * @layer: HLCDC layer structure
287 * @properties: pointer to the property definitions structure
289 struct atmel_hlcdc_plane {
290 struct drm_plane base;
291 struct atmel_hlcdc_layer layer;
292 struct atmel_hlcdc_plane_properties *properties;
295 static inline struct atmel_hlcdc_plane *
296 drm_plane_to_atmel_hlcdc_plane(struct drm_plane *p)
298 return container_of(p, struct atmel_hlcdc_plane, base);
301 static inline struct atmel_hlcdc_plane *
302 atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer)
304 return container_of(layer, struct atmel_hlcdc_plane, layer);
308 * Atmel HLCDC Display Controller description structure.
310 * This structure describes the HLCDC IP capabilities and depends on the
311 * HLCDC IP version (or Atmel SoC family).
313 * @min_width: minimum width supported by the Display Controller
314 * @min_height: minimum height supported by the Display Controller
315 * @max_width: maximum width supported by the Display Controller
316 * @max_height: maximum height supported by the Display Controller
317 * @max_spw: maximum vertical/horizontal pulse width
318 * @max_vpw: maximum vertical back/front porch width
319 * @max_hpw: maximum horizontal back/front porch width
320 * @conflicting_output_formats: true if RGBXXX output formats conflict with
322 * @layers: a layer description table describing available layers
323 * @nlayers: layer description table size
325 struct atmel_hlcdc_dc_desc {
333 bool conflicting_output_formats;
334 const struct atmel_hlcdc_layer_desc *layers;
339 * Atmel HLCDC Plane properties.
341 * This structure stores plane property definitions.
343 * @alpha: alpha blending (or transparency) property
344 * @rotation: rotation property
346 struct atmel_hlcdc_plane_properties {
347 struct drm_property *alpha;
351 * Atmel HLCDC Display Controller.
353 * @desc: HLCDC Display Controller description
354 * @dscrpool: DMA coherent pool used to allocate DMA descriptors
355 * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
356 * @fbdev: framebuffer device attached to the Display Controller
357 * @crtc: CRTC provided by the display controller
358 * @planes: instantiated planes
359 * @layers: active HLCDC layers
360 * @wq: display controller workqueue
361 * @suspend: used to store the HLCDC state when entering suspend
362 * @commit: used for async commit handling
364 struct atmel_hlcdc_dc {
365 const struct atmel_hlcdc_dc_desc *desc;
366 struct dma_pool *dscrpool;
367 struct atmel_hlcdc *hlcdc;
368 struct drm_fbdev_cma *fbdev;
369 struct drm_crtc *crtc;
370 struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS];
371 struct workqueue_struct *wq;
374 struct drm_atomic_state *state;
377 wait_queue_head_t wait;
382 extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats;
383 extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats;
385 static inline void atmel_hlcdc_layer_write_reg(struct atmel_hlcdc_layer *layer,
386 unsigned int reg, u32 val)
388 regmap_write(layer->regmap, layer->desc->regs_offset + reg, val);
391 static inline u32 atmel_hlcdc_layer_read_reg(struct atmel_hlcdc_layer *layer,
396 regmap_read(layer->regmap, layer->desc->regs_offset + reg, &val);
401 static inline void atmel_hlcdc_layer_write_cfg(struct atmel_hlcdc_layer *layer,
402 unsigned int cfgid, u32 val)
404 atmel_hlcdc_layer_write_reg(layer,
405 layer->desc->cfgs_offset +
406 (cfgid * sizeof(u32)), val);
409 static inline u32 atmel_hlcdc_layer_read_cfg(struct atmel_hlcdc_layer *layer,
412 return atmel_hlcdc_layer_read_reg(layer,
413 layer->desc->cfgs_offset +
414 (cfgid * sizeof(u32)));
417 static inline void atmel_hlcdc_layer_init(struct atmel_hlcdc_layer *layer,
418 const struct atmel_hlcdc_layer_desc *desc,
419 struct regmap *regmap)
422 layer->regmap = regmap;
425 int atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
426 struct drm_display_mode *mode);
428 int atmel_hlcdc_create_planes(struct drm_device *dev);
429 void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane);
431 int atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state);
432 int atmel_hlcdc_plane_prepare_ahb_routing(struct drm_crtc_state *c_state);
434 void atmel_hlcdc_crtc_irq(struct drm_crtc *c);
436 int atmel_hlcdc_crtc_create(struct drm_device *dev);
438 int atmel_hlcdc_create_outputs(struct drm_device *dev);
440 #endif /* DRM_ATMEL_HLCDC_H */