2 * Copyright (C) 2014 Free Electrons
3 * Copyright (C) 2014 Atmel
5 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "atmel_hlcdc_dc.h"
23 * Atmel HLCDC Plane state structure.
25 * @base: DRM plane state
26 * @crtc_x: x position of the plane relative to the CRTC
27 * @crtc_y: y position of the plane relative to the CRTC
28 * @crtc_w: visible width of the plane
29 * @crtc_h: visible height of the plane
30 * @src_x: x buffer position
31 * @src_y: y buffer position
32 * @src_w: buffer width
33 * @src_h: buffer height
34 * @alpha: alpha blending of the plane
35 * @disc_x: x discard position
36 * @disc_y: y discard position
37 * @disc_w: discard width
38 * @disc_h: discard height
39 * @bpp: bytes per pixel deduced from pixel_format
40 * @offsets: offsets to apply to the GEM buffers
41 * @xstride: value to add to the pixel pointer between each line
42 * @pstride: value to add to the pixel pointer between each pixel
43 * @nplanes: number of planes (deduced from pixel_format)
44 * @dscrs: DMA descriptors
46 struct atmel_hlcdc_plane_state {
47 struct drm_plane_state base;
66 /* These fields are private and should not be touched */
67 int bpp[ATMEL_HLCDC_LAYER_MAX_PLANES];
68 unsigned int offsets[ATMEL_HLCDC_LAYER_MAX_PLANES];
69 int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
70 int pstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
73 /* DMA descriptors. */
74 struct atmel_hlcdc_dma_channel_dscr *dscrs[ATMEL_HLCDC_LAYER_MAX_PLANES];
77 static inline struct atmel_hlcdc_plane_state *
78 drm_plane_state_to_atmel_hlcdc_plane_state(struct drm_plane_state *s)
80 return container_of(s, struct atmel_hlcdc_plane_state, base);
83 #define SUBPIXEL_MASK 0xffff
85 static uint32_t rgb_formats[] = {
97 struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats = {
98 .formats = rgb_formats,
99 .nformats = ARRAY_SIZE(rgb_formats),
102 static uint32_t rgb_and_yuv_formats[] = {
123 struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats = {
124 .formats = rgb_and_yuv_formats,
125 .nformats = ARRAY_SIZE(rgb_and_yuv_formats),
128 static int atmel_hlcdc_format_to_plane_mode(u32 format, u32 *mode)
131 case DRM_FORMAT_XRGB4444:
132 *mode = ATMEL_HLCDC_XRGB4444_MODE;
134 case DRM_FORMAT_ARGB4444:
135 *mode = ATMEL_HLCDC_ARGB4444_MODE;
137 case DRM_FORMAT_RGBA4444:
138 *mode = ATMEL_HLCDC_RGBA4444_MODE;
140 case DRM_FORMAT_RGB565:
141 *mode = ATMEL_HLCDC_RGB565_MODE;
143 case DRM_FORMAT_RGB888:
144 *mode = ATMEL_HLCDC_RGB888_MODE;
146 case DRM_FORMAT_ARGB1555:
147 *mode = ATMEL_HLCDC_ARGB1555_MODE;
149 case DRM_FORMAT_XRGB8888:
150 *mode = ATMEL_HLCDC_XRGB8888_MODE;
152 case DRM_FORMAT_ARGB8888:
153 *mode = ATMEL_HLCDC_ARGB8888_MODE;
155 case DRM_FORMAT_RGBA8888:
156 *mode = ATMEL_HLCDC_RGBA8888_MODE;
158 case DRM_FORMAT_AYUV:
159 *mode = ATMEL_HLCDC_AYUV_MODE;
161 case DRM_FORMAT_YUYV:
162 *mode = ATMEL_HLCDC_YUYV_MODE;
164 case DRM_FORMAT_UYVY:
165 *mode = ATMEL_HLCDC_UYVY_MODE;
167 case DRM_FORMAT_YVYU:
168 *mode = ATMEL_HLCDC_YVYU_MODE;
170 case DRM_FORMAT_VYUY:
171 *mode = ATMEL_HLCDC_VYUY_MODE;
173 case DRM_FORMAT_NV21:
174 *mode = ATMEL_HLCDC_NV21_MODE;
176 case DRM_FORMAT_NV61:
177 *mode = ATMEL_HLCDC_NV61_MODE;
179 case DRM_FORMAT_YUV420:
180 *mode = ATMEL_HLCDC_YUV420_MODE;
182 case DRM_FORMAT_YUV422:
183 *mode = ATMEL_HLCDC_YUV422_MODE;
192 static bool atmel_hlcdc_format_embeds_alpha(u32 format)
196 for (i = 0; i < sizeof(format); i++) {
197 char tmp = (format >> (8 * i)) & 0xff;
206 static u32 heo_downscaling_xcoef[] = {
225 static u32 heo_downscaling_ycoef[] = {
236 static u32 heo_upscaling_xcoef[] = {
255 static u32 heo_upscaling_ycoef[] = {
266 #define ATMEL_HLCDC_XPHIDEF 4
267 #define ATMEL_HLCDC_YPHIDEF 4
269 static u32 atmel_hlcdc_plane_phiscaler_get_factor(u32 srcsize,
273 u32 factor, max_memsize;
275 factor = (256 * ((8 * (srcsize - 1)) - phidef)) / (dstsize - 1);
276 max_memsize = ((factor * (dstsize - 1)) + (256 * phidef)) / 2048;
278 if (max_memsize > srcsize - 1)
285 atmel_hlcdc_plane_scaler_set_phicoeff(struct atmel_hlcdc_plane *plane,
286 const u32 *coeff_tab, int size,
287 unsigned int cfg_offs)
291 for (i = 0; i < size; i++)
292 atmel_hlcdc_layer_write_cfg(&plane->layer, cfg_offs + i,
296 void atmel_hlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane,
297 struct atmel_hlcdc_plane_state *state)
299 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
300 u32 xfactor, yfactor;
302 if (!desc->layout.scaler_config)
305 if (state->crtc_w == state->src_w && state->crtc_h == state->src_h) {
306 atmel_hlcdc_layer_write_cfg(&plane->layer,
307 desc->layout.scaler_config, 0);
311 if (desc->layout.phicoeffs.x) {
312 xfactor = atmel_hlcdc_plane_phiscaler_get_factor(state->src_w,
314 ATMEL_HLCDC_XPHIDEF);
316 yfactor = atmel_hlcdc_plane_phiscaler_get_factor(state->src_h,
318 ATMEL_HLCDC_YPHIDEF);
320 atmel_hlcdc_plane_scaler_set_phicoeff(plane,
321 state->crtc_w < state->src_w ?
322 heo_downscaling_xcoef :
324 ARRAY_SIZE(heo_upscaling_xcoef),
325 desc->layout.phicoeffs.x);
327 atmel_hlcdc_plane_scaler_set_phicoeff(plane,
328 state->crtc_h < state->src_h ?
329 heo_downscaling_ycoef :
331 ARRAY_SIZE(heo_upscaling_ycoef),
332 desc->layout.phicoeffs.y);
334 xfactor = (1024 * state->src_w) / state->crtc_w;
335 yfactor = (1024 * state->src_h) / state->crtc_h;
338 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config,
339 ATMEL_HLCDC_LAYER_SCALER_ENABLE |
340 ATMEL_HLCDC_LAYER_SCALER_FACTORS(xfactor,
345 atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane,
346 struct atmel_hlcdc_plane_state *state)
348 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
350 if (desc->layout.size)
351 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.size,
352 ATMEL_HLCDC_LAYER_SIZE(state->crtc_w,
355 if (desc->layout.memsize)
356 atmel_hlcdc_layer_write_cfg(&plane->layer,
357 desc->layout.memsize,
358 ATMEL_HLCDC_LAYER_SIZE(state->src_w,
361 if (desc->layout.pos)
362 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.pos,
363 ATMEL_HLCDC_LAYER_POS(state->crtc_x,
366 atmel_hlcdc_plane_setup_scaler(plane, state);
370 atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane,
371 struct atmel_hlcdc_plane_state *state)
373 unsigned int cfg = ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 | state->ahb_id;
374 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
375 u32 format = state->base.fb->format->format;
378 * Rotation optimization is not working on RGB888 (rotation is still
379 * working but without any optimization).
381 if (format == DRM_FORMAT_RGB888)
382 cfg |= ATMEL_HLCDC_LAYER_DMA_ROTDIS;
384 atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_HLCDC_LAYER_DMA_CFG,
387 cfg = ATMEL_HLCDC_LAYER_DMA;
389 if (plane->base.type != DRM_PLANE_TYPE_PRIMARY) {
390 cfg |= ATMEL_HLCDC_LAYER_OVR | ATMEL_HLCDC_LAYER_ITER2BL |
391 ATMEL_HLCDC_LAYER_ITER;
393 if (atmel_hlcdc_format_embeds_alpha(format))
394 cfg |= ATMEL_HLCDC_LAYER_LAEN;
396 cfg |= ATMEL_HLCDC_LAYER_GAEN |
397 ATMEL_HLCDC_LAYER_GA(state->alpha);
400 if (state->disc_h && state->disc_w)
401 cfg |= ATMEL_HLCDC_LAYER_DISCEN;
403 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.general_config,
407 static void atmel_hlcdc_plane_update_format(struct atmel_hlcdc_plane *plane,
408 struct atmel_hlcdc_plane_state *state)
413 ret = atmel_hlcdc_format_to_plane_mode(state->base.fb->format->format,
418 if ((state->base.fb->format->format == DRM_FORMAT_YUV422 ||
419 state->base.fb->format->format == DRM_FORMAT_NV61) &&
420 drm_rotation_90_or_270(state->base.rotation))
421 cfg |= ATMEL_HLCDC_YUV422ROT;
423 atmel_hlcdc_layer_write_cfg(&plane->layer,
424 ATMEL_HLCDC_LAYER_FORMAT_CFG, cfg);
427 static void atmel_hlcdc_plane_update_buffers(struct atmel_hlcdc_plane *plane,
428 struct atmel_hlcdc_plane_state *state)
430 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
431 struct drm_framebuffer *fb = state->base.fb;
435 sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR);
437 for (i = 0; i < state->nplanes; i++) {
438 struct drm_gem_cma_object *gem = drm_fb_cma_get_gem_obj(fb, i);
440 state->dscrs[i]->addr = gem->paddr + state->offsets[i];
442 atmel_hlcdc_layer_write_reg(&plane->layer,
443 ATMEL_HLCDC_LAYER_PLANE_HEAD(i),
444 state->dscrs[i]->self);
446 if (!(sr & ATMEL_HLCDC_LAYER_EN)) {
447 atmel_hlcdc_layer_write_reg(&plane->layer,
448 ATMEL_HLCDC_LAYER_PLANE_ADDR(i),
449 state->dscrs[i]->addr);
450 atmel_hlcdc_layer_write_reg(&plane->layer,
451 ATMEL_HLCDC_LAYER_PLANE_CTRL(i),
452 state->dscrs[i]->ctrl);
453 atmel_hlcdc_layer_write_reg(&plane->layer,
454 ATMEL_HLCDC_LAYER_PLANE_NEXT(i),
455 state->dscrs[i]->self);
458 if (desc->layout.xstride[i])
459 atmel_hlcdc_layer_write_cfg(&plane->layer,
460 desc->layout.xstride[i],
463 if (desc->layout.pstride[i])
464 atmel_hlcdc_layer_write_cfg(&plane->layer,
465 desc->layout.pstride[i],
470 int atmel_hlcdc_plane_prepare_ahb_routing(struct drm_crtc_state *c_state)
472 unsigned int ahb_load[2] = { };
473 struct drm_plane *plane;
475 drm_atomic_crtc_state_for_each_plane(plane, c_state) {
476 struct atmel_hlcdc_plane_state *plane_state;
477 struct drm_plane_state *plane_s;
478 unsigned int pixels, load = 0;
481 plane_s = drm_atomic_get_plane_state(c_state->state, plane);
483 return PTR_ERR(plane_s);
486 drm_plane_state_to_atmel_hlcdc_plane_state(plane_s);
488 pixels = (plane_state->src_w * plane_state->src_h) -
489 (plane_state->disc_w * plane_state->disc_h);
491 for (i = 0; i < plane_state->nplanes; i++)
492 load += pixels * plane_state->bpp[i];
494 if (ahb_load[0] <= ahb_load[1])
495 plane_state->ahb_id = 0;
497 plane_state->ahb_id = 1;
499 ahb_load[plane_state->ahb_id] += load;
506 atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state)
508 int disc_x = 0, disc_y = 0, disc_w = 0, disc_h = 0;
509 const struct atmel_hlcdc_layer_cfg_layout *layout;
510 struct atmel_hlcdc_plane_state *primary_state;
511 struct drm_plane_state *primary_s;
512 struct atmel_hlcdc_plane *primary;
513 struct drm_plane *ovl;
515 primary = drm_plane_to_atmel_hlcdc_plane(c_state->crtc->primary);
516 layout = &primary->layer.desc->layout;
517 if (!layout->disc_pos || !layout->disc_size)
520 primary_s = drm_atomic_get_plane_state(c_state->state,
522 if (IS_ERR(primary_s))
523 return PTR_ERR(primary_s);
525 primary_state = drm_plane_state_to_atmel_hlcdc_plane_state(primary_s);
527 drm_atomic_crtc_state_for_each_plane(ovl, c_state) {
528 struct atmel_hlcdc_plane_state *ovl_state;
529 struct drm_plane_state *ovl_s;
531 if (ovl == c_state->crtc->primary)
534 ovl_s = drm_atomic_get_plane_state(c_state->state, ovl);
536 return PTR_ERR(ovl_s);
538 ovl_state = drm_plane_state_to_atmel_hlcdc_plane_state(ovl_s);
541 atmel_hlcdc_format_embeds_alpha(ovl_s->fb->format->format) ||
542 ovl_state->alpha != 255)
545 /* TODO: implement a smarter hidden area detection */
546 if (ovl_state->crtc_h * ovl_state->crtc_w < disc_h * disc_w)
549 disc_x = ovl_state->crtc_x;
550 disc_y = ovl_state->crtc_y;
551 disc_h = ovl_state->crtc_h;
552 disc_w = ovl_state->crtc_w;
555 primary_state->disc_x = disc_x;
556 primary_state->disc_y = disc_y;
557 primary_state->disc_w = disc_w;
558 primary_state->disc_h = disc_h;
564 atmel_hlcdc_plane_update_disc_area(struct atmel_hlcdc_plane *plane,
565 struct atmel_hlcdc_plane_state *state)
567 const struct atmel_hlcdc_layer_cfg_layout *layout;
569 layout = &plane->layer.desc->layout;
570 if (!layout->disc_pos || !layout->disc_size)
573 atmel_hlcdc_layer_write_cfg(&plane->layer, layout->disc_pos,
574 ATMEL_HLCDC_LAYER_DISC_POS(state->disc_x,
577 atmel_hlcdc_layer_write_cfg(&plane->layer, layout->disc_size,
578 ATMEL_HLCDC_LAYER_DISC_SIZE(state->disc_w,
582 static int atmel_hlcdc_plane_atomic_check(struct drm_plane *p,
583 struct drm_plane_state *s)
585 struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
586 struct atmel_hlcdc_plane_state *state =
587 drm_plane_state_to_atmel_hlcdc_plane_state(s);
588 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
589 struct drm_framebuffer *fb = state->base.fb;
590 const struct drm_display_mode *mode;
591 struct drm_crtc_state *crtc_state;
592 unsigned int patched_crtc_w;
593 unsigned int patched_crtc_h;
594 unsigned int patched_src_w;
595 unsigned int patched_src_h;
603 if (!state->base.crtc || !fb)
606 crtc_state = drm_atomic_get_existing_crtc_state(s->state, s->crtc);
607 mode = &crtc_state->adjusted_mode;
609 state->src_x = s->src_x;
610 state->src_y = s->src_y;
611 state->src_h = s->src_h;
612 state->src_w = s->src_w;
613 state->crtc_x = s->crtc_x;
614 state->crtc_y = s->crtc_y;
615 state->crtc_h = s->crtc_h;
616 state->crtc_w = s->crtc_w;
617 if ((state->src_x | state->src_y | state->src_w | state->src_h) &
626 state->nplanes = fb->format->num_planes;
627 if (state->nplanes > ATMEL_HLCDC_LAYER_MAX_PLANES)
631 * Swap width and size in case of 90 or 270 degrees rotation
633 if (drm_rotation_90_or_270(state->base.rotation)) {
635 state->crtc_w = state->crtc_h;
638 state->src_w = state->src_h;
642 if (state->crtc_x + state->crtc_w > mode->hdisplay)
643 patched_crtc_w = mode->hdisplay - state->crtc_x;
645 patched_crtc_w = state->crtc_w;
647 if (state->crtc_x < 0) {
648 patched_crtc_w += state->crtc_x;
649 x_offset = -state->crtc_x;
653 if (state->crtc_y + state->crtc_h > mode->vdisplay)
654 patched_crtc_h = mode->vdisplay - state->crtc_y;
656 patched_crtc_h = state->crtc_h;
658 if (state->crtc_y < 0) {
659 patched_crtc_h += state->crtc_y;
660 y_offset = -state->crtc_y;
664 patched_src_w = DIV_ROUND_CLOSEST(patched_crtc_w * state->src_w,
666 patched_src_h = DIV_ROUND_CLOSEST(patched_crtc_h * state->src_h,
669 hsub = drm_format_horz_chroma_subsampling(fb->format->format);
670 vsub = drm_format_vert_chroma_subsampling(fb->format->format);
672 for (i = 0; i < state->nplanes; i++) {
673 unsigned int offset = 0;
674 int xdiv = i ? hsub : 1;
675 int ydiv = i ? vsub : 1;
677 state->bpp[i] = fb->format->cpp[i];
681 switch (state->base.rotation & DRM_ROTATE_MASK) {
683 offset = ((y_offset + state->src_y + patched_src_w - 1) /
684 ydiv) * fb->pitches[i];
685 offset += ((x_offset + state->src_x) / xdiv) *
687 state->xstride[i] = ((patched_src_w - 1) / ydiv) *
689 state->pstride[i] = -fb->pitches[i] - state->bpp[i];
692 offset = ((y_offset + state->src_y + patched_src_h - 1) /
693 ydiv) * fb->pitches[i];
694 offset += ((x_offset + state->src_x + patched_src_w - 1) /
695 xdiv) * state->bpp[i];
696 state->xstride[i] = ((((patched_src_w - 1) / xdiv) - 1) *
697 state->bpp[i]) - fb->pitches[i];
698 state->pstride[i] = -2 * state->bpp[i];
701 offset = ((y_offset + state->src_y) / ydiv) *
703 offset += ((x_offset + state->src_x + patched_src_h - 1) /
704 xdiv) * state->bpp[i];
705 state->xstride[i] = -(((patched_src_w - 1) / ydiv) *
708 state->pstride[i] = fb->pitches[i] - state->bpp[i];
712 offset = ((y_offset + state->src_y) / ydiv) *
714 offset += ((x_offset + state->src_x) / xdiv) *
716 state->xstride[i] = fb->pitches[i] -
717 ((patched_src_w / xdiv) *
719 state->pstride[i] = 0;
723 state->offsets[i] = offset + fb->offsets[i];
726 state->src_w = patched_src_w;
727 state->src_h = patched_src_h;
728 state->crtc_w = patched_crtc_w;
729 state->crtc_h = patched_crtc_h;
731 if (!desc->layout.size &&
732 (mode->hdisplay != state->crtc_w ||
733 mode->vdisplay != state->crtc_h))
736 if (desc->max_height && state->crtc_h > desc->max_height)
739 if (desc->max_width && state->crtc_w > desc->max_width)
742 if ((state->crtc_h != state->src_h || state->crtc_w != state->src_w) &&
743 (!desc->layout.memsize ||
744 atmel_hlcdc_format_embeds_alpha(state->base.fb->format->format)))
747 if (state->crtc_x < 0 || state->crtc_y < 0)
750 if (state->crtc_w + state->crtc_x > mode->hdisplay ||
751 state->crtc_h + state->crtc_y > mode->vdisplay)
757 static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p,
758 struct drm_plane_state *old_s)
760 struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
761 struct atmel_hlcdc_plane_state *state =
762 drm_plane_state_to_atmel_hlcdc_plane_state(p->state);
765 if (!p->state->crtc || !p->state->fb)
768 atmel_hlcdc_plane_update_pos_and_size(plane, state);
769 atmel_hlcdc_plane_update_general_settings(plane, state);
770 atmel_hlcdc_plane_update_format(plane, state);
771 atmel_hlcdc_plane_update_buffers(plane, state);
772 atmel_hlcdc_plane_update_disc_area(plane, state);
774 /* Enable the overrun interrupts. */
775 atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER,
776 ATMEL_HLCDC_LAYER_OVR_IRQ(0) |
777 ATMEL_HLCDC_LAYER_OVR_IRQ(1) |
778 ATMEL_HLCDC_LAYER_OVR_IRQ(2));
780 /* Apply the new config at the next SOF event. */
781 sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR);
782 atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER,
783 ATMEL_HLCDC_LAYER_UPDATE |
784 (sr & ATMEL_HLCDC_LAYER_EN ?
785 ATMEL_HLCDC_LAYER_A2Q : ATMEL_HLCDC_LAYER_EN));
788 static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p,
789 struct drm_plane_state *old_state)
791 struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
793 /* Disable interrupts */
794 atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IDR,
797 /* Disable the layer */
798 atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHDR,
799 ATMEL_HLCDC_LAYER_RST |
800 ATMEL_HLCDC_LAYER_A2Q |
801 ATMEL_HLCDC_LAYER_UPDATE);
803 /* Clear all pending interrupts */
804 atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR);
807 static void atmel_hlcdc_plane_destroy(struct drm_plane *p)
809 struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
812 drm_framebuffer_unreference(plane->base.fb);
814 drm_plane_cleanup(p);
817 static int atmel_hlcdc_plane_atomic_set_property(struct drm_plane *p,
818 struct drm_plane_state *s,
819 struct drm_property *property,
822 struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
823 struct atmel_hlcdc_plane_properties *props = plane->properties;
824 struct atmel_hlcdc_plane_state *state =
825 drm_plane_state_to_atmel_hlcdc_plane_state(s);
827 if (property == props->alpha)
835 static int atmel_hlcdc_plane_atomic_get_property(struct drm_plane *p,
836 const struct drm_plane_state *s,
837 struct drm_property *property,
840 struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
841 struct atmel_hlcdc_plane_properties *props = plane->properties;
842 const struct atmel_hlcdc_plane_state *state =
843 container_of(s, const struct atmel_hlcdc_plane_state, base);
845 if (property == props->alpha)
853 static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane,
854 struct atmel_hlcdc_plane_properties *props)
856 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
858 if (desc->type == ATMEL_HLCDC_OVERLAY_LAYER ||
859 desc->type == ATMEL_HLCDC_CURSOR_LAYER)
860 drm_object_attach_property(&plane->base.base,
863 if (desc->layout.xstride && desc->layout.pstride) {
866 ret = drm_plane_create_rotation_property(&plane->base,
876 if (desc->layout.csc) {
878 * TODO: decare a "yuv-to-rgb-conv-factors" property to let
879 * userspace modify these factors (using a BLOB property ?).
881 atmel_hlcdc_layer_write_cfg(&plane->layer,
884 atmel_hlcdc_layer_write_cfg(&plane->layer,
885 desc->layout.csc + 1,
887 atmel_hlcdc_layer_write_cfg(&plane->layer,
888 desc->layout.csc + 2,
895 void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane)
897 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
900 isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR);
903 * There's not much we can do in case of overrun except informing
904 * the user. However, we are in interrupt context here, hence the
908 (ATMEL_HLCDC_LAYER_OVR_IRQ(0) | ATMEL_HLCDC_LAYER_OVR_IRQ(1) |
909 ATMEL_HLCDC_LAYER_OVR_IRQ(2)))
910 dev_dbg(plane->base.dev->dev, "overrun on plane %s\n",
914 static struct drm_plane_helper_funcs atmel_hlcdc_layer_plane_helper_funcs = {
915 .atomic_check = atmel_hlcdc_plane_atomic_check,
916 .atomic_update = atmel_hlcdc_plane_atomic_update,
917 .atomic_disable = atmel_hlcdc_plane_atomic_disable,
920 static int atmel_hlcdc_plane_alloc_dscrs(struct drm_plane *p,
921 struct atmel_hlcdc_plane_state *state)
923 struct atmel_hlcdc_dc *dc = p->dev->dev_private;
926 for (i = 0; i < ARRAY_SIZE(state->dscrs); i++) {
927 struct atmel_hlcdc_dma_channel_dscr *dscr;
930 dscr = dma_pool_alloc(dc->dscrpool, GFP_KERNEL, &dscr_dma);
935 dscr->next = dscr_dma;
936 dscr->self = dscr_dma;
937 dscr->ctrl = ATMEL_HLCDC_LAYER_DFETCH;
939 state->dscrs[i] = dscr;
945 for (i--; i >= 0; i--) {
946 dma_pool_free(dc->dscrpool, state->dscrs[i],
947 state->dscrs[i]->self);
953 static void atmel_hlcdc_plane_reset(struct drm_plane *p)
955 struct atmel_hlcdc_plane_state *state;
958 state = drm_plane_state_to_atmel_hlcdc_plane_state(p->state);
961 drm_framebuffer_unreference(state->base.fb);
967 state = kzalloc(sizeof(*state), GFP_KERNEL);
969 if (atmel_hlcdc_plane_alloc_dscrs(p, state)) {
972 "Failed to allocate initial plane state\n");
977 p->state = &state->base;
982 static struct drm_plane_state *
983 atmel_hlcdc_plane_atomic_duplicate_state(struct drm_plane *p)
985 struct atmel_hlcdc_plane_state *state =
986 drm_plane_state_to_atmel_hlcdc_plane_state(p->state);
987 struct atmel_hlcdc_plane_state *copy;
989 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
993 if (atmel_hlcdc_plane_alloc_dscrs(p, copy)) {
999 drm_framebuffer_reference(copy->base.fb);
1004 static void atmel_hlcdc_plane_atomic_destroy_state(struct drm_plane *p,
1005 struct drm_plane_state *s)
1007 struct atmel_hlcdc_plane_state *state =
1008 drm_plane_state_to_atmel_hlcdc_plane_state(s);
1009 struct atmel_hlcdc_dc *dc = p->dev->dev_private;
1012 for (i = 0; i < ARRAY_SIZE(state->dscrs); i++) {
1013 dma_pool_free(dc->dscrpool, state->dscrs[i],
1014 state->dscrs[i]->self);
1018 drm_framebuffer_unreference(s->fb);
1023 static struct drm_plane_funcs layer_plane_funcs = {
1024 .update_plane = drm_atomic_helper_update_plane,
1025 .disable_plane = drm_atomic_helper_disable_plane,
1026 .set_property = drm_atomic_helper_plane_set_property,
1027 .destroy = atmel_hlcdc_plane_destroy,
1028 .reset = atmel_hlcdc_plane_reset,
1029 .atomic_duplicate_state = atmel_hlcdc_plane_atomic_duplicate_state,
1030 .atomic_destroy_state = atmel_hlcdc_plane_atomic_destroy_state,
1031 .atomic_set_property = atmel_hlcdc_plane_atomic_set_property,
1032 .atomic_get_property = atmel_hlcdc_plane_atomic_get_property,
1035 static int atmel_hlcdc_plane_create(struct drm_device *dev,
1036 const struct atmel_hlcdc_layer_desc *desc,
1037 struct atmel_hlcdc_plane_properties *props)
1039 struct atmel_hlcdc_dc *dc = dev->dev_private;
1040 struct atmel_hlcdc_plane *plane;
1041 enum drm_plane_type type;
1044 plane = devm_kzalloc(dev->dev, sizeof(*plane), GFP_KERNEL);
1048 atmel_hlcdc_layer_init(&plane->layer, desc, dc->hlcdc->regmap);
1049 plane->properties = props;
1051 if (desc->type == ATMEL_HLCDC_BASE_LAYER)
1052 type = DRM_PLANE_TYPE_PRIMARY;
1053 else if (desc->type == ATMEL_HLCDC_CURSOR_LAYER)
1054 type = DRM_PLANE_TYPE_CURSOR;
1056 type = DRM_PLANE_TYPE_OVERLAY;
1058 ret = drm_universal_plane_init(dev, &plane->base, 0,
1060 desc->formats->formats,
1061 desc->formats->nformats, type, NULL);
1065 drm_plane_helper_add(&plane->base,
1066 &atmel_hlcdc_layer_plane_helper_funcs);
1068 /* Set default property values*/
1069 ret = atmel_hlcdc_plane_init_properties(plane, props);
1073 dc->layers[desc->id] = &plane->layer;
1078 static struct atmel_hlcdc_plane_properties *
1079 atmel_hlcdc_plane_create_properties(struct drm_device *dev)
1081 struct atmel_hlcdc_plane_properties *props;
1083 props = devm_kzalloc(dev->dev, sizeof(*props), GFP_KERNEL);
1085 return ERR_PTR(-ENOMEM);
1087 props->alpha = drm_property_create_range(dev, 0, "alpha", 0, 255);
1089 return ERR_PTR(-ENOMEM);
1094 int atmel_hlcdc_create_planes(struct drm_device *dev)
1096 struct atmel_hlcdc_dc *dc = dev->dev_private;
1097 struct atmel_hlcdc_plane_properties *props;
1098 const struct atmel_hlcdc_layer_desc *descs = dc->desc->layers;
1099 int nlayers = dc->desc->nlayers;
1102 props = atmel_hlcdc_plane_create_properties(dev);
1104 return PTR_ERR(props);
1106 dc->dscrpool = dmam_pool_create("atmel-hlcdc-dscr", dev->dev,
1107 sizeof(struct atmel_hlcdc_dma_channel_dscr),
1112 for (i = 0; i < nlayers; i++) {
1113 if (descs[i].type != ATMEL_HLCDC_BASE_LAYER &&
1114 descs[i].type != ATMEL_HLCDC_OVERLAY_LAYER &&
1115 descs[i].type != ATMEL_HLCDC_CURSOR_LAYER)
1118 ret = atmel_hlcdc_plane_create(dev, &descs[i], props);