drivers/gpu/drm/bridge/dw-hdmi.c

   1 /*
   2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
   3  *
   4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
   5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  */
  14 #include <linux/module.h>
  15 #include <linux/irq.h>
  16 #include <linux/delay.h>
  17 #include <linux/err.h>
  18 #include <linux/clk.h>
  19 #include <linux/hdmi.h>
  20 #include <linux/mutex.h>
  21 #include <linux/of_device.h>
  22 #include <linux/spinlock.h>
  23
  24 #include <drm/drm_of.h>
  25 #include <drm/drmP.h>
  26 #include <drm/drm_atomic_helper.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/drm_encoder_slave.h>
  30 #include <drm/bridge/dw_hdmi.h>
  31
  32 #include "dw-hdmi.h"
  33 #include "dw-hdmi-audio.h"
  34
  35 #define HDMI_EDID_LEN           512
  36
  37 #define RGB                     0
  38 #define YCBCR444                1
  39 #define YCBCR422_16BITS         2
  40 #define YCBCR422_8BITS          3
  41 #define XVYCC444                4
  42
  43 enum hdmi_datamap {
  44         RGB444_8B = 0x01,
  45         RGB444_10B = 0x03,
  46         RGB444_12B = 0x05,
  47         RGB444_16B = 0x07,
  48         YCbCr444_8B = 0x09,
  49         YCbCr444_10B = 0x0B,
  50         YCbCr444_12B = 0x0D,
  51         YCbCr444_16B = 0x0F,
  52         YCbCr422_8B = 0x16,
  53         YCbCr422_10B = 0x14,
  54         YCbCr422_12B = 0x12,
  55 };
  56
  57 static const u16 csc_coeff_default[3][4] = {
  58         { 0x2000, 0x0000, 0x0000, 0x0000 },
  59         { 0x0000, 0x2000, 0x0000, 0x0000 },
  60         { 0x0000, 0x0000, 0x2000, 0x0000 }
  61 };
  62
  63 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  64         { 0x2000, 0x6926, 0x74fd, 0x010e },
  65         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  66         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  67 };
  68
  69 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  70         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  71         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  72         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  73 };
  74
  75 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  76         { 0x2591, 0x1322, 0x074b, 0x0000 },
  77         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  78         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  79 };
  80
  81 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  82         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  83         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  84         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  85 };
  86
  87 struct hdmi_vmode {
  88         bool mdataenablepolarity;
  89
  90         unsigned int mpixelclock;
  91         unsigned int mpixelrepetitioninput;
  92         unsigned int mpixelrepetitionoutput;
  93 };
  94
  95 struct hdmi_data_info {
  96         unsigned int enc_in_format;
  97         unsigned int enc_out_format;
  98         unsigned int enc_color_depth;
  99         unsigned int colorimetry;
 100         unsigned int pix_repet_factor;
 101         unsigned int hdcp_enable;
 102         struct hdmi_vmode video_mode;
 103 };
 104
 105 struct dw_hdmi_i2c {
 106         struct i2c_adapter      adap;
 107
 108         struct mutex            lock;   /* used to serialize data transfers */
 109         struct completion       cmp;
 110         u8                      stat;
 111
 112         u8                      slave_reg;
 113         bool                    is_regaddr;
 114 };
 115
 116 struct dw_hdmi_phy_data {
 117         enum dw_hdmi_phy_type type;
 118         const char *name;
 119         bool has_svsret;
 120 };
 121
 122 struct dw_hdmi {
 123         struct drm_connector connector;
 124         struct drm_bridge bridge;
 125
 126         enum dw_hdmi_devtype dev_type;
 127         unsigned int version;
 128
 129         struct platform_device *audio;
 130         struct device *dev;
 131         struct clk *isfr_clk;
 132         struct clk *iahb_clk;
 133         struct dw_hdmi_i2c *i2c;
 134
 135         struct hdmi_data_info hdmi_data;
 136         const struct dw_hdmi_plat_data *plat_data;
 137
 138         int vic;
 139
 140         u8 edid[HDMI_EDID_LEN];
 141         bool cable_plugin;
 142
 143         const struct dw_hdmi_phy_data *phy;
 144         bool phy_enabled;
 145
 146         struct drm_display_mode previous_mode;
 147
 148         struct i2c_adapter *ddc;
 149         void __iomem *regs;
 150         bool sink_is_hdmi;
 151         bool sink_has_audio;
 152
 153         struct mutex mutex;             /* for state below and previous_mode */
 154         enum drm_connector_force force; /* mutex-protected force state */
 155         bool disabled;                  /* DRM has disabled our bridge */
 156         bool bridge_is_on;              /* indicates the bridge is on */
 157         bool rxsense;                   /* rxsense state */
 158         u8 phy_mask;                    /* desired phy int mask settings */
 159
 160         spinlock_t audio_lock;
 161         struct mutex audio_mutex;
 162         unsigned int sample_rate;
 163         unsigned int audio_cts;
 164         unsigned int audio_n;
 165         bool audio_enable;
 166
 167         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 168         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 169 };
 170
 171 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 172         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 173          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 174
 175 #define HDMI_PHY_RX_SENSE \
 176         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 177          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 178
 179 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 180 {
 181         writel(val, hdmi->regs + (offset << 2));
 182 }
 183
 184 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 185 {
 186         return readl(hdmi->regs + (offset << 2));
 187 }
 188
 189 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 190 {
 191         writeb(val, hdmi->regs + offset);
 192 }
 193
 194 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 195 {
 196         return readb(hdmi->regs + offset);
 197 }
 198
 199 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 200 {
 201         hdmi->write(hdmi, val, offset);
 202 }
 203
 204 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 205 {
 206         return hdmi->read(hdmi, offset);
 207 }
 208
 209 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 210 {
 211         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 212
 213         val |= data & mask;
 214         hdmi_writeb(hdmi, val, reg);
 215 }
 216
 217 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 218                              u8 shift, u8 mask)
 219 {
 220         hdmi_modb(hdmi, data << shift, mask, reg);
 221 }
 222
 223 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
 224 {
 225         /* Software reset */
 226         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
 227
 228         /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
 229         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
 230
 231         /* Set done, not acknowledged and arbitration interrupt polarities */
 232         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
 233         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
 234                     HDMI_I2CM_CTLINT);
 235
 236         /* Clear DONE and ERROR interrupts */
 237         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 238                     HDMI_IH_I2CM_STAT0);
 239
 240         /* Mute DONE and ERROR interrupts */
 241         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 242                     HDMI_IH_MUTE_I2CM_STAT0);
 243 }
 244
 245 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 246                             unsigned char *buf, unsigned int length)
 247 {
 248         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 249         int stat;
 250
 251         if (!i2c->is_regaddr) {
 252                 dev_dbg(hdmi->dev, "set read register address to 0\n");
 253                 i2c->slave_reg = 0x00;
 254                 i2c->is_regaddr = true;
 255         }
 256
 257         while (length--) {
 258                 reinit_completion(&i2c->cmp);
 259
 260                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 261                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
 262                             HDMI_I2CM_OPERATION);
 263
 264                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 265                 if (!stat)
 266                         return -EAGAIN;
 267
 268                 /* Check for error condition on the bus */
 269                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 270                         return -EIO;
 271
 272                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
 273         }
 274
 275         return 0;
 276 }
 277
 278 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
 279                              unsigned char *buf, unsigned int length)
 280 {
 281         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 282         int stat;
 283
 284         if (!i2c->is_regaddr) {
 285                 /* Use the first write byte as register address */
 286                 i2c->slave_reg = buf[0];
 287                 length--;
 288                 buf++;
 289                 i2c->is_regaddr = true;
 290         }
 291
 292         while (length--) {
 293                 reinit_completion(&i2c->cmp);
 294
 295                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
 296                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 297                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
 298                             HDMI_I2CM_OPERATION);
 299
 300                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 301                 if (!stat)
 302                         return -EAGAIN;
 303
 304                 /* Check for error condition on the bus */
 305                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 306                         return -EIO;
 307         }
 308
 309         return 0;
 310 }
 311
 312 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
 313                             struct i2c_msg *msgs, int num)
 314 {
 315         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
 316         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 317         u8 addr = msgs[0].addr;
 318         int i, ret = 0;
 319
 320         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 321
 322         for (i = 0; i < num; i++) {
 323                 if (msgs[i].addr != addr) {
 324                         dev_warn(hdmi->dev,
 325                                  "unsupported transfer, changed slave address\n");
 326                         return -EOPNOTSUPP;
 327                 }
 328
 329                 if (msgs[i].len == 0) {
 330                         dev_dbg(hdmi->dev,
 331                                 "unsupported transfer %d/%d, no data\n",
 332                                 i + 1, num);
 333                         return -EOPNOTSUPP;
 334                 }
 335         }
 336
 337         mutex_lock(&i2c->lock);
 338
 339         /* Unmute DONE and ERROR interrupts */
 340         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
 341
 342         /* Set slave device address taken from the first I2C message */
 343         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
 344
 345         /* Set slave device register address on transfer */
 346         i2c->is_regaddr = false;
 347
 348         for (i = 0; i < num; i++) {
 349                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
 350                         i + 1, num, msgs[i].len, msgs[i].flags);
 351
 352                 if (msgs[i].flags & I2C_M_RD)
 353                         ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, msgs[i].len);
 354                 else
 355                         ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, msgs[i].len);
 356
 357                 if (ret < 0)
 358                         break;
 359         }
 360
 361         if (!ret)
 362                 ret = num;
 363
 364         /* Mute DONE and ERROR interrupts */
 365         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 366                     HDMI_IH_MUTE_I2CM_STAT0);
 367
 368         mutex_unlock(&i2c->lock);
 369
 370         return ret;
 371 }
 372
 373 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
 374 {
 375         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 376 }
 377
 378 static const struct i2c_algorithm dw_hdmi_algorithm = {
 379         .master_xfer    = dw_hdmi_i2c_xfer,
 380         .functionality  = dw_hdmi_i2c_func,
 381 };
 382
 383 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
 384 {
 385         struct i2c_adapter *adap;
 386         struct dw_hdmi_i2c *i2c;
 387         int ret;
 388
 389         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 390         if (!i2c)
 391                 return ERR_PTR(-ENOMEM);
 392
 393         mutex_init(&i2c->lock);
 394         init_completion(&i2c->cmp);
 395
 396         adap = &i2c->adap;
 397         adap->class = I2C_CLASS_DDC;
 398         adap->owner = THIS_MODULE;
 399         adap->dev.parent = hdmi->dev;
 400         adap->algo = &dw_hdmi_algorithm;
 401         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
 402         i2c_set_adapdata(adap, hdmi);
 403
 404         ret = i2c_add_adapter(adap);
 405         if (ret) {
 406                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 407                 devm_kfree(hdmi->dev, i2c);
 408                 return ERR_PTR(ret);
 409         }
 410
 411         hdmi->i2c = i2c;
 412
 413         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 414
 415         return adap;
 416 }
 417
 418 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 419                            unsigned int n)
 420 {
 421         /* Must be set/cleared first */
 422         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 423
 424         /* nshift factor = 0 */
 425         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 426
 427         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 428                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 429         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 430         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 431
 432         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 433         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 434         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 435 }
 436
 437 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
 438 {
 439         unsigned int n = (128 * freq) / 1000;
 440         unsigned int mult = 1;
 441
 442         while (freq > 48000) {
 443                 mult *= 2;
 444                 freq /= 2;
 445         }
 446
 447         switch (freq) {
 448         case 32000:
 449                 if (pixel_clk == 25175000)
 450                         n = 4576;
 451                 else if (pixel_clk == 27027000)
 452                         n = 4096;
 453                 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
 454                         n = 11648;
 455                 else
 456                         n = 4096;
 457                 n *= mult;
 458                 break;
 459
 460         case 44100:
 461                 if (pixel_clk == 25175000)
 462                         n = 7007;
 463                 else if (pixel_clk == 74176000)
 464                         n = 17836;
 465                 else if (pixel_clk == 148352000)
 466                         n = 8918;
 467                 else
 468                         n = 6272;
 469                 n *= mult;
 470                 break;
 471
 472         case 48000:
 473                 if (pixel_clk == 25175000)
 474                         n = 6864;
 475                 else if (pixel_clk == 27027000)
 476                         n = 6144;
 477                 else if (pixel_clk == 74176000)
 478                         n = 11648;
 479                 else if (pixel_clk == 148352000)
 480                         n = 5824;
 481                 else
 482                         n = 6144;
 483                 n *= mult;
 484                 break;
 485
 486         default:
 487                 break;
 488         }
 489
 490         return n;
 491 }
 492
 493 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 494         unsigned long pixel_clk, unsigned int sample_rate)
 495 {
 496         unsigned long ftdms = pixel_clk;
 497         unsigned int n, cts;
 498         u64 tmp;
 499
 500         n = hdmi_compute_n(sample_rate, pixel_clk);
 501
 502         /*
 503          * Compute the CTS value from the N value.  Note that CTS and N
 504          * can be up to 20 bits in total, so we need 64-bit math.  Also
 505          * note that our TDMS clock is not fully accurate; it is accurate
 506          * to kHz.  This can introduce an unnecessary remainder in the
 507          * calculation below, so we don't try to warn about that.
 508          */
 509         tmp = (u64)ftdms * n;
 510         do_div(tmp, 128 * sample_rate);
 511         cts = tmp;
 512
 513         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
 514                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
 515                 n, cts);
 516
 517         spin_lock_irq(&hdmi->audio_lock);
 518         hdmi->audio_n = n;
 519         hdmi->audio_cts = cts;
 520         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 521         spin_unlock_irq(&hdmi->audio_lock);
 522 }
 523
 524 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 525 {
 526         mutex_lock(&hdmi->audio_mutex);
 527         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 528         mutex_unlock(&hdmi->audio_mutex);
 529 }
 530
 531 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 532 {
 533         mutex_lock(&hdmi->audio_mutex);
 534         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 535                                  hdmi->sample_rate);
 536         mutex_unlock(&hdmi->audio_mutex);
 537 }
 538
 539 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 540 {
 541         mutex_lock(&hdmi->audio_mutex);
 542         hdmi->sample_rate = rate;
 543         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 544                                  hdmi->sample_rate);
 545         mutex_unlock(&hdmi->audio_mutex);
 546 }
 547 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 548
 549 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 550 {
 551         unsigned long flags;
 552
 553         spin_lock_irqsave(&hdmi->audio_lock, flags);
 554         hdmi->audio_enable = true;
 555         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 556         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 557 }
 558 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 559
 560 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 561 {
 562         unsigned long flags;
 563
 564         spin_lock_irqsave(&hdmi->audio_lock, flags);
 565         hdmi->audio_enable = false;
 566         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 567         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 568 }
 569 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 570
 571 /*
 572  * this submodule is responsible for the video data synchronization.
 573  * for example, for RGB 4:4:4 input, the data map is defined as
 574  *                      pin{47~40} <==> R[7:0]
 575  *                      pin{31~24} <==> G[7:0]
 576  *                      pin{15~8}  <==> B[7:0]
 577  */
 578 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 579 {
 580         int color_format = 0;
 581         u8 val;
 582
 583         if (hdmi->hdmi_data.enc_in_format == RGB) {
 584                 if (hdmi->hdmi_data.enc_color_depth == 8)
 585                         color_format = 0x01;
 586                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 587                         color_format = 0x03;
 588                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 589                         color_format = 0x05;
 590                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 591                         color_format = 0x07;
 592                 else
 593                         return;
 594         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 595                 if (hdmi->hdmi_data.enc_color_depth == 8)
 596                         color_format = 0x09;
 597                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 598                         color_format = 0x0B;
 599                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 600                         color_format = 0x0D;
 601                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 602                         color_format = 0x0F;
 603                 else
 604                         return;
 605         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 606                 if (hdmi->hdmi_data.enc_color_depth == 8)
 607                         color_format = 0x16;
 608                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 609                         color_format = 0x14;
 610                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 611                         color_format = 0x12;
 612                 else
 613                         return;
 614         }
 615
 616         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 617                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 618                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 619         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 620
 621         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 622         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 623                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 624                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 625         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 626         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 627         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 628         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 629         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 630         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 631         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 632 }
 633
 634 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 635 {
 636         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 637 }
 638
 639 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 640 {
 641         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 642                 return 0;
 643         if (hdmi->hdmi_data.enc_in_format == RGB ||
 644             hdmi->hdmi_data.enc_in_format == YCBCR444)
 645                 return 1;
 646         return 0;
 647 }
 648
 649 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 650 {
 651         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 652                 return 0;
 653         if (hdmi->hdmi_data.enc_out_format == RGB ||
 654             hdmi->hdmi_data.enc_out_format == YCBCR444)
 655                 return 1;
 656         return 0;
 657 }
 658
 659 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 660 {
 661         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 662         unsigned i;
 663         u32 csc_scale = 1;
 664
 665         if (is_color_space_conversion(hdmi)) {
 666                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 667                         if (hdmi->hdmi_data.colorimetry ==
 668                                         HDMI_COLORIMETRY_ITU_601)
 669                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 670                         else
 671                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 672                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 673                         if (hdmi->hdmi_data.colorimetry ==
 674                                         HDMI_COLORIMETRY_ITU_601)
 675                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 676                         else
 677                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 678                         csc_scale = 0;
 679                 }
 680         }
 681
 682         /* The CSC registers are sequential, alternating MSB then LSB */
 683         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 684                 u16 coeff_a = (*csc_coeff)[0][i];
 685                 u16 coeff_b = (*csc_coeff)[1][i];
 686                 u16 coeff_c = (*csc_coeff)[2][i];
 687
 688                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 689                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 690                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 691                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 692                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 693                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 694         }
 695
 696         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 697                   HDMI_CSC_SCALE);
 698 }
 699
 700 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 701 {
 702         int color_depth = 0;
 703         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 704         int decimation = 0;
 705
 706         /* YCC422 interpolation to 444 mode */
 707         if (is_color_space_interpolation(hdmi))
 708                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 709         else if (is_color_space_decimation(hdmi))
 710                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 711
 712         if (hdmi->hdmi_data.enc_color_depth == 8)
 713                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 714         else if (hdmi->hdmi_data.enc_color_depth == 10)
 715                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 716         else if (hdmi->hdmi_data.enc_color_depth == 12)
 717                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 718         else if (hdmi->hdmi_data.enc_color_depth == 16)
 719                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 720         else
 721                 return;
 722
 723         /* Configure the CSC registers */
 724         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 725         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 726                   HDMI_CSC_SCALE);
 727
 728         dw_hdmi_update_csc_coeffs(hdmi);
 729 }
 730
 731 /*
 732  * HDMI video packetizer is used to packetize the data.
 733  * for example, if input is YCC422 mode or repeater is used,
 734  * data should be repacked this module can be bypassed.
 735  */
 736 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 737 {
 738         unsigned int color_depth = 0;
 739         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 740         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 741         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 742         u8 val, vp_conf;
 743
 744         if (hdmi_data->enc_out_format == RGB ||
 745             hdmi_data->enc_out_format == YCBCR444) {
 746                 if (!hdmi_data->enc_color_depth) {
 747                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 748                 } else if (hdmi_data->enc_color_depth == 8) {
 749                         color_depth = 4;
 750                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 751                 } else if (hdmi_data->enc_color_depth == 10) {
 752                         color_depth = 5;
 753                 } else if (hdmi_data->enc_color_depth == 12) {
 754                         color_depth = 6;
 755                 } else if (hdmi_data->enc_color_depth == 16) {
 756                         color_depth = 7;
 757                 } else {
 758                         return;
 759                 }
 760         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 761                 if (!hdmi_data->enc_color_depth ||
 762                     hdmi_data->enc_color_depth == 8)
 763                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 764                 else if (hdmi_data->enc_color_depth == 10)
 765                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 766                 else if (hdmi_data->enc_color_depth == 12)
 767                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 768                 else
 769                         return;
 770                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 771         } else {
 772                 return;
 773         }
 774
 775         /* set the packetizer registers */
 776         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 777                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 778                 ((hdmi_data->pix_repet_factor <<
 779                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 780                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 781         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 782
 783         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 784                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 785
 786         /* Data from pixel repeater block */
 787         if (hdmi_data->pix_repet_factor > 1) {
 788                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 789                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 790         } else { /* data from packetizer block */
 791                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 792                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 793         }
 794
 795         hdmi_modb(hdmi, vp_conf,
 796                   HDMI_VP_CONF_PR_EN_MASK |
 797                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 798
 799         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 800                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 801
 802         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 803
 804         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 805                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 806                           HDMI_VP_CONF_PP_EN_ENABLE |
 807                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 808         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 809                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 810                           HDMI_VP_CONF_PP_EN_DISABLE |
 811                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 812         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 813                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 814                           HDMI_VP_CONF_PP_EN_DISABLE |
 815                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 816         } else {
 817                 return;
 818         }
 819
 820         hdmi_modb(hdmi, vp_conf,
 821                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 822                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 823
 824         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 825                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 826                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 827                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 828
 829         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 830                   HDMI_VP_CONF);
 831 }
 832
 833 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 834                                        unsigned char bit)
 835 {
 836         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 837                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 838 }
 839
 840 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 841                                         unsigned char bit)
 842 {
 843         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 844                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 845 }
 846
 847 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 848                                        unsigned char bit)
 849 {
 850         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 851                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 852 }
 853
 854 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 855                                      unsigned char bit)
 856 {
 857         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 858 }
 859
 860 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 861                                       unsigned char bit)
 862 {
 863         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 864 }
 865
 866 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 867 {
 868         u32 val;
 869
 870         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 871                 if (msec-- == 0)
 872                         return false;
 873                 udelay(1000);
 874         }
 875         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
 876
 877         return true;
 878 }
 879
 880 static void hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 881                                  unsigned char addr)
 882 {
 883         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
 884         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 885         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
 886                     HDMI_PHY_I2CM_DATAO_1_ADDR);
 887         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
 888                     HDMI_PHY_I2CM_DATAO_0_ADDR);
 889         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
 890                     HDMI_PHY_I2CM_OPERATION_ADDR);
 891         hdmi_phy_wait_i2c_done(hdmi, 1000);
 892 }
 893
 894 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
 895 {
 896         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
 897                          HDMI_PHY_CONF0_PDZ_OFFSET,
 898                          HDMI_PHY_CONF0_PDZ_MASK);
 899 }
 900
 901 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
 902 {
 903         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 904                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
 905                          HDMI_PHY_CONF0_ENTMDS_MASK);
 906 }
 907
 908 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
 909 {
 910         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 911                          HDMI_PHY_CONF0_SVSRET_OFFSET,
 912                          HDMI_PHY_CONF0_SVSRET_MASK);
 913 }
 914
 915 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
 916 {
 917         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 918                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
 919                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
 920 }
 921
 922 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
 923 {
 924         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 925                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
 926                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
 927 }
 928
 929 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
 930 {
 931         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 932                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
 933                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
 934 }
 935
 936 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
 937 {
 938         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 939                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
 940                          HDMI_PHY_CONF0_SELDIPIF_MASK);
 941 }
 942
 943 static int hdmi_phy_configure(struct dw_hdmi *hdmi, int cscon)
 944 {
 945         u8 val, msec;
 946         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
 947         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
 948         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
 949         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
 950
 951         /* PLL/MPLL Cfg - always match on final entry */
 952         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
 953                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 954                     mpll_config->mpixelclock)
 955                         break;
 956
 957         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
 958                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 959                     curr_ctrl->mpixelclock)
 960                         break;
 961
 962         for (; phy_config->mpixelclock != ~0UL; phy_config++)
 963                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 964                     phy_config->mpixelclock)
 965                         break;
 966
 967         if (mpll_config->mpixelclock == ~0UL ||
 968             curr_ctrl->mpixelclock == ~0UL ||
 969             phy_config->mpixelclock == ~0UL) {
 970                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
 971                         hdmi->hdmi_data.video_mode.mpixelclock);
 972                 return -EINVAL;
 973         }
 974
 975         /* Enable csc path */
 976         if (cscon)
 977                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
 978         else
 979                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
 980
 981         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
 982
 983         /* gen2 tx power off */
 984         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
 985
 986         /* gen2 pddq */
 987         dw_hdmi_phy_gen2_pddq(hdmi, 1);
 988
 989         /* Leave low power consumption mode by asserting SVSRET. */
 990         if (hdmi->phy->has_svsret)
 991                 dw_hdmi_phy_enable_svsret(hdmi, 1);
 992
 993         /* PHY reset. The reset signal is active high on Gen2 PHYs. */
 994         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
 995         hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
 996
 997         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
 998
 999         hdmi_phy_test_clear(hdmi, 1);
1000         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1001                     HDMI_PHY_I2CM_SLAVE_ADDR);
1002         hdmi_phy_test_clear(hdmi, 0);
1003
1004         hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1005                            HDMI_3D_TX_PHY_CPCE_CTRL);
1006         hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1007                            HDMI_3D_TX_PHY_GMPCTRL);
1008         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1009                            HDMI_3D_TX_PHY_CURRCTRL);
1010
1011         hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1012         hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1013                            HDMI_3D_TX_PHY_MSM_CTRL);
1014
1015         hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1016         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1017                            HDMI_3D_TX_PHY_CKSYMTXCTRL);
1018         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1019                            HDMI_3D_TX_PHY_VLEVCTRL);
1020
1021         /* Override and disable clock termination. */
1022         hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1023                            HDMI_3D_TX_PHY_CKCALCTRL);
1024
1025         dw_hdmi_phy_enable_powerdown(hdmi, false);
1026
1027         /* toggle TMDS enable */
1028         dw_hdmi_phy_enable_tmds(hdmi, 0);
1029         dw_hdmi_phy_enable_tmds(hdmi, 1);
1030
1031         /* gen2 tx power on */
1032         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1033         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1034
1035         /* Wait for PHY PLL lock */
1036         msec = 5;
1037         do {
1038                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1039                 if (!val)
1040                         break;
1041
1042                 if (msec == 0) {
1043                         dev_err(hdmi->dev, "PHY PLL not locked\n");
1044                         return -ETIMEDOUT;
1045                 }
1046
1047                 udelay(1000);
1048                 msec--;
1049         } while (1);
1050
1051         return 0;
1052 }
1053
1054 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
1055 {
1056         int i, ret;
1057         bool cscon;
1058
1059         /*check csc whether needed activated in HDMI mode */
1060         cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
1061
1062         /* HDMI Phy spec says to do the phy initialization sequence twice */
1063         for (i = 0; i < 2; i++) {
1064                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1065                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1066                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1067                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1068
1069                 /* Enable CSC */
1070                 ret = hdmi_phy_configure(hdmi, cscon);
1071                 if (ret)
1072                         return ret;
1073         }
1074
1075         hdmi->phy_enabled = true;
1076         return 0;
1077 }
1078
1079 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1080 {
1081         u8 de;
1082
1083         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1084                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1085         else
1086                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1087
1088         /* disable rx detect */
1089         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1090                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1091
1092         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1093
1094         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1095                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1096 }
1097
1098 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1099 {
1100         struct hdmi_avi_infoframe frame;
1101         u8 val;
1102
1103         /* Initialise info frame from DRM mode */
1104         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1105
1106         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1107                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1108         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1109                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1110         else
1111                 frame.colorspace = HDMI_COLORSPACE_RGB;
1112
1113         /* Set up colorimetry */
1114         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1115                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1116                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1117                         frame.extended_colorimetry =
1118                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1119                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1120                         frame.extended_colorimetry =
1121                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1122         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1123                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
1124                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1125         } else { /* Carries no data */
1126                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1127                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1128         }
1129
1130         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1131
1132         /*
1133          * The Designware IP uses a different byte format from standard
1134          * AVI info frames, though generally the bits are in the correct
1135          * bytes.
1136          */
1137
1138         /*
1139          * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1140          * scan info in bits 4,5 rather than 0,1 and active aspect present in
1141          * bit 6 rather than 4.
1142          */
1143         val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1144         if (frame.active_aspect & 15)
1145                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1146         if (frame.top_bar || frame.bottom_bar)
1147                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1148         if (frame.left_bar || frame.right_bar)
1149                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1150         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1151
1152         /* AVI data byte 2 differences: none */
1153         val = ((frame.colorimetry & 0x3) << 6) |
1154               ((frame.picture_aspect & 0x3) << 4) |
1155               (frame.active_aspect & 0xf);
1156         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1157
1158         /* AVI data byte 3 differences: none */
1159         val = ((frame.extended_colorimetry & 0x7) << 4) |
1160               ((frame.quantization_range & 0x3) << 2) |
1161               (frame.nups & 0x3);
1162         if (frame.itc)
1163                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1164         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1165
1166         /* AVI data byte 4 differences: none */
1167         val = frame.video_code & 0x7f;
1168         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1169
1170         /* AVI Data Byte 5- set up input and output pixel repetition */
1171         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1172                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1173                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1174                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1175                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1176                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1177         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1178
1179         /*
1180          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1181          * ycc range in bits 2,3 rather than 6,7
1182          */
1183         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1184               (frame.content_type & 0x3);
1185         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1186
1187         /* AVI Data Bytes 6-13 */
1188         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1189         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1190         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1191         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1192         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1193         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1194         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1195         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1196 }
1197
1198 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1199                              const struct drm_display_mode *mode)
1200 {
1201         u8 inv_val;
1202         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1203         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1204         unsigned int vdisplay;
1205
1206         vmode->mpixelclock = mode->clock * 1000;
1207
1208         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1209
1210         /* Set up HDMI_FC_INVIDCONF */
1211         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1212                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1213                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1214
1215         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1216                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1217                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1218
1219         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1220                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1221                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1222
1223         inv_val |= (vmode->mdataenablepolarity ?
1224                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1225                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1226
1227         if (hdmi->vic == 39)
1228                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1229         else
1230                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1231                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1232                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1233
1234         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1235                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1236                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1237
1238         inv_val |= hdmi->sink_is_hdmi ?
1239                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1240                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1241
1242         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1243
1244         vdisplay = mode->vdisplay;
1245         vblank = mode->vtotal - mode->vdisplay;
1246         v_de_vs = mode->vsync_start - mode->vdisplay;
1247         vsync_len = mode->vsync_end - mode->vsync_start;
1248
1249         /*
1250          * When we're setting an interlaced mode, we need
1251          * to adjust the vertical timing to suit.
1252          */
1253         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1254                 vdisplay /= 2;
1255                 vblank /= 2;
1256                 v_de_vs /= 2;
1257                 vsync_len /= 2;
1258         }
1259
1260         /* Set up horizontal active pixel width */
1261         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1262         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1263
1264         /* Set up vertical active lines */
1265         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1266         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1267
1268         /* Set up horizontal blanking pixel region width */
1269         hblank = mode->htotal - mode->hdisplay;
1270         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1271         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1272
1273         /* Set up vertical blanking pixel region width */
1274         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1275
1276         /* Set up HSYNC active edge delay width (in pixel clks) */
1277         h_de_hs = mode->hsync_start - mode->hdisplay;
1278         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1279         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1280
1281         /* Set up VSYNC active edge delay (in lines) */
1282         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1283
1284         /* Set up HSYNC active pulse width (in pixel clks) */
1285         hsync_len = mode->hsync_end - mode->hsync_start;
1286         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1287         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1288
1289         /* Set up VSYNC active edge delay (in lines) */
1290         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1291 }
1292
1293 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1294 {
1295         if (!hdmi->phy_enabled)
1296                 return;
1297
1298         dw_hdmi_phy_enable_tmds(hdmi, 0);
1299         dw_hdmi_phy_enable_powerdown(hdmi, true);
1300
1301         hdmi->phy_enabled = false;
1302 }
1303
1304 /* HDMI Initialization Step B.4 */
1305 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1306 {
1307         u8 clkdis;
1308
1309         /* control period minimum duration */
1310         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1311         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1312         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1313
1314         /* Set to fill TMDS data channels */
1315         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1316         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1317         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1318
1319         /* Enable pixel clock and tmds data path */
1320         clkdis = 0x7F;
1321         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1322         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1323
1324         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1325         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1326
1327         /* Enable csc path */
1328         if (is_color_space_conversion(hdmi)) {
1329                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1330                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1331         }
1332 }
1333
1334 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1335 {
1336         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1337 }
1338
1339 /* Workaround to clear the overflow condition */
1340 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1341 {
1342         unsigned int count;
1343         unsigned int i;
1344         u8 val;
1345
1346         /*
1347          * Under some circumstances the Frame Composer arithmetic unit can miss
1348          * an FC register write due to being busy processing the previous one.
1349          * The issue can be worked around by issuing a TMDS software reset and
1350          * then write one of the FC registers several times.
1351          *
1352          * The number of iterations matters and depends on the HDMI TX revision
1353          * (and possibly on the platform). So far only i.MX6Q (v1.30a) and
1354          * i.MX6DL (v1.31a) have been identified as needing the workaround, with
1355          * 4 and 1 iterations respectively.
1356          */
1357
1358         switch (hdmi->version) {
1359         case 0x130a:
1360                 count = 4;
1361                 break;
1362         case 0x131a:
1363                 count = 1;
1364                 break;
1365         default:
1366                 return;
1367         }
1368
1369         /* TMDS software reset */
1370         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1371
1372         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1373         for (i = 0; i < count; i++)
1374                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1375 }
1376
1377 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1378 {
1379         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1380         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1381 }
1382
1383 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1384 {
1385         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1386                     HDMI_IH_MUTE_FC_STAT2);
1387 }
1388
1389 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1390 {
1391         int ret;
1392
1393         hdmi_disable_overflow_interrupts(hdmi);
1394
1395         hdmi->vic = drm_match_cea_mode(mode);
1396
1397         if (!hdmi->vic) {
1398                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1399         } else {
1400                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1401         }
1402
1403         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1404             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1405             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1406             (hdmi->vic == 17) || (hdmi->vic == 18))
1407                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1408         else
1409                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1410
1411         hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1412         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1413
1414         /* TODO: Get input format from IPU (via FB driver interface) */
1415         hdmi->hdmi_data.enc_in_format = RGB;
1416
1417         hdmi->hdmi_data.enc_out_format = RGB;
1418
1419         hdmi->hdmi_data.enc_color_depth = 8;
1420         hdmi->hdmi_data.pix_repet_factor = 0;
1421         hdmi->hdmi_data.hdcp_enable = 0;
1422         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1423
1424         /* HDMI Initialization Step B.1 */
1425         hdmi_av_composer(hdmi, mode);
1426
1427         /* HDMI Initializateion Step B.2 */
1428         ret = dw_hdmi_phy_init(hdmi);
1429         if (ret)
1430                 return ret;
1431
1432         /* HDMI Initialization Step B.3 */
1433         dw_hdmi_enable_video_path(hdmi);
1434
1435         if (hdmi->sink_has_audio) {
1436                 dev_dbg(hdmi->dev, "sink has audio support\n");
1437
1438                 /* HDMI Initialization Step E - Configure audio */
1439                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1440                 hdmi_enable_audio_clk(hdmi);
1441         }
1442
1443         /* not for DVI mode */
1444         if (hdmi->sink_is_hdmi) {
1445                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1446
1447                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1448                 hdmi_config_AVI(hdmi, mode);
1449         } else {
1450                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1451         }
1452
1453         hdmi_video_packetize(hdmi);
1454         hdmi_video_csc(hdmi);
1455         hdmi_video_sample(hdmi);
1456         hdmi_tx_hdcp_config(hdmi);
1457
1458         dw_hdmi_clear_overflow(hdmi);
1459         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1460                 hdmi_enable_overflow_interrupts(hdmi);
1461
1462         return 0;
1463 }
1464
1465 /* Wait until we are registered to enable interrupts */
1466 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1467 {
1468         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1469                     HDMI_PHY_I2CM_INT_ADDR);
1470
1471         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1472                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1473                     HDMI_PHY_I2CM_CTLINT_ADDR);
1474
1475         /* enable cable hot plug irq */
1476         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1477
1478         /* Clear Hotplug interrupts */
1479         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1480                     HDMI_IH_PHY_STAT0);
1481
1482         return 0;
1483 }
1484
1485 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1486 {
1487         u8 ih_mute;
1488
1489         /*
1490          * Boot up defaults are:
1491          * HDMI_IH_MUTE   = 0x03 (disabled)
1492          * HDMI_IH_MUTE_* = 0x00 (enabled)
1493          *
1494          * Disable top level interrupt bits in HDMI block
1495          */
1496         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1497                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1498                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1499
1500         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1501
1502         /* by default mask all interrupts */
1503         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1504         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1505         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1506         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1507         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1508         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1509         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1510         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1511         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1512         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1513         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1514         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1515         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1516         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1517         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1518
1519         /* Disable interrupts in the IH_MUTE_* registers */
1520         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1521         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1522         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1523         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1524         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1525         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1526         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1527         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1528         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1529         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1530
1531         /* Enable top level interrupt bits in HDMI block */
1532         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1533                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1534         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1535 }
1536
1537 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1538 {
1539         hdmi->bridge_is_on = true;
1540         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1541 }
1542
1543 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1544 {
1545         dw_hdmi_phy_disable(hdmi);
1546         hdmi->bridge_is_on = false;
1547 }
1548
1549 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1550 {
1551         int force = hdmi->force;
1552
1553         if (hdmi->disabled) {
1554                 force = DRM_FORCE_OFF;
1555         } else if (force == DRM_FORCE_UNSPECIFIED) {
1556                 if (hdmi->rxsense)
1557                         force = DRM_FORCE_ON;
1558                 else
1559                         force = DRM_FORCE_OFF;
1560         }
1561
1562         if (force == DRM_FORCE_OFF) {
1563                 if (hdmi->bridge_is_on)
1564                         dw_hdmi_poweroff(hdmi);
1565         } else {
1566                 if (!hdmi->bridge_is_on)
1567                         dw_hdmi_poweron(hdmi);
1568         }
1569 }
1570
1571 /*
1572  * Adjust the detection of RXSENSE according to whether we have a forced
1573  * connection mode enabled, or whether we have been disabled.  There is
1574  * no point processing RXSENSE interrupts if we have a forced connection
1575  * state, or DRM has us disabled.
1576  *
1577  * We also disable rxsense interrupts when we think we're disconnected
1578  * to avoid floating TDMS signals giving false rxsense interrupts.
1579  *
1580  * Note: we still need to listen for HPD interrupts even when DRM has us
1581  * disabled so that we can detect a connect event.
1582  */
1583 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1584 {
1585         u8 old_mask = hdmi->phy_mask;
1586
1587         if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1588                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1589         else
1590                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1591
1592         if (old_mask != hdmi->phy_mask)
1593                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1594 }
1595
1596 static enum drm_connector_status
1597 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1598 {
1599         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1600                                              connector);
1601
1602         mutex_lock(&hdmi->mutex);
1603         hdmi->force = DRM_FORCE_UNSPECIFIED;
1604         dw_hdmi_update_power(hdmi);
1605         dw_hdmi_update_phy_mask(hdmi);
1606         mutex_unlock(&hdmi->mutex);
1607
1608         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1609                 connector_status_connected : connector_status_disconnected;
1610 }
1611
1612 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1613 {
1614         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1615                                              connector);
1616         struct edid *edid;
1617         int ret = 0;
1618
1619         if (!hdmi->ddc)
1620                 return 0;
1621
1622         edid = drm_get_edid(connector, hdmi->ddc);
1623         if (edid) {
1624                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1625                         edid->width_cm, edid->height_cm);
1626
1627                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1628                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1629                 drm_mode_connector_update_edid_property(connector, edid);
1630                 ret = drm_add_edid_modes(connector, edid);
1631                 /* Store the ELD */
1632                 drm_edid_to_eld(connector, edid);
1633                 kfree(edid);
1634         } else {
1635                 dev_dbg(hdmi->dev, "failed to get edid\n");
1636         }
1637
1638         return ret;
1639 }
1640
1641 static enum drm_mode_status
1642 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1643                              struct drm_display_mode *mode)
1644 {
1645         struct dw_hdmi *hdmi = container_of(connector,
1646                                            struct dw_hdmi, connector);
1647         enum drm_mode_status mode_status = MODE_OK;
1648
1649         /* We don't support double-clocked modes */
1650         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1651                 return MODE_BAD;
1652
1653         if (hdmi->plat_data->mode_valid)
1654                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1655
1656         return mode_status;
1657 }
1658
1659 static void dw_hdmi_connector_force(struct drm_connector *connector)
1660 {
1661         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1662                                              connector);
1663
1664         mutex_lock(&hdmi->mutex);
1665         hdmi->force = connector->force;
1666         dw_hdmi_update_power(hdmi);
1667         dw_hdmi_update_phy_mask(hdmi);
1668         mutex_unlock(&hdmi->mutex);
1669 }
1670
1671 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1672         .dpms = drm_atomic_helper_connector_dpms,
1673         .fill_modes = drm_helper_probe_single_connector_modes,
1674         .detect = dw_hdmi_connector_detect,
1675         .destroy = drm_connector_cleanup,
1676         .force = dw_hdmi_connector_force,
1677         .reset = drm_atomic_helper_connector_reset,
1678         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1679         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1680 };
1681
1682 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1683         .get_modes = dw_hdmi_connector_get_modes,
1684         .mode_valid = dw_hdmi_connector_mode_valid,
1685         .best_encoder = drm_atomic_helper_best_encoder,
1686 };
1687
1688 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
1689 {
1690         struct dw_hdmi *hdmi = bridge->driver_private;
1691         struct drm_encoder *encoder = bridge->encoder;
1692         struct drm_connector *connector = &hdmi->connector;
1693
1694         connector->interlace_allowed = 1;
1695         connector->polled = DRM_CONNECTOR_POLL_HPD;
1696
1697         drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
1698
1699         drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
1700                            DRM_MODE_CONNECTOR_HDMIA);
1701
1702         drm_mode_connector_attach_encoder(connector, encoder);
1703
1704         return 0;
1705 }
1706
1707 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1708                                     struct drm_display_mode *orig_mode,
1709                                     struct drm_display_mode *mode)
1710 {
1711         struct dw_hdmi *hdmi = bridge->driver_private;
1712
1713         mutex_lock(&hdmi->mutex);
1714
1715         /* Store the display mode for plugin/DKMS poweron events */
1716         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1717
1718         mutex_unlock(&hdmi->mutex);
1719 }
1720
1721 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1722 {
1723         struct dw_hdmi *hdmi = bridge->driver_private;
1724
1725         mutex_lock(&hdmi->mutex);
1726         hdmi->disabled = true;
1727         dw_hdmi_update_power(hdmi);
1728         dw_hdmi_update_phy_mask(hdmi);
1729         mutex_unlock(&hdmi->mutex);
1730 }
1731
1732 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1733 {
1734         struct dw_hdmi *hdmi = bridge->driver_private;
1735
1736         mutex_lock(&hdmi->mutex);
1737         hdmi->disabled = false;
1738         dw_hdmi_update_power(hdmi);
1739         dw_hdmi_update_phy_mask(hdmi);
1740         mutex_unlock(&hdmi->mutex);
1741 }
1742
1743 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1744         .attach = dw_hdmi_bridge_attach,
1745         .enable = dw_hdmi_bridge_enable,
1746         .disable = dw_hdmi_bridge_disable,
1747         .mode_set = dw_hdmi_bridge_mode_set,
1748 };
1749
1750 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
1751 {
1752         struct dw_hdmi_i2c *i2c = hdmi->i2c;
1753         unsigned int stat;
1754
1755         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
1756         if (!stat)
1757                 return IRQ_NONE;
1758
1759         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
1760
1761         i2c->stat = stat;
1762
1763         complete(&i2c->cmp);
1764
1765         return IRQ_HANDLED;
1766 }
1767
1768 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1769 {
1770         struct dw_hdmi *hdmi = dev_id;
1771         u8 intr_stat;
1772         irqreturn_t ret = IRQ_NONE;
1773
1774         if (hdmi->i2c)
1775                 ret = dw_hdmi_i2c_irq(hdmi);
1776
1777         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1778         if (intr_stat) {
1779                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1780                 return IRQ_WAKE_THREAD;
1781         }
1782
1783         return ret;
1784 }
1785
1786 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1787 {
1788         struct dw_hdmi *hdmi = dev_id;
1789         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
1790
1791         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1792         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1793         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1794
1795         phy_pol_mask = 0;
1796         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1797                 phy_pol_mask |= HDMI_PHY_HPD;
1798         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
1799                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
1800         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
1801                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
1802         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
1803                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
1804         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
1805                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
1806
1807         if (phy_pol_mask)
1808                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
1809
1810         /*
1811          * RX sense tells us whether the TDMS transmitters are detecting
1812          * load - in other words, there's something listening on the
1813          * other end of the link.  Use this to decide whether we should
1814          * power on the phy as HPD may be toggled by the sink to merely
1815          * ask the source to re-read the EDID.
1816          */
1817         if (intr_stat &
1818             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
1819                 mutex_lock(&hdmi->mutex);
1820                 if (!hdmi->disabled && !hdmi->force) {
1821                         /*
1822                          * If the RX sense status indicates we're disconnected,
1823                          * clear the software rxsense status.
1824                          */
1825                         if (!(phy_stat & HDMI_PHY_RX_SENSE))
1826                                 hdmi->rxsense = false;
1827
1828                         /*
1829                          * Only set the software rxsense status when both
1830                          * rxsense and hpd indicates we're connected.
1831                          * This avoids what seems to be bad behaviour in
1832                          * at least iMX6S versions of the phy.
1833                          */
1834                         if (phy_stat & HDMI_PHY_HPD)
1835                                 hdmi->rxsense = true;
1836
1837                         dw_hdmi_update_power(hdmi);
1838                         dw_hdmi_update_phy_mask(hdmi);
1839                 }
1840                 mutex_unlock(&hdmi->mutex);
1841         }
1842
1843         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1844                 dev_dbg(hdmi->dev, "EVENT=%s\n",
1845                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
1846                 if (hdmi->bridge.dev)
1847                         drm_helper_hpd_irq_event(hdmi->bridge.dev);
1848         }
1849
1850         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1851         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1852                     HDMI_IH_MUTE_PHY_STAT0);
1853
1854         return IRQ_HANDLED;
1855 }
1856
1857 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
1858         {
1859                 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
1860                 .name = "DWC HDMI TX PHY",
1861         }, {
1862                 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
1863                 .name = "DWC MHL PHY + HEAC PHY",
1864                 .has_svsret = true,
1865         }, {
1866                 .type = DW_HDMI_PHY_DWC_MHL_PHY,
1867                 .name = "DWC MHL PHY",
1868                 .has_svsret = true,
1869         }, {
1870                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
1871                 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
1872         }, {
1873                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
1874                 .name = "DWC HDMI 3D TX PHY",
1875         }, {
1876                 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
1877                 .name = "DWC HDMI 2.0 TX PHY",
1878                 .has_svsret = true,
1879         }
1880 };
1881
1882 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
1883 {
1884         unsigned int i;
1885         u8 phy_type;
1886
1887         phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID);
1888
1889         for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
1890                 if (dw_hdmi_phys[i].type == phy_type) {
1891                         hdmi->phy = &dw_hdmi_phys[i];
1892                         return 0;
1893                 }
1894         }
1895
1896         if (phy_type == DW_HDMI_PHY_VENDOR_PHY)
1897                 dev_err(hdmi->dev, "Unsupported vendor HDMI PHY\n");
1898         else
1899                 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n",
1900                         phy_type);
1901
1902         return -ENODEV;
1903 }
1904
1905 static struct dw_hdmi *
1906 __dw_hdmi_probe(struct platform_device *pdev,
1907                 const struct dw_hdmi_plat_data *plat_data)
1908 {
1909         struct device *dev = &pdev->dev;
1910         struct device_node *np = dev->of_node;
1911         struct platform_device_info pdevinfo;
1912         struct device_node *ddc_node;
1913         struct dw_hdmi *hdmi;
1914         struct resource *iores;
1915         int irq;
1916         int ret;
1917         u32 val = 1;
1918         u8 prod_id0;
1919         u8 prod_id1;
1920         u8 config0;
1921         u8 config3;
1922
1923         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1924         if (!hdmi)
1925                 return ERR_PTR(-ENOMEM);
1926
1927         hdmi->plat_data = plat_data;
1928         hdmi->dev = dev;
1929         hdmi->dev_type = plat_data->dev_type;
1930         hdmi->sample_rate = 48000;
1931         hdmi->disabled = true;
1932         hdmi->rxsense = true;
1933         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
1934
1935         mutex_init(&hdmi->mutex);
1936         mutex_init(&hdmi->audio_mutex);
1937         spin_lock_init(&hdmi->audio_lock);
1938
1939         of_property_read_u32(np, "reg-io-width", &val);
1940
1941         switch (val) {
1942         case 4:
1943                 hdmi->write = dw_hdmi_writel;
1944                 hdmi->read = dw_hdmi_readl;
1945                 break;
1946         case 1:
1947                 hdmi->write = dw_hdmi_writeb;
1948                 hdmi->read = dw_hdmi_readb;
1949                 break;
1950         default:
1951                 dev_err(dev, "reg-io-width must be 1 or 4\n");
1952                 return ERR_PTR(-EINVAL);
1953         }
1954
1955         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1956         if (ddc_node) {
1957                 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
1958                 of_node_put(ddc_node);
1959                 if (!hdmi->ddc) {
1960                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
1961                         return ERR_PTR(-EPROBE_DEFER);
1962                 }
1963
1964         } else {
1965                 dev_dbg(hdmi->dev, "no ddc property found\n");
1966         }
1967
1968         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1969         hdmi->regs = devm_ioremap_resource(dev, iores);
1970         if (IS_ERR(hdmi->regs)) {
1971                 ret = PTR_ERR(hdmi->regs);
1972                 goto err_res;
1973         }
1974
1975         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1976         if (IS_ERR(hdmi->isfr_clk)) {
1977                 ret = PTR_ERR(hdmi->isfr_clk);
1978                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1979                 goto err_res;
1980         }
1981
1982         ret = clk_prepare_enable(hdmi->isfr_clk);
1983         if (ret) {
1984                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1985                 goto err_res;
1986         }
1987
1988         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1989         if (IS_ERR(hdmi->iahb_clk)) {
1990                 ret = PTR_ERR(hdmi->iahb_clk);
1991                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1992                 goto err_isfr;
1993         }
1994
1995         ret = clk_prepare_enable(hdmi->iahb_clk);
1996         if (ret) {
1997                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1998                 goto err_isfr;
1999         }
2000
2001         /* Product and revision IDs */
2002         hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2003                       | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
2004         prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
2005         prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
2006
2007         if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
2008             (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
2009                 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
2010                         hdmi->version, prod_id0, prod_id1);
2011                 ret = -ENODEV;
2012                 goto err_iahb;
2013         }
2014
2015         ret = dw_hdmi_detect_phy(hdmi);
2016         if (ret < 0)
2017                 goto err_iahb;
2018
2019         dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
2020                  hdmi->version >> 12, hdmi->version & 0xfff,
2021                  prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
2022                  hdmi->phy->name);
2023
2024         initialize_hdmi_ih_mutes(hdmi);
2025
2026         irq = platform_get_irq(pdev, 0);
2027         if (irq < 0) {
2028                 ret = irq;
2029                 goto err_iahb;
2030         }
2031
2032         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2033                                         dw_hdmi_irq, IRQF_SHARED,
2034                                         dev_name(dev), hdmi);
2035         if (ret)
2036                 goto err_iahb;
2037
2038         /*
2039          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2040          * N and cts values before enabling phy
2041          */
2042         hdmi_init_clk_regenerator(hdmi);
2043
2044         /* If DDC bus is not specified, try to register HDMI I2C bus */
2045         if (!hdmi->ddc) {
2046                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2047                 if (IS_ERR(hdmi->ddc))
2048                         hdmi->ddc = NULL;
2049         }
2050
2051         /*
2052          * Configure registers related to HDMI interrupt
2053          * generation before registering IRQ.
2054          */
2055         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
2056
2057         /* Clear Hotplug interrupts */
2058         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
2059                     HDMI_IH_PHY_STAT0);
2060
2061         hdmi->bridge.driver_private = hdmi;
2062         hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
2063         hdmi->bridge.of_node = pdev->dev.of_node;
2064
2065         ret = dw_hdmi_fb_registered(hdmi);
2066         if (ret)
2067                 goto err_iahb;
2068
2069         /* Unmute interrupts */
2070         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2071                     HDMI_IH_MUTE_PHY_STAT0);
2072
2073         memset(&pdevinfo, 0, sizeof(pdevinfo));
2074         pdevinfo.parent = dev;
2075         pdevinfo.id = PLATFORM_DEVID_AUTO;
2076
2077         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2078         config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
2079
2080         if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
2081                 struct dw_hdmi_audio_data audio;
2082
2083                 audio.phys = iores->start;
2084                 audio.base = hdmi->regs;
2085                 audio.irq = irq;
2086                 audio.hdmi = hdmi;
2087                 audio.eld = hdmi->connector.eld;
2088
2089                 pdevinfo.name = "dw-hdmi-ahb-audio";
2090                 pdevinfo.data = &audio;
2091                 pdevinfo.size_data = sizeof(audio);
2092                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2093                 hdmi->audio = platform_device_register_full(&pdevinfo);
2094         } else if (config0 & HDMI_CONFIG0_I2S) {
2095                 struct dw_hdmi_i2s_audio_data audio;
2096
2097                 audio.hdmi      = hdmi;
2098                 audio.write     = hdmi_writeb;
2099                 audio.read      = hdmi_readb;
2100
2101                 pdevinfo.name = "dw-hdmi-i2s-audio";
2102                 pdevinfo.data = &audio;
2103                 pdevinfo.size_data = sizeof(audio);
2104                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2105                 hdmi->audio = platform_device_register_full(&pdevinfo);
2106         }
2107
2108         /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
2109         if (hdmi->i2c)
2110                 dw_hdmi_i2c_init(hdmi);
2111
2112         platform_set_drvdata(pdev, hdmi);
2113
2114         return hdmi;
2115
2116 err_iahb:
2117         if (hdmi->i2c) {
2118                 i2c_del_adapter(&hdmi->i2c->adap);
2119                 hdmi->ddc = NULL;
2120         }
2121
2122         clk_disable_unprepare(hdmi->iahb_clk);
2123 err_isfr:
2124         clk_disable_unprepare(hdmi->isfr_clk);
2125 err_res:
2126         i2c_put_adapter(hdmi->ddc);
2127
2128         return ERR_PTR(ret);
2129 }
2130
2131 static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
2132 {
2133         if (hdmi->audio && !IS_ERR(hdmi->audio))
2134                 platform_device_unregister(hdmi->audio);
2135
2136         /* Disable all interrupts */
2137         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2138
2139         clk_disable_unprepare(hdmi->iahb_clk);
2140         clk_disable_unprepare(hdmi->isfr_clk);
2141
2142         if (hdmi->i2c)
2143                 i2c_del_adapter(&hdmi->i2c->adap);
2144         else
2145                 i2c_put_adapter(hdmi->ddc);
2146 }
2147
2148 /* -----------------------------------------------------------------------------
2149  * Probe/remove API, used from platforms based on the DRM bridge API.
2150  */
2151 int dw_hdmi_probe(struct platform_device *pdev,
2152                   const struct dw_hdmi_plat_data *plat_data)
2153 {
2154         struct dw_hdmi *hdmi;
2155         int ret;
2156
2157         hdmi = __dw_hdmi_probe(pdev, plat_data);
2158         if (IS_ERR(hdmi))
2159                 return PTR_ERR(hdmi);
2160
2161         ret = drm_bridge_add(&hdmi->bridge);
2162         if (ret < 0) {
2163                 __dw_hdmi_remove(hdmi);
2164                 return ret;
2165         }
2166
2167         return 0;
2168 }
2169 EXPORT_SYMBOL_GPL(dw_hdmi_probe);
2170
2171 void dw_hdmi_remove(struct platform_device *pdev)
2172 {
2173         struct dw_hdmi *hdmi = platform_get_drvdata(pdev);
2174
2175         drm_bridge_remove(&hdmi->bridge);
2176
2177         __dw_hdmi_remove(hdmi);
2178 }
2179 EXPORT_SYMBOL_GPL(dw_hdmi_remove);
2180
2181 /* -----------------------------------------------------------------------------
2182  * Bind/unbind API, used from platforms based on the component framework.
2183  */
2184 int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
2185                  const struct dw_hdmi_plat_data *plat_data)
2186 {
2187         struct dw_hdmi *hdmi;
2188         int ret;
2189
2190         hdmi = __dw_hdmi_probe(pdev, plat_data);
2191         if (IS_ERR(hdmi))
2192                 return PTR_ERR(hdmi);
2193
2194         ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
2195         if (ret) {
2196                 dw_hdmi_remove(pdev);
2197                 DRM_ERROR("Failed to initialize bridge with drm\n");
2198                 return ret;
2199         }
2200
2201         return 0;
2202 }
2203 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2204
2205 void dw_hdmi_unbind(struct device *dev)
2206 {
2207         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2208
2209         __dw_hdmi_remove(hdmi);
2210 }
2211 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2212
2213 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2214 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2215 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2216 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2217 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2218 MODULE_LICENSE("GPL");
2219 MODULE_ALIAS("platform:dw-hdmi");