drivers/gpu/drm/bridge/dw_hdmi-ahb-audio.c

   1 /*
   2  * DesignWare HDMI audio driver
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Written and tested against the Designware HDMI Tx found in iMX6.
   9  */
  10 #include <linux/io.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <drm/bridge/dw_hdmi.h>
  15 #include <drm/drm_edid.h>
  16
  17 #include <sound/asoundef.h>
  18 #include <sound/core.h>
  19 #include <sound/initval.h>
  20 #include <sound/pcm.h>
  21 #include <sound/pcm_drm_eld.h>
  22 #include <sound/pcm_iec958.h>
  23
  24 #include "dw_hdmi-audio.h"
  25
  26 #define DRIVER_NAME "dw-hdmi-ahb-audio"
  27
  28 /* Provide some bits rather than bit offsets */
  29 enum {
  30         HDMI_AHB_DMA_CONF0_SW_FIFO_RST = BIT(7),
  31         HDMI_AHB_DMA_CONF0_EN_HLOCK = BIT(3),
  32         HDMI_AHB_DMA_START_START = BIT(0),
  33         HDMI_AHB_DMA_STOP_STOP = BIT(0),
  34         HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = BIT(5),
  35         HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = BIT(4),
  36         HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = BIT(3),
  37         HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = BIT(2),
  38         HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = BIT(1),
  39         HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = BIT(0),
  40         HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL =
  41                 HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR |
  42                 HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST |
  43                 HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY |
  44                 HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE |
  45                 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL |
  46                 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY,
  47         HDMI_IH_AHBDMAAUD_STAT0_ERROR = BIT(5),
  48         HDMI_IH_AHBDMAAUD_STAT0_LOST = BIT(4),
  49         HDMI_IH_AHBDMAAUD_STAT0_RETRY = BIT(3),
  50         HDMI_IH_AHBDMAAUD_STAT0_DONE = BIT(2),
  51         HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = BIT(1),
  52         HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = BIT(0),
  53         HDMI_IH_AHBDMAAUD_STAT0_ALL =
  54                 HDMI_IH_AHBDMAAUD_STAT0_ERROR |
  55                 HDMI_IH_AHBDMAAUD_STAT0_LOST |
  56                 HDMI_IH_AHBDMAAUD_STAT0_RETRY |
  57                 HDMI_IH_AHBDMAAUD_STAT0_DONE |
  58                 HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL |
  59                 HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY,
  60         HDMI_AHB_DMA_CONF0_INCR16 = 2 << 1,
  61         HDMI_AHB_DMA_CONF0_INCR8 = 1 << 1,
  62         HDMI_AHB_DMA_CONF0_INCR4 = 0,
  63         HDMI_AHB_DMA_CONF0_BURST_MODE = BIT(0),
  64         HDMI_AHB_DMA_MASK_DONE = BIT(7),
  65         HDMI_REVISION_ID = 0x0001,
  66         HDMI_IH_AHBDMAAUD_STAT0 = 0x0109,
  67         HDMI_IH_MUTE_AHBDMAAUD_STAT0 = 0x0189,
  68         HDMI_AHB_DMA_CONF0 = 0x3600,
  69         HDMI_AHB_DMA_START = 0x3601,
  70         HDMI_AHB_DMA_STOP = 0x3602,
  71         HDMI_AHB_DMA_THRSLD = 0x3603,
  72         HDMI_AHB_DMA_STRADDR0 = 0x3604,
  73         HDMI_AHB_DMA_STPADDR0 = 0x3608,
  74         HDMI_AHB_DMA_MASK = 0x3614,
  75         HDMI_AHB_DMA_POL = 0x3615,
  76         HDMI_AHB_DMA_CONF1 = 0x3616,
  77         HDMI_AHB_DMA_BUFFPOL = 0x361a,
  78 };
  79
  80 struct snd_dw_hdmi {
  81         struct snd_card *card;
  82         struct snd_pcm *pcm;
  83         spinlock_t lock;
  84         struct dw_hdmi_audio_data data;
  85         struct snd_pcm_substream *substream;
  86         void (*reformat)(struct snd_dw_hdmi *, size_t, size_t);
  87         void *buf_src;
  88         void *buf_dst;
  89         dma_addr_t buf_addr;
  90         unsigned buf_offset;
  91         unsigned buf_period;
  92         unsigned buf_size;
  93         unsigned channels;
  94         u8 revision;
  95         u8 iec_offset;
  96         u8 cs[192][8];
  97 };
  98
  99 static void dw_hdmi_writel(u32 val, void __iomem *ptr)
 100 {
 101         writeb_relaxed(val, ptr);
 102         writeb_relaxed(val >> 8, ptr + 1);
 103         writeb_relaxed(val >> 16, ptr + 2);
 104         writeb_relaxed(val >> 24, ptr + 3);
 105 }
 106
 107 /*
 108  * Convert to hardware format: The userspace buffer contains IEC958 samples,
 109  * with the PCUV bits in bits 31..28 and audio samples in bits 27..4.  We
 110  * need these to be in bits 27..24, with the IEC B bit in bit 28, and audio
 111  * samples in 23..0.
 112  *
 113  * Default preamble in bits 3..0: 8 = block start, 4 = even 2 = odd
 114  *
 115  * Ideally, we could do with having the data properly formatted in userspace.
 116  */
 117 static void dw_hdmi_reformat_iec958(struct snd_dw_hdmi *dw,
 118         size_t offset, size_t bytes)
 119 {
 120         u32 *src = dw->buf_src + offset;
 121         u32 *dst = dw->buf_dst + offset;
 122         u32 *end = dw->buf_src + offset + bytes;
 123
 124         do {
 125                 u32 b, sample = *src++;
 126
 127                 b = (sample & 8) << (28 - 3);
 128
 129                 sample >>= 4;
 130
 131                 *dst++ = sample | b;
 132         } while (src < end);
 133 }
 134
 135 static u32 parity(u32 sample)
 136 {
 137         sample ^= sample >> 16;
 138         sample ^= sample >> 8;
 139         sample ^= sample >> 4;
 140         sample ^= sample >> 2;
 141         sample ^= sample >> 1;
 142         return (sample & 1) << 27;
 143 }
 144
 145 static void dw_hdmi_reformat_s24(struct snd_dw_hdmi *dw,
 146         size_t offset, size_t bytes)
 147 {
 148         u32 *src = dw->buf_src + offset;
 149         u32 *dst = dw->buf_dst + offset;
 150         u32 *end = dw->buf_src + offset + bytes;
 151
 152         do {
 153                 unsigned i;
 154                 u8 *cs;
 155
 156                 cs = dw->cs[dw->iec_offset++];
 157                 if (dw->iec_offset >= 192)
 158                         dw->iec_offset = 0;
 159
 160                 i = dw->channels;
 161                 do {
 162                         u32 sample = *src++;
 163
 164                         sample &= ~0xff000000;
 165                         sample |= *cs++ << 24;
 166                         sample |= parity(sample & ~0xf8000000);
 167
 168                         *dst++ = sample;
 169                 } while (--i);
 170         } while (src < end);
 171 }
 172
 173 static void dw_hdmi_create_cs(struct snd_dw_hdmi *dw,
 174         struct snd_pcm_runtime *runtime)
 175 {
 176         u8 cs[4];
 177         unsigned ch, i, j;
 178
 179         snd_pcm_create_iec958_consumer(runtime, cs, sizeof(cs));
 180
 181         memset(dw->cs, 0, sizeof(dw->cs));
 182
 183         for (ch = 0; ch < 8; ch++) {
 184                 cs[2] &= ~IEC958_AES2_CON_CHANNEL;
 185                 cs[2] |= (ch + 1) << 4;
 186
 187                 for (i = 0; i < ARRAY_SIZE(cs); i++) {
 188                         unsigned c = cs[i];
 189
 190                         for (j = 0; j < 8; j++, c >>= 1)
 191                                 dw->cs[i * 8 + j][ch] = (c & 1) << 2;
 192                 }
 193         }
 194         dw->cs[0][0] |= BIT(4);
 195 }
 196
 197 static void dw_hdmi_start_dma(struct snd_dw_hdmi *dw)
 198 {
 199         void __iomem *base = dw->data.base;
 200         unsigned offset = dw->buf_offset;
 201         unsigned period = dw->buf_period;
 202         u32 start, stop;
 203
 204         dw->reformat(dw, offset, period);
 205
 206         /* Clear all irqs before enabling irqs and starting DMA */
 207         writeb_relaxed(HDMI_IH_AHBDMAAUD_STAT0_ALL,
 208                        base + HDMI_IH_AHBDMAAUD_STAT0);
 209
 210         start = dw->buf_addr + offset;
 211         stop = start + period - 1;
 212
 213         /* Setup the hardware start/stop addresses */
 214         dw_hdmi_writel(start, base + HDMI_AHB_DMA_STRADDR0);
 215         dw_hdmi_writel(stop, base + HDMI_AHB_DMA_STPADDR0);
 216
 217         writeb_relaxed((u8)~HDMI_AHB_DMA_MASK_DONE, base + HDMI_AHB_DMA_MASK);
 218         writeb(HDMI_AHB_DMA_START_START, base + HDMI_AHB_DMA_START);
 219
 220         offset += period;
 221         if (offset >= dw->buf_size)
 222                 offset = 0;
 223         dw->buf_offset = offset;
 224 }
 225
 226 static void dw_hdmi_stop_dma(struct snd_dw_hdmi *dw)
 227 {
 228         /* Disable interrupts before disabling DMA */
 229         writeb_relaxed(~0, dw->data.base + HDMI_AHB_DMA_MASK);
 230         writeb_relaxed(HDMI_AHB_DMA_STOP_STOP, dw->data.base + HDMI_AHB_DMA_STOP);
 231 }
 232
 233 static irqreturn_t snd_dw_hdmi_irq(int irq, void *data)
 234 {
 235         struct snd_dw_hdmi *dw = data;
 236         struct snd_pcm_substream *substream;
 237         unsigned stat;
 238
 239         stat = readb_relaxed(dw->data.base + HDMI_IH_AHBDMAAUD_STAT0);
 240         if (!stat)
 241                 return IRQ_NONE;
 242
 243         writeb_relaxed(stat, dw->data.base + HDMI_IH_AHBDMAAUD_STAT0);
 244
 245         substream = dw->substream;
 246         if (stat & HDMI_IH_AHBDMAAUD_STAT0_DONE && substream) {
 247                 snd_pcm_period_elapsed(substream);
 248
 249                 spin_lock(&dw->lock);
 250                 if (dw->substream)
 251                         dw_hdmi_start_dma(dw);
 252                 spin_unlock(&dw->lock);
 253         }
 254
 255         return IRQ_HANDLED;
 256 }
 257
 258 static struct snd_pcm_hardware dw_hdmi_hw = {
 259         .info = SNDRV_PCM_INFO_INTERLEAVED |
 260                 SNDRV_PCM_INFO_BLOCK_TRANSFER |
 261                 SNDRV_PCM_INFO_MMAP |
 262                 SNDRV_PCM_INFO_MMAP_VALID,
 263         .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE |
 264                    SNDRV_PCM_FMTBIT_S24_LE,
 265         .rates = SNDRV_PCM_RATE_32000 |
 266                  SNDRV_PCM_RATE_44100 |
 267                  SNDRV_PCM_RATE_48000 |
 268                  SNDRV_PCM_RATE_88200 |
 269                  SNDRV_PCM_RATE_96000 |
 270                  SNDRV_PCM_RATE_176400 |
 271                  SNDRV_PCM_RATE_192000,
 272         .channels_min = 2,
 273         .channels_max = 8,
 274         .buffer_bytes_max = 64 * 1024,
 275         .period_bytes_min = 256,
 276         .period_bytes_max = 8192,       /* ERR004323: must limit to 8k */
 277         .periods_min = 2,
 278         .periods_max = 16,
 279         .fifo_size = 0,
 280 };
 281
 282 static int dw_hdmi_open(struct snd_pcm_substream *substream)
 283 {
 284         struct snd_pcm_runtime *runtime = substream->runtime;
 285         struct snd_dw_hdmi *dw = substream->private_data;
 286         void __iomem *base = dw->data.base;
 287         int ret;
 288
 289         runtime->hw = dw_hdmi_hw;
 290
 291         ret = snd_pcm_hw_constraint_eld(runtime, dw->data.eld);
 292         if (ret < 0)
 293                 return ret;
 294
 295         ret = snd_pcm_limit_hw_rates(runtime);
 296         if (ret < 0)
 297                 return ret;
 298
 299         ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
 300         if (ret < 0)
 301                 return ret;
 302
 303         /* Clear FIFO */
 304         writeb_relaxed(HDMI_AHB_DMA_CONF0_SW_FIFO_RST,
 305                        base + HDMI_AHB_DMA_CONF0);
 306
 307         /* Configure interrupt polarities */
 308         writeb_relaxed(~0, base + HDMI_AHB_DMA_POL);
 309         writeb_relaxed(~0, base + HDMI_AHB_DMA_BUFFPOL);
 310
 311         /* Keep interrupts masked, and clear any pending */
 312         writeb_relaxed(~0, base + HDMI_AHB_DMA_MASK);
 313         writeb_relaxed(~0, base + HDMI_IH_AHBDMAAUD_STAT0);
 314
 315         ret = request_irq(dw->data.irq, snd_dw_hdmi_irq, IRQF_SHARED,
 316                           "dw-hdmi-audio", dw);
 317         if (ret)
 318                 return ret;
 319
 320         /* Un-mute done interrupt */
 321         writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL &
 322                        ~HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE,
 323                        base + HDMI_IH_MUTE_AHBDMAAUD_STAT0);
 324
 325         return 0;
 326 }
 327
 328 static int dw_hdmi_close(struct snd_pcm_substream *substream)
 329 {
 330         struct snd_dw_hdmi *dw = substream->private_data;
 331
 332         /* Mute all interrupts */
 333         writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL,
 334                        dw->data.base + HDMI_IH_MUTE_AHBDMAAUD_STAT0);
 335
 336         free_irq(dw->data.irq, dw);
 337
 338         return 0;
 339 }
 340
 341 static int dw_hdmi_hw_free(struct snd_pcm_substream *substream)
 342 {
 343         return snd_pcm_lib_free_vmalloc_buffer(substream);
 344 }
 345
 346 static int dw_hdmi_hw_params(struct snd_pcm_substream *substream,
 347         struct snd_pcm_hw_params *params)
 348 {
 349         return snd_pcm_lib_alloc_vmalloc_buffer(substream,
 350                                                 params_buffer_bytes(params));
 351 }
 352
 353 static int dw_hdmi_prepare(struct snd_pcm_substream *substream)
 354 {
 355         struct snd_pcm_runtime *runtime = substream->runtime;
 356         struct snd_dw_hdmi *dw = substream->private_data;
 357         u8 threshold, conf0, conf1;
 358
 359         /* Setup as per 3.0.5 FSL 4.1.0 BSP */
 360         switch (dw->revision) {
 361         case 0x0a:
 362                 conf0 = HDMI_AHB_DMA_CONF0_BURST_MODE |
 363                         HDMI_AHB_DMA_CONF0_INCR4;
 364                 if (runtime->channels == 2)
 365                         threshold = 126;
 366                 else
 367                         threshold = 124;
 368                 break;
 369         case 0x1a:
 370                 conf0 = HDMI_AHB_DMA_CONF0_BURST_MODE |
 371                         HDMI_AHB_DMA_CONF0_INCR8;
 372                 threshold = 128;
 373                 break;
 374         default:
 375                 /* NOTREACHED */
 376                 return -EINVAL;
 377         }
 378
 379         dw_hdmi_set_sample_rate(dw->data.hdmi, runtime->rate);
 380
 381         /* Minimum number of bytes in the fifo. */
 382         runtime->hw.fifo_size = threshold * 32;
 383
 384         conf0 |= HDMI_AHB_DMA_CONF0_EN_HLOCK;
 385         conf1 = (1 << runtime->channels) - 1;
 386
 387         writeb_relaxed(threshold, dw->data.base + HDMI_AHB_DMA_THRSLD);
 388         writeb_relaxed(conf0, dw->data.base + HDMI_AHB_DMA_CONF0);
 389         writeb_relaxed(conf1, dw->data.base + HDMI_AHB_DMA_CONF1);
 390
 391         switch (runtime->format) {
 392         case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
 393                 dw->reformat = dw_hdmi_reformat_iec958;
 394                 break;
 395         case SNDRV_PCM_FORMAT_S24_LE:
 396                 dw_hdmi_create_cs(dw, runtime);
 397                 dw->reformat = dw_hdmi_reformat_s24;
 398                 break;
 399         }
 400         dw->iec_offset = 0;
 401         dw->channels = runtime->channels;
 402         dw->buf_src  = runtime->dma_area;
 403         dw->buf_dst  = substream->dma_buffer.area;
 404         dw->buf_addr = substream->dma_buffer.addr;
 405         dw->buf_period = snd_pcm_lib_period_bytes(substream);
 406         dw->buf_size = snd_pcm_lib_buffer_bytes(substream);
 407
 408         return 0;
 409 }
 410
 411 static int dw_hdmi_trigger(struct snd_pcm_substream *substream, int cmd)
 412 {
 413         struct snd_dw_hdmi *dw = substream->private_data;
 414         unsigned long flags;
 415         int ret = 0;
 416
 417         switch (cmd) {
 418         case SNDRV_PCM_TRIGGER_START:
 419                 spin_lock_irqsave(&dw->lock, flags);
 420                 dw->buf_offset = 0;
 421                 dw->substream = substream;
 422                 dw_hdmi_start_dma(dw);
 423                 dw_hdmi_audio_enable(dw->data.hdmi);
 424                 spin_unlock_irqrestore(&dw->lock, flags);
 425                 substream->runtime->delay = substream->runtime->period_size;
 426                 break;
 427
 428         case SNDRV_PCM_TRIGGER_STOP:
 429                 spin_lock_irqsave(&dw->lock, flags);
 430                 dw->substream = NULL;
 431                 dw_hdmi_stop_dma(dw);
 432                 dw_hdmi_audio_disable(dw->data.hdmi);
 433                 spin_unlock_irqrestore(&dw->lock, flags);
 434                 break;
 435
 436         default:
 437                 ret = -EINVAL;
 438                 break;
 439         }
 440
 441         return ret;
 442 }
 443
 444 static snd_pcm_uframes_t dw_hdmi_pointer(struct snd_pcm_substream *substream)
 445 {
 446         struct snd_pcm_runtime *runtime = substream->runtime;
 447         struct snd_dw_hdmi *dw = substream->private_data;
 448
 449         /*
 450          * We are unable to report the exact hardware position as
 451          * reading the 32-bit DMA position using 8-bit reads is racy.
 452          */
 453         return bytes_to_frames(runtime, dw->buf_offset);
 454 }
 455
 456 static struct snd_pcm_ops snd_dw_hdmi_ops = {
 457         .open = dw_hdmi_open,
 458         .close = dw_hdmi_close,
 459         .ioctl = snd_pcm_lib_ioctl,
 460         .hw_params = dw_hdmi_hw_params,
 461         .hw_free = dw_hdmi_hw_free,
 462         .prepare = dw_hdmi_prepare,
 463         .trigger = dw_hdmi_trigger,
 464         .pointer = dw_hdmi_pointer,
 465         .page = snd_pcm_lib_get_vmalloc_page,
 466 };
 467
 468 static int snd_dw_hdmi_probe(struct platform_device *pdev)
 469 {
 470         const struct dw_hdmi_audio_data *data = pdev->dev.platform_data;
 471         struct device *dev = pdev->dev.parent;
 472         struct snd_dw_hdmi *dw;
 473         struct snd_card *card;
 474         struct snd_pcm *pcm;
 475         unsigned revision;
 476         int ret;
 477
 478         writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL,
 479                        data->base + HDMI_IH_MUTE_AHBDMAAUD_STAT0);
 480         revision = readb_relaxed(data->base + HDMI_REVISION_ID);
 481         if (revision != 0x0a && revision != 0x1a) {
 482                 dev_err(dev, "dw-hdmi-audio: unknown revision 0x%02x\n",
 483                         revision);
 484                 return -ENXIO;
 485         }
 486
 487         ret = snd_card_new(dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
 488                               THIS_MODULE, sizeof(struct snd_dw_hdmi), &card);
 489         if (ret < 0)
 490                 return ret;
 491
 492         strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
 493         strlcpy(card->shortname, "DW-HDMI", sizeof(card->shortname));
 494         snprintf(card->longname, sizeof(card->longname),
 495                  "%s rev 0x%02x, irq %d", card->shortname, revision,
 496                  data->irq);
 497
 498         dw = card->private_data;
 499         dw->card = card;
 500         dw->data = *data;
 501         dw->revision = revision;
 502
 503         spin_lock_init(&dw->lock);
 504
 505         ret = snd_pcm_new(card, "DW HDMI", 0, 1, 0, &pcm);
 506         if (ret < 0)
 507                 goto err;
 508
 509         dw->pcm = pcm;
 510         pcm->private_data = dw;
 511         strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
 512         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dw_hdmi_ops);
 513
 514         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
 515                         dev, 64 * 1024, 64 * 1024);
 516
 517         ret = snd_card_register(card);
 518         if (ret < 0)
 519                 goto err;
 520
 521         platform_set_drvdata(pdev, dw);
 522
 523         return 0;
 524
 525 err:
 526         snd_card_free(card);
 527         return ret;
 528 }
 529
 530 static int snd_dw_hdmi_remove(struct platform_device *pdev)
 531 {
 532         struct snd_dw_hdmi *dw = platform_get_drvdata(pdev);
 533
 534         snd_card_free(dw->card);
 535
 536         return 0;
 537 }
 538
 539 #if defined(CONFIG_PM_SLEEP) && defined(IS_NOT_BROKEN)
 540 /*
 541  * This code is fine, but requires implementation in the dw_hdmi_trigger()
 542  * method which is currently missing as I have no way to test this.
 543  */
 544 static int snd_dw_hdmi_suspend(struct device *dev)
 545 {
 546         struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
 547
 548         snd_power_change_state(dw->card, SNDRV_CTL_POWER_D3cold);
 549         snd_pcm_suspend_all(dw->pcm);
 550
 551         return 0;
 552 }
 553
 554 static int snd_dw_hdmi_resume(struct device *dev)
 555 {
 556         struct snd_dw_hdmi *dw = dev_get_drvdata(dev);
 557
 558         snd_power_change_state(dw->card, SNDRV_CTL_POWER_D0);
 559
 560         return 0;
 561 }
 562
 563 static SIMPLE_DEV_PM_OPS(snd_dw_hdmi_pm, snd_dw_hdmi_suspend,
 564                          snd_dw_hdmi_resume);
 565 #define PM_OPS &snd_dw_hdmi_pm
 566 #else
 567 #define PM_OPS NULL
 568 #endif
 569
 570 static struct platform_driver snd_dw_hdmi_driver = {
 571         .probe  = snd_dw_hdmi_probe,
 572         .remove = snd_dw_hdmi_remove,
 573         .driver = {
 574                 .name = DRIVER_NAME,
 575                 .owner = THIS_MODULE,
 576                 .pm = PM_OPS,
 577         },
 578 };
 579
 580 module_platform_driver(snd_dw_hdmi_driver);
 581
 582 MODULE_AUTHOR("Russell King <rmk+kernel@arm.linux.org.uk>");
 583 MODULE_DESCRIPTION("Synopsis Designware HDMI AHB ALSA interface");
 584 MODULE_LICENSE("GPL v2");
 585 MODULE_ALIAS("platform:" DRIVER_NAME);