drivers/gpu/drm/bridge/dw_hdmi.c

   1 /*
   2  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * Designware High-Definition Multimedia Interface (HDMI) driver
  10  *
  11  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  12  */
  13 #include <linux/module.h>
  14 #include <linux/irq.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/hdmi.h>
  19 #include <linux/mutex.h>
  20 #include <linux/of_device.h>
  21 #include <linux/spinlock.h>
  22
  23 #include <drm/drm_of.h>
  24 #include <drm/drmP.h>
  25 #include <drm/drm_crtc_helper.h>
  26 #include <drm/drm_edid.h>
  27 #include <drm/drm_encoder_slave.h>
  28 #include <drm/bridge/dw_hdmi.h>
  29
  30 #include "dw_hdmi.h"
  31 #include "dw_hdmi-audio.h"
  32
  33 #define HDMI_EDID_LEN           512
  34
  35 #define RGB                     0
  36 #define YCBCR444                1
  37 #define YCBCR422_16BITS         2
  38 #define YCBCR422_8BITS          3
  39 #define XVYCC444                4
  40
  41 enum hdmi_datamap {
  42         RGB444_8B = 0x01,
  43         RGB444_10B = 0x03,
  44         RGB444_12B = 0x05,
  45         RGB444_16B = 0x07,
  46         YCbCr444_8B = 0x09,
  47         YCbCr444_10B = 0x0B,
  48         YCbCr444_12B = 0x0D,
  49         YCbCr444_16B = 0x0F,
  50         YCbCr422_8B = 0x16,
  51         YCbCr422_10B = 0x14,
  52         YCbCr422_12B = 0x12,
  53 };
  54
  55 static const u16 csc_coeff_default[3][4] = {
  56         { 0x2000, 0x0000, 0x0000, 0x0000 },
  57         { 0x0000, 0x2000, 0x0000, 0x0000 },
  58         { 0x0000, 0x0000, 0x2000, 0x0000 }
  59 };
  60
  61 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  62         { 0x2000, 0x6926, 0x74fd, 0x010e },
  63         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  64         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  65 };
  66
  67 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  68         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  69         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  70         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  71 };
  72
  73 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  74         { 0x2591, 0x1322, 0x074b, 0x0000 },
  75         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  76         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  77 };
  78
  79 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  80         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  81         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  82         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  83 };
  84
  85 struct hdmi_vmode {
  86         bool mdataenablepolarity;
  87
  88         unsigned int mpixelclock;
  89         unsigned int mpixelrepetitioninput;
  90         unsigned int mpixelrepetitionoutput;
  91 };
  92
  93 struct hdmi_data_info {
  94         unsigned int enc_in_format;
  95         unsigned int enc_out_format;
  96         unsigned int enc_color_depth;
  97         unsigned int colorimetry;
  98         unsigned int pix_repet_factor;
  99         unsigned int hdcp_enable;
 100         struct hdmi_vmode video_mode;
 101 };
 102
 103 struct dw_hdmi {
 104         struct drm_connector connector;
 105         struct drm_encoder *encoder;
 106         struct drm_bridge *bridge;
 107
 108         struct platform_device *audio;
 109         enum dw_hdmi_devtype dev_type;
 110         struct device *dev;
 111         struct clk *isfr_clk;
 112         struct clk *iahb_clk;
 113
 114         struct hdmi_data_info hdmi_data;
 115         const struct dw_hdmi_plat_data *plat_data;
 116
 117         int vic;
 118
 119         u8 edid[HDMI_EDID_LEN];
 120         bool cable_plugin;
 121
 122         bool phy_enabled;
 123         struct drm_display_mode previous_mode;
 124
 125         struct i2c_adapter *ddc;
 126         void __iomem *regs;
 127         bool sink_is_hdmi;
 128         bool sink_has_audio;
 129
 130         struct mutex mutex;             /* for state below and previous_mode */
 131         enum drm_connector_force force; /* mutex-protected force state */
 132         bool disabled;                  /* DRM has disabled our bridge */
 133         bool bridge_is_on;              /* indicates the bridge is on */
 134         bool rxsense;                   /* rxsense state */
 135         u8 phy_mask;                    /* desired phy int mask settings */
 136
 137         spinlock_t audio_lock;
 138         struct mutex audio_mutex;
 139         unsigned int sample_rate;
 140         unsigned int audio_cts;
 141         unsigned int audio_n;
 142         bool audio_enable;
 143
 144         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 145         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 146 };
 147
 148 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 149         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 150          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 151
 152 #define HDMI_PHY_RX_SENSE \
 153         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 154          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 155
 156 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 157 {
 158         writel(val, hdmi->regs + (offset << 2));
 159 }
 160
 161 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 162 {
 163         return readl(hdmi->regs + (offset << 2));
 164 }
 165
 166 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 167 {
 168         writeb(val, hdmi->regs + offset);
 169 }
 170
 171 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 172 {
 173         return readb(hdmi->regs + offset);
 174 }
 175
 176 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 177 {
 178         hdmi->write(hdmi, val, offset);
 179 }
 180
 181 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 182 {
 183         return hdmi->read(hdmi, offset);
 184 }
 185
 186 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 187 {
 188         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 189
 190         val |= data & mask;
 191         hdmi_writeb(hdmi, val, reg);
 192 }
 193
 194 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 195                              u8 shift, u8 mask)
 196 {
 197         hdmi_modb(hdmi, data << shift, mask, reg);
 198 }
 199
 200 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 201                            unsigned int n)
 202 {
 203         /* Must be set/cleared first */
 204         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 205
 206         /* nshift factor = 0 */
 207         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 208
 209         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 210                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 211         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 212         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 213
 214         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 215         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 216         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 217 }
 218
 219 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
 220 {
 221         unsigned int n = (128 * freq) / 1000;
 222         unsigned int mult = 1;
 223
 224         while (freq > 48000) {
 225                 mult *= 2;
 226                 freq /= 2;
 227         }
 228
 229         switch (freq) {
 230         case 32000:
 231                 if (pixel_clk == 25175000)
 232                         n = 4576;
 233                 else if (pixel_clk == 27027000)
 234                         n = 4096;
 235                 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
 236                         n = 11648;
 237                 else
 238                         n = 4096;
 239                 n *= mult;
 240                 break;
 241
 242         case 44100:
 243                 if (pixel_clk == 25175000)
 244                         n = 7007;
 245                 else if (pixel_clk == 74176000)
 246                         n = 17836;
 247                 else if (pixel_clk == 148352000)
 248                         n = 8918;
 249                 else
 250                         n = 6272;
 251                 n *= mult;
 252                 break;
 253
 254         case 48000:
 255                 if (pixel_clk == 25175000)
 256                         n = 6864;
 257                 else if (pixel_clk == 27027000)
 258                         n = 6144;
 259                 else if (pixel_clk == 74176000)
 260                         n = 11648;
 261                 else if (pixel_clk == 148352000)
 262                         n = 5824;
 263                 else
 264                         n = 6144;
 265                 n *= mult;
 266                 break;
 267
 268         default:
 269                 break;
 270         }
 271
 272         return n;
 273 }
 274
 275 static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk)
 276 {
 277         unsigned int cts = 0;
 278
 279         pr_debug("%s: freq: %d pixel_clk: %ld\n", __func__, freq, pixel_clk);
 280
 281         switch (freq) {
 282         case 32000:
 283                 if (pixel_clk == 297000000) {
 284                         cts = 222750;
 285                         break;
 286                 }
 287         case 48000:
 288         case 96000:
 289         case 192000:
 290                 switch (pixel_clk) {
 291                 case 25200000:
 292                 case 27000000:
 293                 case 54000000:
 294                 case 74250000:
 295                 case 148500000:
 296                         cts = pixel_clk / 1000;
 297                         break;
 298                 case 297000000:
 299                         cts = 247500;
 300                         break;
 301                 /*
 302                  * All other TMDS clocks are not supported by
 303                  * DWC_hdmi_tx. The TMDS clocks divided or
 304                  * multiplied by 1,001 coefficients are not
 305                  * supported.
 306                  */
 307                 default:
 308                         break;
 309                 }
 310                 break;
 311         case 44100:
 312         case 88200:
 313         case 176400:
 314                 switch (pixel_clk) {
 315                 case 25200000:
 316                         cts = 28000;
 317                         break;
 318                 case 27000000:
 319                         cts = 30000;
 320                         break;
 321                 case 54000000:
 322                         cts = 60000;
 323                         break;
 324                 case 74250000:
 325                         cts = 82500;
 326                         break;
 327                 case 148500000:
 328                         cts = 165000;
 329                         break;
 330                 case 297000000:
 331                         cts = 247500;
 332                         break;
 333                 default:
 334                         break;
 335                 }
 336                 break;
 337         default:
 338                 break;
 339         }
 340         return cts;
 341 }
 342
 343 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 344         unsigned long pixel_clk, unsigned int sample_rate)
 345 {
 346         unsigned int n, cts;
 347
 348         n = hdmi_compute_n(sample_rate, pixel_clk);
 349         cts = hdmi_compute_cts(sample_rate, pixel_clk);
 350         if (!cts) {
 351                 dev_err(hdmi->dev,
 352                         "%s: pixel clock/sample rate not supported: %luMHz / %ukHz\n",
 353                         __func__, pixel_clk, sample_rate);
 354         }
 355
 356         dev_dbg(hdmi->dev, "%s: samplerate=%ukHz pixelclk=%luMHz N=%d cts=%d\n",
 357                 __func__, sample_rate, pixel_clk, n, cts);
 358
 359         spin_lock_irq(&hdmi->audio_lock);
 360         hdmi->audio_n = n;
 361         hdmi->audio_cts = cts;
 362         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 363         spin_unlock_irq(&hdmi->audio_lock);
 364 }
 365
 366 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 367 {
 368         mutex_lock(&hdmi->audio_mutex);
 369         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 370         mutex_unlock(&hdmi->audio_mutex);
 371 }
 372
 373 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 374 {
 375         mutex_lock(&hdmi->audio_mutex);
 376         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 377                                  hdmi->sample_rate);
 378         mutex_unlock(&hdmi->audio_mutex);
 379 }
 380
 381 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 382 {
 383         mutex_lock(&hdmi->audio_mutex);
 384         hdmi->sample_rate = rate;
 385         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 386                                  hdmi->sample_rate);
 387         mutex_unlock(&hdmi->audio_mutex);
 388 }
 389 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 390
 391 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 392 {
 393         unsigned long flags;
 394
 395         spin_lock_irqsave(&hdmi->audio_lock, flags);
 396         hdmi->audio_enable = true;
 397         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 398         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 399 }
 400 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 401
 402 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 403 {
 404         unsigned long flags;
 405
 406         spin_lock_irqsave(&hdmi->audio_lock, flags);
 407         hdmi->audio_enable = false;
 408         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 409         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 410 }
 411 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 412
 413 /*
 414  * this submodule is responsible for the video data synchronization.
 415  * for example, for RGB 4:4:4 input, the data map is defined as
 416  *                      pin{47~40} <==> R[7:0]
 417  *                      pin{31~24} <==> G[7:0]
 418  *                      pin{15~8}  <==> B[7:0]
 419  */
 420 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 421 {
 422         int color_format = 0;
 423         u8 val;
 424
 425         if (hdmi->hdmi_data.enc_in_format == RGB) {
 426                 if (hdmi->hdmi_data.enc_color_depth == 8)
 427                         color_format = 0x01;
 428                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 429                         color_format = 0x03;
 430                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 431                         color_format = 0x05;
 432                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 433                         color_format = 0x07;
 434                 else
 435                         return;
 436         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 437                 if (hdmi->hdmi_data.enc_color_depth == 8)
 438                         color_format = 0x09;
 439                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 440                         color_format = 0x0B;
 441                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 442                         color_format = 0x0D;
 443                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 444                         color_format = 0x0F;
 445                 else
 446                         return;
 447         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 448                 if (hdmi->hdmi_data.enc_color_depth == 8)
 449                         color_format = 0x16;
 450                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 451                         color_format = 0x14;
 452                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 453                         color_format = 0x12;
 454                 else
 455                         return;
 456         }
 457
 458         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 459                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 460                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 461         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 462
 463         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 464         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 465                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 466                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 467         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 468         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 469         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 470         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 471         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 472         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 473         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 474 }
 475
 476 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 477 {
 478         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 479 }
 480
 481 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 482 {
 483         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 484                 return 0;
 485         if (hdmi->hdmi_data.enc_in_format == RGB ||
 486             hdmi->hdmi_data.enc_in_format == YCBCR444)
 487                 return 1;
 488         return 0;
 489 }
 490
 491 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 492 {
 493         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 494                 return 0;
 495         if (hdmi->hdmi_data.enc_out_format == RGB ||
 496             hdmi->hdmi_data.enc_out_format == YCBCR444)
 497                 return 1;
 498         return 0;
 499 }
 500
 501 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 502 {
 503         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 504         unsigned i;
 505         u32 csc_scale = 1;
 506
 507         if (is_color_space_conversion(hdmi)) {
 508                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 509                         if (hdmi->hdmi_data.colorimetry ==
 510                                         HDMI_COLORIMETRY_ITU_601)
 511                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 512                         else
 513                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 514                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 515                         if (hdmi->hdmi_data.colorimetry ==
 516                                         HDMI_COLORIMETRY_ITU_601)
 517                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 518                         else
 519                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 520                         csc_scale = 0;
 521                 }
 522         }
 523
 524         /* The CSC registers are sequential, alternating MSB then LSB */
 525         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 526                 u16 coeff_a = (*csc_coeff)[0][i];
 527                 u16 coeff_b = (*csc_coeff)[1][i];
 528                 u16 coeff_c = (*csc_coeff)[2][i];
 529
 530                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 531                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 532                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 533                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 534                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 535                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 536         }
 537
 538         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 539                   HDMI_CSC_SCALE);
 540 }
 541
 542 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 543 {
 544         int color_depth = 0;
 545         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 546         int decimation = 0;
 547
 548         /* YCC422 interpolation to 444 mode */
 549         if (is_color_space_interpolation(hdmi))
 550                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 551         else if (is_color_space_decimation(hdmi))
 552                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 553
 554         if (hdmi->hdmi_data.enc_color_depth == 8)
 555                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 556         else if (hdmi->hdmi_data.enc_color_depth == 10)
 557                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 558         else if (hdmi->hdmi_data.enc_color_depth == 12)
 559                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 560         else if (hdmi->hdmi_data.enc_color_depth == 16)
 561                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 562         else
 563                 return;
 564
 565         /* Configure the CSC registers */
 566         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 567         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 568                   HDMI_CSC_SCALE);
 569
 570         dw_hdmi_update_csc_coeffs(hdmi);
 571 }
 572
 573 /*
 574  * HDMI video packetizer is used to packetize the data.
 575  * for example, if input is YCC422 mode or repeater is used,
 576  * data should be repacked this module can be bypassed.
 577  */
 578 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 579 {
 580         unsigned int color_depth = 0;
 581         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 582         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 583         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 584         u8 val, vp_conf;
 585
 586         if (hdmi_data->enc_out_format == RGB ||
 587             hdmi_data->enc_out_format == YCBCR444) {
 588                 if (!hdmi_data->enc_color_depth) {
 589                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 590                 } else if (hdmi_data->enc_color_depth == 8) {
 591                         color_depth = 4;
 592                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 593                 } else if (hdmi_data->enc_color_depth == 10) {
 594                         color_depth = 5;
 595                 } else if (hdmi_data->enc_color_depth == 12) {
 596                         color_depth = 6;
 597                 } else if (hdmi_data->enc_color_depth == 16) {
 598                         color_depth = 7;
 599                 } else {
 600                         return;
 601                 }
 602         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 603                 if (!hdmi_data->enc_color_depth ||
 604                     hdmi_data->enc_color_depth == 8)
 605                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 606                 else if (hdmi_data->enc_color_depth == 10)
 607                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 608                 else if (hdmi_data->enc_color_depth == 12)
 609                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 610                 else
 611                         return;
 612                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 613         } else {
 614                 return;
 615         }
 616
 617         /* set the packetizer registers */
 618         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 619                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 620                 ((hdmi_data->pix_repet_factor <<
 621                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 622                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 623         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 624
 625         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 626                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 627
 628         /* Data from pixel repeater block */
 629         if (hdmi_data->pix_repet_factor > 1) {
 630                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 631                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 632         } else { /* data from packetizer block */
 633                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 634                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 635         }
 636
 637         hdmi_modb(hdmi, vp_conf,
 638                   HDMI_VP_CONF_PR_EN_MASK |
 639                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 640
 641         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 642                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 643
 644         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 645
 646         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 647                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 648                           HDMI_VP_CONF_PP_EN_ENABLE |
 649                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 650         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 651                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 652                           HDMI_VP_CONF_PP_EN_DISABLE |
 653                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 654         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 655                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 656                           HDMI_VP_CONF_PP_EN_DISABLE |
 657                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 658         } else {
 659                 return;
 660         }
 661
 662         hdmi_modb(hdmi, vp_conf,
 663                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 664                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 665
 666         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 667                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 668                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 669                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 670
 671         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 672                   HDMI_VP_CONF);
 673 }
 674
 675 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 676                                        unsigned char bit)
 677 {
 678         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 679                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 680 }
 681
 682 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 683                                         unsigned char bit)
 684 {
 685         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 686                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 687 }
 688
 689 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 690                                        unsigned char bit)
 691 {
 692         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 693                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 694 }
 695
 696 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 697                                      unsigned char bit)
 698 {
 699         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 700 }
 701
 702 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 703                                       unsigned char bit)
 704 {
 705         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 706 }
 707
 708 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 709 {
 710         u32 val;
 711
 712         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 713                 if (msec-- == 0)
 714                         return false;
 715                 udelay(1000);
 716         }
 717         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
 718
 719         return true;
 720 }
 721
 722 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 723                                  unsigned char addr)
 724 {
 725         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
 726         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 727         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
 728                     HDMI_PHY_I2CM_DATAO_1_ADDR);
 729         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
 730                     HDMI_PHY_I2CM_DATAO_0_ADDR);
 731         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
 732                     HDMI_PHY_I2CM_OPERATION_ADDR);
 733         hdmi_phy_wait_i2c_done(hdmi, 1000);
 734 }
 735
 736 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 737                               unsigned char addr)
 738 {
 739         __hdmi_phy_i2c_write(hdmi, data, addr);
 740         return 0;
 741 }
 742
 743 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
 744 {
 745         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
 746                          HDMI_PHY_CONF0_PDZ_OFFSET,
 747                          HDMI_PHY_CONF0_PDZ_MASK);
 748 }
 749
 750 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
 751 {
 752         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 753                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
 754                          HDMI_PHY_CONF0_ENTMDS_MASK);
 755 }
 756
 757 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
 758 {
 759         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 760                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
 761                          HDMI_PHY_CONF0_SPARECTRL_MASK);
 762 }
 763
 764 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
 765 {
 766         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 767                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
 768                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
 769 }
 770
 771 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
 772 {
 773         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 774                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
 775                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
 776 }
 777
 778 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
 779 {
 780         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 781                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
 782                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
 783 }
 784
 785 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
 786 {
 787         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 788                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
 789                          HDMI_PHY_CONF0_SELDIPIF_MASK);
 790 }
 791
 792 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
 793                               unsigned char res, int cscon)
 794 {
 795         unsigned res_idx;
 796         u8 val, msec;
 797         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
 798         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
 799         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
 800         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
 801
 802         if (prep)
 803                 return -EINVAL;
 804
 805         switch (res) {
 806         case 0: /* color resolution 0 is 8 bit colour depth */
 807         case 8:
 808                 res_idx = DW_HDMI_RES_8;
 809                 break;
 810         case 10:
 811                 res_idx = DW_HDMI_RES_10;
 812                 break;
 813         case 12:
 814                 res_idx = DW_HDMI_RES_12;
 815                 break;
 816         default:
 817                 return -EINVAL;
 818         }
 819
 820         /* PLL/MPLL Cfg - always match on final entry */
 821         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
 822                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 823                     mpll_config->mpixelclock)
 824                         break;
 825
 826         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
 827                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 828                     curr_ctrl->mpixelclock)
 829                         break;
 830
 831         for (; phy_config->mpixelclock != ~0UL; phy_config++)
 832                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 833                     phy_config->mpixelclock)
 834                         break;
 835
 836         if (mpll_config->mpixelclock == ~0UL ||
 837             curr_ctrl->mpixelclock == ~0UL ||
 838             phy_config->mpixelclock == ~0UL) {
 839                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
 840                         hdmi->hdmi_data.video_mode.mpixelclock);
 841                 return -EINVAL;
 842         }
 843
 844         /* Enable csc path */
 845         if (cscon)
 846                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
 847         else
 848                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
 849
 850         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
 851
 852         /* gen2 tx power off */
 853         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
 854
 855         /* gen2 pddq */
 856         dw_hdmi_phy_gen2_pddq(hdmi, 1);
 857
 858         /* PHY reset */
 859         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
 860         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
 861
 862         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
 863
 864         hdmi_phy_test_clear(hdmi, 1);
 865         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
 866                     HDMI_PHY_I2CM_SLAVE_ADDR);
 867         hdmi_phy_test_clear(hdmi, 0);
 868
 869         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
 870         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
 871
 872         /* CURRCTRL */
 873         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
 874
 875         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
 876         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
 877
 878         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
 879         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
 880         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
 881
 882         /* REMOVE CLK TERM */
 883         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
 884
 885         dw_hdmi_phy_enable_powerdown(hdmi, false);
 886
 887         /* toggle TMDS enable */
 888         dw_hdmi_phy_enable_tmds(hdmi, 0);
 889         dw_hdmi_phy_enable_tmds(hdmi, 1);
 890
 891         /* gen2 tx power on */
 892         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
 893         dw_hdmi_phy_gen2_pddq(hdmi, 0);
 894
 895         if (hdmi->dev_type == RK3288_HDMI)
 896                 dw_hdmi_phy_enable_spare(hdmi, 1);
 897
 898         /*Wait for PHY PLL lock */
 899         msec = 5;
 900         do {
 901                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
 902                 if (!val)
 903                         break;
 904
 905                 if (msec == 0) {
 906                         dev_err(hdmi->dev, "PHY PLL not locked\n");
 907                         return -ETIMEDOUT;
 908                 }
 909
 910                 udelay(1000);
 911                 msec--;
 912         } while (1);
 913
 914         return 0;
 915 }
 916
 917 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
 918 {
 919         int i, ret;
 920         bool cscon;
 921
 922         /*check csc whether needed activated in HDMI mode */
 923         cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
 924
 925         /* HDMI Phy spec says to do the phy initialization sequence twice */
 926         for (i = 0; i < 2; i++) {
 927                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
 928                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
 929                 dw_hdmi_phy_enable_tmds(hdmi, 0);
 930                 dw_hdmi_phy_enable_powerdown(hdmi, true);
 931
 932                 /* Enable CSC */
 933                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
 934                 if (ret)
 935                         return ret;
 936         }
 937
 938         hdmi->phy_enabled = true;
 939         return 0;
 940 }
 941
 942 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
 943 {
 944         u8 de;
 945
 946         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
 947                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
 948         else
 949                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
 950
 951         /* disable rx detect */
 952         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
 953                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
 954
 955         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
 956
 957         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
 958                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
 959 }
 960
 961 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
 962 {
 963         struct hdmi_avi_infoframe frame;
 964         u8 val;
 965
 966         /* Initialise info frame from DRM mode */
 967         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 968
 969         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
 970                 frame.colorspace = HDMI_COLORSPACE_YUV444;
 971         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
 972                 frame.colorspace = HDMI_COLORSPACE_YUV422;
 973         else
 974                 frame.colorspace = HDMI_COLORSPACE_RGB;
 975
 976         /* Set up colorimetry */
 977         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
 978                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
 979                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
 980                         frame.extended_colorimetry =
 981                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 982                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
 983                         frame.extended_colorimetry =
 984                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
 985         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
 986                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
 987                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 988         } else { /* Carries no data */
 989                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
 990                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 991         }
 992
 993         frame.scan_mode = HDMI_SCAN_MODE_NONE;
 994
 995         /*
 996          * The Designware IP uses a different byte format from standard
 997          * AVI info frames, though generally the bits are in the correct
 998          * bytes.
 999          */
1000
1001         /*
1002          * AVI data byte 1 differences: Colorspace in bits 4,5 rather than 5,6,
1003          * active aspect present in bit 6 rather than 4.
1004          */
1005         val = (frame.colorspace & 3) << 4 | (frame.scan_mode & 0x3);
1006         if (frame.active_aspect & 15)
1007                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1008         if (frame.top_bar || frame.bottom_bar)
1009                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1010         if (frame.left_bar || frame.right_bar)
1011                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1012         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1013
1014         /* AVI data byte 2 differences: none */
1015         val = ((frame.colorimetry & 0x3) << 6) |
1016               ((frame.picture_aspect & 0x3) << 4) |
1017               (frame.active_aspect & 0xf);
1018         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1019
1020         /* AVI data byte 3 differences: none */
1021         val = ((frame.extended_colorimetry & 0x7) << 4) |
1022               ((frame.quantization_range & 0x3) << 2) |
1023               (frame.nups & 0x3);
1024         if (frame.itc)
1025                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1026         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1027
1028         /* AVI data byte 4 differences: none */
1029         val = frame.video_code & 0x7f;
1030         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1031
1032         /* AVI Data Byte 5- set up input and output pixel repetition */
1033         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1034                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1035                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1036                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1037                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1038                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1039         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1040
1041         /*
1042          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1043          * ycc range in bits 2,3 rather than 6,7
1044          */
1045         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1046               (frame.content_type & 0x3);
1047         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1048
1049         /* AVI Data Bytes 6-13 */
1050         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1051         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1052         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1053         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1054         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1055         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1056         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1057         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1058 }
1059
1060 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1061                              const struct drm_display_mode *mode)
1062 {
1063         u8 inv_val;
1064         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1065         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1066         unsigned int vdisplay;
1067
1068         vmode->mpixelclock = mode->clock * 1000;
1069
1070         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1071
1072         /* Set up HDMI_FC_INVIDCONF */
1073         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1074                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1075                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1076
1077         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1078                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1079                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1080
1081         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1082                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1083                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1084
1085         inv_val |= (vmode->mdataenablepolarity ?
1086                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1087                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1088
1089         if (hdmi->vic == 39)
1090                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1091         else
1092                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1093                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1094                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1095
1096         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1097                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1098                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1099
1100         inv_val |= hdmi->sink_is_hdmi ?
1101                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1102                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1103
1104         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1105
1106         vdisplay = mode->vdisplay;
1107         vblank = mode->vtotal - mode->vdisplay;
1108         v_de_vs = mode->vsync_start - mode->vdisplay;
1109         vsync_len = mode->vsync_end - mode->vsync_start;
1110
1111         /*
1112          * When we're setting an interlaced mode, we need
1113          * to adjust the vertical timing to suit.
1114          */
1115         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1116                 vdisplay /= 2;
1117                 vblank /= 2;
1118                 v_de_vs /= 2;
1119                 vsync_len /= 2;
1120         }
1121
1122         /* Set up horizontal active pixel width */
1123         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1124         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1125
1126         /* Set up vertical active lines */
1127         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1128         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1129
1130         /* Set up horizontal blanking pixel region width */
1131         hblank = mode->htotal - mode->hdisplay;
1132         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1133         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1134
1135         /* Set up vertical blanking pixel region width */
1136         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1137
1138         /* Set up HSYNC active edge delay width (in pixel clks) */
1139         h_de_hs = mode->hsync_start - mode->hdisplay;
1140         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1141         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1142
1143         /* Set up VSYNC active edge delay (in lines) */
1144         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1145
1146         /* Set up HSYNC active pulse width (in pixel clks) */
1147         hsync_len = mode->hsync_end - mode->hsync_start;
1148         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1149         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1150
1151         /* Set up VSYNC active edge delay (in lines) */
1152         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1153 }
1154
1155 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1156 {
1157         if (!hdmi->phy_enabled)
1158                 return;
1159
1160         dw_hdmi_phy_enable_tmds(hdmi, 0);
1161         dw_hdmi_phy_enable_powerdown(hdmi, true);
1162
1163         hdmi->phy_enabled = false;
1164 }
1165
1166 /* HDMI Initialization Step B.4 */
1167 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1168 {
1169         u8 clkdis;
1170
1171         /* control period minimum duration */
1172         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1173         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1174         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1175
1176         /* Set to fill TMDS data channels */
1177         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1178         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1179         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1180
1181         /* Enable pixel clock and tmds data path */
1182         clkdis = 0x7F;
1183         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1184         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1185
1186         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1187         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1188
1189         /* Enable csc path */
1190         if (is_color_space_conversion(hdmi)) {
1191                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1192                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1193         }
1194 }
1195
1196 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1197 {
1198         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1199 }
1200
1201 /* Workaround to clear the overflow condition */
1202 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1203 {
1204         int count;
1205         u8 val;
1206
1207         /* TMDS software reset */
1208         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1209
1210         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1211         if (hdmi->dev_type == IMX6DL_HDMI) {
1212                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1213                 return;
1214         }
1215
1216         for (count = 0; count < 4; count++)
1217                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1218 }
1219
1220 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1221 {
1222         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1223         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1224 }
1225
1226 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1227 {
1228         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1229                     HDMI_IH_MUTE_FC_STAT2);
1230 }
1231
1232 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1233 {
1234         int ret;
1235
1236         hdmi_disable_overflow_interrupts(hdmi);
1237
1238         hdmi->vic = drm_match_cea_mode(mode);
1239
1240         if (!hdmi->vic) {
1241                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1242         } else {
1243                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1244         }
1245
1246         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1247             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1248             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1249             (hdmi->vic == 17) || (hdmi->vic == 18))
1250                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1251         else
1252                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1253
1254         hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1255         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1256
1257         /* TODO: Get input format from IPU (via FB driver interface) */
1258         hdmi->hdmi_data.enc_in_format = RGB;
1259
1260         hdmi->hdmi_data.enc_out_format = RGB;
1261
1262         hdmi->hdmi_data.enc_color_depth = 8;
1263         hdmi->hdmi_data.pix_repet_factor = 0;
1264         hdmi->hdmi_data.hdcp_enable = 0;
1265         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1266
1267         /* HDMI Initialization Step B.1 */
1268         hdmi_av_composer(hdmi, mode);
1269
1270         /* HDMI Initializateion Step B.2 */
1271         ret = dw_hdmi_phy_init(hdmi);
1272         if (ret)
1273                 return ret;
1274
1275         /* HDMI Initialization Step B.3 */
1276         dw_hdmi_enable_video_path(hdmi);
1277
1278         if (hdmi->sink_has_audio) {
1279                 dev_dbg(hdmi->dev, "sink has audio support\n");
1280
1281                 /* HDMI Initialization Step E - Configure audio */
1282                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1283                 hdmi_enable_audio_clk(hdmi);
1284         }
1285
1286         /* not for DVI mode */
1287         if (hdmi->sink_is_hdmi) {
1288                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1289
1290                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1291                 hdmi_config_AVI(hdmi, mode);
1292         } else {
1293                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1294         }
1295
1296         hdmi_video_packetize(hdmi);
1297         hdmi_video_csc(hdmi);
1298         hdmi_video_sample(hdmi);
1299         hdmi_tx_hdcp_config(hdmi);
1300
1301         dw_hdmi_clear_overflow(hdmi);
1302         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1303                 hdmi_enable_overflow_interrupts(hdmi);
1304
1305         return 0;
1306 }
1307
1308 /* Wait until we are registered to enable interrupts */
1309 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1310 {
1311         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1312                     HDMI_PHY_I2CM_INT_ADDR);
1313
1314         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1315                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1316                     HDMI_PHY_I2CM_CTLINT_ADDR);
1317
1318         /* enable cable hot plug irq */
1319         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1320
1321         /* Clear Hotplug interrupts */
1322         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1323                     HDMI_IH_PHY_STAT0);
1324
1325         return 0;
1326 }
1327
1328 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1329 {
1330         u8 ih_mute;
1331
1332         /*
1333          * Boot up defaults are:
1334          * HDMI_IH_MUTE   = 0x03 (disabled)
1335          * HDMI_IH_MUTE_* = 0x00 (enabled)
1336          *
1337          * Disable top level interrupt bits in HDMI block
1338          */
1339         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1340                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1341                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1342
1343         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1344
1345         /* by default mask all interrupts */
1346         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1347         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1348         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1349         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1350         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1351         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1352         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1353         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1354         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1355         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1356         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1357         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1358         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1359         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1360         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1361
1362         /* Disable interrupts in the IH_MUTE_* registers */
1363         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1364         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1365         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1366         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1367         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1368         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1369         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1370         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1371         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1372         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1373
1374         /* Enable top level interrupt bits in HDMI block */
1375         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1376                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1377         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1378 }
1379
1380 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1381 {
1382         hdmi->bridge_is_on = true;
1383         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1384 }
1385
1386 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1387 {
1388         dw_hdmi_phy_disable(hdmi);
1389         hdmi->bridge_is_on = false;
1390 }
1391
1392 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1393 {
1394         int force = hdmi->force;
1395
1396         if (hdmi->disabled) {
1397                 force = DRM_FORCE_OFF;
1398         } else if (force == DRM_FORCE_UNSPECIFIED) {
1399                 if (hdmi->rxsense)
1400                         force = DRM_FORCE_ON;
1401                 else
1402                         force = DRM_FORCE_OFF;
1403         }
1404
1405         if (force == DRM_FORCE_OFF) {
1406                 if (hdmi->bridge_is_on)
1407                         dw_hdmi_poweroff(hdmi);
1408         } else {
1409                 if (!hdmi->bridge_is_on)
1410                         dw_hdmi_poweron(hdmi);
1411         }
1412 }
1413
1414 /*
1415  * Adjust the detection of RXSENSE according to whether we have a forced
1416  * connection mode enabled, or whether we have been disabled.  There is
1417  * no point processing RXSENSE interrupts if we have a forced connection
1418  * state, or DRM has us disabled.
1419  *
1420  * We also disable rxsense interrupts when we think we're disconnected
1421  * to avoid floating TDMS signals giving false rxsense interrupts.
1422  *
1423  * Note: we still need to listen for HPD interrupts even when DRM has us
1424  * disabled so that we can detect a connect event.
1425  */
1426 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1427 {
1428         u8 old_mask = hdmi->phy_mask;
1429
1430         if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1431                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1432         else
1433                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1434
1435         if (old_mask != hdmi->phy_mask)
1436                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1437 }
1438
1439 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1440                                     struct drm_display_mode *orig_mode,
1441                                     struct drm_display_mode *mode)
1442 {
1443         struct dw_hdmi *hdmi = bridge->driver_private;
1444
1445         mutex_lock(&hdmi->mutex);
1446
1447         /* Store the display mode for plugin/DKMS poweron events */
1448         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1449
1450         mutex_unlock(&hdmi->mutex);
1451 }
1452
1453 static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1454                                       const struct drm_display_mode *mode,
1455                                       struct drm_display_mode *adjusted_mode)
1456 {
1457         return true;
1458 }
1459
1460 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1461 {
1462         struct dw_hdmi *hdmi = bridge->driver_private;
1463
1464         mutex_lock(&hdmi->mutex);
1465         hdmi->disabled = true;
1466         dw_hdmi_update_power(hdmi);
1467         dw_hdmi_update_phy_mask(hdmi);
1468         mutex_unlock(&hdmi->mutex);
1469 }
1470
1471 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1472 {
1473         struct dw_hdmi *hdmi = bridge->driver_private;
1474
1475         mutex_lock(&hdmi->mutex);
1476         hdmi->disabled = false;
1477         dw_hdmi_update_power(hdmi);
1478         dw_hdmi_update_phy_mask(hdmi);
1479         mutex_unlock(&hdmi->mutex);
1480 }
1481
1482 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1483 {
1484         /* do nothing */
1485 }
1486
1487 static enum drm_connector_status
1488 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1489 {
1490         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1491                                              connector);
1492
1493         mutex_lock(&hdmi->mutex);
1494         hdmi->force = DRM_FORCE_UNSPECIFIED;
1495         dw_hdmi_update_power(hdmi);
1496         dw_hdmi_update_phy_mask(hdmi);
1497         mutex_unlock(&hdmi->mutex);
1498
1499         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1500                 connector_status_connected : connector_status_disconnected;
1501 }
1502
1503 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1504 {
1505         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1506                                              connector);
1507         struct edid *edid;
1508         int ret = 0;
1509
1510         if (!hdmi->ddc)
1511                 return 0;
1512
1513         edid = drm_get_edid(connector, hdmi->ddc);
1514         if (edid) {
1515                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1516                         edid->width_cm, edid->height_cm);
1517
1518                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1519                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1520                 drm_mode_connector_update_edid_property(connector, edid);
1521                 ret = drm_add_edid_modes(connector, edid);
1522                 /* Store the ELD */
1523                 drm_edid_to_eld(connector, edid);
1524                 kfree(edid);
1525         } else {
1526                 dev_dbg(hdmi->dev, "failed to get edid\n");
1527         }
1528
1529         return ret;
1530 }
1531
1532 static enum drm_mode_status
1533 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1534                              struct drm_display_mode *mode)
1535 {
1536         struct dw_hdmi *hdmi = container_of(connector,
1537                                            struct dw_hdmi, connector);
1538         enum drm_mode_status mode_status = MODE_OK;
1539
1540         /* We don't support double-clocked modes */
1541         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1542                 return MODE_BAD;
1543
1544         if (hdmi->plat_data->mode_valid)
1545                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1546
1547         return mode_status;
1548 }
1549
1550 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1551                                                            *connector)
1552 {
1553         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1554                                              connector);
1555
1556         return hdmi->encoder;
1557 }
1558
1559 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1560 {
1561         drm_connector_unregister(connector);
1562         drm_connector_cleanup(connector);
1563 }
1564
1565 static void dw_hdmi_connector_force(struct drm_connector *connector)
1566 {
1567         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1568                                              connector);
1569
1570         mutex_lock(&hdmi->mutex);
1571         hdmi->force = connector->force;
1572         dw_hdmi_update_power(hdmi);
1573         dw_hdmi_update_phy_mask(hdmi);
1574         mutex_unlock(&hdmi->mutex);
1575 }
1576
1577 static struct drm_connector_funcs dw_hdmi_connector_funcs = {
1578         .dpms = drm_helper_connector_dpms,
1579         .fill_modes = drm_helper_probe_single_connector_modes,
1580         .detect = dw_hdmi_connector_detect,
1581         .destroy = dw_hdmi_connector_destroy,
1582         .force = dw_hdmi_connector_force,
1583 };
1584
1585 static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1586         .get_modes = dw_hdmi_connector_get_modes,
1587         .mode_valid = dw_hdmi_connector_mode_valid,
1588         .best_encoder = dw_hdmi_connector_best_encoder,
1589 };
1590
1591 static struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1592         .enable = dw_hdmi_bridge_enable,
1593         .disable = dw_hdmi_bridge_disable,
1594         .pre_enable = dw_hdmi_bridge_nop,
1595         .post_disable = dw_hdmi_bridge_nop,
1596         .mode_set = dw_hdmi_bridge_mode_set,
1597         .mode_fixup = dw_hdmi_bridge_mode_fixup,
1598 };
1599
1600 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1601 {
1602         struct dw_hdmi *hdmi = dev_id;
1603         u8 intr_stat;
1604
1605         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1606         if (intr_stat)
1607                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1608
1609         return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1610 }
1611
1612 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1613 {
1614         struct dw_hdmi *hdmi = dev_id;
1615         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
1616
1617         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1618         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1619         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1620
1621         phy_pol_mask = 0;
1622         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1623                 phy_pol_mask |= HDMI_PHY_HPD;
1624         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
1625                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
1626         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
1627                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
1628         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
1629                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
1630         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
1631                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
1632
1633         if (phy_pol_mask)
1634                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
1635
1636         /*
1637          * RX sense tells us whether the TDMS transmitters are detecting
1638          * load - in other words, there's something listening on the
1639          * other end of the link.  Use this to decide whether we should
1640          * power on the phy as HPD may be toggled by the sink to merely
1641          * ask the source to re-read the EDID.
1642          */
1643         if (intr_stat &
1644             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
1645                 mutex_lock(&hdmi->mutex);
1646                 if (!hdmi->disabled && !hdmi->force) {
1647                         /*
1648                          * If the RX sense status indicates we're disconnected,
1649                          * clear the software rxsense status.
1650                          */
1651                         if (!(phy_stat & HDMI_PHY_RX_SENSE))
1652                                 hdmi->rxsense = false;
1653
1654                         /*
1655                          * Only set the software rxsense status when both
1656                          * rxsense and hpd indicates we're connected.
1657                          * This avoids what seems to be bad behaviour in
1658                          * at least iMX6S versions of the phy.
1659                          */
1660                         if (phy_stat & HDMI_PHY_HPD)
1661                                 hdmi->rxsense = true;
1662
1663                         dw_hdmi_update_power(hdmi);
1664                         dw_hdmi_update_phy_mask(hdmi);
1665                 }
1666                 mutex_unlock(&hdmi->mutex);
1667         }
1668
1669         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1670                 dev_dbg(hdmi->dev, "EVENT=%s\n",
1671                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
1672                 drm_helper_hpd_irq_event(hdmi->bridge->dev);
1673         }
1674
1675         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1676         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1677                     HDMI_IH_MUTE_PHY_STAT0);
1678
1679         return IRQ_HANDLED;
1680 }
1681
1682 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1683 {
1684         struct drm_encoder *encoder = hdmi->encoder;
1685         struct drm_bridge *bridge;
1686         int ret;
1687
1688         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1689         if (!bridge) {
1690                 DRM_ERROR("Failed to allocate drm bridge\n");
1691                 return -ENOMEM;
1692         }
1693
1694         hdmi->bridge = bridge;
1695         bridge->driver_private = hdmi;
1696         bridge->funcs = &dw_hdmi_bridge_funcs;
1697         ret = drm_bridge_attach(drm, bridge);
1698         if (ret) {
1699                 DRM_ERROR("Failed to initialize bridge with drm\n");
1700                 return -EINVAL;
1701         }
1702
1703         encoder->bridge = bridge;
1704         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1705
1706         drm_connector_helper_add(&hdmi->connector,
1707                                  &dw_hdmi_connector_helper_funcs);
1708         drm_connector_init(drm, &hdmi->connector, &dw_hdmi_connector_funcs,
1709                            DRM_MODE_CONNECTOR_HDMIA);
1710
1711         hdmi->connector.encoder = encoder;
1712
1713         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1714
1715         return 0;
1716 }
1717
1718 int dw_hdmi_bind(struct device *dev, struct device *master,
1719                  void *data, struct drm_encoder *encoder,
1720                  struct resource *iores, int irq,
1721                  const struct dw_hdmi_plat_data *plat_data)
1722 {
1723         struct drm_device *drm = data;
1724         struct device_node *np = dev->of_node;
1725         struct platform_device_info pdevinfo;
1726         struct device_node *ddc_node;
1727         struct dw_hdmi_audio_data audio;
1728         struct dw_hdmi *hdmi;
1729         int ret;
1730         u32 val = 1;
1731
1732         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1733         if (!hdmi)
1734                 return -ENOMEM;
1735
1736         hdmi->connector.interlace_allowed = 1;
1737
1738         hdmi->plat_data = plat_data;
1739         hdmi->dev = dev;
1740         hdmi->dev_type = plat_data->dev_type;
1741         hdmi->sample_rate = 48000;
1742         hdmi->encoder = encoder;
1743         hdmi->disabled = true;
1744         hdmi->rxsense = true;
1745         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
1746
1747         mutex_init(&hdmi->mutex);
1748         mutex_init(&hdmi->audio_mutex);
1749         spin_lock_init(&hdmi->audio_lock);
1750
1751         of_property_read_u32(np, "reg-io-width", &val);
1752
1753         switch (val) {
1754         case 4:
1755                 hdmi->write = dw_hdmi_writel;
1756                 hdmi->read = dw_hdmi_readl;
1757                 break;
1758         case 1:
1759                 hdmi->write = dw_hdmi_writeb;
1760                 hdmi->read = dw_hdmi_readb;
1761                 break;
1762         default:
1763                 dev_err(dev, "reg-io-width must be 1 or 4\n");
1764                 return -EINVAL;
1765         }
1766
1767         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1768         if (ddc_node) {
1769                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1770                 of_node_put(ddc_node);
1771                 if (!hdmi->ddc) {
1772                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
1773                         return -EPROBE_DEFER;
1774                 }
1775
1776         } else {
1777                 dev_dbg(hdmi->dev, "no ddc property found\n");
1778         }
1779
1780         hdmi->regs = devm_ioremap_resource(dev, iores);
1781         if (IS_ERR(hdmi->regs))
1782                 return PTR_ERR(hdmi->regs);
1783
1784         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1785         if (IS_ERR(hdmi->isfr_clk)) {
1786                 ret = PTR_ERR(hdmi->isfr_clk);
1787                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1788                 return ret;
1789         }
1790
1791         ret = clk_prepare_enable(hdmi->isfr_clk);
1792         if (ret) {
1793                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1794                 return ret;
1795         }
1796
1797         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1798         if (IS_ERR(hdmi->iahb_clk)) {
1799                 ret = PTR_ERR(hdmi->iahb_clk);
1800                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1801                 goto err_isfr;
1802         }
1803
1804         ret = clk_prepare_enable(hdmi->iahb_clk);
1805         if (ret) {
1806                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1807                 goto err_isfr;
1808         }
1809
1810         /* Product and revision IDs */
1811         dev_info(dev,
1812                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1813                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
1814                  hdmi_readb(hdmi, HDMI_REVISION_ID),
1815                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1816                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1817
1818         initialize_hdmi_ih_mutes(hdmi);
1819
1820         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1821                                         dw_hdmi_irq, IRQF_SHARED,
1822                                         dev_name(dev), hdmi);
1823         if (ret)
1824                 goto err_iahb;
1825
1826         /*
1827          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1828          * N and cts values before enabling phy
1829          */
1830         hdmi_init_clk_regenerator(hdmi);
1831
1832         /*
1833          * Configure registers related to HDMI interrupt
1834          * generation before registering IRQ.
1835          */
1836         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1837
1838         /* Clear Hotplug interrupts */
1839         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1840                     HDMI_IH_PHY_STAT0);
1841
1842         ret = dw_hdmi_fb_registered(hdmi);
1843         if (ret)
1844                 goto err_iahb;
1845
1846         ret = dw_hdmi_register(drm, hdmi);
1847         if (ret)
1848                 goto err_iahb;
1849
1850         /* Unmute interrupts */
1851         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1852                     HDMI_IH_MUTE_PHY_STAT0);
1853
1854         memset(&pdevinfo, 0, sizeof(pdevinfo));
1855         pdevinfo.parent = dev;
1856         pdevinfo.id = PLATFORM_DEVID_AUTO;
1857
1858         if (hdmi_readb(hdmi, HDMI_CONFIG1_ID) & HDMI_CONFIG1_AHB) {
1859                 audio.phys = iores->start;
1860                 audio.base = hdmi->regs;
1861                 audio.irq = irq;
1862                 audio.hdmi = hdmi;
1863                 audio.eld = hdmi->connector.eld;
1864
1865                 pdevinfo.name = "dw-hdmi-ahb-audio";
1866                 pdevinfo.data = &audio;
1867                 pdevinfo.size_data = sizeof(audio);
1868                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
1869                 hdmi->audio = platform_device_register_full(&pdevinfo);
1870         }
1871
1872         dev_set_drvdata(dev, hdmi);
1873
1874         return 0;
1875
1876 err_iahb:
1877         clk_disable_unprepare(hdmi->iahb_clk);
1878 err_isfr:
1879         clk_disable_unprepare(hdmi->isfr_clk);
1880
1881         return ret;
1882 }
1883 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
1884
1885 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
1886 {
1887         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
1888
1889         if (hdmi->audio && !IS_ERR(hdmi->audio))
1890                 platform_device_unregister(hdmi->audio);
1891
1892         /* Disable all interrupts */
1893         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1894
1895         hdmi->connector.funcs->destroy(&hdmi->connector);
1896         hdmi->encoder->funcs->destroy(hdmi->encoder);
1897
1898         clk_disable_unprepare(hdmi->iahb_clk);
1899         clk_disable_unprepare(hdmi->isfr_clk);
1900         i2c_put_adapter(hdmi->ddc);
1901 }
1902 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
1903
1904 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1905 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1906 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
1907 MODULE_DESCRIPTION("DW HDMI transmitter driver");
1908 MODULE_LICENSE("GPL");
1909 MODULE_ALIAS("platform:dw-hdmi");