drivers/gpu/drm/bridge/dw_hdmi.c

   1 /*
   2  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * Designware High-Definition Multimedia Interface (HDMI) driver
  10  *
  11  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  12  */
  13 #include <linux/module.h>
  14 #include <linux/irq.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/hdmi.h>
  19 #include <linux/mutex.h>
  20 #include <linux/of_device.h>
  21 #include <linux/spinlock.h>
  22
  23 #include <drm/drm_of.h>
  24 #include <drm/drmP.h>
  25 #include <drm/drm_crtc_helper.h>
  26 #include <drm/drm_edid.h>
  27 #include <drm/drm_encoder_slave.h>
  28 #include <drm/bridge/dw_hdmi.h>
  29
  30 #include "dw_hdmi.h"
  31
  32 #define HDMI_EDID_LEN           512
  33
  34 #define RGB                     0
  35 #define YCBCR444                1
  36 #define YCBCR422_16BITS         2
  37 #define YCBCR422_8BITS          3
  38 #define XVYCC444                4
  39
  40 enum hdmi_datamap {
  41         RGB444_8B = 0x01,
  42         RGB444_10B = 0x03,
  43         RGB444_12B = 0x05,
  44         RGB444_16B = 0x07,
  45         YCbCr444_8B = 0x09,
  46         YCbCr444_10B = 0x0B,
  47         YCbCr444_12B = 0x0D,
  48         YCbCr444_16B = 0x0F,
  49         YCbCr422_8B = 0x16,
  50         YCbCr422_10B = 0x14,
  51         YCbCr422_12B = 0x12,
  52 };
  53
  54 static const u16 csc_coeff_default[3][4] = {
  55         { 0x2000, 0x0000, 0x0000, 0x0000 },
  56         { 0x0000, 0x2000, 0x0000, 0x0000 },
  57         { 0x0000, 0x0000, 0x2000, 0x0000 }
  58 };
  59
  60 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  61         { 0x2000, 0x6926, 0x74fd, 0x010e },
  62         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  63         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  64 };
  65
  66 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  67         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  68         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  69         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  70 };
  71
  72 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  73         { 0x2591, 0x1322, 0x074b, 0x0000 },
  74         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  75         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  76 };
  77
  78 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  79         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  80         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  81         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  82 };
  83
  84 struct hdmi_vmode {
  85         bool mdataenablepolarity;
  86
  87         unsigned int mpixelclock;
  88         unsigned int mpixelrepetitioninput;
  89         unsigned int mpixelrepetitionoutput;
  90 };
  91
  92 struct hdmi_data_info {
  93         unsigned int enc_in_format;
  94         unsigned int enc_out_format;
  95         unsigned int enc_color_depth;
  96         unsigned int colorimetry;
  97         unsigned int pix_repet_factor;
  98         unsigned int hdcp_enable;
  99         struct hdmi_vmode video_mode;
 100 };
 101
 102 struct dw_hdmi {
 103         struct drm_connector connector;
 104         struct drm_encoder *encoder;
 105         struct drm_bridge *bridge;
 106
 107         enum dw_hdmi_devtype dev_type;
 108         struct device *dev;
 109         struct clk *isfr_clk;
 110         struct clk *iahb_clk;
 111
 112         struct hdmi_data_info hdmi_data;
 113         const struct dw_hdmi_plat_data *plat_data;
 114
 115         int vic;
 116
 117         u8 edid[HDMI_EDID_LEN];
 118         bool cable_plugin;
 119
 120         bool phy_enabled;
 121         struct drm_display_mode previous_mode;
 122
 123         struct i2c_adapter *ddc;
 124         void __iomem *regs;
 125         bool sink_is_hdmi;
 126         bool sink_has_audio;
 127
 128         struct mutex mutex;             /* for state below and previous_mode */
 129         enum drm_connector_force force; /* mutex-protected force state */
 130         bool disabled;                  /* DRM has disabled our bridge */
 131         bool bridge_is_on;              /* indicates the bridge is on */
 132         bool rxsense;                   /* rxsense state */
 133         u8 phy_mask;                    /* desired phy int mask settings */
 134
 135         spinlock_t audio_lock;
 136         struct mutex audio_mutex;
 137         unsigned int sample_rate;
 138         unsigned int audio_cts;
 139         unsigned int audio_n;
 140         bool audio_enable;
 141         int ratio;
 142
 143         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 144         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 145 };
 146
 147 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 148         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 149          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 150
 151 #define HDMI_PHY_RX_SENSE \
 152         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 153          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 154
 155 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 156 {
 157         writel(val, hdmi->regs + (offset << 2));
 158 }
 159
 160 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 161 {
 162         return readl(hdmi->regs + (offset << 2));
 163 }
 164
 165 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 166 {
 167         writeb(val, hdmi->regs + offset);
 168 }
 169
 170 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 171 {
 172         return readb(hdmi->regs + offset);
 173 }
 174
 175 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 176 {
 177         hdmi->write(hdmi, val, offset);
 178 }
 179
 180 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 181 {
 182         return hdmi->read(hdmi, offset);
 183 }
 184
 185 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 186 {
 187         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 188
 189         val |= data & mask;
 190         hdmi_writeb(hdmi, val, reg);
 191 }
 192
 193 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 194                              u8 shift, u8 mask)
 195 {
 196         hdmi_modb(hdmi, data << shift, mask, reg);
 197 }
 198
 199 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 200                            unsigned int n)
 201 {
 202         /* Must be set/cleared first */
 203         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 204
 205         /* nshift factor = 0 */
 206         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 207
 208         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 209                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 210         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 211         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 212
 213         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 214         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 215         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 216 }
 217
 218 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
 219                                    unsigned int ratio)
 220 {
 221         unsigned int n = (128 * freq) / 1000;
 222
 223         switch (freq) {
 224         case 32000:
 225                 if (pixel_clk == 25170000)
 226                         n = (ratio == 150) ? 9152 : 4576;
 227                 else if (pixel_clk == 27020000)
 228                         n = (ratio == 150) ? 8192 : 4096;
 229                 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
 230                         n = 11648;
 231                 else
 232                         n = 4096;
 233                 break;
 234
 235         case 44100:
 236                 if (pixel_clk == 25170000)
 237                         n = 7007;
 238                 else if (pixel_clk == 74170000)
 239                         n = 17836;
 240                 else if (pixel_clk == 148350000)
 241                         n = (ratio == 150) ? 17836 : 8918;
 242                 else
 243                         n = 6272;
 244                 break;
 245
 246         case 48000:
 247                 if (pixel_clk == 25170000)
 248                         n = (ratio == 150) ? 9152 : 6864;
 249                 else if (pixel_clk == 27020000)
 250                         n = (ratio == 150) ? 8192 : 6144;
 251                 else if (pixel_clk == 74170000)
 252                         n = 11648;
 253                 else if (pixel_clk == 148350000)
 254                         n = (ratio == 150) ? 11648 : 5824;
 255                 else
 256                         n = 6144;
 257                 break;
 258
 259         case 88200:
 260                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
 261                 break;
 262
 263         case 96000:
 264                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
 265                 break;
 266
 267         case 176400:
 268                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
 269                 break;
 270
 271         case 192000:
 272                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
 273                 break;
 274
 275         default:
 276                 break;
 277         }
 278
 279         return n;
 280 }
 281
 282 static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
 283                                      unsigned int ratio)
 284 {
 285         unsigned int cts = 0;
 286
 287         pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
 288                  pixel_clk, ratio);
 289
 290         switch (freq) {
 291         case 32000:
 292                 if (pixel_clk == 297000000) {
 293                         cts = 222750;
 294                         break;
 295                 }
 296         case 48000:
 297         case 96000:
 298         case 192000:
 299                 switch (pixel_clk) {
 300                 case 25200000:
 301                 case 27000000:
 302                 case 54000000:
 303                 case 74250000:
 304                 case 148500000:
 305                         cts = pixel_clk / 1000;
 306                         break;
 307                 case 297000000:
 308                         cts = 247500;
 309                         break;
 310                 /*
 311                  * All other TMDS clocks are not supported by
 312                  * DWC_hdmi_tx. The TMDS clocks divided or
 313                  * multiplied by 1,001 coefficients are not
 314                  * supported.
 315                  */
 316                 default:
 317                         break;
 318                 }
 319                 break;
 320         case 44100:
 321         case 88200:
 322         case 176400:
 323                 switch (pixel_clk) {
 324                 case 25200000:
 325                         cts = 28000;
 326                         break;
 327                 case 27000000:
 328                         cts = 30000;
 329                         break;
 330                 case 54000000:
 331                         cts = 60000;
 332                         break;
 333                 case 74250000:
 334                         cts = 82500;
 335                         break;
 336                 case 148500000:
 337                         cts = 165000;
 338                         break;
 339                 case 297000000:
 340                         cts = 247500;
 341                         break;
 342                 default:
 343                         break;
 344                 }
 345                 break;
 346         default:
 347                 break;
 348         }
 349         if (ratio == 100)
 350                 return cts;
 351         return (cts * ratio) / 100;
 352 }
 353
 354 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 355         unsigned long pixel_clk, unsigned int sample_rate, unsigned int ratio)
 356 {
 357         unsigned int n, cts;
 358
 359         n = hdmi_compute_n(sample_rate, pixel_clk, ratio);
 360         cts = hdmi_compute_cts(sample_rate, pixel_clk, ratio);
 361         if (!cts) {
 362                 dev_err(hdmi->dev,
 363                         "%s: pixel clock/sample rate not supported: %luMHz / %ukHz\n",
 364                         __func__, pixel_clk, sample_rate);
 365         }
 366
 367         dev_dbg(hdmi->dev, "%s: samplerate=%ukHz ratio=%d pixelclk=%luMHz N=%d cts=%d\n",
 368                 __func__, sample_rate, ratio, pixel_clk, n, cts);
 369
 370         spin_lock_irq(&hdmi->audio_lock);
 371         hdmi->audio_n = n;
 372         hdmi->audio_cts = cts;
 373         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 374         spin_unlock_irq(&hdmi->audio_lock);
 375 }
 376
 377 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 378 {
 379         mutex_lock(&hdmi->audio_mutex);
 380         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate,
 381                                  hdmi->ratio);
 382         mutex_unlock(&hdmi->audio_mutex);
 383 }
 384
 385 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 386 {
 387         mutex_lock(&hdmi->audio_mutex);
 388         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 389                                  hdmi->sample_rate, hdmi->ratio);
 390         mutex_unlock(&hdmi->audio_mutex);
 391 }
 392
 393 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 394 {
 395         mutex_lock(&hdmi->audio_mutex);
 396         hdmi->sample_rate = rate;
 397         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 398                                  hdmi->sample_rate, hdmi->ratio);
 399         mutex_unlock(&hdmi->audio_mutex);
 400 }
 401 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 402
 403 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 404 {
 405         unsigned long flags;
 406
 407         spin_lock_irqsave(&hdmi->audio_lock, flags);
 408         hdmi->audio_enable = true;
 409         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 410         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 411 }
 412 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 413
 414 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 415 {
 416         unsigned long flags;
 417
 418         spin_lock_irqsave(&hdmi->audio_lock, flags);
 419         hdmi->audio_enable = false;
 420         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 421         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 422 }
 423 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 424
 425 /*
 426  * this submodule is responsible for the video data synchronization.
 427  * for example, for RGB 4:4:4 input, the data map is defined as
 428  *                      pin{47~40} <==> R[7:0]
 429  *                      pin{31~24} <==> G[7:0]
 430  *                      pin{15~8}  <==> B[7:0]
 431  */
 432 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 433 {
 434         int color_format = 0;
 435         u8 val;
 436
 437         if (hdmi->hdmi_data.enc_in_format == RGB) {
 438                 if (hdmi->hdmi_data.enc_color_depth == 8)
 439                         color_format = 0x01;
 440                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 441                         color_format = 0x03;
 442                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 443                         color_format = 0x05;
 444                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 445                         color_format = 0x07;
 446                 else
 447                         return;
 448         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 449                 if (hdmi->hdmi_data.enc_color_depth == 8)
 450                         color_format = 0x09;
 451                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 452                         color_format = 0x0B;
 453                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 454                         color_format = 0x0D;
 455                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 456                         color_format = 0x0F;
 457                 else
 458                         return;
 459         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 460                 if (hdmi->hdmi_data.enc_color_depth == 8)
 461                         color_format = 0x16;
 462                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 463                         color_format = 0x14;
 464                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 465                         color_format = 0x12;
 466                 else
 467                         return;
 468         }
 469
 470         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 471                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 472                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 473         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 474
 475         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 476         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 477                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 478                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 479         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 480         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 481         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 482         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 483         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 484         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 485         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 486 }
 487
 488 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 489 {
 490         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 491 }
 492
 493 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 494 {
 495         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 496                 return 0;
 497         if (hdmi->hdmi_data.enc_in_format == RGB ||
 498             hdmi->hdmi_data.enc_in_format == YCBCR444)
 499                 return 1;
 500         return 0;
 501 }
 502
 503 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 504 {
 505         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 506                 return 0;
 507         if (hdmi->hdmi_data.enc_out_format == RGB ||
 508             hdmi->hdmi_data.enc_out_format == YCBCR444)
 509                 return 1;
 510         return 0;
 511 }
 512
 513 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 514 {
 515         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 516         unsigned i;
 517         u32 csc_scale = 1;
 518
 519         if (is_color_space_conversion(hdmi)) {
 520                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 521                         if (hdmi->hdmi_data.colorimetry ==
 522                                         HDMI_COLORIMETRY_ITU_601)
 523                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 524                         else
 525                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 526                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 527                         if (hdmi->hdmi_data.colorimetry ==
 528                                         HDMI_COLORIMETRY_ITU_601)
 529                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 530                         else
 531                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 532                         csc_scale = 0;
 533                 }
 534         }
 535
 536         /* The CSC registers are sequential, alternating MSB then LSB */
 537         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 538                 u16 coeff_a = (*csc_coeff)[0][i];
 539                 u16 coeff_b = (*csc_coeff)[1][i];
 540                 u16 coeff_c = (*csc_coeff)[2][i];
 541
 542                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 543                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 544                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 545                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 546                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 547                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 548         }
 549
 550         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 551                   HDMI_CSC_SCALE);
 552 }
 553
 554 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 555 {
 556         int color_depth = 0;
 557         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 558         int decimation = 0;
 559
 560         /* YCC422 interpolation to 444 mode */
 561         if (is_color_space_interpolation(hdmi))
 562                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 563         else if (is_color_space_decimation(hdmi))
 564                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 565
 566         if (hdmi->hdmi_data.enc_color_depth == 8)
 567                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 568         else if (hdmi->hdmi_data.enc_color_depth == 10)
 569                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 570         else if (hdmi->hdmi_data.enc_color_depth == 12)
 571                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 572         else if (hdmi->hdmi_data.enc_color_depth == 16)
 573                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 574         else
 575                 return;
 576
 577         /* Configure the CSC registers */
 578         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 579         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 580                   HDMI_CSC_SCALE);
 581
 582         dw_hdmi_update_csc_coeffs(hdmi);
 583 }
 584
 585 /*
 586  * HDMI video packetizer is used to packetize the data.
 587  * for example, if input is YCC422 mode or repeater is used,
 588  * data should be repacked this module can be bypassed.
 589  */
 590 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 591 {
 592         unsigned int color_depth = 0;
 593         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 594         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 595         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 596         u8 val, vp_conf;
 597
 598         if (hdmi_data->enc_out_format == RGB ||
 599             hdmi_data->enc_out_format == YCBCR444) {
 600                 if (!hdmi_data->enc_color_depth) {
 601                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 602                 } else if (hdmi_data->enc_color_depth == 8) {
 603                         color_depth = 4;
 604                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 605                 } else if (hdmi_data->enc_color_depth == 10) {
 606                         color_depth = 5;
 607                 } else if (hdmi_data->enc_color_depth == 12) {
 608                         color_depth = 6;
 609                 } else if (hdmi_data->enc_color_depth == 16) {
 610                         color_depth = 7;
 611                 } else {
 612                         return;
 613                 }
 614         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 615                 if (!hdmi_data->enc_color_depth ||
 616                     hdmi_data->enc_color_depth == 8)
 617                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 618                 else if (hdmi_data->enc_color_depth == 10)
 619                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 620                 else if (hdmi_data->enc_color_depth == 12)
 621                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 622                 else
 623                         return;
 624                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 625         } else {
 626                 return;
 627         }
 628
 629         /* set the packetizer registers */
 630         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 631                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 632                 ((hdmi_data->pix_repet_factor <<
 633                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 634                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 635         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 636
 637         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 638                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 639
 640         /* Data from pixel repeater block */
 641         if (hdmi_data->pix_repet_factor > 1) {
 642                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 643                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 644         } else { /* data from packetizer block */
 645                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 646                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 647         }
 648
 649         hdmi_modb(hdmi, vp_conf,
 650                   HDMI_VP_CONF_PR_EN_MASK |
 651                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 652
 653         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 654                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 655
 656         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 657
 658         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 659                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 660                           HDMI_VP_CONF_PP_EN_ENABLE |
 661                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 662         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 663                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 664                           HDMI_VP_CONF_PP_EN_DISABLE |
 665                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 666         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 667                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 668                           HDMI_VP_CONF_PP_EN_DISABLE |
 669                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 670         } else {
 671                 return;
 672         }
 673
 674         hdmi_modb(hdmi, vp_conf,
 675                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 676                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 677
 678         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 679                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 680                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 681                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 682
 683         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 684                   HDMI_VP_CONF);
 685 }
 686
 687 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 688                                        unsigned char bit)
 689 {
 690         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 691                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 692 }
 693
 694 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 695                                         unsigned char bit)
 696 {
 697         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 698                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 699 }
 700
 701 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 702                                        unsigned char bit)
 703 {
 704         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 705                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 706 }
 707
 708 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 709                                      unsigned char bit)
 710 {
 711         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 712 }
 713
 714 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 715                                       unsigned char bit)
 716 {
 717         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 718 }
 719
 720 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 721 {
 722         u32 val;
 723
 724         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 725                 if (msec-- == 0)
 726                         return false;
 727                 udelay(1000);
 728         }
 729         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
 730
 731         return true;
 732 }
 733
 734 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 735                                  unsigned char addr)
 736 {
 737         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
 738         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 739         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
 740                     HDMI_PHY_I2CM_DATAO_1_ADDR);
 741         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
 742                     HDMI_PHY_I2CM_DATAO_0_ADDR);
 743         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
 744                     HDMI_PHY_I2CM_OPERATION_ADDR);
 745         hdmi_phy_wait_i2c_done(hdmi, 1000);
 746 }
 747
 748 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 749                               unsigned char addr)
 750 {
 751         __hdmi_phy_i2c_write(hdmi, data, addr);
 752         return 0;
 753 }
 754
 755 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
 756 {
 757         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
 758                          HDMI_PHY_CONF0_PDZ_OFFSET,
 759                          HDMI_PHY_CONF0_PDZ_MASK);
 760 }
 761
 762 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
 763 {
 764         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 765                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
 766                          HDMI_PHY_CONF0_ENTMDS_MASK);
 767 }
 768
 769 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
 770 {
 771         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 772                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
 773                          HDMI_PHY_CONF0_SPARECTRL_MASK);
 774 }
 775
 776 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
 777 {
 778         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 779                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
 780                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
 781 }
 782
 783 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
 784 {
 785         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 786                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
 787                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
 788 }
 789
 790 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
 791 {
 792         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 793                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
 794                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
 795 }
 796
 797 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
 798 {
 799         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 800                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
 801                          HDMI_PHY_CONF0_SELDIPIF_MASK);
 802 }
 803
 804 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
 805                               unsigned char res, int cscon)
 806 {
 807         unsigned res_idx;
 808         u8 val, msec;
 809         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
 810         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
 811         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
 812         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
 813
 814         if (prep)
 815                 return -EINVAL;
 816
 817         switch (res) {
 818         case 0: /* color resolution 0 is 8 bit colour depth */
 819         case 8:
 820                 res_idx = DW_HDMI_RES_8;
 821                 break;
 822         case 10:
 823                 res_idx = DW_HDMI_RES_10;
 824                 break;
 825         case 12:
 826                 res_idx = DW_HDMI_RES_12;
 827                 break;
 828         default:
 829                 return -EINVAL;
 830         }
 831
 832         /* PLL/MPLL Cfg - always match on final entry */
 833         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
 834                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 835                     mpll_config->mpixelclock)
 836                         break;
 837
 838         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
 839                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 840                     curr_ctrl->mpixelclock)
 841                         break;
 842
 843         for (; phy_config->mpixelclock != ~0UL; phy_config++)
 844                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 845                     phy_config->mpixelclock)
 846                         break;
 847
 848         if (mpll_config->mpixelclock == ~0UL ||
 849             curr_ctrl->mpixelclock == ~0UL ||
 850             phy_config->mpixelclock == ~0UL) {
 851                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
 852                         hdmi->hdmi_data.video_mode.mpixelclock);
 853                 return -EINVAL;
 854         }
 855
 856         /* Enable csc path */
 857         if (cscon)
 858                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
 859         else
 860                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
 861
 862         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
 863
 864         /* gen2 tx power off */
 865         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
 866
 867         /* gen2 pddq */
 868         dw_hdmi_phy_gen2_pddq(hdmi, 1);
 869
 870         /* PHY reset */
 871         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
 872         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
 873
 874         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
 875
 876         hdmi_phy_test_clear(hdmi, 1);
 877         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
 878                     HDMI_PHY_I2CM_SLAVE_ADDR);
 879         hdmi_phy_test_clear(hdmi, 0);
 880
 881         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
 882         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
 883
 884         /* CURRCTRL */
 885         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
 886
 887         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
 888         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
 889
 890         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
 891         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
 892         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
 893
 894         /* REMOVE CLK TERM */
 895         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
 896
 897         dw_hdmi_phy_enable_powerdown(hdmi, false);
 898
 899         /* toggle TMDS enable */
 900         dw_hdmi_phy_enable_tmds(hdmi, 0);
 901         dw_hdmi_phy_enable_tmds(hdmi, 1);
 902
 903         /* gen2 tx power on */
 904         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
 905         dw_hdmi_phy_gen2_pddq(hdmi, 0);
 906
 907         if (hdmi->dev_type == RK3288_HDMI)
 908                 dw_hdmi_phy_enable_spare(hdmi, 1);
 909
 910         /*Wait for PHY PLL lock */
 911         msec = 5;
 912         do {
 913                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
 914                 if (!val)
 915                         break;
 916
 917                 if (msec == 0) {
 918                         dev_err(hdmi->dev, "PHY PLL not locked\n");
 919                         return -ETIMEDOUT;
 920                 }
 921
 922                 udelay(1000);
 923                 msec--;
 924         } while (1);
 925
 926         return 0;
 927 }
 928
 929 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
 930 {
 931         int i, ret;
 932         bool cscon;
 933
 934         /*check csc whether needed activated in HDMI mode */
 935         cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
 936
 937         /* HDMI Phy spec says to do the phy initialization sequence twice */
 938         for (i = 0; i < 2; i++) {
 939                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
 940                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
 941                 dw_hdmi_phy_enable_tmds(hdmi, 0);
 942                 dw_hdmi_phy_enable_powerdown(hdmi, true);
 943
 944                 /* Enable CSC */
 945                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
 946                 if (ret)
 947                         return ret;
 948         }
 949
 950         hdmi->phy_enabled = true;
 951         return 0;
 952 }
 953
 954 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
 955 {
 956         u8 de;
 957
 958         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
 959                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
 960         else
 961                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
 962
 963         /* disable rx detect */
 964         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
 965                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
 966
 967         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
 968
 969         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
 970                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
 971 }
 972
 973 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
 974 {
 975         struct hdmi_avi_infoframe frame;
 976         u8 val;
 977
 978         /* Initialise info frame from DRM mode */
 979         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 980
 981         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
 982                 frame.colorspace = HDMI_COLORSPACE_YUV444;
 983         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
 984                 frame.colorspace = HDMI_COLORSPACE_YUV422;
 985         else
 986                 frame.colorspace = HDMI_COLORSPACE_RGB;
 987
 988         /* Set up colorimetry */
 989         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
 990                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
 991                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
 992                         frame.extended_colorimetry =
 993                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 994                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
 995                         frame.extended_colorimetry =
 996                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
 997         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
 998                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
 999                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1000         } else { /* Carries no data */
1001                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1002                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1003         }
1004
1005         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1006
1007         /*
1008          * The Designware IP uses a different byte format from standard
1009          * AVI info frames, though generally the bits are in the correct
1010          * bytes.
1011          */
1012
1013         /*
1014          * AVI data byte 1 differences: Colorspace in bits 4,5 rather than 5,6,
1015          * active aspect present in bit 6 rather than 4.
1016          */
1017         val = (frame.colorspace & 3) << 4 | (frame.scan_mode & 0x3);
1018         if (frame.active_aspect & 15)
1019                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1020         if (frame.top_bar || frame.bottom_bar)
1021                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1022         if (frame.left_bar || frame.right_bar)
1023                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1024         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1025
1026         /* AVI data byte 2 differences: none */
1027         val = ((frame.colorimetry & 0x3) << 6) |
1028               ((frame.picture_aspect & 0x3) << 4) |
1029               (frame.active_aspect & 0xf);
1030         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1031
1032         /* AVI data byte 3 differences: none */
1033         val = ((frame.extended_colorimetry & 0x7) << 4) |
1034               ((frame.quantization_range & 0x3) << 2) |
1035               (frame.nups & 0x3);
1036         if (frame.itc)
1037                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1038         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1039
1040         /* AVI data byte 4 differences: none */
1041         val = frame.video_code & 0x7f;
1042         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1043
1044         /* AVI Data Byte 5- set up input and output pixel repetition */
1045         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1046                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1047                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1048                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1049                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1050                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1051         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1052
1053         /*
1054          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1055          * ycc range in bits 2,3 rather than 6,7
1056          */
1057         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1058               (frame.content_type & 0x3);
1059         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1060
1061         /* AVI Data Bytes 6-13 */
1062         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1063         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1064         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1065         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1066         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1067         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1068         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1069         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1070 }
1071
1072 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1073                              const struct drm_display_mode *mode)
1074 {
1075         u8 inv_val;
1076         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1077         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1078         unsigned int vdisplay;
1079
1080         vmode->mpixelclock = mode->clock * 1000;
1081
1082         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1083
1084         /* Set up HDMI_FC_INVIDCONF */
1085         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1086                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1087                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1088
1089         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1090                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1091                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1092
1093         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1094                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1095                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1096
1097         inv_val |= (vmode->mdataenablepolarity ?
1098                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1099                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1100
1101         if (hdmi->vic == 39)
1102                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1103         else
1104                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1105                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1106                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1107
1108         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1109                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1110                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1111
1112         inv_val |= hdmi->sink_is_hdmi ?
1113                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1114                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1115
1116         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1117
1118         vdisplay = mode->vdisplay;
1119         vblank = mode->vtotal - mode->vdisplay;
1120         v_de_vs = mode->vsync_start - mode->vdisplay;
1121         vsync_len = mode->vsync_end - mode->vsync_start;
1122
1123         /*
1124          * When we're setting an interlaced mode, we need
1125          * to adjust the vertical timing to suit.
1126          */
1127         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1128                 vdisplay /= 2;
1129                 vblank /= 2;
1130                 v_de_vs /= 2;
1131                 vsync_len /= 2;
1132         }
1133
1134         /* Set up horizontal active pixel width */
1135         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1136         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1137
1138         /* Set up vertical active lines */
1139         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1140         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1141
1142         /* Set up horizontal blanking pixel region width */
1143         hblank = mode->htotal - mode->hdisplay;
1144         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1145         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1146
1147         /* Set up vertical blanking pixel region width */
1148         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1149
1150         /* Set up HSYNC active edge delay width (in pixel clks) */
1151         h_de_hs = mode->hsync_start - mode->hdisplay;
1152         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1153         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1154
1155         /* Set up VSYNC active edge delay (in lines) */
1156         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1157
1158         /* Set up HSYNC active pulse width (in pixel clks) */
1159         hsync_len = mode->hsync_end - mode->hsync_start;
1160         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1161         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1162
1163         /* Set up VSYNC active edge delay (in lines) */
1164         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1165 }
1166
1167 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1168 {
1169         if (!hdmi->phy_enabled)
1170                 return;
1171
1172         dw_hdmi_phy_enable_tmds(hdmi, 0);
1173         dw_hdmi_phy_enable_powerdown(hdmi, true);
1174
1175         hdmi->phy_enabled = false;
1176 }
1177
1178 /* HDMI Initialization Step B.4 */
1179 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1180 {
1181         u8 clkdis;
1182
1183         /* control period minimum duration */
1184         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1185         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1186         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1187
1188         /* Set to fill TMDS data channels */
1189         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1190         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1191         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1192
1193         /* Enable pixel clock and tmds data path */
1194         clkdis = 0x7F;
1195         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1196         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1197
1198         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1199         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1200
1201         /* Enable csc path */
1202         if (is_color_space_conversion(hdmi)) {
1203                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1204                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1205         }
1206 }
1207
1208 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1209 {
1210         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1211 }
1212
1213 /* Workaround to clear the overflow condition */
1214 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1215 {
1216         int count;
1217         u8 val;
1218
1219         /* TMDS software reset */
1220         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1221
1222         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1223         if (hdmi->dev_type == IMX6DL_HDMI) {
1224                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1225                 return;
1226         }
1227
1228         for (count = 0; count < 4; count++)
1229                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1230 }
1231
1232 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1233 {
1234         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1235         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1236 }
1237
1238 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1239 {
1240         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1241                     HDMI_IH_MUTE_FC_STAT2);
1242 }
1243
1244 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1245 {
1246         int ret;
1247
1248         hdmi_disable_overflow_interrupts(hdmi);
1249
1250         hdmi->vic = drm_match_cea_mode(mode);
1251
1252         if (!hdmi->vic) {
1253                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1254         } else {
1255                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1256         }
1257
1258         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1259             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1260             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1261             (hdmi->vic == 17) || (hdmi->vic == 18))
1262                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1263         else
1264                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1265
1266         hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1267         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1268
1269         /* TODO: Get input format from IPU (via FB driver interface) */
1270         hdmi->hdmi_data.enc_in_format = RGB;
1271
1272         hdmi->hdmi_data.enc_out_format = RGB;
1273
1274         hdmi->hdmi_data.enc_color_depth = 8;
1275         hdmi->hdmi_data.pix_repet_factor = 0;
1276         hdmi->hdmi_data.hdcp_enable = 0;
1277         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1278
1279         /* HDMI Initialization Step B.1 */
1280         hdmi_av_composer(hdmi, mode);
1281
1282         /* HDMI Initializateion Step B.2 */
1283         ret = dw_hdmi_phy_init(hdmi);
1284         if (ret)
1285                 return ret;
1286
1287         /* HDMI Initialization Step B.3 */
1288         dw_hdmi_enable_video_path(hdmi);
1289
1290         if (hdmi->sink_has_audio) {
1291                 dev_dbg(hdmi->dev, "sink has audio support\n");
1292
1293                 /* HDMI Initialization Step E - Configure audio */
1294                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1295                 hdmi_enable_audio_clk(hdmi);
1296         }
1297
1298         /* not for DVI mode */
1299         if (hdmi->sink_is_hdmi) {
1300                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1301
1302                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1303                 hdmi_config_AVI(hdmi, mode);
1304         } else {
1305                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1306         }
1307
1308         hdmi_video_packetize(hdmi);
1309         hdmi_video_csc(hdmi);
1310         hdmi_video_sample(hdmi);
1311         hdmi_tx_hdcp_config(hdmi);
1312
1313         dw_hdmi_clear_overflow(hdmi);
1314         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1315                 hdmi_enable_overflow_interrupts(hdmi);
1316
1317         return 0;
1318 }
1319
1320 /* Wait until we are registered to enable interrupts */
1321 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1322 {
1323         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1324                     HDMI_PHY_I2CM_INT_ADDR);
1325
1326         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1327                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1328                     HDMI_PHY_I2CM_CTLINT_ADDR);
1329
1330         /* enable cable hot plug irq */
1331         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1332
1333         /* Clear Hotplug interrupts */
1334         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1335                     HDMI_IH_PHY_STAT0);
1336
1337         return 0;
1338 }
1339
1340 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1341 {
1342         u8 ih_mute;
1343
1344         /*
1345          * Boot up defaults are:
1346          * HDMI_IH_MUTE   = 0x03 (disabled)
1347          * HDMI_IH_MUTE_* = 0x00 (enabled)
1348          *
1349          * Disable top level interrupt bits in HDMI block
1350          */
1351         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1352                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1353                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1354
1355         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1356
1357         /* by default mask all interrupts */
1358         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1359         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1360         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1361         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1362         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1363         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1364         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1365         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1366         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1367         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1368         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1369         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1370         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1371         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1372         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1373
1374         /* Disable interrupts in the IH_MUTE_* registers */
1375         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1376         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1377         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1378         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1379         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1380         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1381         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1382         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1383         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1384         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1385
1386         /* Enable top level interrupt bits in HDMI block */
1387         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1388                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1389         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1390 }
1391
1392 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1393 {
1394         hdmi->bridge_is_on = true;
1395         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1396 }
1397
1398 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1399 {
1400         dw_hdmi_phy_disable(hdmi);
1401         hdmi->bridge_is_on = false;
1402 }
1403
1404 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1405 {
1406         int force = hdmi->force;
1407
1408         if (hdmi->disabled) {
1409                 force = DRM_FORCE_OFF;
1410         } else if (force == DRM_FORCE_UNSPECIFIED) {
1411                 if (hdmi->rxsense)
1412                         force = DRM_FORCE_ON;
1413                 else
1414                         force = DRM_FORCE_OFF;
1415         }
1416
1417         if (force == DRM_FORCE_OFF) {
1418                 if (hdmi->bridge_is_on)
1419                         dw_hdmi_poweroff(hdmi);
1420         } else {
1421                 if (!hdmi->bridge_is_on)
1422                         dw_hdmi_poweron(hdmi);
1423         }
1424 }
1425
1426 /*
1427  * Adjust the detection of RXSENSE according to whether we have a forced
1428  * connection mode enabled, or whether we have been disabled.  There is
1429  * no point processing RXSENSE interrupts if we have a forced connection
1430  * state, or DRM has us disabled.
1431  *
1432  * We also disable rxsense interrupts when we think we're disconnected
1433  * to avoid floating TDMS signals giving false rxsense interrupts.
1434  *
1435  * Note: we still need to listen for HPD interrupts even when DRM has us
1436  * disabled so that we can detect a connect event.
1437  */
1438 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1439 {
1440         u8 old_mask = hdmi->phy_mask;
1441
1442         if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1443                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1444         else
1445                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1446
1447         if (old_mask != hdmi->phy_mask)
1448                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1449 }
1450
1451 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1452                                     struct drm_display_mode *orig_mode,
1453                                     struct drm_display_mode *mode)
1454 {
1455         struct dw_hdmi *hdmi = bridge->driver_private;
1456
1457         mutex_lock(&hdmi->mutex);
1458
1459         /* Store the display mode for plugin/DKMS poweron events */
1460         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1461
1462         mutex_unlock(&hdmi->mutex);
1463 }
1464
1465 static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1466                                       const struct drm_display_mode *mode,
1467                                       struct drm_display_mode *adjusted_mode)
1468 {
1469         return true;
1470 }
1471
1472 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1473 {
1474         struct dw_hdmi *hdmi = bridge->driver_private;
1475
1476         mutex_lock(&hdmi->mutex);
1477         hdmi->disabled = true;
1478         dw_hdmi_update_power(hdmi);
1479         dw_hdmi_update_phy_mask(hdmi);
1480         mutex_unlock(&hdmi->mutex);
1481 }
1482
1483 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1484 {
1485         struct dw_hdmi *hdmi = bridge->driver_private;
1486
1487         mutex_lock(&hdmi->mutex);
1488         hdmi->disabled = false;
1489         dw_hdmi_update_power(hdmi);
1490         dw_hdmi_update_phy_mask(hdmi);
1491         mutex_unlock(&hdmi->mutex);
1492 }
1493
1494 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1495 {
1496         /* do nothing */
1497 }
1498
1499 static enum drm_connector_status
1500 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1501 {
1502         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1503                                              connector);
1504
1505         mutex_lock(&hdmi->mutex);
1506         hdmi->force = DRM_FORCE_UNSPECIFIED;
1507         dw_hdmi_update_power(hdmi);
1508         dw_hdmi_update_phy_mask(hdmi);
1509         mutex_unlock(&hdmi->mutex);
1510
1511         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1512                 connector_status_connected : connector_status_disconnected;
1513 }
1514
1515 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1516 {
1517         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1518                                              connector);
1519         struct edid *edid;
1520         int ret = 0;
1521
1522         if (!hdmi->ddc)
1523                 return 0;
1524
1525         edid = drm_get_edid(connector, hdmi->ddc);
1526         if (edid) {
1527                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1528                         edid->width_cm, edid->height_cm);
1529
1530                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1531                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1532                 drm_mode_connector_update_edid_property(connector, edid);
1533                 ret = drm_add_edid_modes(connector, edid);
1534                 kfree(edid);
1535         } else {
1536                 dev_dbg(hdmi->dev, "failed to get edid\n");
1537         }
1538
1539         return ret;
1540 }
1541
1542 static enum drm_mode_status
1543 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1544                              struct drm_display_mode *mode)
1545 {
1546         struct dw_hdmi *hdmi = container_of(connector,
1547                                            struct dw_hdmi, connector);
1548         enum drm_mode_status mode_status = MODE_OK;
1549
1550         /* We don't support double-clocked modes */
1551         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1552                 return MODE_BAD;
1553
1554         if (hdmi->plat_data->mode_valid)
1555                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1556
1557         return mode_status;
1558 }
1559
1560 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1561                                                            *connector)
1562 {
1563         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1564                                              connector);
1565
1566         return hdmi->encoder;
1567 }
1568
1569 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1570 {
1571         drm_connector_unregister(connector);
1572         drm_connector_cleanup(connector);
1573 }
1574
1575 static void dw_hdmi_connector_force(struct drm_connector *connector)
1576 {
1577         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1578                                              connector);
1579
1580         mutex_lock(&hdmi->mutex);
1581         hdmi->force = connector->force;
1582         dw_hdmi_update_power(hdmi);
1583         dw_hdmi_update_phy_mask(hdmi);
1584         mutex_unlock(&hdmi->mutex);
1585 }
1586
1587 static struct drm_connector_funcs dw_hdmi_connector_funcs = {
1588         .dpms = drm_helper_connector_dpms,
1589         .fill_modes = drm_helper_probe_single_connector_modes,
1590         .detect = dw_hdmi_connector_detect,
1591         .destroy = dw_hdmi_connector_destroy,
1592         .force = dw_hdmi_connector_force,
1593 };
1594
1595 static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1596         .get_modes = dw_hdmi_connector_get_modes,
1597         .mode_valid = dw_hdmi_connector_mode_valid,
1598         .best_encoder = dw_hdmi_connector_best_encoder,
1599 };
1600
1601 static struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1602         .enable = dw_hdmi_bridge_enable,
1603         .disable = dw_hdmi_bridge_disable,
1604         .pre_enable = dw_hdmi_bridge_nop,
1605         .post_disable = dw_hdmi_bridge_nop,
1606         .mode_set = dw_hdmi_bridge_mode_set,
1607         .mode_fixup = dw_hdmi_bridge_mode_fixup,
1608 };
1609
1610 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1611 {
1612         struct dw_hdmi *hdmi = dev_id;
1613         u8 intr_stat;
1614
1615         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1616         if (intr_stat)
1617                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1618
1619         return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1620 }
1621
1622 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1623 {
1624         struct dw_hdmi *hdmi = dev_id;
1625         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
1626
1627         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1628         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1629         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1630
1631         phy_pol_mask = 0;
1632         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1633                 phy_pol_mask |= HDMI_PHY_HPD;
1634         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
1635                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
1636         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
1637                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
1638         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
1639                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
1640         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
1641                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
1642
1643         if (phy_pol_mask)
1644                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
1645
1646         /*
1647          * RX sense tells us whether the TDMS transmitters are detecting
1648          * load - in other words, there's something listening on the
1649          * other end of the link.  Use this to decide whether we should
1650          * power on the phy as HPD may be toggled by the sink to merely
1651          * ask the source to re-read the EDID.
1652          */
1653         if (intr_stat &
1654             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
1655                 mutex_lock(&hdmi->mutex);
1656                 if (!hdmi->disabled && !hdmi->force) {
1657                         /*
1658                          * If the RX sense status indicates we're disconnected,
1659                          * clear the software rxsense status.
1660                          */
1661                         if (!(phy_stat & HDMI_PHY_RX_SENSE))
1662                                 hdmi->rxsense = false;
1663
1664                         /*
1665                          * Only set the software rxsense status when both
1666                          * rxsense and hpd indicates we're connected.
1667                          * This avoids what seems to be bad behaviour in
1668                          * at least iMX6S versions of the phy.
1669                          */
1670                         if (phy_stat & HDMI_PHY_HPD)
1671                                 hdmi->rxsense = true;
1672
1673                         dw_hdmi_update_power(hdmi);
1674                         dw_hdmi_update_phy_mask(hdmi);
1675                 }
1676                 mutex_unlock(&hdmi->mutex);
1677         }
1678
1679         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1680                 dev_dbg(hdmi->dev, "EVENT=%s\n",
1681                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
1682                 drm_helper_hpd_irq_event(hdmi->bridge->dev);
1683         }
1684
1685         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1686         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1687                     HDMI_IH_MUTE_PHY_STAT0);
1688
1689         return IRQ_HANDLED;
1690 }
1691
1692 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1693 {
1694         struct drm_encoder *encoder = hdmi->encoder;
1695         struct drm_bridge *bridge;
1696         int ret;
1697
1698         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1699         if (!bridge) {
1700                 DRM_ERROR("Failed to allocate drm bridge\n");
1701                 return -ENOMEM;
1702         }
1703
1704         hdmi->bridge = bridge;
1705         bridge->driver_private = hdmi;
1706         bridge->funcs = &dw_hdmi_bridge_funcs;
1707         ret = drm_bridge_attach(drm, bridge);
1708         if (ret) {
1709                 DRM_ERROR("Failed to initialize bridge with drm\n");
1710                 return -EINVAL;
1711         }
1712
1713         encoder->bridge = bridge;
1714         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1715
1716         drm_connector_helper_add(&hdmi->connector,
1717                                  &dw_hdmi_connector_helper_funcs);
1718         drm_connector_init(drm, &hdmi->connector, &dw_hdmi_connector_funcs,
1719                            DRM_MODE_CONNECTOR_HDMIA);
1720
1721         hdmi->connector.encoder = encoder;
1722
1723         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1724
1725         return 0;
1726 }
1727
1728 int dw_hdmi_bind(struct device *dev, struct device *master,
1729                  void *data, struct drm_encoder *encoder,
1730                  struct resource *iores, int irq,
1731                  const struct dw_hdmi_plat_data *plat_data)
1732 {
1733         struct drm_device *drm = data;
1734         struct device_node *np = dev->of_node;
1735         struct device_node *ddc_node;
1736         struct dw_hdmi *hdmi;
1737         int ret;
1738         u32 val = 1;
1739
1740         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1741         if (!hdmi)
1742                 return -ENOMEM;
1743
1744         hdmi->connector.interlace_allowed = 1;
1745
1746         hdmi->plat_data = plat_data;
1747         hdmi->dev = dev;
1748         hdmi->dev_type = plat_data->dev_type;
1749         hdmi->sample_rate = 48000;
1750         hdmi->ratio = 100;
1751         hdmi->encoder = encoder;
1752         hdmi->disabled = true;
1753         hdmi->rxsense = true;
1754         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
1755
1756         mutex_init(&hdmi->mutex);
1757         mutex_init(&hdmi->audio_mutex);
1758         spin_lock_init(&hdmi->audio_lock);
1759
1760         of_property_read_u32(np, "reg-io-width", &val);
1761
1762         switch (val) {
1763         case 4:
1764                 hdmi->write = dw_hdmi_writel;
1765                 hdmi->read = dw_hdmi_readl;
1766                 break;
1767         case 1:
1768                 hdmi->write = dw_hdmi_writeb;
1769                 hdmi->read = dw_hdmi_readb;
1770                 break;
1771         default:
1772                 dev_err(dev, "reg-io-width must be 1 or 4\n");
1773                 return -EINVAL;
1774         }
1775
1776         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1777         if (ddc_node) {
1778                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1779                 of_node_put(ddc_node);
1780                 if (!hdmi->ddc) {
1781                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
1782                         return -EPROBE_DEFER;
1783                 }
1784
1785         } else {
1786                 dev_dbg(hdmi->dev, "no ddc property found\n");
1787         }
1788
1789         hdmi->regs = devm_ioremap_resource(dev, iores);
1790         if (IS_ERR(hdmi->regs))
1791                 return PTR_ERR(hdmi->regs);
1792
1793         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1794         if (IS_ERR(hdmi->isfr_clk)) {
1795                 ret = PTR_ERR(hdmi->isfr_clk);
1796                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1797                 return ret;
1798         }
1799
1800         ret = clk_prepare_enable(hdmi->isfr_clk);
1801         if (ret) {
1802                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1803                 return ret;
1804         }
1805
1806         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1807         if (IS_ERR(hdmi->iahb_clk)) {
1808                 ret = PTR_ERR(hdmi->iahb_clk);
1809                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1810                 goto err_isfr;
1811         }
1812
1813         ret = clk_prepare_enable(hdmi->iahb_clk);
1814         if (ret) {
1815                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1816                 goto err_isfr;
1817         }
1818
1819         /* Product and revision IDs */
1820         dev_info(dev,
1821                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1822                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
1823                  hdmi_readb(hdmi, HDMI_REVISION_ID),
1824                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1825                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1826
1827         initialize_hdmi_ih_mutes(hdmi);
1828
1829         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1830                                         dw_hdmi_irq, IRQF_SHARED,
1831                                         dev_name(dev), hdmi);
1832         if (ret)
1833                 goto err_iahb;
1834
1835         /*
1836          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1837          * N and cts values before enabling phy
1838          */
1839         hdmi_init_clk_regenerator(hdmi);
1840
1841         /*
1842          * Configure registers related to HDMI interrupt
1843          * generation before registering IRQ.
1844          */
1845         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1846
1847         /* Clear Hotplug interrupts */
1848         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1849                     HDMI_IH_PHY_STAT0);
1850
1851         ret = dw_hdmi_fb_registered(hdmi);
1852         if (ret)
1853                 goto err_iahb;
1854
1855         ret = dw_hdmi_register(drm, hdmi);
1856         if (ret)
1857                 goto err_iahb;
1858
1859         /* Unmute interrupts */
1860         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1861                     HDMI_IH_MUTE_PHY_STAT0);
1862
1863         dev_set_drvdata(dev, hdmi);
1864
1865         return 0;
1866
1867 err_iahb:
1868         clk_disable_unprepare(hdmi->iahb_clk);
1869 err_isfr:
1870         clk_disable_unprepare(hdmi->isfr_clk);
1871
1872         return ret;
1873 }
1874 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
1875
1876 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
1877 {
1878         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
1879
1880         /* Disable all interrupts */
1881         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1882
1883         hdmi->connector.funcs->destroy(&hdmi->connector);
1884         hdmi->encoder->funcs->destroy(hdmi->encoder);
1885
1886         clk_disable_unprepare(hdmi->iahb_clk);
1887         clk_disable_unprepare(hdmi->isfr_clk);
1888         i2c_put_adapter(hdmi->ddc);
1889 }
1890 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
1891
1892 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1893 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1894 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
1895 MODULE_DESCRIPTION("DW HDMI transmitter driver");
1896 MODULE_LICENSE("GPL");
1897 MODULE_ALIAS("platform:dw-hdmi");