2 * Silicon Image SiI8620 HDMI/MHL bridge driver
4 * Copyright (C) 2015, Samsung Electronics Co., Ltd.
5 * Andrzej Hajda <a.hajda@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <drm/bridge/mhl.h>
13 #include <drm/drm_crtc.h>
14 #include <drm/drm_edid.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/i2c.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/mutex.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/slab.h>
29 #include "sil-sii8620.h"
31 #define VAL_RX_HDMI_CTRL2_DEFVAL VAL_RX_HDMI_CTRL2_IDLE_CNT(3)
41 enum sii8620_sink_type {
47 enum sii8620_mt_state {
54 struct drm_bridge bridge;
57 struct gpio_desc *gpio_reset;
58 struct gpio_desc *gpio_int;
59 struct regulator_bulk_data supplies[2];
60 struct mutex lock; /* context lock, protects fields below */
62 enum sii8620_mode mode;
63 enum sii8620_sink_type sink_type;
65 u8 stat[MHL_DST_SIZE];
66 u8 xstat[MHL_XDS_SIZE];
67 u8 devcap[MHL_DCAP_SIZE];
68 u8 xdevcap[MHL_XDC_SIZE];
71 unsigned int gen2_write_burst:1;
72 enum sii8620_mt_state mt_state;
73 struct list_head mt_queue;
76 struct sii8620_mt_msg;
78 typedef void (*sii8620_mt_msg_cb)(struct sii8620 *ctx,
79 struct sii8620_mt_msg *msg);
81 struct sii8620_mt_msg {
82 struct list_head node;
85 sii8620_mt_msg_cb send;
86 sii8620_mt_msg_cb recv;
89 static const u8 sii8620_i2c_page[] = {
90 0x39, /* Main System */
91 0x3d, /* TDM and HSIC */
92 0x49, /* TMDS Receiver, MHL EDID */
93 0x4d, /* eMSC, HDCP, HSIC */
96 0x59, /* Hardware TPI (Transmitter Programming Interface) */
97 0x61, /* eCBUS-S, eCBUS-D */
100 static void sii8620_fetch_edid(struct sii8620 *ctx);
101 static void sii8620_set_upstream_edid(struct sii8620 *ctx);
102 static void sii8620_enable_hpd(struct sii8620 *ctx);
103 static void sii8620_mhl_disconnected(struct sii8620 *ctx);
105 static int sii8620_clear_error(struct sii8620 *ctx)
107 int ret = ctx->error;
113 static void sii8620_read_buf(struct sii8620 *ctx, u16 addr, u8 *buf, int len)
115 struct device *dev = ctx->dev;
116 struct i2c_client *client = to_i2c_client(dev);
118 struct i2c_msg msg[] = {
120 .addr = sii8620_i2c_page[addr >> 8],
121 .flags = client->flags,
126 .addr = sii8620_i2c_page[addr >> 8],
127 .flags = client->flags | I2C_M_RD,
137 ret = i2c_transfer(client->adapter, msg, 2);
138 dev_dbg(dev, "read at %04x: %*ph, %d\n", addr, len, buf, ret);
141 dev_err(dev, "Read at %#06x of %d bytes failed with code %d.\n",
143 ctx->error = ret < 0 ? ret : -EIO;
147 static u8 sii8620_readb(struct sii8620 *ctx, u16 addr)
151 sii8620_read_buf(ctx, addr, &ret, 1);
155 static void sii8620_write_buf(struct sii8620 *ctx, u16 addr, const u8 *buf,
158 struct device *dev = ctx->dev;
159 struct i2c_client *client = to_i2c_client(dev);
161 struct i2c_msg msg = {
162 .addr = sii8620_i2c_page[addr >> 8],
163 .flags = client->flags,
172 msg.buf = kmalloc(len + 1, GFP_KERNEL);
174 ctx->error = -ENOMEM;
177 memcpy(msg.buf + 1, buf, len);
185 ret = i2c_transfer(client->adapter, &msg, 1);
186 dev_dbg(dev, "write at %04x: %*ph, %d\n", addr, len, buf, ret);
189 dev_err(dev, "Write at %#06x of %*ph failed with code %d.\n",
190 addr, len, buf, ret);
191 ctx->error = ret ?: -EIO;
198 #define sii8620_write(ctx, addr, arr...) \
201 sii8620_write_buf(ctx, addr, d, ARRAY_SIZE(d)); \
204 static void __sii8620_write_seq(struct sii8620 *ctx, const u16 *seq, int len)
208 for (i = 0; i < len; i += 2)
209 sii8620_write(ctx, seq[i], seq[i + 1]);
212 #define sii8620_write_seq(ctx, seq...) \
214 const u16 d[] = { seq }; \
215 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \
218 #define sii8620_write_seq_static(ctx, seq...) \
220 static const u16 d[] = { seq }; \
221 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \
224 static void sii8620_setbits(struct sii8620 *ctx, u16 addr, u8 mask, u8 val)
226 val = (val & mask) | (sii8620_readb(ctx, addr) & ~mask);
227 sii8620_write(ctx, addr, val);
230 static void sii8620_mt_cleanup(struct sii8620 *ctx)
232 struct sii8620_mt_msg *msg, *n;
234 list_for_each_entry_safe(msg, n, &ctx->mt_queue, node) {
235 list_del(&msg->node);
238 ctx->mt_state = MT_STATE_READY;
241 static void sii8620_mt_work(struct sii8620 *ctx)
243 struct sii8620_mt_msg *msg;
247 if (ctx->mt_state == MT_STATE_BUSY || list_empty(&ctx->mt_queue))
250 if (ctx->mt_state == MT_STATE_DONE) {
251 ctx->mt_state = MT_STATE_READY;
252 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg,
256 list_del(&msg->node);
260 if (ctx->mt_state != MT_STATE_READY || list_empty(&ctx->mt_queue))
263 ctx->mt_state = MT_STATE_BUSY;
264 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node);
269 static void sii8620_mt_msc_cmd_send(struct sii8620 *ctx,
270 struct sii8620_mt_msg *msg)
272 switch (msg->reg[0]) {
275 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg + 1, 2);
276 sii8620_write(ctx, REG_MSC_COMMAND_START,
277 BIT_MSC_COMMAND_START_WRITE_STAT);
280 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg, 3);
281 sii8620_write(ctx, REG_MSC_COMMAND_START,
282 BIT_MSC_COMMAND_START_MSC_MSG);
285 dev_err(ctx->dev, "%s: command %#x not supported\n", __func__,
290 static struct sii8620_mt_msg *sii8620_mt_msg_new(struct sii8620 *ctx)
292 struct sii8620_mt_msg *msg = kzalloc(sizeof(*msg), GFP_KERNEL);
295 ctx->error = -ENOMEM;
297 list_add_tail(&msg->node, &ctx->mt_queue);
302 static void sii8620_mt_msc_cmd(struct sii8620 *ctx, u8 cmd, u8 arg1, u8 arg2)
304 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
312 msg->send = sii8620_mt_msc_cmd_send;
315 static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val)
317 sii8620_mt_msc_cmd(ctx, MHL_WRITE_STAT, reg, val);
320 static inline void sii8620_mt_set_int(struct sii8620 *ctx, u8 irq, u8 mask)
322 sii8620_mt_msc_cmd(ctx, MHL_SET_INT, irq, mask);
325 static void sii8620_mt_msc_msg(struct sii8620 *ctx, u8 cmd, u8 data)
327 sii8620_mt_msc_cmd(ctx, MHL_MSC_MSG, cmd, data);
330 static void sii8620_mt_rap(struct sii8620 *ctx, u8 code)
332 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RAP, code);
335 static void sii8620_mt_read_devcap_send(struct sii8620 *ctx,
336 struct sii8620_mt_msg *msg)
338 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP
339 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
340 | BIT_EDID_CTRL_EDID_MODE_EN;
342 if (msg->reg[0] == MHL_READ_XDEVCAP)
343 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN;
345 sii8620_write_seq(ctx,
346 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE,
348 REG_TPI_CBUS_START, BIT_TPI_CBUS_START_GET_DEVCAP_START
352 /* copy src to dst and set changed bits in src */
353 static void sii8620_update_array(u8 *dst, u8 *src, int count)
355 while (--count >= 0) {
361 static void sii8620_mr_devcap(struct sii8620 *ctx)
363 static const char * const sink_str[] = {
364 [SINK_NONE] = "NONE",
365 [SINK_HDMI] = "HDMI",
369 u8 dcap[MHL_DCAP_SIZE];
371 struct device *dev = ctx->dev;
373 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, dcap, MHL_DCAP_SIZE);
377 dev_info(dev, "dcap: %*ph\n", MHL_DCAP_SIZE, dcap);
378 dev_info(dev, "detected dongle MHL %d.%d, ChipID %02x%02x:%02x%02x\n",
379 dcap[MHL_DCAP_MHL_VERSION] / 16,
380 dcap[MHL_DCAP_MHL_VERSION] % 16, dcap[MHL_DCAP_ADOPTER_ID_H],
381 dcap[MHL_DCAP_ADOPTER_ID_L], dcap[MHL_DCAP_DEVICE_ID_H],
382 dcap[MHL_DCAP_DEVICE_ID_L]);
383 sii8620_update_array(ctx->devcap, dcap, MHL_DCAP_SIZE);
385 if (!(dcap[MHL_DCAP_CAT] & MHL_DCAP_CAT_SINK))
388 sii8620_fetch_edid(ctx);
390 dev_err(ctx->dev, "Cannot fetch EDID\n");
391 sii8620_mhl_disconnected(ctx);
395 if (drm_detect_hdmi_monitor(ctx->edid))
396 ctx->sink_type = SINK_HDMI;
398 ctx->sink_type = SINK_DVI;
400 drm_edid_get_monitor_name(ctx->edid, sink_name, ARRAY_SIZE(sink_name));
402 dev_info(dev, "detected sink(type: %s): %s\n",
403 sink_str[ctx->sink_type], sink_name);
404 sii8620_set_upstream_edid(ctx);
405 sii8620_enable_hpd(ctx);
408 static void sii8620_mr_xdevcap(struct sii8620 *ctx)
410 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, ctx->xdevcap,
413 sii8620_mt_write_stat(ctx, MHL_XDS_REG(CURR_ECBUS_MODE),
414 MHL_XDS_ECBUS_S | MHL_XDS_SLOT_MODE_8BIT);
415 sii8620_mt_rap(ctx, MHL_RAP_CBUS_MODE_UP);
418 static void sii8620_mt_read_devcap_recv(struct sii8620 *ctx,
419 struct sii8620_mt_msg *msg)
421 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP
422 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
423 | BIT_EDID_CTRL_EDID_MODE_EN;
425 if (msg->reg[0] == MHL_READ_XDEVCAP)
426 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN;
428 sii8620_write_seq(ctx,
429 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE | BIT_INTR9_EDID_DONE
430 | BIT_INTR9_EDID_ERROR,
432 REG_EDID_FIFO_ADDR, 0
435 if (msg->reg[0] == MHL_READ_XDEVCAP)
436 sii8620_mr_xdevcap(ctx);
438 sii8620_mr_devcap(ctx);
441 static void sii8620_mt_read_devcap(struct sii8620 *ctx, bool xdevcap)
443 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
448 msg->reg[0] = xdevcap ? MHL_READ_XDEVCAP : MHL_READ_DEVCAP;
449 msg->send = sii8620_mt_read_devcap_send;
450 msg->recv = sii8620_mt_read_devcap_recv;
453 static void sii8620_fetch_edid(struct sii8620 *ctx)
455 u8 lm_ddc, ddc_cmd, int3, cbus;
457 int edid_len = EDID_LENGTH;
460 sii8620_readb(ctx, REG_CBUS_STATUS);
461 lm_ddc = sii8620_readb(ctx, REG_LM_DDC);
462 ddc_cmd = sii8620_readb(ctx, REG_DDC_CMD);
464 sii8620_write_seq(ctx,
466 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO,
467 REG_HDCP2X_POLL_CS, 0x71,
468 REG_HDCP2X_CTRL_0, BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX,
469 REG_LM_DDC, lm_ddc | BIT_LM_DDC_SW_TPI_EN_DISABLED,
472 for (i = 0; i < 256; ++i) {
473 u8 ddc_stat = sii8620_readb(ctx, REG_DDC_STATUS);
475 if (!(ddc_stat & BIT_DDC_STATUS_DDC_I2C_IN_PROG))
477 sii8620_write(ctx, REG_DDC_STATUS,
478 BIT_DDC_STATUS_DDC_FIFO_EMPTY);
481 sii8620_write(ctx, REG_DDC_ADDR, 0x50 << 1);
483 edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
485 ctx->error = -ENOMEM;
489 #define FETCH_SIZE 16
490 for (fetched = 0; fetched < edid_len; fetched += FETCH_SIZE) {
491 sii8620_readb(ctx, REG_DDC_STATUS);
492 sii8620_write_seq(ctx,
493 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_ABORT,
494 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO,
495 REG_DDC_STATUS, BIT_DDC_STATUS_DDC_FIFO_EMPTY
497 sii8620_write_seq(ctx,
498 REG_DDC_SEGM, fetched >> 8,
499 REG_DDC_OFFSET, fetched & 0xff,
500 REG_DDC_DIN_CNT1, FETCH_SIZE,
502 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_ENH_DDC_READ_NO_ACK
506 int3 = sii8620_readb(ctx, REG_INTR3);
507 cbus = sii8620_readb(ctx, REG_CBUS_STATUS);
509 if (int3 & BIT_DDC_CMD_DONE)
512 if (!(cbus & BIT_CBUS_STATUS_CBUS_CONNECTED)) {
519 sii8620_readb(ctx, REG_DDC_STATUS);
520 while (sii8620_readb(ctx, REG_DDC_DOUT_CNT) < FETCH_SIZE)
521 usleep_range(10, 20);
523 sii8620_read_buf(ctx, REG_DDC_DATA, edid + fetched, FETCH_SIZE);
524 if (fetched + FETCH_SIZE == EDID_LENGTH) {
525 u8 ext = ((struct edid *)edid)->extensions;
530 edid_len += ext * EDID_LENGTH;
531 new_edid = krealloc(edid, edid_len, GFP_KERNEL);
534 ctx->error = -ENOMEM;
541 if (fetched + FETCH_SIZE == edid_len)
542 sii8620_write(ctx, REG_INTR3, int3);
545 sii8620_write(ctx, REG_LM_DDC, lm_ddc);
549 ctx->edid = (struct edid *)edid;
552 static void sii8620_set_upstream_edid(struct sii8620 *ctx)
554 sii8620_setbits(ctx, REG_DPD, BIT_DPD_PDNRX12 | BIT_DPD_PDIDCK_N
555 | BIT_DPD_PD_MHL_CLK_N, 0xff);
557 sii8620_write_seq_static(ctx,
558 REG_RX_HDMI_CTRL3, 0x00,
559 REG_PKT_FILTER_0, 0xFF,
560 REG_PKT_FILTER_1, 0xFF,
561 REG_ALICE0_BW_I2C, 0x06
564 sii8620_setbits(ctx, REG_RX_HDMI_CLR_BUFFER,
565 BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN, 0xff);
567 sii8620_write_seq_static(ctx,
568 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
569 | BIT_EDID_CTRL_EDID_MODE_EN,
570 REG_EDID_FIFO_ADDR, 0,
573 sii8620_write_buf(ctx, REG_EDID_FIFO_WR_DATA, (u8 *)ctx->edid,
574 (ctx->edid->extensions + 1) * EDID_LENGTH);
576 sii8620_write_seq_static(ctx,
577 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID
578 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
579 | BIT_EDID_CTRL_EDID_MODE_EN,
580 REG_INTR5_MASK, BIT_INTR_SCDT_CHANGE,
585 static void sii8620_xtal_set_rate(struct sii8620 *ctx)
587 static const struct {
592 { 19200, 0x04, 0x53 },
593 { 20000, 0x04, 0x62 },
594 { 24000, 0x05, 0x75 },
595 { 30000, 0x06, 0x92 },
596 { 38400, 0x0c, 0xbc },
598 unsigned long rate = clk_get_rate(ctx->clk_xtal) / 1000;
601 for (i = 0; i < ARRAY_SIZE(rates) - 1; ++i)
602 if (rate <= rates[i].rate)
605 if (rate != rates[i].rate)
606 dev_err(ctx->dev, "xtal clock rate(%lukHz) not supported, setting MHL for %ukHz.\n",
607 rate, rates[i].rate);
609 sii8620_write(ctx, REG_DIV_CTL_MAIN, rates[i].div);
610 sii8620_write(ctx, REG_HDCP2X_TP1, rates[i].tp1);
613 static int sii8620_hw_on(struct sii8620 *ctx)
617 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
620 usleep_range(10000, 20000);
621 return clk_prepare_enable(ctx->clk_xtal);
624 static int sii8620_hw_off(struct sii8620 *ctx)
626 clk_disable_unprepare(ctx->clk_xtal);
627 gpiod_set_value(ctx->gpio_reset, 1);
628 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
631 static void sii8620_hw_reset(struct sii8620 *ctx)
633 usleep_range(10000, 20000);
634 gpiod_set_value(ctx->gpio_reset, 0);
635 usleep_range(5000, 20000);
636 gpiod_set_value(ctx->gpio_reset, 1);
637 usleep_range(10000, 20000);
638 gpiod_set_value(ctx->gpio_reset, 0);
642 static void sii8620_cbus_reset(struct sii8620 *ctx)
644 sii8620_write_seq_static(ctx,
645 REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST
646 | BIT_PWD_SRST_CBUS_RST_SW_EN,
647 REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN
651 static void sii8620_set_auto_zone(struct sii8620 *ctx)
653 if (ctx->mode != CM_MHL1) {
654 sii8620_write_seq_static(ctx,
655 REG_TX_ZONE_CTL1, 0x0,
656 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
657 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
658 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE
661 sii8620_write_seq_static(ctx,
662 REG_TX_ZONE_CTL1, VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE,
663 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
664 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE
669 static void sii8620_stop_video(struct sii8620 *ctx)
671 u8 uninitialized_var(val);
673 sii8620_write_seq_static(ctx,
675 REG_HDCP2X_INTR0_MASK, 0,
676 REG_TPI_COPP_DATA2, 0,
677 REG_TPI_INTR_ST0, ~0,
680 switch (ctx->sink_type) {
682 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN
683 | BIT_TPI_SC_TPI_AV_MUTE;
686 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN
687 | BIT_TPI_SC_TPI_AV_MUTE
688 | BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI;
694 sii8620_write(ctx, REG_TPI_SC, val);
697 static void sii8620_start_hdmi(struct sii8620 *ctx)
699 sii8620_write_seq_static(ctx,
700 REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL
701 | BIT_RX_HDMI_CTRL2_USE_AV_MUTE,
702 REG_VID_OVRRD, BIT_VID_OVRRD_PP_AUTO_DISABLE
703 | BIT_VID_OVRRD_M1080P_OVRRD,
705 REG_MHL_TOP_CTL, 0x1,
706 REG_MHLTX_CTL6, 0xa0,
707 REG_TPI_INPUT, VAL_TPI_FORMAT(RGB, FULL),
708 REG_TPI_OUTPUT, VAL_TPI_FORMAT(RGB, FULL),
711 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
712 MHL_DST_LM_CLK_MODE_NORMAL |
713 MHL_DST_LM_PATH_ENABLED);
715 sii8620_set_auto_zone(ctx);
717 sii8620_write(ctx, REG_TPI_SC, BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI);
719 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, ctx->avif,
720 ARRAY_SIZE(ctx->avif));
722 sii8620_write(ctx, REG_PKT_FILTER_0, 0xa1, 0x2);
725 static void sii8620_start_video(struct sii8620 *ctx)
727 if (ctx->mode < CM_MHL3)
728 sii8620_stop_video(ctx);
730 switch (ctx->sink_type) {
732 sii8620_start_hdmi(ctx);
740 static void sii8620_disable_hpd(struct sii8620 *ctx)
742 sii8620_setbits(ctx, REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID, 0);
743 sii8620_write_seq_static(ctx,
744 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN,
749 static void sii8620_enable_hpd(struct sii8620 *ctx)
751 sii8620_setbits(ctx, REG_TMDS_CSTAT_P3,
752 BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS
753 | BIT_TMDS_CSTAT_P3_CLR_AVI, ~0);
754 sii8620_write_seq_static(ctx,
755 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN
756 | BIT_HPD_CTRL_HPD_HIGH,
760 static void sii8620_enable_gen2_write_burst(struct sii8620 *ctx)
762 if (ctx->gen2_write_burst)
765 sii8620_write_seq_static(ctx,
766 REG_MDT_RCV_TIMEOUT, 100,
767 REG_MDT_RCV_CTRL, BIT_MDT_RCV_CTRL_MDT_RCV_EN
769 ctx->gen2_write_burst = 1;
772 static void sii8620_disable_gen2_write_burst(struct sii8620 *ctx)
774 if (!ctx->gen2_write_burst)
777 sii8620_write_seq_static(ctx,
778 REG_MDT_XMIT_CTRL, 0,
781 ctx->gen2_write_burst = 0;
784 static void sii8620_start_gen2_write_burst(struct sii8620 *ctx)
786 sii8620_write_seq_static(ctx,
787 REG_MDT_INT_1_MASK, BIT_MDT_RCV_TIMEOUT
788 | BIT_MDT_RCV_SM_ABORT_PKT_RCVD | BIT_MDT_RCV_SM_ERROR
789 | BIT_MDT_XMIT_TIMEOUT | BIT_MDT_XMIT_SM_ABORT_PKT_RCVD
790 | BIT_MDT_XMIT_SM_ERROR,
791 REG_MDT_INT_0_MASK, BIT_MDT_XFIFO_EMPTY
792 | BIT_MDT_IDLE_AFTER_HAWB_DISABLE
793 | BIT_MDT_RFIFO_DATA_RDY
795 sii8620_enable_gen2_write_burst(ctx);
798 static void sii8620_mhl_discover(struct sii8620 *ctx)
800 sii8620_write_seq_static(ctx,
801 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
802 | BIT_DISC_CTRL9_DISC_PULSE_PROCEED,
803 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_5K, VAL_PUP_20K),
804 REG_CBUS_DISC_INTR0_MASK, BIT_MHL3_EST_INT
806 | BIT_NOT_MHL_EST_INT
807 | BIT_CBUS_MHL3_DISCON_INT
808 | BIT_CBUS_MHL12_DISCON_INT
809 | BIT_RGND_READY_INT,
810 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
811 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
812 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE,
813 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE
814 | BIT_MHL_DP_CTL0_TX_OE_OVR,
815 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE,
816 REG_MHL_DP_CTL1, 0xA2,
817 REG_MHL_DP_CTL2, 0x03,
818 REG_MHL_DP_CTL3, 0x35,
819 REG_MHL_DP_CTL5, 0x02,
820 REG_MHL_DP_CTL6, 0x02,
821 REG_MHL_DP_CTL7, 0x03,
823 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12
824 | BIT_DPD_OSC_EN | BIT_DPD_PWRON_HSIC,
825 REG_COC_INTR_MASK, BIT_COC_PLL_LOCK_STATUS_CHANGE
826 | BIT_COC_CALIBRATION_DONE,
827 REG_CBUS_INT_1_MASK, BIT_CBUS_MSC_ABORT_RCVD
828 | BIT_CBUS_CMD_ABORT,
829 REG_CBUS_INT_0_MASK, BIT_CBUS_MSC_MT_DONE
831 | BIT_CBUS_MSC_MR_WRITE_STAT
832 | BIT_CBUS_MSC_MR_MSC_MSG
833 | BIT_CBUS_MSC_MR_WRITE_BURST
834 | BIT_CBUS_MSC_MR_SET_INT
835 | BIT_CBUS_MSC_MT_DONE_NACK
839 static void sii8620_peer_specific_init(struct sii8620 *ctx)
841 if (ctx->mode == CM_MHL3)
842 sii8620_write_seq_static(ctx,
843 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD,
845 BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR
848 sii8620_write_seq_static(ctx,
849 REG_HDCP2X_INTR0_MASK, 0x00,
850 REG_EMSCINTRMASK1, 0x00,
851 REG_HDCP2X_INTR0, 0xFF,
853 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD
854 | BIT_SYS_CTRL1_TX_CTRL_HDMI
858 #define SII8620_MHL_VERSION 0x32
859 #define SII8620_SCRATCHPAD_SIZE 16
860 #define SII8620_INT_STAT_SIZE 0x33
862 static void sii8620_set_dev_cap(struct sii8620 *ctx)
864 static const u8 devcap[MHL_DCAP_SIZE] = {
865 [MHL_DCAP_MHL_VERSION] = SII8620_MHL_VERSION,
866 [MHL_DCAP_CAT] = MHL_DCAP_CAT_SOURCE | MHL_DCAP_CAT_POWER,
867 [MHL_DCAP_ADOPTER_ID_H] = 0x01,
868 [MHL_DCAP_ADOPTER_ID_L] = 0x41,
869 [MHL_DCAP_VID_LINK_MODE] = MHL_DCAP_VID_LINK_RGB444
870 | MHL_DCAP_VID_LINK_PPIXEL
871 | MHL_DCAP_VID_LINK_16BPP,
872 [MHL_DCAP_AUD_LINK_MODE] = MHL_DCAP_AUD_LINK_2CH,
873 [MHL_DCAP_VIDEO_TYPE] = MHL_DCAP_VT_GRAPHICS,
874 [MHL_DCAP_LOG_DEV_MAP] = MHL_DCAP_LD_GUI,
875 [MHL_DCAP_BANDWIDTH] = 0x0f,
876 [MHL_DCAP_FEATURE_FLAG] = MHL_DCAP_FEATURE_RCP_SUPPORT
877 | MHL_DCAP_FEATURE_RAP_SUPPORT
878 | MHL_DCAP_FEATURE_SP_SUPPORT,
879 [MHL_DCAP_SCRATCHPAD_SIZE] = SII8620_SCRATCHPAD_SIZE,
880 [MHL_DCAP_INT_STAT_SIZE] = SII8620_INT_STAT_SIZE,
882 static const u8 xdcap[MHL_XDC_SIZE] = {
883 [MHL_XDC_ECBUS_SPEEDS] = MHL_XDC_ECBUS_S_075
884 | MHL_XDC_ECBUS_S_8BIT,
885 [MHL_XDC_TMDS_SPEEDS] = MHL_XDC_TMDS_150
886 | MHL_XDC_TMDS_300 | MHL_XDC_TMDS_600,
887 [MHL_XDC_ECBUS_ROLES] = MHL_XDC_DEV_HOST,
888 [MHL_XDC_LOG_DEV_MAPX] = MHL_XDC_LD_PHONE,
891 sii8620_write_buf(ctx, REG_MHL_DEVCAP_0, devcap, ARRAY_SIZE(devcap));
892 sii8620_write_buf(ctx, REG_MHL_EXTDEVCAP_0, xdcap, ARRAY_SIZE(xdcap));
895 static void sii8620_mhl_init(struct sii8620 *ctx)
897 sii8620_write_seq_static(ctx,
898 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
899 REG_CBUS_MSC_COMPAT_CTRL,
900 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN,
903 sii8620_peer_specific_init(ctx);
905 sii8620_disable_hpd(ctx);
907 sii8620_write_seq_static(ctx,
908 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO,
909 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
910 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
911 REG_TMDS0_CCTRL1, 0x90,
912 REG_TMDS_CLK_EN, 0x01,
913 REG_TMDS_CH_EN, 0x11,
915 REG_ALICE0_ZONE_CTRL, 0xE8,
916 REG_ALICE0_MODE_CTRL, 0x04,
918 sii8620_setbits(ctx, REG_LM_DDC, BIT_LM_DDC_SW_TPI_EN_DISABLED, 0);
919 sii8620_write_seq_static(ctx,
920 REG_TPI_HW_OPT3, 0x76,
921 REG_TMDS_CCTRL, BIT_TMDS_CCTRL_TMDS_OE,
924 sii8620_set_dev_cap(ctx);
925 sii8620_write_seq_static(ctx,
926 REG_MDT_XMIT_TIMEOUT, 100,
927 REG_MDT_XMIT_CTRL, 0x03,
928 REG_MDT_XFIFO_STAT, 0x00,
929 REG_MDT_RCV_TIMEOUT, 100,
930 REG_CBUS_LINK_CTRL_8, 0x1D,
933 sii8620_start_gen2_write_burst(ctx);
934 sii8620_write_seq_static(ctx,
944 REG_MHL_COC_CTL3, BIT_MHL_COC_CTL3_COC_AECHO_EN,
945 REG_MHL_COC_CTL4, 0x2D,
946 REG_MHL_COC_CTL5, 0xF9,
947 REG_MSC_HEARTBEAT_CTRL, 0x27,
949 sii8620_disable_gen2_write_burst(ctx);
951 /* currently MHL3 is not supported, so we force version to 0 */
952 sii8620_mt_write_stat(ctx, MHL_DST_REG(VERSION), 0);
953 sii8620_mt_write_stat(ctx, MHL_DST_REG(CONNECTED_RDY),
954 MHL_DST_CONN_DCAP_RDY | MHL_DST_CONN_XDEVCAPP_SUPP
955 | MHL_DST_CONN_POW_STAT);
956 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), MHL_INT_RC_DCAP_CHG);
959 static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode)
961 if (ctx->mode == mode)
968 sii8620_write_seq_static(ctx,
969 REG_CBUS_MSC_COMPAT_CTRL, 0x02,
970 REG_M3_CTRL, VAL_M3_CTRL_MHL1_2_VALUE,
971 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12
977 sii8620_write_seq_static(ctx,
978 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE,
980 REG_MHL_COC_CTL1, 0x07
983 case CM_DISCONNECTED:
986 dev_err(ctx->dev, "%s mode %d not supported\n", __func__, mode);
990 sii8620_set_auto_zone(ctx);
995 sii8620_write_seq_static(ctx,
996 REG_MHL_DP_CTL0, 0xBC,
997 REG_MHL_DP_CTL1, 0xBB,
998 REG_MHL_DP_CTL3, 0x48,
999 REG_MHL_DP_CTL5, 0x39,
1000 REG_MHL_DP_CTL2, 0x2A,
1001 REG_MHL_DP_CTL6, 0x2A,
1002 REG_MHL_DP_CTL7, 0x08
1006 static void sii8620_disconnect(struct sii8620 *ctx)
1008 sii8620_disable_gen2_write_burst(ctx);
1009 sii8620_stop_video(ctx);
1011 sii8620_cbus_reset(ctx);
1012 sii8620_set_mode(ctx, CM_DISCONNECTED);
1013 sii8620_write_seq_static(ctx,
1015 REG_CBUS3_CNVT, 0x84,
1016 REG_COC_CTL14, 0x00,
1019 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
1020 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
1021 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE,
1022 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE
1023 | BIT_MHL_DP_CTL0_TX_OE_OVR,
1024 REG_MHL_DP_CTL1, 0xBB,
1025 REG_MHL_DP_CTL3, 0x48,
1026 REG_MHL_DP_CTL5, 0x3F,
1027 REG_MHL_DP_CTL2, 0x2F,
1028 REG_MHL_DP_CTL6, 0x2A,
1029 REG_MHL_DP_CTL7, 0x03
1031 sii8620_disable_hpd(ctx);
1032 sii8620_write_seq_static(ctx,
1033 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE,
1034 REG_MHL_COC_CTL1, 0x07,
1035 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
1036 REG_DISC_CTRL8, 0x00,
1037 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1038 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
1040 REG_MSC_HEARTBEAT_CTRL, 0x27,
1041 REG_DISC_CTRL1, 0x25,
1042 REG_CBUS_DISC_INTR0, (u8)~BIT_RGND_READY_INT,
1043 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT,
1044 REG_MDT_INT_1, 0xff,
1045 REG_MDT_INT_1_MASK, 0x00,
1046 REG_MDT_INT_0, 0xff,
1047 REG_MDT_INT_0_MASK, 0x00,
1049 REG_COC_INTR_MASK, 0x00,
1052 REG_CBUS_INT_0, 0xff,
1053 REG_CBUS_INT_0_MASK, 0x00,
1054 REG_CBUS_INT_1, 0xff,
1055 REG_CBUS_INT_1_MASK, 0x00,
1057 REG_EMSCINTRMASK, 0x00,
1058 REG_EMSCINTR1, 0xff,
1059 REG_EMSCINTRMASK1, 0x00,
1061 REG_INTR8_MASK, 0x00,
1062 REG_TPI_INTR_ST0, 0xff,
1063 REG_TPI_INTR_EN, 0x00,
1064 REG_HDCP2X_INTR0, 0xff,
1065 REG_HDCP2X_INTR0_MASK, 0x00,
1067 REG_INTR9_MASK, 0x00,
1069 REG_INTR3_MASK, 0x00,
1071 REG_INTR5_MASK, 0x00,
1073 REG_INTR2_MASK, 0x00,
1075 memset(ctx->stat, 0, sizeof(ctx->stat));
1076 memset(ctx->xstat, 0, sizeof(ctx->xstat));
1077 memset(ctx->devcap, 0, sizeof(ctx->devcap));
1078 memset(ctx->xdevcap, 0, sizeof(ctx->xdevcap));
1079 ctx->cbus_status = 0;
1080 ctx->sink_type = SINK_NONE;
1083 sii8620_mt_cleanup(ctx);
1086 static void sii8620_mhl_disconnected(struct sii8620 *ctx)
1088 sii8620_write_seq_static(ctx,
1089 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
1090 REG_CBUS_MSC_COMPAT_CTRL,
1091 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN
1093 sii8620_disconnect(ctx);
1096 static void sii8620_irq_disc(struct sii8620 *ctx)
1098 u8 stat = sii8620_readb(ctx, REG_CBUS_DISC_INTR0);
1100 if (stat & VAL_CBUS_MHL_DISCON)
1101 sii8620_mhl_disconnected(ctx);
1103 if (stat & BIT_RGND_READY_INT) {
1104 u8 stat2 = sii8620_readb(ctx, REG_DISC_STAT2);
1106 if ((stat2 & MSK_DISC_STAT2_RGND) == VAL_RGND_1K) {
1107 sii8620_mhl_discover(ctx);
1109 sii8620_write_seq_static(ctx,
1110 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1111 | BIT_DISC_CTRL9_NOMHL_EST
1112 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
1113 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT
1114 | BIT_CBUS_MHL3_DISCON_INT
1115 | BIT_CBUS_MHL12_DISCON_INT
1116 | BIT_NOT_MHL_EST_INT
1120 if (stat & BIT_MHL_EST_INT)
1121 sii8620_mhl_init(ctx);
1123 sii8620_write(ctx, REG_CBUS_DISC_INTR0, stat);
1126 static void sii8620_irq_g2wb(struct sii8620 *ctx)
1128 u8 stat = sii8620_readb(ctx, REG_MDT_INT_0);
1130 if (stat & BIT_MDT_IDLE_AFTER_HAWB_DISABLE)
1131 dev_dbg(ctx->dev, "HAWB idle\n");
1133 sii8620_write(ctx, REG_MDT_INT_0, stat);
1136 static void sii8620_status_changed_dcap(struct sii8620 *ctx)
1138 if (ctx->stat[MHL_DST_CONNECTED_RDY] & MHL_DST_CONN_DCAP_RDY) {
1139 sii8620_set_mode(ctx, CM_MHL1);
1140 sii8620_peer_specific_init(ctx);
1141 sii8620_write(ctx, REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE
1142 | BIT_INTR9_EDID_DONE | BIT_INTR9_EDID_ERROR);
1146 static void sii8620_status_changed_path(struct sii8620 *ctx)
1148 if (ctx->stat[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) {
1149 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
1150 MHL_DST_LM_CLK_MODE_NORMAL
1151 | MHL_DST_LM_PATH_ENABLED);
1152 sii8620_mt_read_devcap(ctx, false);
1154 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
1155 MHL_DST_LM_CLK_MODE_NORMAL);
1159 static void sii8620_msc_mr_write_stat(struct sii8620 *ctx)
1161 u8 st[MHL_DST_SIZE], xst[MHL_XDS_SIZE];
1163 sii8620_read_buf(ctx, REG_MHL_STAT_0, st, MHL_DST_SIZE);
1164 sii8620_read_buf(ctx, REG_MHL_EXTSTAT_0, xst, MHL_XDS_SIZE);
1166 sii8620_update_array(ctx->stat, st, MHL_DST_SIZE);
1167 sii8620_update_array(ctx->xstat, xst, MHL_XDS_SIZE);
1169 if (st[MHL_DST_CONNECTED_RDY] & MHL_DST_CONN_DCAP_RDY)
1170 sii8620_status_changed_dcap(ctx);
1172 if (st[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED)
1173 sii8620_status_changed_path(ctx);
1176 static void sii8620_msc_mr_set_int(struct sii8620 *ctx)
1178 u8 ints[MHL_INT_SIZE];
1180 sii8620_read_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE);
1181 sii8620_write_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE);
1184 static struct sii8620_mt_msg *sii8620_msc_msg_first(struct sii8620 *ctx)
1186 struct device *dev = ctx->dev;
1188 if (list_empty(&ctx->mt_queue)) {
1189 dev_err(dev, "unexpected MSC MT response\n");
1193 return list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node);
1196 static void sii8620_msc_mt_done(struct sii8620 *ctx)
1198 struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx);
1203 msg->ret = sii8620_readb(ctx, REG_MSC_MT_RCVD_DATA0);
1204 ctx->mt_state = MT_STATE_DONE;
1207 static void sii8620_msc_mr_msc_msg(struct sii8620 *ctx)
1209 struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx);
1215 sii8620_read_buf(ctx, REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA, buf, 2);
1218 case MHL_MSC_MSG_RAPK:
1220 ctx->mt_state = MT_STATE_DONE;
1223 dev_err(ctx->dev, "%s message type %d,%d not supported",
1224 __func__, buf[0], buf[1]);
1228 static void sii8620_irq_msc(struct sii8620 *ctx)
1230 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_0);
1232 if (stat & ~BIT_CBUS_HPD_CHG)
1233 sii8620_write(ctx, REG_CBUS_INT_0, stat & ~BIT_CBUS_HPD_CHG);
1235 if (stat & BIT_CBUS_HPD_CHG) {
1236 u8 cbus_stat = sii8620_readb(ctx, REG_CBUS_STATUS);
1238 if ((cbus_stat ^ ctx->cbus_status) & BIT_CBUS_STATUS_CBUS_HPD) {
1239 sii8620_write(ctx, REG_CBUS_INT_0, BIT_CBUS_HPD_CHG);
1241 stat ^= BIT_CBUS_STATUS_CBUS_HPD;
1242 cbus_stat ^= BIT_CBUS_STATUS_CBUS_HPD;
1244 ctx->cbus_status = cbus_stat;
1247 if (stat & BIT_CBUS_MSC_MR_WRITE_STAT)
1248 sii8620_msc_mr_write_stat(ctx);
1250 if (stat & BIT_CBUS_MSC_MR_SET_INT)
1251 sii8620_msc_mr_set_int(ctx);
1253 if (stat & BIT_CBUS_MSC_MT_DONE)
1254 sii8620_msc_mt_done(ctx);
1256 if (stat & BIT_CBUS_MSC_MR_MSC_MSG)
1257 sii8620_msc_mr_msc_msg(ctx);
1260 static void sii8620_irq_coc(struct sii8620 *ctx)
1262 u8 stat = sii8620_readb(ctx, REG_COC_INTR);
1264 sii8620_write(ctx, REG_COC_INTR, stat);
1267 static void sii8620_irq_merr(struct sii8620 *ctx)
1269 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_1);
1271 sii8620_write(ctx, REG_CBUS_INT_1, stat);
1274 static void sii8620_irq_edid(struct sii8620 *ctx)
1276 u8 stat = sii8620_readb(ctx, REG_INTR9);
1278 sii8620_write(ctx, REG_INTR9, stat);
1280 if (stat & BIT_INTR9_DEVCAP_DONE)
1281 ctx->mt_state = MT_STATE_DONE;
1284 static void sii8620_scdt_high(struct sii8620 *ctx)
1286 sii8620_write_seq_static(ctx,
1287 REG_INTR8_MASK, BIT_CEA_NEW_AVI | BIT_CEA_NEW_VSI,
1288 REG_TPI_SC, BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI,
1292 static void sii8620_scdt_low(struct sii8620 *ctx)
1294 sii8620_write(ctx, REG_TMDS_CSTAT_P3,
1295 BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS |
1296 BIT_TMDS_CSTAT_P3_CLR_AVI);
1298 sii8620_stop_video(ctx);
1300 sii8620_write(ctx, REG_INTR8_MASK, 0);
1303 static void sii8620_irq_scdt(struct sii8620 *ctx)
1305 u8 stat = sii8620_readb(ctx, REG_INTR5);
1307 if (stat & BIT_INTR_SCDT_CHANGE) {
1308 u8 cstat = sii8620_readb(ctx, REG_TMDS_CSTAT_P3);
1310 if (cstat & BIT_TMDS_CSTAT_P3_SCDT)
1311 sii8620_scdt_high(ctx);
1313 sii8620_scdt_low(ctx);
1316 sii8620_write(ctx, REG_INTR5, stat);
1319 static void sii8620_new_vsi(struct sii8620 *ctx)
1323 sii8620_write(ctx, REG_RX_HDMI_CTRL2,
1324 VAL_RX_HDMI_CTRL2_DEFVAL |
1325 BIT_RX_HDMI_CTRL2_VSI_MON_SEL_VSI);
1326 sii8620_read_buf(ctx, REG_RX_HDMI_MON_PKT_HEADER1, vsif,
1330 static void sii8620_new_avi(struct sii8620 *ctx)
1332 sii8620_write(ctx, REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL);
1333 sii8620_read_buf(ctx, REG_RX_HDMI_MON_PKT_HEADER1, ctx->avif,
1334 ARRAY_SIZE(ctx->avif));
1337 static void sii8620_irq_infr(struct sii8620 *ctx)
1339 u8 stat = sii8620_readb(ctx, REG_INTR8)
1340 & (BIT_CEA_NEW_VSI | BIT_CEA_NEW_AVI);
1342 sii8620_write(ctx, REG_INTR8, stat);
1344 if (stat & BIT_CEA_NEW_VSI)
1345 sii8620_new_vsi(ctx);
1347 if (stat & BIT_CEA_NEW_AVI)
1348 sii8620_new_avi(ctx);
1350 if (stat & (BIT_CEA_NEW_VSI | BIT_CEA_NEW_AVI))
1351 sii8620_start_video(ctx);
1354 /* endian agnostic, non-volatile version of test_bit */
1355 static bool sii8620_test_bit(unsigned int nr, const u8 *addr)
1357 return 1 & (addr[nr / BITS_PER_BYTE] >> (nr % BITS_PER_BYTE));
1360 static irqreturn_t sii8620_irq_thread(int irq, void *data)
1362 static const struct {
1364 void (*handler)(struct sii8620 *ctx);
1366 { BIT_FAST_INTR_STAT_DISC, sii8620_irq_disc },
1367 { BIT_FAST_INTR_STAT_G2WB, sii8620_irq_g2wb },
1368 { BIT_FAST_INTR_STAT_COC, sii8620_irq_coc },
1369 { BIT_FAST_INTR_STAT_MSC, sii8620_irq_msc },
1370 { BIT_FAST_INTR_STAT_MERR, sii8620_irq_merr },
1371 { BIT_FAST_INTR_STAT_EDID, sii8620_irq_edid },
1372 { BIT_FAST_INTR_STAT_SCDT, sii8620_irq_scdt },
1373 { BIT_FAST_INTR_STAT_INFR, sii8620_irq_infr },
1375 struct sii8620 *ctx = data;
1376 u8 stats[LEN_FAST_INTR_STAT];
1379 mutex_lock(&ctx->lock);
1381 sii8620_read_buf(ctx, REG_FAST_INTR_STAT, stats, ARRAY_SIZE(stats));
1382 for (i = 0; i < ARRAY_SIZE(irq_vec); ++i)
1383 if (sii8620_test_bit(irq_vec[i].bit, stats))
1384 irq_vec[i].handler(ctx);
1386 sii8620_mt_work(ctx);
1388 ret = sii8620_clear_error(ctx);
1390 dev_err(ctx->dev, "Error during IRQ handling, %d.\n", ret);
1391 sii8620_mhl_disconnected(ctx);
1393 mutex_unlock(&ctx->lock);
1398 static void sii8620_cable_in(struct sii8620 *ctx)
1400 struct device *dev = ctx->dev;
1404 ret = sii8620_hw_on(ctx);
1406 dev_err(dev, "Error powering on, %d.\n", ret);
1409 sii8620_hw_reset(ctx);
1411 sii8620_read_buf(ctx, REG_VND_IDL, ver, ARRAY_SIZE(ver));
1412 ret = sii8620_clear_error(ctx);
1414 dev_err(dev, "Error accessing I2C bus, %d.\n", ret);
1418 dev_info(dev, "ChipID %02x%02x:%02x%02x rev %02x.\n", ver[1], ver[0],
1419 ver[3], ver[2], ver[4]);
1421 sii8620_write(ctx, REG_DPD,
1422 BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN);
1424 sii8620_xtal_set_rate(ctx);
1425 sii8620_disconnect(ctx);
1427 sii8620_write_seq_static(ctx,
1428 REG_MHL_CBUS_CTL0, VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG
1429 | VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734,
1430 REG_MHL_CBUS_CTL1, VAL_MHL_CBUS_CTL1_1115_OHM,
1431 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN,
1434 ret = sii8620_clear_error(ctx);
1436 dev_err(dev, "Error accessing I2C bus, %d.\n", ret);
1440 enable_irq(to_i2c_client(ctx->dev)->irq);
1443 static inline struct sii8620 *bridge_to_sii8620(struct drm_bridge *bridge)
1445 return container_of(bridge, struct sii8620, bridge);
1448 static bool sii8620_mode_fixup(struct drm_bridge *bridge,
1449 const struct drm_display_mode *mode,
1450 struct drm_display_mode *adjusted_mode)
1452 struct sii8620 *ctx = bridge_to_sii8620(bridge);
1454 int max_clock = 74250;
1456 mutex_lock(&ctx->lock);
1458 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1461 if (ctx->devcap[MHL_DCAP_VID_LINK_MODE] & MHL_DCAP_VID_LINK_PPIXEL)
1464 ret = mode->clock <= max_clock;
1467 mutex_unlock(&ctx->lock);
1472 static const struct drm_bridge_funcs sii8620_bridge_funcs = {
1473 .mode_fixup = sii8620_mode_fixup,
1476 static int sii8620_probe(struct i2c_client *client,
1477 const struct i2c_device_id *id)
1479 struct device *dev = &client->dev;
1480 struct sii8620 *ctx;
1483 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1488 mutex_init(&ctx->lock);
1489 INIT_LIST_HEAD(&ctx->mt_queue);
1491 ctx->clk_xtal = devm_clk_get(dev, "xtal");
1492 if (IS_ERR(ctx->clk_xtal)) {
1493 dev_err(dev, "failed to get xtal clock from DT\n");
1494 return PTR_ERR(ctx->clk_xtal);
1498 dev_err(dev, "no irq provided\n");
1501 irq_set_status_flags(client->irq, IRQ_NOAUTOEN);
1502 ret = devm_request_threaded_irq(dev, client->irq, NULL,
1504 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1507 ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
1508 if (IS_ERR(ctx->gpio_reset)) {
1509 dev_err(dev, "failed to get reset gpio from DT\n");
1510 return PTR_ERR(ctx->gpio_reset);
1513 ctx->supplies[0].supply = "cvcc10";
1514 ctx->supplies[1].supply = "iovcc18";
1515 ret = devm_regulator_bulk_get(dev, 2, ctx->supplies);
1519 i2c_set_clientdata(client, ctx);
1521 ctx->bridge.funcs = &sii8620_bridge_funcs;
1522 ctx->bridge.of_node = dev->of_node;
1523 drm_bridge_add(&ctx->bridge);
1525 sii8620_cable_in(ctx);
1530 static int sii8620_remove(struct i2c_client *client)
1532 struct sii8620 *ctx = i2c_get_clientdata(client);
1534 disable_irq(to_i2c_client(ctx->dev)->irq);
1535 drm_bridge_remove(&ctx->bridge);
1536 sii8620_hw_off(ctx);
1541 static const struct of_device_id sii8620_dt_match[] = {
1542 { .compatible = "sil,sii8620" },
1545 MODULE_DEVICE_TABLE(of, sii8620_dt_match);
1547 static const struct i2c_device_id sii8620_id[] = {
1552 MODULE_DEVICE_TABLE(i2c, sii8620_id);
1553 static struct i2c_driver sii8620_driver = {
1556 .of_match_table = of_match_ptr(sii8620_dt_match),
1558 .probe = sii8620_probe,
1559 .remove = sii8620_remove,
1560 .id_table = sii8620_id,
1563 module_i2c_driver(sii8620_driver);
1564 MODULE_LICENSE("GPL v2");