drivers/gpu/drm/etnaviv/etnaviv_gpu.c

   1 /*
   2  * Copyright (C) 2015 Etnaviv Project
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published by
   6  * the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/component.h>
  18 #include <linux/dma-fence.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/of_device.h>
  21 #include "etnaviv_dump.h"
  22 #include "etnaviv_gpu.h"
  23 #include "etnaviv_gem.h"
  24 #include "etnaviv_mmu.h"
  25 #include "common.xml.h"
  26 #include "state.xml.h"
  27 #include "state_hi.xml.h"
  28 #include "cmdstream.xml.h"
  29
  30 static const struct platform_device_id gpu_ids[] = {
  31         { .name = "etnaviv-gpu,2d" },
  32         { },
  33 };
  34
  35 static bool etnaviv_dump_core = true;
  36 module_param_named(dump_core, etnaviv_dump_core, bool, 0600);
  37
  38 /*
  39  * Driver functions:
  40  */
  41
  42 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
  43 {
  44         switch (param) {
  45         case ETNAVIV_PARAM_GPU_MODEL:
  46                 *value = gpu->identity.model;
  47                 break;
  48
  49         case ETNAVIV_PARAM_GPU_REVISION:
  50                 *value = gpu->identity.revision;
  51                 break;
  52
  53         case ETNAVIV_PARAM_GPU_FEATURES_0:
  54                 *value = gpu->identity.features;
  55                 break;
  56
  57         case ETNAVIV_PARAM_GPU_FEATURES_1:
  58                 *value = gpu->identity.minor_features0;
  59                 break;
  60
  61         case ETNAVIV_PARAM_GPU_FEATURES_2:
  62                 *value = gpu->identity.minor_features1;
  63                 break;
  64
  65         case ETNAVIV_PARAM_GPU_FEATURES_3:
  66                 *value = gpu->identity.minor_features2;
  67                 break;
  68
  69         case ETNAVIV_PARAM_GPU_FEATURES_4:
  70                 *value = gpu->identity.minor_features3;
  71                 break;
  72
  73         case ETNAVIV_PARAM_GPU_FEATURES_5:
  74                 *value = gpu->identity.minor_features4;
  75                 break;
  76
  77         case ETNAVIV_PARAM_GPU_FEATURES_6:
  78                 *value = gpu->identity.minor_features5;
  79                 break;
  80
  81         case ETNAVIV_PARAM_GPU_STREAM_COUNT:
  82                 *value = gpu->identity.stream_count;
  83                 break;
  84
  85         case ETNAVIV_PARAM_GPU_REGISTER_MAX:
  86                 *value = gpu->identity.register_max;
  87                 break;
  88
  89         case ETNAVIV_PARAM_GPU_THREAD_COUNT:
  90                 *value = gpu->identity.thread_count;
  91                 break;
  92
  93         case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
  94                 *value = gpu->identity.vertex_cache_size;
  95                 break;
  96
  97         case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
  98                 *value = gpu->identity.shader_core_count;
  99                 break;
 100
 101         case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
 102                 *value = gpu->identity.pixel_pipes;
 103                 break;
 104
 105         case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
 106                 *value = gpu->identity.vertex_output_buffer_size;
 107                 break;
 108
 109         case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
 110                 *value = gpu->identity.buffer_size;
 111                 break;
 112
 113         case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
 114                 *value = gpu->identity.instruction_count;
 115                 break;
 116
 117         case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
 118                 *value = gpu->identity.num_constants;
 119                 break;
 120
 121         case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
 122                 *value = gpu->identity.varyings_count;
 123                 break;
 124
 125         default:
 126                 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
 127                 return -EINVAL;
 128         }
 129
 130         return 0;
 131 }
 132
 133
 134 #define etnaviv_is_model_rev(gpu, mod, rev) \
 135         ((gpu)->identity.model == chipModel_##mod && \
 136          (gpu)->identity.revision == rev)
 137 #define etnaviv_field(val, field) \
 138         (((val) & field##__MASK) >> field##__SHIFT)
 139
 140 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
 141 {
 142         if (gpu->identity.minor_features0 &
 143             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 144                 u32 specs[4];
 145                 unsigned int streams;
 146
 147                 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
 148                 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
 149                 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
 150                 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
 151
 152                 gpu->identity.stream_count = etnaviv_field(specs[0],
 153                                         VIVS_HI_CHIP_SPECS_STREAM_COUNT);
 154                 gpu->identity.register_max = etnaviv_field(specs[0],
 155                                         VIVS_HI_CHIP_SPECS_REGISTER_MAX);
 156                 gpu->identity.thread_count = etnaviv_field(specs[0],
 157                                         VIVS_HI_CHIP_SPECS_THREAD_COUNT);
 158                 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
 159                                         VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
 160                 gpu->identity.shader_core_count = etnaviv_field(specs[0],
 161                                         VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
 162                 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
 163                                         VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
 164                 gpu->identity.vertex_output_buffer_size =
 165                         etnaviv_field(specs[0],
 166                                 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
 167
 168                 gpu->identity.buffer_size = etnaviv_field(specs[1],
 169                                         VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
 170                 gpu->identity.instruction_count = etnaviv_field(specs[1],
 171                                         VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
 172                 gpu->identity.num_constants = etnaviv_field(specs[1],
 173                                         VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
 174
 175                 gpu->identity.varyings_count = etnaviv_field(specs[2],
 176                                         VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
 177
 178                 /* This overrides the value from older register if non-zero */
 179                 streams = etnaviv_field(specs[3],
 180                                         VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
 181                 if (streams)
 182                         gpu->identity.stream_count = streams;
 183         }
 184
 185         /* Fill in the stream count if not specified */
 186         if (gpu->identity.stream_count == 0) {
 187                 if (gpu->identity.model >= 0x1000)
 188                         gpu->identity.stream_count = 4;
 189                 else
 190                         gpu->identity.stream_count = 1;
 191         }
 192
 193         /* Convert the register max value */
 194         if (gpu->identity.register_max)
 195                 gpu->identity.register_max = 1 << gpu->identity.register_max;
 196         else if (gpu->identity.model == chipModel_GC400)
 197                 gpu->identity.register_max = 32;
 198         else
 199                 gpu->identity.register_max = 64;
 200
 201         /* Convert thread count */
 202         if (gpu->identity.thread_count)
 203                 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
 204         else if (gpu->identity.model == chipModel_GC400)
 205                 gpu->identity.thread_count = 64;
 206         else if (gpu->identity.model == chipModel_GC500 ||
 207                  gpu->identity.model == chipModel_GC530)
 208                 gpu->identity.thread_count = 128;
 209         else
 210                 gpu->identity.thread_count = 256;
 211
 212         if (gpu->identity.vertex_cache_size == 0)
 213                 gpu->identity.vertex_cache_size = 8;
 214
 215         if (gpu->identity.shader_core_count == 0) {
 216                 if (gpu->identity.model >= 0x1000)
 217                         gpu->identity.shader_core_count = 2;
 218                 else
 219                         gpu->identity.shader_core_count = 1;
 220         }
 221
 222         if (gpu->identity.pixel_pipes == 0)
 223                 gpu->identity.pixel_pipes = 1;
 224
 225         /* Convert virtex buffer size */
 226         if (gpu->identity.vertex_output_buffer_size) {
 227                 gpu->identity.vertex_output_buffer_size =
 228                         1 << gpu->identity.vertex_output_buffer_size;
 229         } else if (gpu->identity.model == chipModel_GC400) {
 230                 if (gpu->identity.revision < 0x4000)
 231                         gpu->identity.vertex_output_buffer_size = 512;
 232                 else if (gpu->identity.revision < 0x4200)
 233                         gpu->identity.vertex_output_buffer_size = 256;
 234                 else
 235                         gpu->identity.vertex_output_buffer_size = 128;
 236         } else {
 237                 gpu->identity.vertex_output_buffer_size = 512;
 238         }
 239
 240         switch (gpu->identity.instruction_count) {
 241         case 0:
 242                 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 243                     gpu->identity.model == chipModel_GC880)
 244                         gpu->identity.instruction_count = 512;
 245                 else
 246                         gpu->identity.instruction_count = 256;
 247                 break;
 248
 249         case 1:
 250                 gpu->identity.instruction_count = 1024;
 251                 break;
 252
 253         case 2:
 254                 gpu->identity.instruction_count = 2048;
 255                 break;
 256
 257         default:
 258                 gpu->identity.instruction_count = 256;
 259                 break;
 260         }
 261
 262         if (gpu->identity.num_constants == 0)
 263                 gpu->identity.num_constants = 168;
 264
 265         if (gpu->identity.varyings_count == 0) {
 266                 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
 267                         gpu->identity.varyings_count = 12;
 268                 else
 269                         gpu->identity.varyings_count = 8;
 270         }
 271
 272         /*
 273          * For some cores, two varyings are consumed for position, so the
 274          * maximum varying count needs to be reduced by one.
 275          */
 276         if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
 277             etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
 278             etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
 279             etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
 280             etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
 281             etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
 282             etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
 283             etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 284             etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
 285             etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
 286             etnaviv_is_model_rev(gpu, GC880, 0x5106))
 287                 gpu->identity.varyings_count -= 1;
 288 }
 289
 290 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
 291 {
 292         u32 chipIdentity;
 293
 294         chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
 295
 296         /* Special case for older graphic cores. */
 297         if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
 298                 gpu->identity.model    = chipModel_GC500;
 299                 gpu->identity.revision = etnaviv_field(chipIdentity,
 300                                          VIVS_HI_CHIP_IDENTITY_REVISION);
 301         } else {
 302
 303                 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
 304                 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
 305
 306                 /*
 307                  * !!!! HACK ALERT !!!!
 308                  * Because people change device IDs without letting software
 309                  * know about it - here is the hack to make it all look the
 310                  * same.  Only for GC400 family.
 311                  */
 312                 if ((gpu->identity.model & 0xff00) == 0x0400 &&
 313                     gpu->identity.model != chipModel_GC420) {
 314                         gpu->identity.model = gpu->identity.model & 0x0400;
 315                 }
 316
 317                 /* Another special case */
 318                 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
 319                         u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
 320                         u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
 321
 322                         if (chipDate == 0x20080814 && chipTime == 0x12051100) {
 323                                 /*
 324                                  * This IP has an ECO; put the correct
 325                                  * revision in it.
 326                                  */
 327                                 gpu->identity.revision = 0x1051;
 328                         }
 329                 }
 330
 331                 /*
 332                  * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
 333                  * reality it's just a re-branded GC3000. We can identify this
 334                  * core by the upper half of the revision register being all 1.
 335                  * Fix model/rev here, so all other places can refer to this
 336                  * core by its real identity.
 337                  */
 338                 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
 339                         gpu->identity.model = chipModel_GC3000;
 340                         gpu->identity.revision &= 0xffff;
 341                 }
 342         }
 343
 344         dev_info(gpu->dev, "model: GC%x, revision: %x\n",
 345                  gpu->identity.model, gpu->identity.revision);
 346
 347         gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
 348
 349         /* Disable fast clear on GC700. */
 350         if (gpu->identity.model == chipModel_GC700)
 351                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 352
 353         if ((gpu->identity.model == chipModel_GC500 &&
 354              gpu->identity.revision < 2) ||
 355             (gpu->identity.model == chipModel_GC300 &&
 356              gpu->identity.revision < 0x2000)) {
 357
 358                 /*
 359                  * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
 360                  * registers.
 361                  */
 362                 gpu->identity.minor_features0 = 0;
 363                 gpu->identity.minor_features1 = 0;
 364                 gpu->identity.minor_features2 = 0;
 365                 gpu->identity.minor_features3 = 0;
 366                 gpu->identity.minor_features4 = 0;
 367                 gpu->identity.minor_features5 = 0;
 368         } else
 369                 gpu->identity.minor_features0 =
 370                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
 371
 372         if (gpu->identity.minor_features0 &
 373             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 374                 gpu->identity.minor_features1 =
 375                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
 376                 gpu->identity.minor_features2 =
 377                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
 378                 gpu->identity.minor_features3 =
 379                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
 380                 gpu->identity.minor_features4 =
 381                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
 382                 gpu->identity.minor_features5 =
 383                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
 384         }
 385
 386         /* GC600 idle register reports zero bits where modules aren't present */
 387         if (gpu->identity.model == chipModel_GC600) {
 388                 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
 389                                  VIVS_HI_IDLE_STATE_RA |
 390                                  VIVS_HI_IDLE_STATE_SE |
 391                                  VIVS_HI_IDLE_STATE_PA |
 392                                  VIVS_HI_IDLE_STATE_SH |
 393                                  VIVS_HI_IDLE_STATE_PE |
 394                                  VIVS_HI_IDLE_STATE_DE |
 395                                  VIVS_HI_IDLE_STATE_FE;
 396         } else {
 397                 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
 398         }
 399
 400         etnaviv_hw_specs(gpu);
 401 }
 402
 403 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
 404 {
 405         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
 406                   VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
 407         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
 408 }
 409
 410 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
 411 {
 412         u32 control, idle;
 413         unsigned long timeout;
 414         bool failed = true;
 415
 416         /* TODO
 417          *
 418          * - clock gating
 419          * - puls eater
 420          * - what about VG?
 421          */
 422
 423         /* We hope that the GPU resets in under one second */
 424         timeout = jiffies + msecs_to_jiffies(1000);
 425
 426         while (time_is_after_jiffies(timeout)) {
 427                 control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
 428                           VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
 429
 430                 /* enable clock */
 431                 etnaviv_gpu_load_clock(gpu, control);
 432
 433                 /* Wait for stable clock.  Vivante's code waited for 1ms */
 434                 usleep_range(1000, 10000);
 435
 436                 /* isolate the GPU. */
 437                 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 438                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 439
 440                 /* set soft reset. */
 441                 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 442                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 443
 444                 /* wait for reset. */
 445                 msleep(1);
 446
 447                 /* reset soft reset bit. */
 448                 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 449                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 450
 451                 /* reset GPU isolation. */
 452                 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 453                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 454
 455                 /* read idle register. */
 456                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 457
 458                 /* try reseting again if FE it not idle */
 459                 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
 460                         dev_dbg(gpu->dev, "FE is not idle\n");
 461                         continue;
 462                 }
 463
 464                 /* read reset register. */
 465                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 466
 467                 /* is the GPU idle? */
 468                 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
 469                     ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
 470                         dev_dbg(gpu->dev, "GPU is not idle\n");
 471                         continue;
 472                 }
 473
 474                 failed = false;
 475                 break;
 476         }
 477
 478         if (failed) {
 479                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 480                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 481
 482                 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
 483                         idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
 484                         control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
 485                         control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
 486
 487                 return -EBUSY;
 488         }
 489
 490         /* We rely on the GPU running, so program the clock */
 491         control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
 492                   VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
 493
 494         /* enable clock */
 495         etnaviv_gpu_load_clock(gpu, control);
 496
 497         return 0;
 498 }
 499
 500 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
 501 {
 502         u32 pmc, ppc;
 503
 504         /* enable clock gating */
 505         ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
 506         ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
 507
 508         /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
 509         if (gpu->identity.revision == 0x4301 ||
 510             gpu->identity.revision == 0x4302)
 511                 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
 512
 513         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
 514
 515         pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
 516
 517         /* Disable PA clock gating for GC400+ except for GC420 */
 518         if (gpu->identity.model >= chipModel_GC400 &&
 519             gpu->identity.model != chipModel_GC420)
 520                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
 521
 522         /*
 523          * Disable PE clock gating on revs < 5.0.0.0 when HZ is
 524          * present without a bug fix.
 525          */
 526         if (gpu->identity.revision < 0x5000 &&
 527             gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
 528             !(gpu->identity.minor_features1 &
 529               chipMinorFeatures1_DISABLE_PE_GATING))
 530                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
 531
 532         if (gpu->identity.revision < 0x5422)
 533                 pmc |= BIT(15); /* Unknown bit */
 534
 535         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
 536         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
 537
 538         gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
 539 }
 540
 541 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
 542 {
 543         gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
 544         gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
 545                   VIVS_FE_COMMAND_CONTROL_ENABLE |
 546                   VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
 547 }
 548
 549 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
 550 {
 551         u16 prefetch;
 552
 553         if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
 554              etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
 555             gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
 556                 u32 mc_memory_debug;
 557
 558                 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
 559
 560                 if (gpu->identity.revision == 0x5007)
 561                         mc_memory_debug |= 0x0c;
 562                 else
 563                         mc_memory_debug |= 0x08;
 564
 565                 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
 566         }
 567
 568         /* enable module-level clock gating */
 569         etnaviv_gpu_enable_mlcg(gpu);
 570
 571         /*
 572          * Update GPU AXI cache atttribute to "cacheable, no allocate".
 573          * This is necessary to prevent the iMX6 SoC locking up.
 574          */
 575         gpu_write(gpu, VIVS_HI_AXI_CONFIG,
 576                   VIVS_HI_AXI_CONFIG_AWCACHE(2) |
 577                   VIVS_HI_AXI_CONFIG_ARCACHE(2));
 578
 579         /* GC2000 rev 5108 needs a special bus config */
 580         if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
 581                 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
 582                 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
 583                                 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
 584                 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
 585                               VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
 586                 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
 587         }
 588
 589         /* setup the MMU */
 590         etnaviv_iommu_restore(gpu);
 591
 592         /* Start command processor */
 593         prefetch = etnaviv_buffer_init(gpu);
 594
 595         gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
 596         etnaviv_gpu_start_fe(gpu, etnaviv_iommu_get_cmdbuf_va(gpu, gpu->buffer),
 597                              prefetch);
 598 }
 599
 600 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
 601 {
 602         int ret, i;
 603
 604         ret = pm_runtime_get_sync(gpu->dev);
 605         if (ret < 0) {
 606                 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
 607                 return ret;
 608         }
 609
 610         etnaviv_hw_identify(gpu);
 611
 612         if (gpu->identity.model == 0) {
 613                 dev_err(gpu->dev, "Unknown GPU model\n");
 614                 ret = -ENXIO;
 615                 goto fail;
 616         }
 617
 618         /* Exclude VG cores with FE2.0 */
 619         if (gpu->identity.features & chipFeatures_PIPE_VG &&
 620             gpu->identity.features & chipFeatures_FE20) {
 621                 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
 622                 ret = -ENXIO;
 623                 goto fail;
 624         }
 625
 626         /*
 627          * Set the GPU linear window to be at the end of the DMA window, where
 628          * the CMA area is likely to reside. This ensures that we are able to
 629          * map the command buffers while having the linear window overlap as
 630          * much RAM as possible, so we can optimize mappings for other buffers.
 631          *
 632          * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
 633          * to different views of the memory on the individual engines.
 634          */
 635         if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
 636             (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
 637                 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
 638                 if (dma_mask < PHYS_OFFSET + SZ_2G)
 639                         gpu->memory_base = PHYS_OFFSET;
 640                 else
 641                         gpu->memory_base = dma_mask - SZ_2G + 1;
 642         } else if (PHYS_OFFSET >= SZ_2G) {
 643                 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n");
 644                 gpu->memory_base = PHYS_OFFSET;
 645                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 646         }
 647
 648         ret = etnaviv_hw_reset(gpu);
 649         if (ret) {
 650                 dev_err(gpu->dev, "GPU reset failed\n");
 651                 goto fail;
 652         }
 653
 654         gpu->mmu = etnaviv_iommu_new(gpu);
 655         if (IS_ERR(gpu->mmu)) {
 656                 dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n");
 657                 ret = PTR_ERR(gpu->mmu);
 658                 goto fail;
 659         }
 660
 661         /* Create buffer: */
 662         gpu->buffer = etnaviv_gpu_cmdbuf_new(gpu, PAGE_SIZE, 0);
 663         if (!gpu->buffer) {
 664                 ret = -ENOMEM;
 665                 dev_err(gpu->dev, "could not create command buffer\n");
 666                 goto destroy_iommu;
 667         }
 668
 669         if (gpu->mmu->version == ETNAVIV_IOMMU_V1 &&
 670             gpu->buffer->paddr - gpu->memory_base > 0x80000000) {
 671                 ret = -EINVAL;
 672                 dev_err(gpu->dev,
 673                         "command buffer outside valid memory window\n");
 674                 goto free_buffer;
 675         }
 676
 677         /* Setup event management */
 678         spin_lock_init(&gpu->event_spinlock);
 679         init_completion(&gpu->event_free);
 680         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
 681                 gpu->event[i].used = false;
 682                 complete(&gpu->event_free);
 683         }
 684
 685         /* Now program the hardware */
 686         mutex_lock(&gpu->lock);
 687         etnaviv_gpu_hw_init(gpu);
 688         gpu->exec_state = -1;
 689         mutex_unlock(&gpu->lock);
 690
 691         pm_runtime_mark_last_busy(gpu->dev);
 692         pm_runtime_put_autosuspend(gpu->dev);
 693
 694         return 0;
 695
 696 free_buffer:
 697         etnaviv_gpu_cmdbuf_free(gpu->buffer);
 698         gpu->buffer = NULL;
 699 destroy_iommu:
 700         etnaviv_iommu_destroy(gpu->mmu);
 701         gpu->mmu = NULL;
 702 fail:
 703         pm_runtime_mark_last_busy(gpu->dev);
 704         pm_runtime_put_autosuspend(gpu->dev);
 705
 706         return ret;
 707 }
 708
 709 #ifdef CONFIG_DEBUG_FS
 710 struct dma_debug {
 711         u32 address[2];
 712         u32 state[2];
 713 };
 714
 715 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
 716 {
 717         u32 i;
 718
 719         debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 720         debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 721
 722         for (i = 0; i < 500; i++) {
 723                 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 724                 debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 725
 726                 if (debug->address[0] != debug->address[1])
 727                         break;
 728
 729                 if (debug->state[0] != debug->state[1])
 730                         break;
 731         }
 732 }
 733
 734 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
 735 {
 736         struct dma_debug debug;
 737         u32 dma_lo, dma_hi, axi, idle;
 738         int ret;
 739
 740         seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
 741
 742         ret = pm_runtime_get_sync(gpu->dev);
 743         if (ret < 0)
 744                 return ret;
 745
 746         dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
 747         dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
 748         axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
 749         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 750
 751         verify_dma(gpu, &debug);
 752
 753         seq_puts(m, "\tfeatures\n");
 754         seq_printf(m, "\t minor_features0: 0x%08x\n",
 755                    gpu->identity.minor_features0);
 756         seq_printf(m, "\t minor_features1: 0x%08x\n",
 757                    gpu->identity.minor_features1);
 758         seq_printf(m, "\t minor_features2: 0x%08x\n",
 759                    gpu->identity.minor_features2);
 760         seq_printf(m, "\t minor_features3: 0x%08x\n",
 761                    gpu->identity.minor_features3);
 762         seq_printf(m, "\t minor_features4: 0x%08x\n",
 763                    gpu->identity.minor_features4);
 764         seq_printf(m, "\t minor_features5: 0x%08x\n",
 765                    gpu->identity.minor_features5);
 766
 767         seq_puts(m, "\tspecs\n");
 768         seq_printf(m, "\t stream_count:  %d\n",
 769                         gpu->identity.stream_count);
 770         seq_printf(m, "\t register_max: %d\n",
 771                         gpu->identity.register_max);
 772         seq_printf(m, "\t thread_count: %d\n",
 773                         gpu->identity.thread_count);
 774         seq_printf(m, "\t vertex_cache_size: %d\n",
 775                         gpu->identity.vertex_cache_size);
 776         seq_printf(m, "\t shader_core_count: %d\n",
 777                         gpu->identity.shader_core_count);
 778         seq_printf(m, "\t pixel_pipes: %d\n",
 779                         gpu->identity.pixel_pipes);
 780         seq_printf(m, "\t vertex_output_buffer_size: %d\n",
 781                         gpu->identity.vertex_output_buffer_size);
 782         seq_printf(m, "\t buffer_size: %d\n",
 783                         gpu->identity.buffer_size);
 784         seq_printf(m, "\t instruction_count: %d\n",
 785                         gpu->identity.instruction_count);
 786         seq_printf(m, "\t num_constants: %d\n",
 787                         gpu->identity.num_constants);
 788         seq_printf(m, "\t varyings_count: %d\n",
 789                         gpu->identity.varyings_count);
 790
 791         seq_printf(m, "\taxi: 0x%08x\n", axi);
 792         seq_printf(m, "\tidle: 0x%08x\n", idle);
 793         idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
 794         if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
 795                 seq_puts(m, "\t FE is not idle\n");
 796         if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
 797                 seq_puts(m, "\t DE is not idle\n");
 798         if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
 799                 seq_puts(m, "\t PE is not idle\n");
 800         if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
 801                 seq_puts(m, "\t SH is not idle\n");
 802         if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
 803                 seq_puts(m, "\t PA is not idle\n");
 804         if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
 805                 seq_puts(m, "\t SE is not idle\n");
 806         if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
 807                 seq_puts(m, "\t RA is not idle\n");
 808         if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
 809                 seq_puts(m, "\t TX is not idle\n");
 810         if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
 811                 seq_puts(m, "\t VG is not idle\n");
 812         if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
 813                 seq_puts(m, "\t IM is not idle\n");
 814         if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
 815                 seq_puts(m, "\t FP is not idle\n");
 816         if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
 817                 seq_puts(m, "\t TS is not idle\n");
 818         if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
 819                 seq_puts(m, "\t AXI low power mode\n");
 820
 821         if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
 822                 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
 823                 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
 824                 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
 825
 826                 seq_puts(m, "\tMC\n");
 827                 seq_printf(m, "\t read0: 0x%08x\n", read0);
 828                 seq_printf(m, "\t read1: 0x%08x\n", read1);
 829                 seq_printf(m, "\t write: 0x%08x\n", write);
 830         }
 831
 832         seq_puts(m, "\tDMA ");
 833
 834         if (debug.address[0] == debug.address[1] &&
 835             debug.state[0] == debug.state[1]) {
 836                 seq_puts(m, "seems to be stuck\n");
 837         } else if (debug.address[0] == debug.address[1]) {
 838                 seq_puts(m, "address is constant\n");
 839         } else {
 840                 seq_puts(m, "is running\n");
 841         }
 842
 843         seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
 844         seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
 845         seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
 846         seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
 847         seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
 848                    dma_lo, dma_hi);
 849
 850         ret = 0;
 851
 852         pm_runtime_mark_last_busy(gpu->dev);
 853         pm_runtime_put_autosuspend(gpu->dev);
 854
 855         return ret;
 856 }
 857 #endif
 858
 859 /*
 860  * Hangcheck detection for locked gpu:
 861  */
 862 static void recover_worker(struct work_struct *work)
 863 {
 864         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
 865                                                recover_work);
 866         unsigned long flags;
 867         unsigned int i;
 868
 869         dev_err(gpu->dev, "hangcheck recover!\n");
 870
 871         if (pm_runtime_get_sync(gpu->dev) < 0)
 872                 return;
 873
 874         mutex_lock(&gpu->lock);
 875
 876         /* Only catch the first event, or when manually re-armed */
 877         if (etnaviv_dump_core) {
 878                 etnaviv_core_dump(gpu);
 879                 etnaviv_dump_core = false;
 880         }
 881
 882         etnaviv_hw_reset(gpu);
 883
 884         /* complete all events, the GPU won't do it after the reset */
 885         spin_lock_irqsave(&gpu->event_spinlock, flags);
 886         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
 887                 if (!gpu->event[i].used)
 888                         continue;
 889                 dma_fence_signal(gpu->event[i].fence);
 890                 gpu->event[i].fence = NULL;
 891                 gpu->event[i].used = false;
 892                 complete(&gpu->event_free);
 893         }
 894         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
 895         gpu->completed_fence = gpu->active_fence;
 896
 897         etnaviv_gpu_hw_init(gpu);
 898         gpu->lastctx = NULL;
 899         gpu->exec_state = -1;
 900
 901         mutex_unlock(&gpu->lock);
 902         pm_runtime_mark_last_busy(gpu->dev);
 903         pm_runtime_put_autosuspend(gpu->dev);
 904
 905         /* Retire the buffer objects in a work */
 906         etnaviv_queue_work(gpu->drm, &gpu->retire_work);
 907 }
 908
 909 static void hangcheck_timer_reset(struct etnaviv_gpu *gpu)
 910 {
 911         DBG("%s", dev_name(gpu->dev));
 912         mod_timer(&gpu->hangcheck_timer,
 913                   round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES));
 914 }
 915
 916 static void hangcheck_handler(unsigned long data)
 917 {
 918         struct etnaviv_gpu *gpu = (struct etnaviv_gpu *)data;
 919         u32 fence = gpu->completed_fence;
 920         bool progress = false;
 921
 922         if (fence != gpu->hangcheck_fence) {
 923                 gpu->hangcheck_fence = fence;
 924                 progress = true;
 925         }
 926
 927         if (!progress) {
 928                 u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 929                 int change = dma_addr - gpu->hangcheck_dma_addr;
 930
 931                 if (change < 0 || change > 16) {
 932                         gpu->hangcheck_dma_addr = dma_addr;
 933                         progress = true;
 934                 }
 935         }
 936
 937         if (!progress && fence_after(gpu->active_fence, fence)) {
 938                 dev_err(gpu->dev, "hangcheck detected gpu lockup!\n");
 939                 dev_err(gpu->dev, "     completed fence: %u\n", fence);
 940                 dev_err(gpu->dev, "     active fence: %u\n",
 941                         gpu->active_fence);
 942                 etnaviv_queue_work(gpu->drm, &gpu->recover_work);
 943         }
 944
 945         /* if still more pending work, reset the hangcheck timer: */
 946         if (fence_after(gpu->active_fence, gpu->hangcheck_fence))
 947                 hangcheck_timer_reset(gpu);
 948 }
 949
 950 static void hangcheck_disable(struct etnaviv_gpu *gpu)
 951 {
 952         del_timer_sync(&gpu->hangcheck_timer);
 953         cancel_work_sync(&gpu->recover_work);
 954 }
 955
 956 /* fence object management */
 957 struct etnaviv_fence {
 958         struct etnaviv_gpu *gpu;
 959         struct dma_fence base;
 960 };
 961
 962 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
 963 {
 964         return container_of(fence, struct etnaviv_fence, base);
 965 }
 966
 967 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
 968 {
 969         return "etnaviv";
 970 }
 971
 972 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
 973 {
 974         struct etnaviv_fence *f = to_etnaviv_fence(fence);
 975
 976         return dev_name(f->gpu->dev);
 977 }
 978
 979 static bool etnaviv_fence_enable_signaling(struct dma_fence *fence)
 980 {
 981         return true;
 982 }
 983
 984 static bool etnaviv_fence_signaled(struct dma_fence *fence)
 985 {
 986         struct etnaviv_fence *f = to_etnaviv_fence(fence);
 987
 988         return fence_completed(f->gpu, f->base.seqno);
 989 }
 990
 991 static void etnaviv_fence_release(struct dma_fence *fence)
 992 {
 993         struct etnaviv_fence *f = to_etnaviv_fence(fence);
 994
 995         kfree_rcu(f, base.rcu);
 996 }
 997
 998 static const struct dma_fence_ops etnaviv_fence_ops = {
 999         .get_driver_name = etnaviv_fence_get_driver_name,
1000         .get_timeline_name = etnaviv_fence_get_timeline_name,
1001         .enable_signaling = etnaviv_fence_enable_signaling,
1002         .signaled = etnaviv_fence_signaled,
1003         .wait = dma_fence_default_wait,
1004         .release = etnaviv_fence_release,
1005 };
1006
1007 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1008 {
1009         struct etnaviv_fence *f;
1010
1011         f = kzalloc(sizeof(*f), GFP_KERNEL);
1012         if (!f)
1013                 return NULL;
1014
1015         f->gpu = gpu;
1016
1017         dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1018                        gpu->fence_context, ++gpu->next_fence);
1019
1020         return &f->base;
1021 }
1022
1023 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
1024         unsigned int context, bool exclusive)
1025 {
1026         struct reservation_object *robj = etnaviv_obj->resv;
1027         struct reservation_object_list *fobj;
1028         struct dma_fence *fence;
1029         int i, ret;
1030
1031         if (!exclusive) {
1032                 ret = reservation_object_reserve_shared(robj);
1033                 if (ret)
1034                         return ret;
1035         }
1036
1037         /*
1038          * If we have any shared fences, then the exclusive fence
1039          * should be ignored as it will already have been signalled.
1040          */
1041         fobj = reservation_object_get_list(robj);
1042         if (!fobj || fobj->shared_count == 0) {
1043                 /* Wait on any existing exclusive fence which isn't our own */
1044                 fence = reservation_object_get_excl(robj);
1045                 if (fence && fence->context != context) {
1046                         ret = dma_fence_wait(fence, true);
1047                         if (ret)
1048                                 return ret;
1049                 }
1050         }
1051
1052         if (!exclusive || !fobj)
1053                 return 0;
1054
1055         for (i = 0; i < fobj->shared_count; i++) {
1056                 fence = rcu_dereference_protected(fobj->shared[i],
1057                                                 reservation_object_held(robj));
1058                 if (fence->context != context) {
1059                         ret = dma_fence_wait(fence, true);
1060                         if (ret)
1061                                 return ret;
1062                 }
1063         }
1064
1065         return 0;
1066 }
1067
1068 /*
1069  * event management:
1070  */
1071
1072 static unsigned int event_alloc(struct etnaviv_gpu *gpu)
1073 {
1074         unsigned long ret, flags;
1075         unsigned int i, event = ~0U;
1076
1077         ret = wait_for_completion_timeout(&gpu->event_free,
1078                                           msecs_to_jiffies(10 * 10000));
1079         if (!ret)
1080                 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1081
1082         spin_lock_irqsave(&gpu->event_spinlock, flags);
1083
1084         /* find first free event */
1085         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
1086                 if (gpu->event[i].used == false) {
1087                         gpu->event[i].used = true;
1088                         event = i;
1089                         break;
1090                 }
1091         }
1092
1093         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1094
1095         return event;
1096 }
1097
1098 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1099 {
1100         unsigned long flags;
1101
1102         spin_lock_irqsave(&gpu->event_spinlock, flags);
1103
1104         if (gpu->event[event].used == false) {
1105                 dev_warn(gpu->dev, "event %u is already marked as free",
1106                          event);
1107                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1108         } else {
1109                 gpu->event[event].used = false;
1110                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1111
1112                 complete(&gpu->event_free);
1113         }
1114 }
1115
1116 /*
1117  * Cmdstream submission/retirement:
1118  */
1119
1120 struct etnaviv_cmdbuf *etnaviv_gpu_cmdbuf_new(struct etnaviv_gpu *gpu, u32 size,
1121         size_t nr_bos)
1122 {
1123         struct etnaviv_cmdbuf *cmdbuf;
1124         size_t sz = size_vstruct(nr_bos, sizeof(cmdbuf->bo_map[0]),
1125                                  sizeof(*cmdbuf));
1126
1127         cmdbuf = kzalloc(sz, GFP_KERNEL);
1128         if (!cmdbuf)
1129                 return NULL;
1130
1131         if (gpu->mmu->version == ETNAVIV_IOMMU_V2)
1132                 size = ALIGN(size, SZ_4K);
1133
1134         cmdbuf->vaddr = dma_alloc_wc(gpu->dev, size, &cmdbuf->paddr,
1135                                      GFP_KERNEL);
1136         if (!cmdbuf->vaddr) {
1137                 kfree(cmdbuf);
1138                 return NULL;
1139         }
1140
1141         cmdbuf->gpu = gpu;
1142         cmdbuf->size = size;
1143
1144         return cmdbuf;
1145 }
1146
1147 void etnaviv_gpu_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf)
1148 {
1149         etnaviv_iommu_put_cmdbuf_va(cmdbuf->gpu, cmdbuf);
1150         dma_free_wc(cmdbuf->gpu->dev, cmdbuf->size, cmdbuf->vaddr,
1151                     cmdbuf->paddr);
1152         kfree(cmdbuf);
1153 }
1154
1155 static void retire_worker(struct work_struct *work)
1156 {
1157         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1158                                                retire_work);
1159         u32 fence = gpu->completed_fence;
1160         struct etnaviv_cmdbuf *cmdbuf, *tmp;
1161         unsigned int i;
1162
1163         mutex_lock(&gpu->lock);
1164         list_for_each_entry_safe(cmdbuf, tmp, &gpu->active_cmd_list, node) {
1165                 if (!dma_fence_is_signaled(cmdbuf->fence))
1166                         break;
1167
1168                 list_del(&cmdbuf->node);
1169                 dma_fence_put(cmdbuf->fence);
1170
1171                 for (i = 0; i < cmdbuf->nr_bos; i++) {
1172                         struct etnaviv_vram_mapping *mapping = cmdbuf->bo_map[i];
1173                         struct etnaviv_gem_object *etnaviv_obj = mapping->object;
1174
1175                         atomic_dec(&etnaviv_obj->gpu_active);
1176                         /* drop the refcount taken in etnaviv_gpu_submit */
1177                         etnaviv_gem_mapping_unreference(mapping);
1178                 }
1179
1180                 etnaviv_gpu_cmdbuf_free(cmdbuf);
1181                 /*
1182                  * We need to balance the runtime PM count caused by
1183                  * each submission.  Upon submission, we increment
1184                  * the runtime PM counter, and allocate one event.
1185                  * So here, we put the runtime PM count for each
1186                  * completed event.
1187                  */
1188                 pm_runtime_put_autosuspend(gpu->dev);
1189         }
1190
1191         gpu->retired_fence = fence;
1192
1193         mutex_unlock(&gpu->lock);
1194
1195         wake_up_all(&gpu->fence_event);
1196 }
1197
1198 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1199         u32 fence, struct timespec *timeout)
1200 {
1201         int ret;
1202
1203         if (fence_after(fence, gpu->next_fence)) {
1204                 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
1205                                 fence, gpu->next_fence);
1206                 return -EINVAL;
1207         }
1208
1209         if (!timeout) {
1210                 /* No timeout was requested: just test for completion */
1211                 ret = fence_completed(gpu, fence) ? 0 : -EBUSY;
1212         } else {
1213                 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1214
1215                 ret = wait_event_interruptible_timeout(gpu->fence_event,
1216                                                 fence_completed(gpu, fence),
1217                                                 remaining);
1218                 if (ret == 0) {
1219                         DBG("timeout waiting for fence: %u (retired: %u completed: %u)",
1220                                 fence, gpu->retired_fence,
1221                                 gpu->completed_fence);
1222                         ret = -ETIMEDOUT;
1223                 } else if (ret != -ERESTARTSYS) {
1224                         ret = 0;
1225                 }
1226         }
1227
1228         return ret;
1229 }
1230
1231 /*
1232  * Wait for an object to become inactive.  This, on it's own, is not race
1233  * free: the object is moved by the retire worker off the active list, and
1234  * then the iova is put.  Moreover, the object could be re-submitted just
1235  * after we notice that it's become inactive.
1236  *
1237  * Although the retirement happens under the gpu lock, we don't want to hold
1238  * that lock in this function while waiting.
1239  */
1240 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1241         struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1242 {
1243         unsigned long remaining;
1244         long ret;
1245
1246         if (!timeout)
1247                 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1248
1249         remaining = etnaviv_timeout_to_jiffies(timeout);
1250
1251         ret = wait_event_interruptible_timeout(gpu->fence_event,
1252                                                !is_active(etnaviv_obj),
1253                                                remaining);
1254         if (ret > 0) {
1255                 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
1256
1257                 /* Synchronise with the retire worker */
1258                 flush_workqueue(priv->wq);
1259                 return 0;
1260         } else if (ret == -ERESTARTSYS) {
1261                 return -ERESTARTSYS;
1262         } else {
1263                 return -ETIMEDOUT;
1264         }
1265 }
1266
1267 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu)
1268 {
1269         return pm_runtime_get_sync(gpu->dev);
1270 }
1271
1272 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu)
1273 {
1274         pm_runtime_mark_last_busy(gpu->dev);
1275         pm_runtime_put_autosuspend(gpu->dev);
1276 }
1277
1278 /* add bo's to gpu's ring, and kick gpu: */
1279 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
1280         struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf)
1281 {
1282         struct dma_fence *fence;
1283         unsigned int event, i;
1284         int ret;
1285
1286         ret = etnaviv_gpu_pm_get_sync(gpu);
1287         if (ret < 0)
1288                 return ret;
1289
1290         /*
1291          * TODO
1292          *
1293          * - flush
1294          * - data endian
1295          * - prefetch
1296          *
1297          */
1298
1299         event = event_alloc(gpu);
1300         if (unlikely(event == ~0U)) {
1301                 DRM_ERROR("no free event\n");
1302                 ret = -EBUSY;
1303                 goto out_pm_put;
1304         }
1305
1306         fence = etnaviv_gpu_fence_alloc(gpu);
1307         if (!fence) {
1308                 event_free(gpu, event);
1309                 ret = -ENOMEM;
1310                 goto out_pm_put;
1311         }
1312
1313         mutex_lock(&gpu->lock);
1314
1315         gpu->event[event].fence = fence;
1316         submit->fence = fence->seqno;
1317         gpu->active_fence = submit->fence;
1318
1319         if (gpu->lastctx != cmdbuf->ctx) {
1320                 gpu->mmu->need_flush = true;
1321                 gpu->switch_context = true;
1322                 gpu->lastctx = cmdbuf->ctx;
1323         }
1324
1325         etnaviv_buffer_queue(gpu, event, cmdbuf);
1326
1327         cmdbuf->fence = fence;
1328         list_add_tail(&cmdbuf->node, &gpu->active_cmd_list);
1329
1330         /* We're committed to adding this command buffer, hold a PM reference */
1331         pm_runtime_get_noresume(gpu->dev);
1332
1333         for (i = 0; i < submit->nr_bos; i++) {
1334                 struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj;
1335
1336                 /* Each cmdbuf takes a refcount on the mapping */
1337                 etnaviv_gem_mapping_reference(submit->bos[i].mapping);
1338                 cmdbuf->bo_map[i] = submit->bos[i].mapping;
1339                 atomic_inc(&etnaviv_obj->gpu_active);
1340
1341                 if (submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE)
1342                         reservation_object_add_excl_fence(etnaviv_obj->resv,
1343                                                           fence);
1344                 else
1345                         reservation_object_add_shared_fence(etnaviv_obj->resv,
1346                                                             fence);
1347         }
1348         cmdbuf->nr_bos = submit->nr_bos;
1349         hangcheck_timer_reset(gpu);
1350         ret = 0;
1351
1352         mutex_unlock(&gpu->lock);
1353
1354 out_pm_put:
1355         etnaviv_gpu_pm_put(gpu);
1356
1357         return ret;
1358 }
1359
1360 /*
1361  * Init/Cleanup:
1362  */
1363 static irqreturn_t irq_handler(int irq, void *data)
1364 {
1365         struct etnaviv_gpu *gpu = data;
1366         irqreturn_t ret = IRQ_NONE;
1367
1368         u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1369
1370         if (intr != 0) {
1371                 int event;
1372
1373                 pm_runtime_mark_last_busy(gpu->dev);
1374
1375                 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1376
1377                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1378                         dev_err(gpu->dev, "AXI bus error\n");
1379                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1380                 }
1381
1382                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1383                         int i;
1384
1385                         dev_err_ratelimited(gpu->dev,
1386                                 "MMU fault status 0x%08x\n",
1387                                 gpu_read(gpu, VIVS_MMUv2_STATUS));
1388                         for (i = 0; i < 4; i++) {
1389                                 dev_err_ratelimited(gpu->dev,
1390                                         "MMU %d fault addr 0x%08x\n",
1391                                         i, gpu_read(gpu,
1392                                         VIVS_MMUv2_EXCEPTION_ADDR(i)));
1393                         }
1394                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1395                 }
1396
1397                 while ((event = ffs(intr)) != 0) {
1398                         struct dma_fence *fence;
1399
1400                         event -= 1;
1401
1402                         intr &= ~(1 << event);
1403
1404                         dev_dbg(gpu->dev, "event %u\n", event);
1405
1406                         fence = gpu->event[event].fence;
1407                         gpu->event[event].fence = NULL;
1408                         dma_fence_signal(fence);
1409
1410                         /*
1411                          * Events can be processed out of order.  Eg,
1412                          * - allocate and queue event 0
1413                          * - allocate event 1
1414                          * - event 0 completes, we process it
1415                          * - allocate and queue event 0
1416                          * - event 1 and event 0 complete
1417                          * we can end up processing event 0 first, then 1.
1418                          */
1419                         if (fence_after(fence->seqno, gpu->completed_fence))
1420                                 gpu->completed_fence = fence->seqno;
1421
1422                         event_free(gpu, event);
1423                 }
1424
1425                 /* Retire the buffer objects in a work */
1426                 etnaviv_queue_work(gpu->drm, &gpu->retire_work);
1427
1428                 ret = IRQ_HANDLED;
1429         }
1430
1431         return ret;
1432 }
1433
1434 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1435 {
1436         int ret;
1437
1438         if (gpu->clk_bus) {
1439                 ret = clk_prepare_enable(gpu->clk_bus);
1440                 if (ret)
1441                         return ret;
1442         }
1443
1444         if (gpu->clk_core) {
1445                 ret = clk_prepare_enable(gpu->clk_core);
1446                 if (ret)
1447                         goto disable_clk_bus;
1448         }
1449
1450         if (gpu->clk_shader) {
1451                 ret = clk_prepare_enable(gpu->clk_shader);
1452                 if (ret)
1453                         goto disable_clk_core;
1454         }
1455
1456         return 0;
1457
1458 disable_clk_core:
1459         if (gpu->clk_core)
1460                 clk_disable_unprepare(gpu->clk_core);
1461 disable_clk_bus:
1462         if (gpu->clk_bus)
1463                 clk_disable_unprepare(gpu->clk_bus);
1464
1465         return ret;
1466 }
1467
1468 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1469 {
1470         if (gpu->clk_shader)
1471                 clk_disable_unprepare(gpu->clk_shader);
1472         if (gpu->clk_core)
1473                 clk_disable_unprepare(gpu->clk_core);
1474         if (gpu->clk_bus)
1475                 clk_disable_unprepare(gpu->clk_bus);
1476
1477         return 0;
1478 }
1479
1480 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1481 {
1482         unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1483
1484         do {
1485                 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1486
1487                 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1488                         return 0;
1489
1490                 if (time_is_before_jiffies(timeout)) {
1491                         dev_warn(gpu->dev,
1492                                  "timed out waiting for idle: idle=0x%x\n",
1493                                  idle);
1494                         return -ETIMEDOUT;
1495                 }
1496
1497                 udelay(5);
1498         } while (1);
1499 }
1500
1501 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1502 {
1503         if (gpu->buffer) {
1504                 /* Replace the last WAIT with END */
1505                 etnaviv_buffer_end(gpu);
1506
1507                 /*
1508                  * We know that only the FE is busy here, this should
1509                  * happen quickly (as the WAIT is only 200 cycles).  If
1510                  * we fail, just warn and continue.
1511                  */
1512                 etnaviv_gpu_wait_idle(gpu, 100);
1513         }
1514
1515         return etnaviv_gpu_clk_disable(gpu);
1516 }
1517
1518 #ifdef CONFIG_PM
1519 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1520 {
1521         u32 clock;
1522         int ret;
1523
1524         ret = mutex_lock_killable(&gpu->lock);
1525         if (ret)
1526                 return ret;
1527
1528         clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
1529                 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
1530
1531         etnaviv_gpu_load_clock(gpu, clock);
1532         etnaviv_gpu_hw_init(gpu);
1533
1534         gpu->switch_context = true;
1535         gpu->exec_state = -1;
1536
1537         mutex_unlock(&gpu->lock);
1538
1539         return 0;
1540 }
1541 #endif
1542
1543 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1544         void *data)
1545 {
1546         struct drm_device *drm = data;
1547         struct etnaviv_drm_private *priv = drm->dev_private;
1548         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1549         int ret;
1550
1551 #ifdef CONFIG_PM
1552         ret = pm_runtime_get_sync(gpu->dev);
1553 #else
1554         ret = etnaviv_gpu_clk_enable(gpu);
1555 #endif
1556         if (ret < 0)
1557                 return ret;
1558
1559         gpu->drm = drm;
1560         gpu->fence_context = dma_fence_context_alloc(1);
1561         spin_lock_init(&gpu->fence_spinlock);
1562
1563         INIT_LIST_HEAD(&gpu->active_cmd_list);
1564         INIT_WORK(&gpu->retire_work, retire_worker);
1565         INIT_WORK(&gpu->recover_work, recover_worker);
1566         init_waitqueue_head(&gpu->fence_event);
1567
1568         setup_deferrable_timer(&gpu->hangcheck_timer, hangcheck_handler,
1569                                (unsigned long)gpu);
1570
1571         priv->gpu[priv->num_gpus++] = gpu;
1572
1573         pm_runtime_mark_last_busy(gpu->dev);
1574         pm_runtime_put_autosuspend(gpu->dev);
1575
1576         return 0;
1577 }
1578
1579 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1580         void *data)
1581 {
1582         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1583
1584         DBG("%s", dev_name(gpu->dev));
1585
1586         hangcheck_disable(gpu);
1587
1588 #ifdef CONFIG_PM
1589         pm_runtime_get_sync(gpu->dev);
1590         pm_runtime_put_sync_suspend(gpu->dev);
1591 #else
1592         etnaviv_gpu_hw_suspend(gpu);
1593 #endif
1594
1595         if (gpu->buffer) {
1596                 etnaviv_gpu_cmdbuf_free(gpu->buffer);
1597                 gpu->buffer = NULL;
1598         }
1599
1600         if (gpu->mmu) {
1601                 etnaviv_iommu_destroy(gpu->mmu);
1602                 gpu->mmu = NULL;
1603         }
1604
1605         gpu->drm = NULL;
1606 }
1607
1608 static const struct component_ops gpu_ops = {
1609         .bind = etnaviv_gpu_bind,
1610         .unbind = etnaviv_gpu_unbind,
1611 };
1612
1613 static const struct of_device_id etnaviv_gpu_match[] = {
1614         {
1615                 .compatible = "vivante,gc"
1616         },
1617         { /* sentinel */ }
1618 };
1619
1620 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1621 {
1622         struct device *dev = &pdev->dev;
1623         struct etnaviv_gpu *gpu;
1624         int err;
1625
1626         gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1627         if (!gpu)
1628                 return -ENOMEM;
1629
1630         gpu->dev = &pdev->dev;
1631         mutex_init(&gpu->lock);
1632
1633         /* Map registers: */
1634         gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev));
1635         if (IS_ERR(gpu->mmio))
1636                 return PTR_ERR(gpu->mmio);
1637
1638         /* Get Interrupt: */
1639         gpu->irq = platform_get_irq(pdev, 0);
1640         if (gpu->irq < 0) {
1641                 dev_err(dev, "failed to get irq: %d\n", gpu->irq);
1642                 return gpu->irq;
1643         }
1644
1645         err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1646                                dev_name(gpu->dev), gpu);
1647         if (err) {
1648                 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1649                 return err;
1650         }
1651
1652         /* Get Clocks: */
1653         gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1654         DBG("clk_bus: %p", gpu->clk_bus);
1655         if (IS_ERR(gpu->clk_bus))
1656                 gpu->clk_bus = NULL;
1657
1658         gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1659         DBG("clk_core: %p", gpu->clk_core);
1660         if (IS_ERR(gpu->clk_core))
1661                 gpu->clk_core = NULL;
1662
1663         gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1664         DBG("clk_shader: %p", gpu->clk_shader);
1665         if (IS_ERR(gpu->clk_shader))
1666                 gpu->clk_shader = NULL;
1667
1668         /* TODO: figure out max mapped size */
1669         dev_set_drvdata(dev, gpu);
1670
1671         /*
1672          * We treat the device as initially suspended.  The runtime PM
1673          * autosuspend delay is rather arbitary: no measurements have
1674          * yet been performed to determine an appropriate value.
1675          */
1676         pm_runtime_use_autosuspend(gpu->dev);
1677         pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1678         pm_runtime_enable(gpu->dev);
1679
1680         err = component_add(&pdev->dev, &gpu_ops);
1681         if (err < 0) {
1682                 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1683                 return err;
1684         }
1685
1686         return 0;
1687 }
1688
1689 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1690 {
1691         component_del(&pdev->dev, &gpu_ops);
1692         pm_runtime_disable(&pdev->dev);
1693         return 0;
1694 }
1695
1696 #ifdef CONFIG_PM
1697 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1698 {
1699         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1700         u32 idle, mask;
1701
1702         /* If we have outstanding fences, we're not idle */
1703         if (gpu->completed_fence != gpu->active_fence)
1704                 return -EBUSY;
1705
1706         /* Check whether the hardware (except FE) is idle */
1707         mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1708         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1709         if (idle != mask)
1710                 return -EBUSY;
1711
1712         return etnaviv_gpu_hw_suspend(gpu);
1713 }
1714
1715 static int etnaviv_gpu_rpm_resume(struct device *dev)
1716 {
1717         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1718         int ret;
1719
1720         ret = etnaviv_gpu_clk_enable(gpu);
1721         if (ret)
1722                 return ret;
1723
1724         /* Re-initialise the basic hardware state */
1725         if (gpu->drm && gpu->buffer) {
1726                 ret = etnaviv_gpu_hw_resume(gpu);
1727                 if (ret) {
1728                         etnaviv_gpu_clk_disable(gpu);
1729                         return ret;
1730                 }
1731         }
1732
1733         return 0;
1734 }
1735 #endif
1736
1737 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1738         SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1739                            NULL)
1740 };
1741
1742 struct platform_driver etnaviv_gpu_driver = {
1743         .driver = {
1744                 .name = "etnaviv-gpu",
1745                 .owner = THIS_MODULE,
1746                 .pm = &etnaviv_gpu_pm_ops,
1747                 .of_match_table = etnaviv_gpu_match,
1748         },
1749         .probe = etnaviv_gpu_platform_probe,
1750         .remove = etnaviv_gpu_platform_remove,
1751         .id_table = gpu_ids,
1752 };